Features & Benefits
MagniVu™Technology Provides
500 ps Timing Resolution on All
Channels All the Time Through
the Same Probe
Up to 200 MHz State
Acquisition with 400 MHz Data
Rate for Advanced Processors
and Buses
Simultaneous State and High
Speed Timing Analysis Through
the Same Probes Pinpoints
Elusive Faults
500 MHz Deep Timing Analysis
with Up to 128 Mb Per Channel
Broad Processor and Bus
Support
Universal Source Code Support
for Correlating High-level
Language Source with Realtime Trace
Performance Analysis Support
for Optimizing Target System
Remote Control Using
Microsoft COM/DCOM
Technology Supports Advanced
Data Analysis
Microsoft Windows 2000
Professional PC Platform
Provides Familiar User Interface
With Network Connectivity
All Probes, Software and
Accessories Fully
Interchangeable Between all
TLAs
Applications
Hardware Debug and
Verification
Processor/Bus Debug and
Verification
Embedded Software
Integration, Debug and
Verification
Logic Analyzers
TLA Family
Breakthrough Solutions for Real-time Digital
Systems Analysis
Today’s digital design engineers face daily pressures to speed new products to the marketplace.
The TLA answers the need with breakthrough solutions for the entire design team, providing the ability
to quickly monitor,capture and analyze real-time
system operation in order to debug, verify, optimize
and validate digital systems.
Hardware developers, Hardware/Software integrators and embedded software developers will appreciate the range of capabilities of the TLA.Its broad
feature set includes capturing and correlating elusive hardware and software faults; providing simultaneous state and high-speed timing analysis; using
deep state acquisition to find the cause of complex
problems; generating the digital stimulus for functional verification, debugging and stress testing;
and offering non-intrusive real-time software execution tracing that correlates to the source code and
to the hardware events.
This kind of performance is matched by value.
Productivity and connectivity features such as the
open Microsoft Windows platform make all TLA logic
analyzers easy to use and easily networked into the
design environment. Modularity and flexibility features help you protect your current investment.
TLA Family • Logic Analyzers • www.tektronix.com/LA
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The TLA family of logic analyzers consists of the TLA600 Series and the TLA700 Series. The TLA600 offers a
selection of standalone logic analyzer instruments at prices that make 500 ps timing resolution available to
designers of today’s mainstream embedded systems.The TLA700 Series offers the highest performance for
today’s demanding applications and consists of portable and benchtop modular mainframes with expansion
mainframe capability.Instrument modules include logic analyzer,pattern generator and digitizing oscilloscope.A full line of complementary support products for popular processors and buses is available for the
entire TLA family.
Logic Analyzers
TLA Family
Characteristics
TLA Logic Analyzers
General
Number of Channels (all channels are acquired including clocks) –
TLA601/611/621,TLA7N1: 34 channels (2 are clock
channels).
TLA602/612/622,TLA7N2,TLA7P2: 68 channels (4 are
clock channels).
TLA603/613/623,TLA7N3: 102 channels (4 are clock and
2 are qualifier channels).
TLA604/614/624,TLA 7N4,TLA 7P4: 136 channels (4 are
clock and 4 are qualifier channels).
Channel Grouping – No limit to number of groups or number of channels per group (all channels can be reused in
multiple groups).
TLA700 Module “Merging”– Three 102 channel or 136
channel modules can be “merged”to make up to a 408
channel module. Merged modules exhibit the same depth
as the lesser of the three individual modules.
Word/range/setup-and-hold/glitch/transition recognizers
span all three modules. Only one set of clock connections
is required.
Time Stamp – 50-Bits at 500 ps resolution (6.5 day
range).
Clocking/Acquisition Modes – State, timing, 2x timing,
simultaneous.
Number of Mainframe Slots Required per TLA700
Module – 2.
Input Characteristics (with P6417,
P6418 or P6434 Probes)
Capacitive Loading – 1.4 pF typical data; 2 pF typical
clock (P6418).
2 pF typical data and clock (P6417 & P6434).
Threshold Selection Range – From +5.0 V to –2.0 V in
50 mV increments.
Threshold Selection Channel Granularity – Separate
selection for clock (1) and data (16) for each 17 channel
probe connector.
Threshold Accuracy (including probe)– ±100 mV.
Input Voltage Range – Operating: 6.5 V
p-p
centered
around the programmed threshold.
Non-destructive: ±15 V.
Input Signal Swing (probe overdrive) – ±250mV or
±25% of signal swing, whichever is greater (P6417 &
P6418).
±300 mV or ±25% of signal swing (P6434).
Input Signal Minimum Slew Rate – 200 mV/ns typical.
State Acquisition Characteristics
(with P6417, P6418 or P6434
Probes)
State Clock Rate – 100 MHz standard, 200 MHz optional.
State Data Rate (half/full channels) –
400 MHz/200 MHz, typical. Requires 200 MHz state
option.
State Memory Depth with Timestamps – 64 Kb,
256 Kb, 1 Mb, 4 Mb, 16 Mb or 64 Mb Bits per channel
(4 Mb, 16 Mb and 64 Mb available only on TLA700).
Setup Time Selection Range– From 8.5 ns before, to
7.0 ns after clock edge.
Setup-and-hold Window – 2.0ns typical.
Minimum Clock Pulse Width– 2 ns.
Active Clock Edge Separation – 5 ns.
Demux Channel Selection – Channels can be demulti-
plexed to other channels through user interface with 8
channel granularity.
Timing Acquisition Characteristics
(with P6417, P6418 or P6434
Probes)
MagniVu™ Timing – 500 ps.
MagniVu Timing Memory Depth– 2 Kb (2048) per
channel.
Deep Timing Resolution (half/full channels)– 2 ns,
4 ns to 50 ms.
Deep Timing Resolution with Glitch Storage Enabled–
10 ns to 50 ms.
Deep Timing Memory Depth (half/full channels with
timestamps and with or without transitional storage) –
128/64 Kb, 512/256 Kb, 2/1 Mb, 8/4 Mb, 32/16 Mb,
128/64 Mb per channel (8/4 Mb, 32/16 Mb and
128/64 Mb available only on TLA700).
Deep Timing Memory Depth with Glitch Storage
Enabled – Half of default main memory depth.
Channel-to-channel Skew – ≤1 ns typical.
Minimum Recognizable Pulse Width (single channel)–
2 ns.
Minimum Recognizable Glitch Width (single channel)–
2 ns.
Minimum Recognizable Multi-channel Trigger Event –
Sample period + 2 ns.
Trigger Characteristics
Independent Trigger States – 16.
Maximum Independent If/then Clauses per State – 16.
Maximum Number of Events per If/then Clause – 8.
Maximum Number of Actions per If/then Clause – 8.
Maximum Number of Trigger Events – 18
(2 counter/timers plus any 16 other resources).
Number of Word Recognizers– 16.
Number of Range Recognizers – 4.
Number of Counter/Timers – 2.
Trigger Event Types– Word,group, channel, transition,
range, anything, counter value,timer value, signal, glitch,
setup-and-hold violation.
Trigger Action Types – Trigger module, trigger all, store,
don’t store, start store, stop store,increment counter,
reset counter,start timer, stop timer, reset timer, goto
state, set/clear signal, do nothing.
Trigger Sequence Rate– DC to 250 MHz (4 ns).
Counter/Timer Range – 51-Bits each (>100 days @
4 ns).
Counter Rate – DC to 250 MHz (4 ns).
Timer Clock Rate – 250 MHz (4 ns).
Counter/Timer Latency – None (can be tested or reset
immediately after starting).
Range Recognizers – Double bounded (can be as wide
as any group, must be grouped according to specified
order of significance).
Setup-and-hold Violation Recognizer Setup Time
Range – From 8 ns before to 7 ns after clock edge in
0.5 ns increments.
Setup-and-hold Violation Recognizer Hold Time
Range – From 7ns before to 8 ns after clock edge in
0.5 ns increments.
Trigger Position– Any data sample.
MagniVu T rigger Position – MagniVu data is centered
around the module trigger.
Storage Control (data qualification) – Global (condition-
al), by state (start/stop), by trigger action,or transitional.
Storage Window Granularity – Single sample or block-
of-31 samples before and after.
TLA Family • Logic Analyzers • www.tektronix.com/LA
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Logic Analyzers
TLA Family
P6417 Probe Cable Length – 1.8 m (6 ft.).
P6418 Probe Cable Length – 1.9 m (6.25 ft.).
P6434 Probe Cable Length – 1.5 m (5 ft.).
All three probes have the same electrical length.
TLA700 Pattern
Generator Modules
General
Data Width –
64 Channel full channel mode.
32 Channel half channel mode.
Module “Merging”– Five modules can be “merged”to
make up to a 320 channel module. Merged modules
exhibit the same depth as the lesser of the 5 individual
modules.
Number of mainframe slots required – 2.
Data Rate –
Internal Clock:
0.5 Hz to 134 MHz full channel mode.
1.0 Hz to 268 MHz half channel mode.
External Clock:
DC to 134 MHz full channel mode.
DC to 268 MHz half channel mode.
External Clock Input –
Polarity: positive or negative.
Threshold: –2.56 V to +2.54 V,nominal; programmable in
20 mV increments.
Sensitivity: ≤500 mV
p-p
.
Impedance: 1 kΩ terminated to ground.
Data Depth –
256 K full channel/512 K half channel.
1 M full channel/2 M half channel (optional).
Pattern Sequencing
Characteristics
Blocks – Separate sections of pattern program that are
output in a user definable order by the Sequencer.Block
pattern depth can be from 40 sequences (full channel
mode) or 80 sequences (half channel mode) up to the
entire depth of the TLA7PG2.A maximum of 4,000 Blocks
may be defined.
Sequencer – A 4000 line memory that allows the user to
pick the output order of individual Blocks. Each line in the
sequencer allows the definition of a Block to be output, a
Repeat Count for that Block,A Wait For event condition for
the Block, the Signal state for that Block (asserted or
unasserted), and a Jump If event condition, with a
sequence line to jump to if the condition is satisfied.
Sub-sequences – Up to 50 contiguous lines of the
Sequencer memory may be defined as a Sub-sequence.
A Sub-sequence can then be treated like a block.
(Example: 15 Sequences of Blocks are defined as Subsequence A1.Now any line in the Sequencer can output
A1. Five calls to Sub-sequence A1 will be flattened out to
75 sequences at run time.)
Jump If – Jumps to the specified sequence if a user
defined event is true.The user defined event is a boolean
combination of the eight external event input lines and
the one-of-four intermodule signals.The user defined
Event is selectable between level and edge (event going
from false to true). One Jump If may be defined for every
Block.The Jump If command works at all clock rates,
including the maximum half channel mode rate of
268 MHz.
Wait For – Pattern output is paused until the user
defined Event is true. One Wait For may be defined for
every Block.
Assert Signal – One of the four inter-module signals is
selected to be controlled from the pattern generator program. Signals may be asserted and unasserted allowing
true interaction with the logic analyzer modules and with
other pattern generator modules. Signal action (assert or
unassert) may be defined for every Block.
Repeat Count – The sequence is repeated from 1 to
65,536 times. Infinite may also be selected. One Repeat
Count may be defined for every Block. Note that a Repeat
value of 10,000 takes one sequence line in memory,not
10,000.
Step – While in Step mode, the TLA7PG2,the user can
manually satisfy (i.e., click an icon) Wait For and Jump
conditional events.This allows the user to debug the logic
flow of the program’s sequencing.
Initialization Block – The unconditional Jump command
allows the user to implement an equivalent function.
Common to P6470 TTL/CMOS &
P6471 ECL Probes
Number of Data Outputs – 16 in Full Channel Mode. 8 in
Half Channel Mode.
Number of Clock Outputs – 1. (Only one of Clock Output
and Strobe Output can be enabled.)
Number of Strobe Outputs – 1. (Only one of Clock
Output and Strobe Output can be enabled.)
Number of External Event Input – 2.
Clock Output Polarity – Positive.
Strobe Type– RZ only.
Strobe Delay – Zero or Trailing Edge.
P6470 TTL/CMOS Probe
Output Type–
HD74LVC541A for Data Output.
HD74LVC244A for Clock/Strobe Output.
Rise/Fall Time (20% to 80%)–
Timing values Timing values
measured using measured using
75 Ω termination 75 Ω termination
(internal to probe), (internal to probe),
1 MΩ + <1 pF 510Ω + 51 pF
load and V
OH
load and V
OH
set to 5.0 V. set to 5.0 V.
Clock/Strobe Output:
Rise: 640 ps typical. 6.5ns typical.
Fall: 1.1 ns typical. 6.3 ns typical.
Data Output:
Rise: 680 ps typical. 5.2ns typical.
Fall: 2.9 ns typical. 4.5 ns typical.
Output Voltage (nominal, load: 1 MΩ)–
VOH: 2.0 V to 5.5 V,tri-stateable,programmable in 25 mV
increments.
VOL:0V.
Data Output Skew –
<510 ps typical between all data output pins of all modules in the mainframe after inter-module skew is adjusted
manually.
<480 ps typical between all data output pins of single
probe.
Data Output to Strobe Output Delay – 1.7 ns typical
when strobe delay set to zero.
Data Output to Clock Output Delay – 2.4 ns typical.
External Clock Input to Clock Output Delay –
Full Channel mode: 61.5 ns typical.
Half Channel mode: 61.5 ns typical.
Number of External Inhibit Input – 1.
External Inhibit Input to Output Enable Delay – 34 ns
typical for Data Output.
External Inhibit Input to Output Disable Delay – 86 ns
typical for Data Output.
Probe D Data Output to Output Enable Delay –
(for Internal Inhibit) 7 ns typical for Data Output.
Probe D Data Output to Output Disable Delay –
(for Internal Inhibit) 8 ns typical for Data Output.
TLA Family • Logic Analyzers • www.tektronix.com/LA
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