Tektronix TLA7ABx, TLA7AAx Service Manual

Service Manual

Tektronix Logic Analyzer Module (TLA7AAx & TLA7ABx)

071-1043-01

This document applies to TLA application software version 4.2 and above.

Warning

The servicing instructions are for use by qualified personnel only. To avoid personal injury, do not perform any servicing unless you are qualified to do so. Refer to all safety summaries prior to performing service.

www.tektronix.com

Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes that in all previously published material. Specifications and price change privileges reserved.

Tektronix, Inc., P.O. Box 500, Beaverton, OR 97077

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

WARRANTY

Tektronix warrants that the products that it manufactures and sells will be free from defects in materials and workmanship for a period of one (1) year from the date of shipment. If a product proves defective during thi s warranty period, Tektronix, at its option, e ither will repair the defective product without charge for parts and labor, or will provide a replacement in exchange for the defective product.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges prepaid. Tektronix shall pay for the return of the product to Custome r if the shipment is to a location within the country in which the Tektronix service center is located. Customer shall be responsible for paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.

This warranty shall not apply to any de fect, failure or damage caused by improper use or i mproper or inadequate maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a ) to repair damage resulting from attempts by personnel other tha n Tektronix representatives to install, repair or service the product; b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any damage or malfunction caused by the use of non-Tektronix supplies; or d) to service a product that has been modified or integrated with other products when the effect of such modification or integration increases the time or difficulty of servicing the product.

THIS W ARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’ RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

Specifications

General Safety Summary ix...................................

Service Safety Summary xi....................................

Preface xiii...................................................

Manual Structure xiii................................................

Manual Conventions xiv..............................................

Related Manuals xvi.................................................

Contacting Tektronix xvii.............................................

Introduction xix..............................................

Adjustment and Certification Interval xix................................

Strategy for Servicing xix.............................................

Service Offerings xx................................................

Warranty Repair Service xx.......................................

Calibration and Repair Service xx..................................

Service Options xx..............................................

Service Agreements xx...........................................

Service On Demand xx...........................................

Self Service xx.................................................

For More Information xxi.........................................

Operating Information

Logic Analyzer Module Description 1--1.................................

TLACAL2 Performance Verification and Adjustment Test Fixture Description 1--2

Characteristic Tables 1--2.............................................

Installation 2--1.....................................................

Logical Address 2--1.............................................

Merged Modules 2--2.............................................

Module Installation 2--2...........................................

TLACAL2 Fixture Installation 2--3.................................

Software Installation 2--7.............................................

Verify the Performance Verification Software Version 2--7................

Install the Performance Verification Software 2--7......................

Removing the Software 2--8........................................

Operating Information 2--8............................................

Front Panel 2--8..................................................

Merge Cable Connectors 2--10.......................................

Rear Panel 2--11..................................................

Online Help 2--11.................................................

Diagnostics 2--11.................................................

Self Calibration 2--12..............................................

Menu Overview 2--12..............................................

Merged Modules 2--14................................................

TLA7AXX Logic Analyzer Module Service Manual

Table of Contents

Theory of Operation

Merging Rules 2--14...............................................

Merge Procedure 2--15.............................................

Unmerge Procedure 2--19...........................................

Block Level Description 3--1...........................................

Local Processor Unit (LPU) Board 3--1..................................

Processor System 3--1.............................................

Communications Interface 3--2.....................................

Power Supplies 3--2..............................................

Acquisition Board 3--2................................................

Clock Circuitry 3--2..............................................

Probe Interface 3--2..............................................

Analog Output Interface 3--2.......................................

Power Supplies 3--2..............................................

Trigger and Storage Control Circuitry 3--3............................

Acquisition Memory 3--3..........................................

Backplane Interface 3--3...........................................

Probes 3--4.........................................................

Merged Modules 3--4.................................................

Performance Verification

Summary Verification 4--1.............................................

Test Equipment 4--3..................................................

Test Equipment Setup 4--4.............................................

Functional Verification 4--7............................................

Performance Verification Instructions 4--10................................

Performance Verification Procedures 4--12................................

Logic Analyzer Module Certification 4--30................................

Starting the Performance Verification Software 4--4.....................

Software Overview 4--5...........................................

Obtaining Test Results 4--6.........................................

Troubleshooting 4--6..............................................

Test Equipment 4--7..............................................

Setup 4--7......................................................

Module Self Tests and Power-On Diagnostics 4--8......................

Logic Analyzer Module Functional Verification Procedure 4--8............

Probe Functional Verification 4--9...................................

Prerequisites 4--10................................................

Procedure Overview 4--11..........................................

Probe+PIC Procedure 4--15.........................................

Module+MIC Procedures 4--18......................................

Module+Probe Gain and Offset Procedures 4--20........................

Module+Probe Timing Procedures 4--23...............................

Setup and Hold Procedure 4--27......................................

Equipment Setups 4--30............................................

Start the Software 4--32............................................

TLA7AXX Logic Analyzer Module Service Manual

Adjustment Procedures

Table of Contents

Test Equipment and Initial Setup 5--1....................................

Prerequisites 5--1....................................................

Merged Modules 5--2.................................................

Using the Software 5--2...............................................

Performing the Adjustments 5--2....................................

Adjustment After Repair 5--3.......................................

Tests Performed 5--3.................................................

Self Calibration 5--5.............................................

Probe+PIC Procedures 5--6............................................

Equipment Setups 5-- 6............................................

Start the Software 5--7............................................

Module+MIC Procedures 5--9..........................................

Equipment Setups 5-- 9............................................

Start the Software 5--10............................................

Module+Probe Timing Procedures 5--12...................................

Equipment Setups 5--12............................................

Start the Software 5--13............................................

Merged Deskew Procedures 5--16........................................

Equipment Setups 5--16............................................

Start the Software 5--17............................................

Completing the Adjustment Steps 5 --18...................................

Maintenance

Related Maintenance Procedures 6--1....................................

Preventing Electrostatic Discharge 6--1..................................

Inspection and Cleaning 6--2...........................................

General Care 6--2................................................

Inspection and Cleaning Procedures 6--2..............................

Exterior Inspection 6--3...........................................

Exterior Cleaning Procedure 6--3....................................

Interior Inspection 6--4............................................

Interior Cleaning Procedure 6--4....................................

Cleaning the Probes 6--5...........................................

Cleaning the P6860 and P6880 Compression Footprints 6--6..................

Cleaning the P6860 and P6880 Probe Heads 6--6...........................

Storing the P6860 and P6880 Probe Heads 6--7............................

Removal and Installation Procedures 6--9.........................

Tools Required 6--9..................................................

Torque Requirements 6--9.............................................

Injector/Ejector Handles 6 --10...........................................

Removal 6--10....................................................

Installation 6 --11..................................................

Covers 6--11.........................................................

Removal 6-- 11....................................................

Installation 6--13..................................................

Local Processor Unit Board 6--16.......................................

Removal 6--16....................................................

Installation 6--17.................................................

TLA7AXX Logic Analyzer Module Service Manual

iii

Table of Contents

Acquisition Board 6--19................................................

Removal 6--19....................................................

Installation 6--22..................................................

Fuses 6--23..........................................................

Front and Rear EMI Gaskets 6--23.......................................

Removal 6--23....................................................

Installation 6--24..................................................

Side EMI Gaskets 6--24................................................

Troubleshooting 6--25..........................................

Service Level 6--25...................................................

Required Documentation 6--26..........................................

Check for Common Problems 6--26......................................

Eliminate Other Problem Sources 6--28...................................

Substitute a Good Module 6--28......................................

Probe-Level Troubleshooting 6--28...................................

Troubleshoot the Logic Analyzer Module 6--29.............................

Equipment Required 6--29..........................................

Preparation 6--29..................................................

Calibration and Diagnostic Procedures 6--29............................

Fault Isolation Procedure 6--31......................................

Primary Troubleshooting Chart 6--32..................................

Diagnostics Table 6--33............................................

Adjustment After Repair 6--35..........................................

Updating or Restoring the Logic Analyzer Firmware 6--35...................

Overview of Procedures 6--37...........................................

Repackaging Instructions 6--39..................................

Packaging 6--39......................................................

Shipping to the Service Center 6--39......................................

Storage 6--40........................................................

Options

Electrical Parts List Diagrams Mechanical Parts List

TLA7AA1, TLA7AA2, TLA7AA3 and TLA7AA4 Options 7--1..............

TLA7AB2 and TLA7AB4 Options 7--2..................................

Service Options 7--2..................................................

Parts Ordering Information 10--1.........................................

Module Servicing 10--1............................................

Using the Replaceable Parts List 10--2....................................

Abbreviations 10--2...............................................

Mfr. Code to Manufacturer Cross Index 10--2...........................

TLA7AXX Logic Analyzer Module Service Manual

List of Figures

Table of Contents

Figure 1--1: Location of modules in merged configurations 1--11.......

Figure 2--1: Logical address switches 2--2..........................

Figure 2--2: Installing modules in the mainframe 2--3...............

Figure 2--3: MIC and PIC board identification 2--5.................

Figure 2--4: TLACAL2 performance verification and adjustment

test fixture 2--6............................................

Figure 2--5: Front panel of the logic analyzer module 2--9............

Figure 2--6: Merge connector (shown in the extended position) 2--10....

Figure 2--7: Rear panel controls and connectors 2--11................

Figure 2--8: Location of modules in a merged system 2--15............

Figure 2--9: Removing the merge connector assembly from the

module 2--16...............................................

Figure 2--10: Connecting the logic analyzer modules together 2--17.....

Figure 2--11: Installing the merged module set in the mainframe 2--18..

Figure 4--1: Calibration/certification procedure flow chart 4--2.......

Figure 4--2: Performance verification software startup window 4--5....

Figure 4--3: TLACAL2 test fixture connections 4--14.................

Figure 4--4: Default Verification d ialog box 4--17....................

Figure 4--5: Module+Probe timing procedure probe connections 4--25...

Figure 4--6: P6860 Setup & Hold procedure connections 4--28.........

Figure 4--7: Default Certification procedure dialog box 4--33..........

Figure 5--1: TLACAL2 test fixture connections 5--4.................

Figure 5--2: Performance verification software startup window 5--7....

Figure 5--3: Default Adjustment procedure dialog box 5-- 8...........

Figure 5--4: Deskew procedure probe connections 5--14...............

Figure 6--1: Cleaning the probe h eads 6--7.........................

Figure 6--2: Storing the probe head 6--8...........................

Figure 6--3: Injector/ejector handle replacement 6--10................

Figure 6--4: Removing the merge cable bracket from the cover 6--12....

Figure 6--5: Cover removal 6--13..................................

Figure 6--6: Installing the cover onto the chassis 6--14................

TLA7AXX Logic Analyzer Module Service Manual

Table of Contents

Figure 6--7: Seating the cover on the chassis 6--15....................

Figure 6--8: LPU board removal 6--17..............................

Figure 6--9: Inserting LPU board tabs into front subpanel 6--18........

Figure 6--10: Remove the single screw from the merge cable bracket 6--19

Figure 6--11: Removing the merge cable assembly 6--20...............

Figure 6--12: Removing the acquisition board from the chassis 6--21....

Figure 6--13: Rear EMI gasket removal 6--23........................

Figure 6--14: Rear EMI gasket replacement 6--24....................

Figure 6--15: Primary troubleshooting chart 6--32...................

Figure 9--1: Logic analyzer block diagram 9--2.....................

Figure 10--1: TLA7AAX and TLA7ABX Logic Analyzer Module

exploded view 10--4.........................................

TLA7AXX Logic Analyzer Module Service Manual

List of Tables

Table of Contents

Table 1--1: Input parameters (with probes) 1-- 3....................

Table 1--2: Analog output 1--3...................................

Table 1--3: Channel width and depth 1--4.........................

Table 1--4: Clocking 1 -- 4.......................................

Table 1--5: TLA7Axx module trigger system 1--8...................

Table 1--6: MagniVu acquisition 1--10.............................

T able 1--7: Merged modules 1--11................................

Table 1--8: Data handling 1--12...................................

Table 1--9: Environmental 1--12..................................

T able 1--10: Mechanical 1--13....................................

Table 1--11: TLA7Axx Logic Analyzer Module Certifications and

compliances 1--13..........................................

Table 1--12: TLACAL2 Performance verification and adjustment

fixture characteristics 1--14..................................

Table 1--13: TLACAL2 Performance verification and adjustment

fixture certifications and compliances 1--16.....................

Table 4--1: Test equipment 4 -- 3..................................

T able 4--2: Performance verification tests 4--11.....................

T able 4--3: TLA7Axx performance verification procedures 4--12.......

Table 4--4: Module+Probe Timing procedure probe connections 4--24..

T able 4--5: Logic analyzer certification test 4--30....................

Table 5--1: Logic analyzer adjustment procedures 5--3..............

Table 5--2: Deskew procedure probe connections 5--13...............

T able 5--3: Merged Deskew procedure probe connections 5--17........

T able 6--1: External inspection check list 6--3......................

T able 6--2: Internal inspection check list 6--4......................

Table 6--3: Tools required for circuit board replacement 6--9.........

Table 6--4: Failure symptoms and possible causes 6--27...............

Table 6--5: Diagnostic tests 6--33..................................

Table 6--6: Requirements after replacement 6--35....................

Table 6--7: Troubleshooting overview 6--37.........................

TLA7AXX Logic Analyzer Module Service Manual

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Table of Contents

Table 7--1: TLA7AA1, TLA7AA2, TLA7AA3 and TLA7AA4 options 7--1

Table 7--2: TLA7AB2 and TLA7AB4 options 7--2..................

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TLA7AXX Logic Analyzer Module Service Manual

General Safety Summary

Review the following safety precautions to avoid injury and prevent damage to this product or any products connected to it. To avoid potential hazards, use this product only as specified.

Only qualified personnel should perform service procedures.

While using this product, you may need to access other parts of the system. Read the General Safety Summary in other system manuals for warnings and cautions related to operating the system.

ToAvoidFireor

Personal Injury

Use Proper Power Cord. Use only the power cord specified for this product and certified for the country of use.

Use Proper Voltage Setting. Before applying power, ensure that the line selector is in the proper position for the power source being used.

Ground the Product. The TLACAL2 test fixture is grounded through the grounding conductor of the power cord. To avoid electric shock, the grounding conductor must be connected to earth ground. Before making connections to the input or output terminals of the fixture, ensure that the fixture is properly grounded.

Ground the Product. The logic analyzer modules are indirectly grounded through the grounding conductor of the mainframe power cord. To avoid electric shock, the grounding conductor must be connected to earth ground. Before making connections to the input or output terminals of the modules, ensure that the modules are properly grounded indirectly.

Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings and markings on the product. Consult the product manual for further ratings information before making connections to the product.

Do not apply a potential to any terminal, including the common terminal, that exceeds the maximum rating of that terminal.

Replace Batteries Properly. Replace batteries only with the proper type and rating specified.

Do Not Operate Without Covers. Do not operate this product with covers or panels removed.

Use Proper Fuse. Use only the fuse type and rating specified for this product.

Avoid Exposed Circuitry. Do not touch exposed connections and components

when power is present.

Do Not Operate With Suspected Failures. If you suspect there is damage to this product, have it inspected by qualified service personnel.

TLA7AXX Logic Analyzer Module Service Manual

General Safety Summary

Do Not Operate in Wet/Damp Conditions.

Do Not Operate in an Explosive Atmosphere.

Keep Product Surfaces Clean and Dry.

Provide Proper Ventilation. Refer to the manual’s installation instructions for

details on installing the product so it has proper ventilation.

Symbols and Terms

Terms in this Manual. These terms may appear in this manual:

WARNING. Warning statements identify conditions or practices that could result in injury or loss of life.

CAUTION. Caution statements identify conditions or practices that could result in damage to this product or other property.

Terms on the Product. These terms may appear on the product:

DANGER indicates an injury hazard immediately accessible as you read the marking.

WARNING indicates an injury hazard not immediately accessible as you read the marking.

CAUTION indicates a hazard to property including the product.

Symbols on the Product. The following symbol may appear on the product:

CAUTION

Refer to Manual

TLA7AXX Logic Analyzer Module Service Manual

Service Safety Summary

Only qualified personnel should perform service procedures. Read this Service Safety Summary and the General Safety Summary before performing any service

procedures.

Do Not Service Alone. Do not perform internal service or adjustments of this product unless another person capable of rendering first aid and resuscitation is present.

Disconnect Power. To avoid electric shock, switch off the instrument power, then disconnect the power cord from the mains power.

Use Care When Servicing With Power On. Dangerous voltages or currents may exist in this product. Disconnect power, remove battery (if applicable), and disconnect test leads before removing protective panels, soldering, or replacing components.

To avoid electric shock, do not touch exposed connections.

TLA7AXX Logic Analyzer Module Service Manual

Service Safety Summary

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TLA7AXX Logic Analyzer Module Service Manual

Preface

Manual Structure

This is the service manual for the TLA7Axx Series Logic Analyzer Module. Read this preface to learn how this manual is structured, what conventions it uses, and where you can find other information related to servicing this product. Read the Introduction, which follows this preface, for important background information needed before using this manual for servicing this product.

A brief description of each chapter of this service manual follows:

H Specifications contains a product description of the logic analyzer module

and tables of the characteristics and descriptions that apply to it.

H Operating Information includes basic installation and operating instructions

at the level needed to safely operate and service the logic analyzer module. For complete installation and configuration procedures, refer to the Tektronix Logic Analyzer Family User Manual.

H Theory of Operation contains circuit descriptions that support general service

to the circuit board level.

H Performance Verification contains the performance verification procedures

for the logic analyzer module and logic analyzer module probes.

H Adjustment Procedures contains the adjustment procedures for the logic

analyzer module.

H Maintenance contains information and procedures for doing preventive and

corrective maintenance on the logic analyzer module. Included are instructions for cleaning, for removal and installation of replacement parts, and for troubleshooting to the circuit board level.

H Options contains information on servicing any of the factory-installed

options that may be available for the logic analyzer module.

H Diagrams contains block diagrams and interconnection diagrams that are

useful when isolating failed circuit boards.

H Mechanical Parts List includes a table of all replaceable parts, their

descriptions, and their Tektronix part numbers.

TLA7AXX Logic Analyzer Module Service Manual

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Preface

Manual Conventions

This manual uses certain conventions that you should be familiar with before attempting service.

Acquisition Board

Adjustment Procedures

Adjustment/Verification

Fixture

Certification Procedures

Functional Verification

Procedures

The acquisition board is one of the circuit boards inside the logic analyzer module. The circuit board receives and stores acquisition data from the probes and works with the local processor unit (LPU) board to provide logic analysis information to the operator of the logic analyzer.

Adjustment procedures check for, and if necessary, correct any adjustment errors discovered when performing functional or performance verification procedures.

The adjustment verification fixture is a test fixture used to perform the adjustment, functional check, and performance verification procedures. This fixture is also known as the TLACAL2 fixture in this document. Specifications and replaceable parts information are documented in this service manual.

Certification procedures certify a product and provide a traceability path to national standards.

Functional verification procedures verify the basic functionality of the instrument. These procedures include power-on and extended diagnostics, self calibration, as well as semi-automated or manual check procedures. These procedures can be used as incoming inspection purposes. This manual provides information on power-on and extended diagnostics and the self calibration.

LPU Board

Maintenance Procedures

Modules

xiv

The LPU board is one of the circuit boards inside the logic analyzer module that provides the main communications interface with the acquisition board and the mainframe.

Maintenance procedures are used for fault isolation and repair to the circuit board level or to the replaceable part level.

Throughout this manual, the term “module” refers to a logic analyzer or digital oscilloscope, or pattern generator unit that mounts inside a mainframe. A module is composed of circuit boards, interconnecting cables, and a user-accessible front panel.

TLA7AXX Logic Analyzer Module Service Manual

Preface

P6810 General Purpose

Logic Analyzer Probe

P6880 Differential Probe

P6860 High Density Probe

Performance Verification

Procedures

This is a 34-channel general purpose probe used with the TLA7Axx series logic analyzers. It provides support for single-ended, differential clocks, and data with no trade-off in channels. It connects to a wide variety of probing accessories including SMT KlipChips for quick connections to a variety of IC pins and connectors.

This is a 34-channel differential probe used with the TLA7Axx series logic analyzers. This probe is designed for use with differential clocks and single-ended data. It uses a connector-less interface that use a compression contact which is mechanically reliable and minimizes impact on board layout and design. Adaptors are available to connect to Mictor probing interfaces.

This is a 34-channel high-density probe used with the TLA7Axx series logic analyzers. This probe is designed for use with differential clocks and data with no trade-offs in channels. It uses a connector-less interface that use a compression contact which is mechanically reliable and minimizes impact on board layout and design. Adaptors are available to connect to Mictor probing interfaces.

Performance verification procedures confirm that a product meets or exceeds the performance requirements for each of the published specifications.

Replaceable Parts

Safety

TLACAL2 Performance

Verification and

Adjustment Fixture

This manual refers to any field-replaceable assembly or mechanical part specifically by its name or generically as a replaceable part. In general, a replaceable part is any circuit board or assembly that is listed in the replaceable parts list near the end of this manual.

Symbols and terms related to safety appear in the Safety Summary found at the beginning of this manual.

This is a test fixture used with the performance verification procedures, adjustment procedures, and certification procedures described in this document. It is used with software to adjust, verify, and certify the P68xx probes and the TLA7Axx series logic analyzers.

TLA7AXX Logic Analyzer Module Service Manual

Preface

Related Manuals

The following manuals are available as part of the TLA700 Series Logic Analyzer documentation set.

Manual name Description Service use

Tektronix Logic Analyzer Family User Manual

TLA715 Portable Mainframe Service Manual

TLA721 Benchtop Mainframe and TLA7XM Expansion Mainframe Service Manual

TLA7Dx/TLA7Ex Digitizing Oscilloscope Service Manual

TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module Service Manual

TLA7Lx, & TLA7Mx Logic Analyzer Module Service Manual

TLA7PG2 Pattern Generator Service Manual

Provides operating information on the TLA Series Logic Analyzer

Provides service information for the portable mainframes

Provides service information for the benchtop mainframe and expansion mainframe

Provides service information for the digitizing oscilloscope modules

Provides service information for the TLA7Nx, TLA7Px, and TLA7Qx logic analyzer modules

Provides service information for the TLA7Lx, and TLA7Mx logic analyzer modules

Provides service information for the TLA7PG2 pattern generator modules

Augments operating information found in chapter 2 of this manual

Isolating and correcting failures in the portable mainframe

Isolating and correcting failures in the benchtop mainframe, controller, or expansion mainframe

Isolating and correcting failures in the DSO module. Provides adjustment procedures, performance verification procedures, and certification procedures for the DSO modules

Isolating and correcting failures in the logic analyzer module. Provides adjustment procedures, performance verification procedures, and certification procedures for the logic analyzer modules and logic analyzer probes

Isolating and correcting failures in the pattern generator module. Provides adjustment procedures and performance verification procedures for the pattern generator modules and probes

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TLA7AXX Logic Analyzer Module Service Manual

Contacting Tektronix

Preface

Phone 1-800-833-9200*

Address Tektronix, Inc.

Department or name (if known) 14200 SW Karl Braun Drive P.O. Box 500 Beaverton, OR 97077 USA

Web site www.tektronix.com

Sales support 1-800-833-9200, select option 1*

Service sup-

port

Technical sup-

port

* This phone number is toll free in North America. After office hours, please leave a

voice mail message. Outside North America, contact a Tektronix sales office or distributor; see the Tektronix web site for a list of offices.

1-800-833-9200, select option 2*

Email: techsupport@tektronix.com

1-800-833-9200, select option 3*

6:00 a.m. -- 5:00 p.m. Pacific time

TLA7AXX Logic Analyzer Module Service Manual

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Preface

xviii

TLA7AXX Logic Analyzer Module Service Manual

Introduction

This manual contains information needed to properly service the logic analyzer module, as well as general information critical to safe servicing.

To prevent personal injury or damage consider the following requirements before attempting service:

H The procedures in this manual should be performed only by qualified service

personnel.

H Read the General Safety Summary and Service Safety Summary found at the

beginning of this manual.

When using this manual for servicing follow all warnings and cautions.

Adjustment and Certification Interval

Generally, you should perform the adjustments and certification (calibration) described in the Performance Verification and Adjustment Procedures chapters in this manual once per year, or following repairs that affect adjustment or calibration.

Strategy for Servicing

This manual contains information for corrective maintenance of this product:

H Supports isolation of faults to the failed circuit board or assembly level

shown in the replaceable parts list

H Supports removal and replacement of those boards or assemblies

H Supports removal and replacement of fuses, knobs, chassis, and other

mechanical parts listed in the replaceable parts list

This manual does not support component-level fault isolation and replacement.

TLA7AXX Logic Analyzer Module Service Manual

xix

Introduction

Service Offerings

Tektronix provides service to cover repair under warranty as well as other services that are designed to meet your specific service needs.

Whether providing warranty repair service or any of the other services listed below, Tektronix service technicians are well equipped to service the logic analyzer module.

Warranty Repair Service

Calibration and Repair

Service

Service Options

Service Agreements

Tektronix warrants this product for one year from date of purchase. (The warranty appears behind the title page in this manual.) Tektronix technicians provide warranty service at most Tektronix service locations worldwide. The Tektronix product catalog lists all service locations worldwide or you can visit us on our web site at http://www.tektronix.com/Measurement/Service. See our latest service offerings and contact us by email.

In addition to warranty repair, Tektronix Service offers calibration and other services that provide cost-effective solutions to your service needs and qualitystandards compliance requirements. Our instruments are supported worldwide by the leading-edge design, manufacturing, and service resources of Tektronix to provide the best possible service.

The following services can be tailored to fit your requirements for calibration and/or repair of the logic analyzer module.

Tektronix Service Options can be selected at the time you purchase your instrument. You select these options to provide the services that best meet your service needs.

If service options are not added to the instrument purchase, then service agreements are available on an annual basis to provide calibration services or post-warranty repair coverage for the logic analyzer module. Service agreements may be customized to meet special turn-around time and/or on-site requirements.

Service On Demand

Self Service

Tektronix also offers calibration and repair services on a “per-incident” basis that is available with standard prices for many products.

Tektronix supports repair to the replaceable-part level by providing for circuit board exchange. Use this service to reduce down-time for repair by exchanging circuit boards for remanufactured ones. Tektronix ships updated and tested exchange boards. Each board comes with a 90-day service warranty.

TLA7AXX Logic Analyzer Module Service Manual

Introduction

When you exchange circuit boards, you must supply the following information to allow the board to be preconfigured to the proper PowerFlex level. You can also return the repaired module to your local service center for configuration.

H Model number and serial number

H PowerFlex option upgrade number

H Firmware level

For More Information

Contact your local Tektronix service center or sales engineer for more information on any of the Calibration and Repair Services just described.

TLA7AXX Logic Analyzer Module Service Manual

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Introduction

xxii

TLA7AXX Logic Analyzer Module Service Manual

Specifications

This chapter provides a general description of the TLA7Axx series logic analyzer modules and the TLACAL2 Performance Verification and Adjustment test fixture. This chapter also includes a list of specifications for the logic analyzer module and for the test fixture under Characteristic Tables beginning on page 1--2.

Logic Analyzer Module Description

The TLA7Axx series logic analyzer modules are designed as part of the Tektronix Logic Analyzer Family for use in the TLA700 series logic analyzer mainframes. The logic analyzer module is used as a test and measurement tool for high-speed digital timing and state acquisition across several channels with deep acquisition memory.

Some of the key features of the logic analyzer modules include the following:

H Up to 128 data channels and 8 stored clock or qualifier channels per module

H Ability to merge five modules to provide up to 680 data channels with full

clocking and triggering capabilities across all modules

H Software configurable channels, memory depth, and user synchronous speed

(PowerFlex)

H Data correlation with other Tektronix logic analyzer modules in a TLA

mainframe

H Enhanced clocking to minimize skew between the data bus and the system

clock

H Four analog output connectors that send the analog signal of any channel to

an oscilloscope or other modules without requiring additional probe connections

The logic analyzer acquires data from the target systems through the P68xx series logic analyzer probes. The following probes are supported:

H P6810 General Purpose Logic Analyzer Probes with flying lead sets. These

probes are designed for most general purpose logic analyzer applications.

H P686x High-Density Logic Analyzer Probes. These probes feature a

connectorless system that connect directly to the target system; no adaptors or connectors are required.

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Specifications

H P6880 High Density Differential Logic Analyzer Probes. These probes also

feature a connectorless system for differential signals.

Refer to the P68xx Logic Analyzer Probe Instruction Manual for complete information on the P68xx series logic analyzer probes. This document also contains circuit board design information required for designing the probe interfaces for the target system.

TLACAL2 Performance Verification and Adjustment Test Fixture Description

The TLACAL2 Performance Verification and Adjustment test fixture is designed to be used with the TLA7Axx series logic analyzer modules and probes for performance verification procedures, certification procedures, and adjustment procedures. These procedures are documented in the Performance Verification and Adjustment Procedures chapters of this manual.

Characteristic Tables

All specifications listed in this section are guaranteed unless noted Typical. Specification that are marked with the n symbol are checked either directly or indirectly in the Performance Verification chapter of this manual. The specifica- tions apply to all variations of the TLA7Axx series logic analyzer module unless otherwise noted.

This section also includes specifications for the performance verification test fixture.

The performance limits under these specifications are valid under the following conditions:

H The logic analyzer modules must have been calibrated (adjusted) at an

ambient temperature between +20 °C and +30 °C.

H The logic analyzer modules must be in an environment with temperature,

altitude, humidity, and vibration within the operating limits described in

these specifications.

H The logic analyzer must have had a warm-up period of at least 30 minutes.

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TLA7AXX Logic Analyzer Module Service Manual

Table 1- 1: Input parameters (with probes)

Characteristic Description

Specifications

n Threshold accuracy

±(35 mV + 1% of the threshold voltage setting)

(Certifiable parameter)

Threshold range and step size Setable from +4.5 V to --2.0 V in 5 mV steps

Threshold channel selection 16 threshold groups assigned to channels. Each probe has four threshold settings,

one for each of the clock/qualifier channels and one per group of 16 data channels.

n Channel to channel skew ≤400 ps

Channel to channel skew (Typical) ≤300 ps

Sample uncertainty

Asynchronous Sample period

Synchronous 125 ps

Minimum slew rate (Typical) 0.2 V/ns

Input voltage range -- 2 . 5 V t o + 5 V

Maximum operating voltage swing 6.0 V peak-to-peak

Probe overdrive

Single ended probes ±150 mV or ±25% of signal swing minimum required beyond threshold, whichever

one is greater

Differential probes V

pos

-- V

neg

is ≥ 150mV

p-p

Maximum nondestructive input signal to probe ±15 V

Minimum input pulse width (single channel) (Typical)

P6860 and P6880 probes 500 ps

P6810 probes 750 ps

Delay time from probe tip to input probe

For P6880 High Density Probe: 7.7 ns ±60 ps

connector (Typical)

Table 1- 2: Analog output

Characteristic Description

Number of outputs Four analog outputs regardless of the module channel width. Any four of the module’s

channels can be mapped to the four Analog outputs.

Attenuation 10X mode for normal operation

5X mode for small signals (--1.5 V to +2.5 V)

Bandwidth (Typical) 2GHz

Accuracy (gain and offset)

±(50 mV + 2% of signal amplitude)

(Typical)

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Specifications

lockcha

ProductC

lockcha

lavec

lockcha

ProductC

lockcha

(

Table 1- 3: Channel width and depth

Characteristic Description

Number of channels

TLA7AA4, TLA7AB4 128 data, 8 clock/qualifier

TLA7AA3 96 data, 6 clock/qualifier

TLA7AA2, TLA7AB2 64 data, 4 clock/qualifier

TLA7AA1 32 data, 2 clock/qualifier

Acquisition memory depth

TLA7AAx series 32 M per channel

TLA7ABx series 64 M per channel

Table 1- 4: Clocking

Characteristic Description

Asynchronous clocking

n Internal sampling period 500 ps to 50 ms in a 1--2--5 sequence. Storage control can be used to only store data

when it has changed (transitional storage)

2 ns minimum for all channels 1 ns minimum for half channels (using 2:1 Demul tiplex mode)

0.5 ns minimum for quarter channels (using 4:1 Demultiplex mode)

n Minimum recognizable word

(across all channels)

Channel-to-channel skew + sample uncertainty

Example for a P6860 high-density probe anda2nssampleperiod: 400 ps + 2 ns = 2.4 ns

Synchronous clocking

ster

nnels

32+2 module 2

64+4 module 4

96+6 module 4

128+8 module 4

ergeds

(64+4 channel modules and 32+2 channel modules

nnot be merged.)

nnels

96+6 module 4

128+8 module 4

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TLA7AXX Logic Analyzer Module Service Manual

Table 1- 4: Clocking (Cont.)

Qualifiercha

ProductQualifiercha

Characteristic Description

Specifications

nnels

32+2 module 0

64+4 module 0

96+6 module 2

128+8 module 4

n Setup and hold window size

P686x high density probe = 750 ps

(data and qualifiers)

Setup and hold window size

P686x high density probe = 625 ps

(data and qualifiers) (Typical)

Setup and hold window range The setup and hold window can be moved for each channel group from +8.0 ns (T

typical) to --8.0 ns (Tstypical) in 0.125 ns steps (setup time).

The setup and hold window can be shifted toward the setup region by 0 ns, 4 ns, or 8ns.Witha0nsshift,therange is +8 ns to --8 ns; witha4nsshift,therange is +12 ns to --4 ns; with an 8 ns shift, the range is +16 ns to 0 ns. The sample point selection region is the same setup and hold window. Setup times are specified as typical figures. Hold time follows the setup time by the setup and hold window size.

Sample point selection window range The setup and hold window can be moved for each channel group from +8.0 ns to

--8.0 ns in 0.125 ns steps.

This window can be shifted toward the positive region by 0 ns, 4 ns, or 8 ns. With a 0 ns shift, the range is +8 ns to --8 ns; witha4nsshift,therange is +12 ns to --4 ns; with an 8 ns shift, the range is +16 ns to 0 ns. The sample point selection region is the same setup and hold window.

n Maximum synchronous clock rate 450 MHz in full-speed mode (2.2 ns minimum between active clock edges)

235 MHz in half-speed mode (4.25 ns minimum between active clock edges)

120 MHz in quarter-speed mode (8.3 ns minimum between active clock edges)

800 MHz on half channels

Software controls the selection between full-speed and half-speed modes.

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Specifications

TLA7AA3,TLA7AA4,TLA7AB4modul

Table 1- 4: Clocking (Cont.)

Characteristic Description

Demultiplex clocking (two clock edges required)

Demultiplex channels (2:1)

TLA7AA3, TLA7AA4, TLA7AB4 modules

TLA7AA1, TLA7AA2, TLA7AB2 modules Any individual channel can be demultiplexed with its partner channel. If multiplexi ng is

Demultiplex channels (4:1)

TLA7AA1, TLA7AA2, TLA7AB2 modules Unlike the 2:1 Demultiplex, the channels within a group of four cannot arbitrarily drive

Time between Demultiplex clock edges (Typical)

Source synchronous clocking

Clocks per module Four

Clocks with merged modules When merged, the slave modules have two clocks available from the master module.

Clock groups Four for a single module and for a merged system

Size of clock group valid FIFO Four stages; this allows four (source synchronous or other) clocks to occur before the

Source synchronous clock alignment window Channel-to-channel skew only

Any individual channel can be demultiplexed with its partner channel. If multiplexi ng is enabled, all of the A and D channels are multiplexed; there is no individual selection. Channels demultiplex as follows:

A3(7:0) to/from D3(7:0)

A2(7:0) to/from D2(7:0)

A1(7:0) to/from D1(7:0)

A0(7:0) to/from D0(7:0)

enabled, all of the A and D channels are multiplexed; there is no individual selection. Channels demultiplex as follows:

A3(7:0) to/from C3(7:0)

A2(7:0) to/from C2(7:0)

A1(7:0) to/from D1(7:0) 64+4 modules only

A0(7:0) to/from D0(7:0) 64+4 modules only

Unlike the 2:1 Demultiplex, the channels within a group of four cannot arbitrarily drive the others.

E3(7:0) to E2(7:0), E1(7:0), E0(7:0) 128+8 modules only

A3(7:0) to A2(7:0), D3(7:0), D2(7:0)

A1(7:0) to A0(7:0), D1(7:0), D0(7:0)

C3(7:0) to C2(7:0), C1(7:0), C0(7:0)

CK3 to CK2, Q3, Q2 128+8 modules only

CK1 to CK0, Q1, Q0

the others.

A1(7:0) to A0(7:0), D1(7:0), D0(7:0) 64+4 modules only

C3(7:0) to C2(7:0), A3(7:0), A2(7:0)

Same limitations as normal synchronous acquisition

Including the local clocks, the total is six clocks.

clock that completes the Clock Group Valid signal for that group

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Specifications

Table 1- 4: Clocking (Cont.)

Characteristic Description

Source synchronous clock reset The Clock Group Valid FIFO can be reset in one of the two ways:

1. By the overflow of a presettable (1--255) 8-bit counter that counts one of the following clocks: 2 ns Clock or the master “heartbeat” clock (synchronous or asynchronous). An active edge places the reset count to its preset value. An active clock edge will clear the Clock Group Valid reset before the clock gets to the FIFO so that no data is lost.

2. By enabling an external reset. In this mode, one of the clock channels must be traded on the master module to act as a level-sensitive reset input. Any one of the clocks can be selected. A polarity selection is available. This mode affects all Clock Group Complete circuits.

Neither one of the above modes can be intermixed; one or the other must be selected.

Clocking state machine

Pipeline delays Channel groups can be programmed with a pipeline delay of 0 through 7 active clock

changes.

Specification only applies with asynchronous (internal) clocking. With synchronous clocking, the setup and hold window size applies.

Any or all clock channels can be enabled. For an enabled clock channel, either the rising, falling, or both edges can be selected as active clock edges. Clock channels are stored.

Qualifier channels are stored.

This is a special mode and has some limitations such as the clocking state machine and trigger state machine only running at 500 MHz.

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Specifications

Table 1- 5: TLA7Axx module trigger system

Characteristic Description

Trigger resources

Word recognizers and range recognizers 16, word recognizers can be combined to form full width, double bounded range

recognizers. The following selections are available:

16 word recognizers 0 range recognizers 13 word recognizers 1 range recognizer 10 word recognizers 2 range recognizers 7 word recognizers 3 range recognizers 4 word recognizers 4 range recognizers

Range recognizer channel order From most-significant probe group to least-significant probe group:

C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 Ck1 CK0

Missing channels for modules with fewer than 136 channels are omitted. When merged, the range recognition extends across the modules. The master module contains the most-significant groups.

Glitch detector (normal asynchronous clock mode)

Minimum detectable glitch pulse width (Typical)

Setup and hold violation detector (normal asynchronous clock mode)

Channel groups can be enabled to detect glitches.

Glitches are subject to pulse width variations of up to ±125 ps

Minimum input pulse width (single channel) P6860 high density probe: 500 ps P6880 differential probe: 500 ps P6810 general purpose probe: 750 ps

Any channel group can be enabled to detect a setup or hold violation. The range is from 8.0 ns before the clock edge to 8.0 ns after the clock edge in 0.125 ns steps. The channel setup and hold violation size can be individually programmed.

The range can be shifted towards the positive region by 0 ns, 4 ns, or 8 ns. W ith a 0 ns shift, the range is +8 ns to --8 ns; witha4nsshift,therange is +12 ns to --4 ns; with an 8 ns shift, the range is +16 ns to 0 ns. The sample point selection region is the same as the setup and hold window.

Any setup value is subject to variation of up to the channel skew specification. Any hold value is subject to variation of up to the channel skew specification.

Transition detector 16 transition detectors.

Any channel group can be enabled or disabled to detect a rising transition, a falling transition, or both rising and falling transitions between the current valid data sample and the previous valid data sample.

Counter/timers 2 counter/timers, 51 bits wide, can be cl ocked up to 500 MHz

Maximum count is 2 Maximum time is 4.5 × 106seconds or 52 days

Counters can be used as setable, resetable, and testable flags. Counters can be reset, do nothing, incremented, or decremented. Timers can be reset, started, stopped, or not changed. Counters and timers have zero reset latency and one clock terminal count latency.

Signal In 1 A backplane input signal.

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Specifications

Table 1- 5: TLA7Axx module trigger system (Cont.)

Characteristic Description

Signal In 2 A backplane input signal.

Trigger In A backplane input signal that causes the main acquisition and the MagniVu

acquisition to trigger if they are not already triggered.

Active trigger resources 16 maximum (excluding counter/timers)

Word recognizers are traded off one-for-one as Signal In 1, Signal In 2, glitch detection, setup and hold detection, or transition detection resources are added.

Trigger states 16

n Trigger state sequence rate Same rate as valid data samples received. 500 MHz maximum.

Trigger machine actions

Main acquisition trigger Triggers the main acquisition memory

Main trigger position Programmable to any data sample (2 ns boundaries)

MagniVu trigger Main acquisition machine controls the triggering of the MagniVu memory

MagniVu trigger position Programmable within 2 ns boundaries and separate from the main acquisition

memory trigger position

Increment/decrement counter Counter/timers used as counters can be incremented or decremented.

Start/stop timer Either of the two counter/timers used as timers can be started or stopped.

Reset counter/timer Either of the two counter/timers can be reset.

When a counter/timer used as a timer is reset, the timer continues in the started or stopped state that it was prior to the reset.

Reloadable word recognizer (snapshot) Loads the current acquired data sample into the reference value of the word

recognizer via a trigger machine action. All data channels are loaded into their respective word recognizer reference register on a one-to-one manner.

Reloadable word recognizer latency 378 ns

Signal Out A signal sent to the backplane to be used by other modules

Trigger Out A signal sent to the backplane to trigger other modules

Storage control

Storage Storage is allowed only if a specific condition is met. The condition can use any of the

trigger resources except for counter/timers. Storage commands defined in the current trigger state will override the global storage control.

Storage can be used to start the acquisition with storage initially turned on (default setting) or off.

By event Storage can be turned on or off; only the current sample can be stored. Event storage

control overrides any global storage commands.

Block storage (store stretch) When enabled, 31 samples are stored before and after the valid sample.

This allows the storage of a group of samples around a valid data sample when storage control is being used. This only has meaning when storage control is used. Block storage is disallowed when glitch storage or setup and hold violation storage is enabled.

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Specifications

Table 1- 5: TLA7Axx module trigger system (Cont.)

Characteristic Description

Glitch violation storage Glitch violation information can be stored to acquisition memory with each data

sample when asynchronous clocking is used. The acquisition data storage size is reduced by half when this mode is enabled (the other half holds violation information). The fastest asynchronous clock rate is reduced to 4 ns.

Setup and hold violation storage Setup and hold violation information can be stored to acquisition memory with each

data sample when synchronous clocking is used. The acquisition data storage size is reduced by half when this mode is enabled (the other half holds violation information). The maximum synchronous clock rate in this mode is 235 MHz.

Table 1- 6: MagniVu acquisition

Characteristic Description

MagniVu sampling period Data is asynchronously sampled and stored every 125 ps in a separate MagniVu

(high-resolution) memory. The storage speed can be changed by software to 250 ps, 500 ps, or 1000 ps with no loss in memory depth so that the high resolution memory covers more time at a higher resolution.

MagniVu memory depth Approximately 16 K per channel. The MagniVu memory is separate from the main

acquisition memory.

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TLA7AXX Logic Analyzer Module Service Manual

Specifications

Table 1- 7: Merged modules

Characteristic Description

Number of merged modules 2, 3, 4, or 5 adjacent modules can be merged. Only 102-channel modules or

136-channel modules can be merged. Merged modules can have unequal channel widths and channel depths.

See Figure 1--1 for location of modules in a merged configuration.

Number of channels after merging The sum of all channels available on each of the merged modul es incl uding clocks

and qualifiers. No channels are lost when modules are merged.

Merged system acquisition depth Channel depth is equal to that of the shallowest module.

Number of clock and qualifier channels after merging

Merged system trigger resources The same as a single module except for word recognizer width, setup and hold

Merged range significance Most significant Master, Slave 1, Slave 2

The qualifier channels on the slave modules can only be used as data channels. They cannot influence the actual clocking function of the logic analyzer (for example, l og strobe generation).

The clock channels on the slave TLA7Axx modules can capture data on those modules for source-synchronous applications. Each slave module contributes four additional clock channels to the merged set. All clock and qualifier channels are stored to acquisition memory.

violation detector width, glitch detector width, and transition detector width has increased to equal that of the merged channel width. Range recognizers will increase to the merged channel width up to three modules; range recognition is not supported on the two outside slave modules.

S L A V E 4

Figure 1- 1: Location of modules in merged configurations

TLA7AXX Logic Analyzer Module Service Manual

S L A V E 2

M A S T E R

S L A V E 1

S L A V E 3

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Specifications

Table 1- 8: Data handling

Characteristic Description

Nonvolatile memory retention time (Typical) The battery life is integral to the NVRAM; battery life is > 10 years.

Table 1- 9: Environmental

Characteristic Description

Temperature

Operating 5 _Cto+40 _C/hour maximum gradient, non-condensing

The maximum operating temperature is derated at altitudes above 305 m (1000 ft.) by 1 _C per 305 m (1000 ft.) above 1525 m (5000 ft.) altitude

Non-operating --20 _Cto+60 _Cwith15 _C/hour maximum gradient, without disk media

installed in disk drives.

Humidity

Operating (No media in floppy or CD in mainframe drive):

20% to 80% relative humidity, noncondensing, maximum wet-bulb temperature of +29 _C (derates relative humidity to 45% at 40 _C)

Non-operating (No media in floppy or CD in mainframe drive):

8% to 80% relative humidity, non-condensing, maxi mum wet-bulb temperature of +29 _C (derates relative humidity to 22% relative humidity at 50 _C)

Altitude

Operating To 3048 m (10,000 ft.) provide maximum ambient temperature is derated by 1 _C per

305 m (1000 ft.) above 1525m (5000 ft.)

Non-operating 12192 m (40,000 ft.)

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Specifications

Table 1- 10: Mechanical

Characteristic Description

Material Chassis parts are constructed of aluminum alloy. The front panel is constructed of

plastic laminated to steel front panel. Circuit boards are c onstructed of glass laminate.

Weight

136-channel module 2.438 kg (5 lb 6 oz.)

102-channel module 2.381 kg (5 lb 4 oz.)

68-channel module 2.282 kg (5 lb 0.5 oz.)

34-channel module 2.254 kg (4 lb 15.5 oz.)

Shipping weight 3.515 kg (7 lb 12 oz.) for 136-channel module when packaged for domestic shipment

Overall dimensions

Height 262 mm (10.32 in)

Width 61 mm (2.39 in) with merge connector in the recessed position

Width increases by 10.41 mm (0.41 in) with merge connector in the extended position

Length 373 mm (14.7 in)

Mainframe interlock 1.4 ECL keying is implemented

Table 1- 11: TLA7Axx Logic Analyzer Module Certifications and compliances

Category Standards or description

EC Declaration of Conformity -EMC

Emissions which exceed the levels required by this standard may occur when this equipment is connected to a test object.

Meets intent of Directive 89/336/EEC for Electromagnetic Compatibility. Compliance was demonstrated to the following specifications as listed in the Official Journal of the European Communities:

EN 61326 EMC requirements for Class A electrical equipment for

measurement, control and laboratory use.

IEC 61000--4--2 Electrostatic discharge immunity (Performance criterion B) IEC 61000--4--3 RF electromagnetic field immunity (Performance criterion A) IEC 61000--4--4 Electrical fast transient / burst immunity (Performance criterion B) IEC 61000--4--5 Power line surge i mmunity (Performance criterion B) IEC 61000--4--6 Conducted RF immunity (Performance criterion A) IEC 61000--4--11 Voltage dips and interruptions immunity (Performance criterion B)

EN 61000--3--2 AC power line harmonic emissions

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Specifications

Table 1- 12: TLACAL2 Performance verification and adjustment fixture characteristics

Characteristic Description

Input channels One external clock input

Input voltage < 1 V referenced to ground, 50 Ω termination

P6860 deskew and minimum pulse timing outputs

P6860-setup and hold outputs 136 grouped into eight 17-channel connectors

P6880 deskew and minimum pulse timing outputs

P6860/80 gain and offset outputs 68 grouped into four 17-channel connectors

P6810 gain and offset outputs 34 grouped into four 8-channel connectors and one 2-channel connector for the clocks

Analog output SMB inputs Four inputs with 50 Ω termination each

DMM test points One connection to a GPIB-controlled digital voltmeter

Number of module interface connector (MIC) boards connected at one time

Number of Probe interface connector (PIC) boards connected at one time

Timing section output amplitude 100E Motorola ECLinPS family outputs referenced to +2 V amplitude

Gain/Offset output voltage range -- 5 V t o + 5 V

MIC board test current range ¦3mA

Interface ports

RS-232 9-pin RS-232 serial communications interface

JTAG Programming interface for the xilinx CPLD

Power distribution system

Power consumption 40 W maximum

Source voltage and frequency 100 V

Fuse ratings

34 + 5 grouped into three P6860 connectors, two with 17 channels and one with five channels

Four. Each board requires a ribbon cable and two MCX cable attachments to the main board

One. The board must be connected to the ribbon connector labeled PIC.

115 V

to 240 V

RMS

±10%, 400 Hz, continuous range CAT II

RMS

±10%, 50 Hz to 60 Hz continuous range CAT II

RMS

1- 14

100 V to 120 V operation

200 V to 240 V operation

Internal power supply

5.0 mm x 20 mm, 1.0 A FAST 250 V; Tektronix part number 159-0356-00

5.0 mm x 20 mm, 0.5 A FAST 250 V; Tektronix part number 159-0351-00

5.0 mm x 20 mm, 3.15 A, 250 V

TLA7AXX Logic Analyzer Module Service Manual

Specifications

Table 1- 12: TLACAL2 Performance verification and adjustment fixture characteristics (Cont.)

Characteristic Description

Secondary power supply output voltages

+15 V +10%, --3%

-- 1 5 V ¦5%

+12 V ¦10%

+5 V ¦2%

+3 V ¦100 mV

-- 3 V ¦100 mV

+2 V ¦100 mV

Secondary power supply output voltage ripple

¦3V <50mV

+2 V <50mV

Cooling clearance 51 mm (2 in) front, sides, and rear. Prevent blockage of airflow to bottom of

instrument by placing on a solid, noncompresable surface.

Atmospherics

Temperature

Operating 20 °Cto30°C

Non-operating +5 °Cto+50°Cwith15°C gradient per hour noncondensing

Humidity

Operating 20% to 80% relative humidity, noncondensing

Non-operating 8% to 80% relative humidity, noncondensing and as limited by a maximum wet bulb

temperature of +40 °C

Altitude

Operating To 3048 m (10,000 ft.)

Non-operating To 12192 m (40,000 ft.)

Mechanical shock 30 Gs maximum

with respect to ground

P-P

with respect to ground

P-P

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Specifications

gyp

Table 1- 13: TLACAL2 Performance verification and adjustment fixture certifications and compliances

Category Standards or description

EC Declaration of Conformity -Low Voltage

U.S. Nationally Recognized Testing Laboratory Listing

Canadian Certification CAN/CSA C22.2 No. 1010.1 Safety requirements for electrical equipment for measurement,

Additional Compliance IEC61010-1/A2:1995 Safety requirements for electrical equipment for measurement,

Installation (Overvoltage) Category Descriptions

Pollution Degree Descriptions A measure of the contaminates that could occur in the environment around and within a product.

Equipment Type Test and measuring

Safety Class Class 1 (as defined in IEC 61010-1, Annex H) -- grounded product

Overvoltage Category Overvoltage Category II (as defined in IEC 61010-1, Annex J)

Pollution Degree Pollution Degree 2 (as defined in IEC 61010-1). Note: Rated for indoor use only.

Compliance was demonstrated to the following specification as listed in the Official Journal of the European Communities:

Low Voltage Directive 73/23/EEC, amended by 93/68/EEC

EN 61010-1/A2:1995 Safety requirements for electrical equipment for measurement

control and laboratory use.

UL3111-1 Standard for electrical measuring and test equipment.

control, and laboratory use.

Terminals on this product may have different installation (overvoltage) category designations. The installation categories are:

CAT III Distribution-level mains (usually permanently connected). Equipment at this level is

typically in a fixed industrial location.

CAT II Local-level mains (wall sockets). Equipment at this level includes appliances, portable

tools, and similar products. Equipment is usually cord-connected.

CAT I Secondary (signal level) or battery operated circuits of electronic equipment.

Typically the internal environment inside a product is considered to be the same as the external. Products should be used only in the environment for which they are rated.

Pollution Degree 1 No pollution or only dry, nonconductive pollution occurs. Products in

this category are generally encapsulated, hermetically sealed, or located in clean rooms.

Pollution Degree 2 Normally only dry, nonconductive pollution occurs. Occasionally a

temporary conductivity that is caused by condensation must be expected. This location is a typical office/home environment. Temporary condensation occurs only when the product is out of service.

Pollution Degree 3 Conductive pollution, or dry, nonconductive pollution that becomes

conductive due to condensation. These are sheltered locations where neither temperature nor humidity is controlled. The area is protected from direct sunshine, rain, or direct wind.

Pollution Degree 4 Pollution that generates persistent conductivity through conductive

dust, rain, or snow. Typical outdoor locations.

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TLA7AXX Logic Analyzer Module Service Manual

Operating Information

This chapter provides a high-level overview of installation instructions and operating information for the logic analyzer module. The operating information is limited to the functions you need to perform the procedures found in this document. You can find detailed operating instructions in the Tektronix Logic Analyzer Family User Manual and in the online help.

Installation

The Tektronix Logic Analyzer User Manual provides detailed installation instructions for the logic analyzer module and the mainframes. This section contains a summary of those installation procedures. This section also describes the installation procedures for the TLACAL2 Performance Verification and Adjustment fixture; this fixture is required for the TLA7Axx series logic analyzer module performance verification procedures, certification procedures, and adjustment procedures.

Logical Address

Every plug-in module in the logic analyzer must have a unique logical address; no two modules can have the same address. Two rotary switches on rear panel select the logical address (see Figure 2--1 for the switch locations). When servicing the logic analyzer module, you should have no need for changing the address. However, in most cases the switches should be set to FF, the factory default setting to enable dynamic auto configuration.

NOTE. Do not set the logic analyzer module logical address to 00. Logical address 00 is reserved for the controller.

Dynamic Autoconfiguration With Dynamic Auto Configuration (recommended) selected (hexadecimal FF or decimal 255), the logic analyzer automatically sets the address to an unused value. For example, if there are modules set to addresses 01 and 02 already in your system, the resource manager will automatically assign the logic analyzer module an address other than 01 or 02.

Static Logical Address Static logical address selections set the address to a fixed value. A static logical address ensures that the logic analyzer module address remains fixed for compatibility with modules that require a specific address value. Remember that each module within the logic analyzer must have a unique address to avoid communication problems.

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Operating Information

Least-significant

digit

Most-significant

digit

Merged Modules

Module Installation

Figure 2- 1: Logical address switches

You can combine up to five logic analyzer modules to create a single module that operates off a single time base. This process is called merging modules. The procedures for merging modules is described under Merged Modules beginning on page 2--14.

Install the modules in a mainframe before applying power to the mainframe. Before installing the modules, determine if you want to merge the modules. You must physically connect the module together before installing them in the mainframe.

Slide the module all of the way into the mainframe. Use the injector/ejector handles to seat the module and then hold the modules in place by tightening the retaining screws (see Figure 2--2 on page 2--3). If you are installing merged modules, slide them into the mainframe as a group and then seat them in place individually.

2- 2

TLA7AXX Logic Analyzer Module Service Manual

Operating Information

For more detailed information on installing modules, refer to Appendix D:

TLA700 Module Installation in the Tektronix Logic Analyzer Family User Manual.

Portable mainframe Benchtop mainframe

TLACAL2 Fixture

Installation

Retaining screws

Injector/ejector handles

Figure 2- 2: Installing modules in t he mainframe

The TLACAL2 Performance V erification and Adjustment test fixture is required to perform the performance verification procedures, certification procedures, and adjustment procedures. If you will not be running the performance verification or adjustment procedures, you can skip this section.

You will need to connect the TLACAL2 fixture to the logic analyzer and associated test equipment before running procedures. A complete list of test equipment is listed in Table 4--1 on page 4--3.

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Operating Information

CAUTION. Static discharge can damage the TLACAL2 fixture and its associated circuit boards. Make sure that you install the fixture in a static-free environment. Always wear a grounded wrist strap while handling the TLACAL2 fixture and its associated equipment. For more information on antistatic procedures, see

Preventing Electrostatic Discharge on page 6--1.

Due to the short cable lengths, you must decide upon a location for the TLACAL2 fixture that allows you to connect the test fixture to the logic analyzer module under test (less than two feet). The fixture can be placed on top of a benchtop mainframe or on a static free work surface adjacent to the logic analyzer.

The following steps assume that you have all the required test equipment necessary to run the performance verification procedures, certification procedures, and adjustment procedures. See Table 4--1 on page 4--3 for a complete list of test equipment.

1. If you have not already done so, power down the mainframe and install the

logic analyzer module.

2. Connect the RS-232 cable from the COM A connector of the logic analyzer

mainframe to the RS-232 connector on the performance verification fixture.

NOTE. When using GPIB, make sure that you select unique GPIB addresses on the individual instruments to avoid conflicts.

3. Connect the GPIB cable from the digital multimeter to the oscilloscope.

4. Connect the iView cable from the USB connector on the logic analyzer

mainframe to the GPIB connector on the DMM.

NOTE. Steps 5 and 6 assume that you will be connecting the TLACAL2 fixture to a 136-channel logic analyzer module. You only need to connect one MIC board and one ribbon cable per 34 channels on the logic analyzer module. If your logic analyzer module has less than 136 channels, you can reduce clutter by only connecting the cables that you need for your instrument configuration.

5. Connect one end of the ribbon cables to the MIC 0/P IC, MIC 1, MIC 2 and

MIC 3 connectors on the performance verification fixture.

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Operating Information

NOTE. The MIC boards and the PIC board look very similar. The MIC boards have two coaxial cable connections while the PIC board has only one (see Figure 2--3).

To quickly identify the MIC and PIC boards, you may want to attach a small label on the plastic housing of the MIC connector with the name of the MIC and PIC connectors (such as MIC0).

MIC PIC

Two connector

Figure 2- 3: MIC and PIC board identification

6. Connect the four MIC boards (labeled 6795258B1 on the anti-static bags) to the other end of each ribbon cable.

7. Connect a black coaxial cable from each of the Current Source (CS) connectors from the performance verification fixture to the CS connectors on each of the MIC boards.

8. Attach one of the color bands to each end of the current source cables to help you identify them. Use your own color-scheme when connecting the color bands.

9. Connect a black coaxial cable from each of the Test Voltage (TV) connectors from the performance verification fixture to the TV connectors on each of the MIC boards.

CAUTION. Power down the performance verification test fixture, before connecting or disconnecting any Module Interface Cards (MICs) or the Probe Interface Cards (PICs). Connecting or disconnecting items to the performance verification fixture while power is applied will damage the performance verification fixture or other test equipment.

One connector

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Operating Information

10. Connect the power cord to the performance verification fixture.

11. Leave the four P6041 cables and the PIC board disconnected. You will

connect these to the performance verification fixture and logic analyzer module during the actual procedures.

Figure 2--4 shows the TLACAL2 fixture with the major components connected to the logic analyzer.

MIC board

Ribbon cables

Black coaxial cable (8)

P6041 cable (4)

Figure 2- 4: TLACAL2 performance verification and adjustment test fixture

Digital

multimeter lead

RS-- 232 cable

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TLA7AXX Logic Analyzer Module Service Manual

Software Installation

Operating Information

The logic analyzer module operation is controlled by the Tektronix logic analyzer application software located on the hard disk of the mainframe. This software is installed when you purchased your logic analyzer or when you upgrade the software through one of the TLA7UP Field Upgrade Kit options. The logic analyzer module contains firmware which may need to be upgraded to function with the latest system software version; the firmware upgrade procedure is provided with the TLA7UP Field Upgrade Kit. The procedure is also described in this manual under Updating or Restoring the Logic Analyzer Firmware beginning on page 6--35.

To service the logic analyzer module and to complete the performance verification or adjustment procedures, you must install the Performance Verification software from disc 1 of the TLA application CD on the mainframe’sharddisk.

Verify the Performance

Verification Software

Version

Install the Performance

Verification Software

If your logic analyzer mainframe already has the performance verification software installed on the hard disk, you should verify that the software version matches that of the TLA application software. The TLA application software version is printed on disc 1 of the Tektronix Logic Family Analyzer application software CD.

If the version of the performance verification software on the hard disk does not match the CD label or the TLA application software, you must delete the older version before you can install the newer version. Refer to Removing the Software for instructions on removing the software.

Use the following steps to install the performance verification software:

1. Close all open applications.

2. Insert Disc 1 of the Tektronix Logic Analyzer Family application software

CD in the CD-ROM drive.

3. On the desktop select Start → Run to display the Run dialog.

4. In the Run dialog box, enter the following path or use the Browse button to

navigate to the path:

D:\TLA7Axx PV Adjust\Setup.exe

5. Click OK to begin the installation program and then follow the on-screen instructions to install the software.

6. Remove the CD when the installation is complete.

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Operating Information

Removing the Software

Operating Information

Front Panel

Use the following steps to remove the performance verification software from the hard disk in the mainframe. These steps are necessary when you want to upgrade the performance verification software.

1. On the desktop, select Start → Settings→ Control Panel

2. Double-click on Add/Remove Programs.

3. Select TLA7AxxPVAdjust.

4. Click the Change/Remove button.

This section provides a high-level overview of the controls and connectors of the logic analyzer module. It provides a high-level overview of the logic analyzer user interface and software.

Figure 2--5 shows the connectors and indicators on the front panel of a 136-channel logic analyzer module. Modules with fewer channels look and operate the same, but without the additional probe connectors.

Injector/Ejector Handles. The injector/ejector tabs are used to seat and unseat the modules in the mainframe.

READY Indicator. The READY indicator lights continuously after the logic analyzer module successfully completes the power-on process. If the indicator fails to light within five seconds of power-on, an internal module failure may be present.

ACCESSED Indicator. The ACCESSED indicator lights anytime the controller accesses the logic analyzer module.

ARM’D Indicator. The ARM’D indicator lights when the logic analyzer module is armed during an acquisition.

TRIG’D Indicator. The TRIG’D indicator lights when the logic analyzer module triggers and stays on until the module finishes acquiring data.

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TLA7AXX Logic Analyzer Module Service Manual

Operating Information

Injector/ejector handle

READY Indicator

ACCESSED Indicator

ARM’D Indicator

TRIG’D Indicator

Probe connectors

Analog signal

outputs

Configuration label

Probe retainer mounting holes

Figure 2- 5: Front panel of the logic analyzer module

Probe Connectors. The probe connectors are color-coded to match the labels on

the probes. Each probe connector accepts a 34-channel active probe consisting of 32 data channels and two clock/qualifier channels.

Probe Retainer Mounting Holes. The threaded probe retainer mounting holes provide a means of securely holding the probes in place. You must tighten the retaining screws to ensure a good ground connection for the probes to the module.

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Operating Information

Analog Outputs. Each module has four analog output BNC connectors regardless of the number of acquisition channels. The analog output connectors allow you to tap into the analog signal of any channel and connect the signals to an external instrument, such as an oscilloscope. This feature allows you to view the analog component of a selected channels without requiring a separate oscilloscope probe connection.

Configuration Label. The configuration label indicates the speed and memory depth of the logic analyzer module.

Merge Cable Connectors

Merge connectors on both sides of the module allow you to merge up to five individual modules to create a single module with up to 680 channels with full clock and trigger functionality. The 34-channel and 68-channel modules do not have merge connectors.

The merge connector on the left side of the module can be physically extended to connect with the connector of an adjacent module. The connector is shipped in the recessed position and must be extended when merging modules (see Figure 2--6).

The merge connector on the right side of the module provides play between modules allow easy installation of the module set in a mainframe.

2- 10

Merge connector

Figure 2- 6: Merge connector (shown in the extended position)

TLA7AXX Logic Analyzer Module Service Manual

Operating Information

Rear Panel

Figure 2--7 shows the connectors and controls on the rear panel of the logic analyzer module.

P1 Connector P2 Connector

Logical address

switches

Figure 2- 7: Rear panel controls and connectors

P1 and P2 Connectors. The acquisition board and the local processor unit (LPU)

provide the electrical connections from the module to the mainframe. These electrical connections include power distribution, processor communications, and intermodule communications.

Logical Address Switches. The logical address switches determine the logical address of the module. These switches should normally be set to address FF. For more information on these switches and their settings, refer to Logical Address on page 2--1.

Online Help

Diagnostics

Most user information for operating the logic analyzer module is available through the online help within the logic analyzer application. You can select the online help from the pull-down help menu, by clicking the Help button in a dialog box, or by using the what’s this help (click the question mark icon, drag the cursor to the item of interest on the screen, and then release the mouse button).

The logic analyzer module performs power-on diagnostics each time you power on the mainframe. The Calibration and Diagnostics property sheet appears at power-on if one or more of the diagnostics fail.

For more detailed tests, you can execute the extended diagnostics or the self calibration. For more information on the diagnostics, refer to Calibration and Diagnostic Procedures beginning on page 6--29.

NOTE. For best results, only run the diagnostics with the probes disconnected from the module.

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Operating Information

Self Calibration

Self calibration is an internal routine that optimizes performance. No external equipment or user actions are required to complete the procedure. The logic analyzer saves the data generated by the self calibration in non-volatile memory.

NOTE. Performing the self calibration does not guarantee that all logic analyzer module parameters operate within limits. Operation within limits is achieved by performing the Adjustment Procedures. Proper operation may be confirmed by performing the performance verification procedures in this same manual.

You can run the self calibration at any time during normal operation. To maintain measurement accuracy, perform the self calibration if more than one year has elapsed since the last self calibration.

You can check the status of the self calibration in the Calibration and Diagnostics property sheet.

If the logic analyzer module loses power during the self calibration, rerun the self calibration following the next power-on. The self calibration data generated before power was interrupted must be replaced with a complete set of new data. For best results, always perform the self calibration after at least a 30 minute warm-up.

Menu Overview

The logic analyzer module may require several minutes to run the self calibration depending on the number of channels. Select Calibration and Diagnostics property sheet from the System menu. Select the Self Calibration tab page and select the logic analyzer module. Click on the Run button to start the self calibration. Upon completing the self calibration the logic analyzer module menu selection changes from Running to Calibrated.

The logic analyzer is controlled by interactive windows through the TLA application. The TLA application consists of the following windows:

H System Window. This window provides an overview of the entire logic

analyzer. Use this window to navigate through the logic analyzer.

The center of the System window displays icons that represent hardware modules installed in the logic analyzer. The icons are linked to the other windows in the logic analyzer.

H Setup Window. A setup window exists for each module in the logic analyzer.

It contains all of the setup information for the logic analyzer module such as clocking, memory depth, threshold information, and channel information. Menus and dialogs contain information to set up the window as needed.

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TLA7AXX Logic Analyzer Module Service Manual

Operating Information

For the DSO, the Setup window contains setup information for each DSO channel such as the input voltage ranges, bandwidth, coupling, and termination. It also contains horizontal setup information and a link to the DSO Trigger window.

An External Oscilloscope setup window may be present if your logic analyzer connects to an external oscilloscope through the iView cable. This setup window provides setup, trigger, and connection information for oscilloscope and logic analyzer.

H Trigger Window. The Trigger window provides access to the logic analyzer

module or DSO module trigger setups. For either module, you can specify various trigger events and trigger actions to help you capture the data that you are interested in.

H Listing Data Window. The Listing Data window displays acquired data as

tabular text. Each column of data represents one group of data or other logical data information, such as time stamps. Each row of data represents a different time that the data was acquired; newer samples of data display below older samples.

H Waveform Data Window. The Waveform Data window displays acquired

data as graphical waveforms. All defined channel groups display as busforms for the logic analyzer and as individual analog channels for the DSO module.

H On/Off Buttons. These buttons enable or disable the operation of the

modules. Click the appropriate button to enable or disable the modules.

Refer to the online help for more information on the individual menus, icons, and fields within each window. You may also want to refer to the Tektronix Logic Analyzer Family User Manual for additional information.

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Operating Information

Merged Modules

The logic analyzer allows you to merge individual 102-channel or 136-channel module modules to provide a logic analyzer module with up to 680 channels. The following procedures provide information for merging and unmerging logic analyzer modules.

Merging Rules

Before merging modules to create a merged module set, review the following guidelines.

H You can only merge 102-channel and 136-channel modules.

H You cannot merge TLA7Axx modules with TLA7Lx, TLA7Mx, TLA7Nx,

TLA7Px, or TLA7Qx logic analyzer modules.

H Modules containing different memory depths can be merged, but will default

to the shallowest memory depth being used.

H All modules in a merged set must have the same maximum clock rate.

H Modules must be physically adjacent and connected before you can merge

them together in the System Configuration dialog box (see the instructions under Merge Procedure).

H You can merge two, three, four, or five modules together.

H The master module must have an equal or greater number of channels than

the module(s) with which it is merged. If there is a second slave module, the Slave 1 must have an equal or greater number of channels as the Slave 2. Slave 3 cannot have more channels than the master module or Slave 1 and Slave 2. Slave 4 cannot have more channels than the master modules or any other slave modules.

2- 14

H A merged module set can only reside in a single mainframe. You cannot

merge modules across mainframes.

H To merge a module to an established merged module set, the established

merged module set must be first unmerged through software via the System Configuration dialog box. Unmerged modules are the only potential candidates to add to a merged configuration.

TLA7AXX Logic Analyzer Module Service Manual

Operating Information

Merge Procedure

Complete the following steps to create a merged module from two or more individual modules. You must complete these steps prior to installing the modules in a mainframe.

CAUTION. To avoid damaging the mainframe or any modules, always power down the mainframe before removing or installing modules.

1. Determine which modules will reside in the higher-numbered slots in a single mainframe. You will need to place the merge connector of these modules in the extended position. The module in the lowest-numbered slot must have the merge connector in the recessed position.

Use Figure 2--8 as a guide for determining the location of the master module with the merged module set. Even though Figure 2--8 shows a five module set, you can still use the illustration to position the master module with respect to the slave module. For example, if you have a two module set, the master module is located in the lower-numbered slot, and the slave module is in the higher-numbered slot.

S L A V E 4

Figure 2- 8: Location of modules in a merged system

2. Place the module on the right side.

3. Using a Torx T-10 screw driver, remove the two screws holding the merge

connector to the module (see Figure 2--9).

4. Gently lift the merge connector out of the slot and place it in the extended position such that the screw holes line up over the two standoff posts.

5. Install the two screws into the standoff posts. Tighten the screws to 4-in. lbs.

S L A V E 2

M A S T E R

S L A V E 1

S L A V E 3

6. Repeat steps 2 through 5 for the remaining modules.

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Operating Information

Remove two screws

Standoff posts

Figure 2- 9: Removing the merge connector assembly from the module

NOTE. When installing the merged modules into a mainframe, you may need the help of another individual.

7. Place the first pair of modules to be merged side-by-side such that the merge connector assemblies line up and connect between the two modules.

8. Push the two modules together until the connectors are seated in place.

9. Add any additional modules to the set.

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TLA7AXX Logic Analyzer Module Service Manual

Operating Information

Figure 2- 10: Connecting the logic analyzer modules together

CAUTION. Ensure that the mainframe is powered down before installing or removing the modules.

10. Place the merged module set into the mainframe.

11. Align the tops and bottoms of the modules with the slots in the mainframe

(see Figure 2--11 on page 2--18). You may need the help of another individual if your merged module set contains more than two modules.

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Operating Information

Align

Slide module set

all the way in

2- 18

Latch in place

Figure 2- 11: Installing the merged module set in the mainframe

12. Slide the modules all the way into the mainframe until they rest against the rear panel connectors.

TLA7AXX Logic Analyzer Module Service Manual

Operating Information

13. Use the injector handles to firmly seat the modules in place one at a time and then tighten the hold-down screws on each module. The merge cable assembly should allow enough play between two side-by-side modules.

14. After installing all of the modules, power on the mainframe and complete the merge process listed under the Merged Modules tab in the System Configuration dialog box.

Unmerge Procedure

Although you can unmerge modules from a merged set from within the TLA application without physically separating modules, there will be times when you have to physically unmerge the modules. The following procedures provide the steps for unmerging the modules.

1. Power down the mainframe before removing the modules from the mainframe.

2. Use the ejector handles to disengage each module in the merged module set from the mainframe.

3. With the assistance of another individual, slide all of the merged modules out of the mainframe and place them on a static-free working surface.

4. Gently separate the modules on at a time from the merged module set.

5. Lay the modules on their right sides.

6. Remove the two Torx T-10 screws that hold the merge cable assembly to the

module.

7. Place the merge cable assembly into the recessed position.

8. Install the two Torx T-10 screws onto the assembly and tighten the screws to

4in-lbs.

9. Repeat steps 6 through 8 for the other modules.

You can now reinstall the modules in the mainframe as needed.

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Operating Information

2- 20

TLA7AXX Logic Analyzer Module Service Manual

Theory of Operation

This chapter describes the general operation of the logic analyzer module. This information is intended to help you isolate faults to the circuit board or probe level. It supplements diagnostic and troubleshooting information presented in the Troubleshooting section beginning on page 6--25.

The following Block Level Description describes circuit operation to the functional block level. Block diagrams are located in the Diagrams chapter beginning on page 9--1.

Block Level Description

The block level description provides an overview of each functional circuit within the logic analyzer module. Except for the number of channels, the basic operation is the same for each individual module and for merged modules.

The basic logic analyzer module consists of two main circuit boards: the Local Processing Unit (LPU) board and the Acquisition board. Each circuit board has two connectors on the rear of the boards that provide connections to the mainframe.

Up to four active probes per module acquire data from the target system and send it to the logic analyzer module for processing. The logic analyzer module can use different types of probes (such as general purpose, high-density, or differential) depending on the user’s application.

A single 102-channel or a 136-channel logic analyzer module can be merged with up to five modules to create a two-, three-, four-, or five-module-wide logic analyzer. The 34-channel and 68-channel modules do not support merging.

Local Processor Unit (LPU) Board

The LPU board controls instrument hardware, signal acquisition, power conditioning, and communications functions. A 160-pin connector provides interconnections with the acquisition board for power supplies, data and control signals.

Processor System

The processor system contains a microprocessor that controls the entire instrument. Commands and data sent to the instrument through the mainframe pass through the communications interface, which resides on the bus. The bus also routes data between the main processor system and the acquisition board.

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Theory of Operation

The processor system includes the instrument firmware. To facilitate upgrades, the firmware resides in Flash ROM. The processor system also includes the nonvolatile RAM (NVRAM) used for the calibration constants, module serial numbers, and PowerFlex configuration information.

Communications Interface

Power Supplies

Acquisition Board

Clock Circuitry

Probe Interface

The Communications Interface transfers commands and data between the mainframe and the mainframe controller. Signals pass between the logic analyzer module and the mainframe through the rear connectors.

The onboard power supplies receive +5 V, --5.2 V, ±12 V, and ±24 V from the mainframe through the rear connectors. Voltage converters produce the +2.5 V supply for use on the acquisition board through the 160-pin connector between the LPU and acquisition board.

The acquisition board accepts input signals from the probes and converts them to digital information. A 160-pin connector provides interconnections with the LPU board.

The system clock is derived from the 10 MHz clock from the backplane through a phase-locked loop. The acquisition run circuitry is integrated with the clock circuitry to support time correlation.

The probe interface consists of ASICs that receive data from the probes, compare the data against a threshold, and transfer the digital information to CMOS ASICs via differential outputs. Each ASIC in the probe interface receives 16 data channels and one clock channel. In addition to providing digital signals to the CMOS ASICs, the probe interface ASICs contain outputs for the Analog output signals.

Analog Output Interface

Power Supplies

3- 2

The acquisition board has four SMA connectors that connect to the four BNC connectors on the front panel. The software (via the user interface) determines which signals will be sent to the four Analog output connectors. Regardless of the number of channels in the module, there will always be four signals available to route to the Analog output connectors.

Voltage converters produce the +3.3 V supply on the acquisition board and the ±3 V supplies for the active probes.

TLA7AXX Logic Analyzer Module Service Manual

Theory of Operation

Trigger and Storage

Control Circuitry

Acquisition Memory

Clocking and triggering is controlled by a single ASIC. This ASIC determines when acquisition data should be sampled based on the clock information and qualifier information. The ASIC also contains 16 Event resources for the purposes of word recognition, range recognition, and other trigger functions. In merged configuration, the ASIC communicates information between modules to ensure proper triggering.

The acquisition memory stores acquired data. The memory can be set up to store all data samples, or it can be split to store data samples and either glitch information or setup and hold violation information.

When the memory is split, only half the memory depth is available and can only run at half the speed. Every stored data sample takes up two memory locations, one to hold the actual data sample and the other to hold the corresponding glitch information or the setup and hold information.

Glitch storage is only enabled with asynchronous clocking while setup and hold storage is only enabled with synchronous clocking.

The trigger machine can trigger on either glitches or setup and hold violations without storing information. This allows the user to trigger on a glitch or on a setup and hold violation at maximum speed and maximum memory depth.

Backplane Interface

The backplane interface provides the interface with the mainframe and the acquisition board. This interface contains intermodule signals that communicate to other modules in the logic analyzer mainframe. The interface also provides the 10 MHz reference clock for the clocking circuitry.

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Theory of Operation

Probes

The logic analyzer module connects to the target system through 34-channel probes (32 data channels and two clock/qualifier channels). Depending on the number of channels in the logic analyzer module, you can connect up to four logic analyzer probes to the module.

Currently four different types of active probes are supported for the logic analyzer module:

H P6810 34-channel general purpose probe

H P6860 34-channel high-density single-ended probe

H P6864 17-channel high-density 4X single-ended probe

H P6880 34-channel high-density differential probe

The two high-density probes connect directly to the circuit boards in the target system. The probe connections are footprints designed on the circuit boards. The footprints eliminate the need for additional electro-mechanical parts for probe connectors.

Merged Modules

The general purpose probes have lead sets that connect to several general-purpose connectors on the target system.

Detailed information on the probes is available in the P68xx Logic Analyzer Probe Instruction Manual.

A merged module consists of a Master module and one or more Slave modules connected together by a merge cable connector. Each module has its own merge cable connectors. The local bus sends the system clock of the Master module to the Slave modules. The merged modules must be located in adjacent slots.

The merge connector passes 48 signals between adjacent modules excluding the system clock. These signals consist of 16 trigger event signals, two storage control signals, 26 clock sample/control signals, and four data-login control signals.

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TLA7AXX Logic Analyzer Module Service Manual

Performance Verification

This chapter contains procedures for functional verification, certification, and performance verification procedures for the logic analyzer modules. Generally, you should perform these procedures once per year or following repairs that affect certification.

NOTE. This chapter does not contain any procedures for verifying, adjusting, or certifying the TLACAL2 Performance Verification fixture. If the test fixture requires, verification, adjustment, or certification, you must return the test fixture to the factory.; contact your local Tektronix service center for more information.

Summary V erification

Functional verification procedures verify the basic functionality of the instrument inputs, outputs, and basic instrument actions. These procedures include power-on diagnostics, extended diagnostics, and manual check procedures. These procedures can be used for incoming inspection purposes.

Certification procedures certify the accuracy of an instrument and provide a traceability path to national standards. Calibration data reports are produced for the logic analyzer modules as output from the performance verification and adjustment software.

Performance verification procedures confirm that a product meets or exceeds the performance requirements for the published specifications documented in the Specifications chapter of this manual. Refer to Figure 4--1 on page 4--2 for a graphic overview of the procedures.

Adjustment procedures check for, and if necessary, correct any adjustment errors discovered when performing functional or performance verification procedures. The adjustment procedures for the logic analyzer modules are controlled by software but some of the adjustment procedures require manual intervention to move probes or to change test equipment settings.

The performance verification and adjustment software is provided on the product CD-ROM. If you have not already done so, refer to Software Installation beginning on page 2--7 for instructions on installing the software.

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4- 1

Performance Verification

Determine equipment

to certify.

Use

Tektronix-supplied

probes.

Go to appropriate

procedure(s).

Gather required test

equipment.

Is it OK

with customer to

remove/reconnect probes

from System

Under Test?

Select procedure.

Configure customer’s

mainframe and modules as

described in procedure.

Set up test equipment.

Yes

Allow all mainframes, modules and

equipment to warm up (30 minutes).

Load PV/Adjust

software.

Perform procedure

using software.

Do tests

pass?

Yes

Print Calibration

Data Report.

Create necessary

Calibration Certificate.

Are

all certifications

complete?

Repair or adjust

equipment as

required.

Figure 4- 1: Calibration/certification procedure flow chart

4- 2

Yes

Done

TLA7AXX Logic Analyzer Module Service Manual

Test Equipment

The procedures use external, traceable signal sources to directly test characteristics that are designated as checked (n)intheSpecifications chapter of this manual. Table 4--1 shows the required equipment list; this equipment is required for the performance verification and adjustment procedures.

Table 4- 1: Test equipment

Item number and description Minimum requirements Example

Performance Verification

1. Mainframe TLA700 Series Mainframe with TLA Application software V4.2 or higher

2. Logic analyzer module with

probes

3. Logic analyzer probes P6810, P686x, or P6880 logic analyzer

4. Performance Verification test

fixture with accessories

5. Digital Multimeter with probes1Agilent 34401A, 6.5 digit display, 35 ppm, 1

6. Oscilloscope

7. USB-GPIB controller: National Instruments 778195-01

8. GPIB cable 2 m GPIB cable Tektronix part number 012-0991-00

9. RS-232 cable 2 m RS-232 cable, 9-pin female-to-female

10. BNC cables 4 Analog Output BNC-to-BNC, low loss, 33 in.

The digital multimeter is required to complete the Probe+PIC performance verification and adjustment procedure, the Module+MIC performance verification and adjustment procedures, the Module+Probe Gain & Offset performance verification procedures, and the certification procedures.

The oscilloscope is required to complete the performance verification procedures for the Analog Output tests.

TLA7Axx Series logic analyzer module No substitute allowed

probes. One probe required for every 34-channels on the logic analyzer module

TLACAL2 test fixture; Includes: 4 Ribbon cables 4 Module interface connectors (MICs) 1 Probe interface connector (PIC) 4 P6041 BNC-to-SMB cables 8 MCX-to-MCX coaxial cables, with

identification color bands

year accuracy, 1000 readings per minute, 100 nV sensitivity, GPIB controllable

Tektronix TDS694C Four channels, 3 GHz, 10GS/s

Windows 2000 compatible with 2 m cable

connector

10x cables

TLA721 Benchtop Mainframe or TLA715 Portable Mainframe

No substitute allowed

Tektronix iView cable

Tektronix part number 012-1379-00

Tektronix part number 174-4595-00

TLA7AXX Logic Analyzer Module Service Manual

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Performance Verification

Test Equipment Setup

The TLACAL2 Performance Verification and Adjustment fixture and other test equipment requires preliminary installation and setups. You will need the equipment listed in Table 4--1 on page 4--3 to complete the performance verification procedures. If you have not already installed the test fixture and test equipment, refer to TLACAL2 Fixture Installation on page 2--3 for the prelimi- nary installation instructions.

Most of the individual procedures require specific test equipment setups depending on your logic analyzer configuration. These setups are listed prior to each test and are also described in the TLACAL2 software windows.

CAUTION. Always power down the TLACAL2 test fixture before connecting or disconnecting the ribbon cables. Failure to do so can damage the test fixture, the PIC, or the MICs.

Starting the Performance

Verification Software

The performance verification software is a separate application that consists of executable software files. The software must be installed on the hard disk before you can use it; refer to Software Installation on page 2--7 for instructions on installing the software. You must quit the logic analyzer application before starting the performance verification software; you cannot run both applications at the same time.

Use the following steps to start and run the software. These steps are repeated under the individual procedures but are listed here to give you an overview of using the software.

1. Allow the logic analyzer and all test equipment to warm up for at least 30 minutes.

2. Exit the logic analyzer application.

3. Select Start → Programs → Tektronix Logic Analyzer → TLA7AxxPVAd-

just (or double-click on the TLA7AxxPVAdjust icon on the desktop). An application window similar to Figure 4--2 appears.

4. Select the module that you want to test from the list and then click either the Verification button, Adjustment button, or Certification button depending on the type of procedure that you want to perform.

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Figure 4- 2: Performance verification software startup window

Software Overview

After selecting the type of test that you want to run, a new dialog box appears. The dialog box contains the following information:

H Name, slot location, and serial number of the module to be tested

H Probe selection box

H A list of procedures organized by groups

The individual procedures are organized by groups that require the same test equipment setups. When moving between different groups, you will be asked to power down the test fixture, make the necessary connections In some cases, you will be asked to power down the test fixture, close the application, change the connections, and then restart the application.

Depending on the type of probe selected, the related procedures are indicated by a checkmark adjacent to the procedure. You can disable any procedures by clearing the procedure. All selected procedures will be tested beginning with the top-most procedure in the dialog box. In most cases, you will want to run all of the selected tests.

The software determines which GPIB instruments are required to perform the selected procedures and sets up the individual instruments. If any equipment problems are found, an appropriate error message will be displayed.

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Performance Verification

NOTE. Some of the procedures require a TDS694C oscilloscope and a Agilent 34401A digital multimeter connected to the logic analyzer via GPIB (see the footnotes in Table 4--1 for details). If you do not have the TDS694C oscilloscope or the digital multimeter connected to the GPIB, you cannot start the performance verification procedures that require those instruments.

Obtaining Test Results

Troubleshooting

After completing the various procedures, you have the option of saving the test results to a text file on the hard disk. You can assign a name to the file from a dialog box. You can then edit the file as necessary using any of the Windows tools or print the file.

If any tests fail, use the following steps to troubleshoot the problems:

1. Check that all test equipment is powered on and has the proper warm-up time.

2. Check all test equipment for improper or loose connections.

3. Verify that the probes are properly connected to the logic analyzer module

and that the retaining screws are tightened. The retaining screws must be tightened to provide a good ground connection for the probes.

4. Verify that all probes are properly connected to the test fixture. If you are using P686x or P6880 probes, make sure that the alignment pin on the probe head is aligned with the hole on the test fixture. You must ensure a tight connection on the test fixture for these probes.

5. If you are using P686x or P6880 probes, verify that the test fixture connections are clean and free of dust or dirt. If necessary, refer to the cleaning procedures in the Maintenance chapter.

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6. Rerun mainframe or module diagnostics.

7. Run the self calibration for the module in question from the TLA applica-

tion.

8. Run the adjustment procedures for the module in question.

9. Run the tests a second time to verify the failure.

10. If all else fails, contact your local Tektronix service center for additional

information.

TLA7AXX Logic Analyzer Module Service Manual

Functional Verification

Performance Verification

This section contains instructions for performing the functional verification procedures for the logic analyzer modules. These procedures provide an easy way to check the basic functionality of the logic analyzer modules and probes. The TLACAL2 test fixture or software is not required for any of the functional verification checks.

If any check within this section fails, refer to the Troubleshooting section in the Maintenance chapter of this manual for assistance. Failed tests indicate the instrument needs to be serviced.

The functional verification procedure consists of the following parts:

H Module self tests and power-on diagnostics

H Extended diagnostics

H Probe functional verification

This procedure provides a functional check only. If more detailed testing is required, perform the Performance Verification Procedures beginning on page 4--12 after completing this procedure.

Test Equipment

Setup

Perform these tests whenever you need to gain confidence that the instrument is operating properly.

You will need the following equipment to complete the functional verification procedure:

H TLA700 Series logic analyzer mainframe with one logic analyzer module

installed (more modules are required to check the merged functionality)

H At least one logic analyzer probe

It is assumed that the logic analyzer module is properly installed in the mainframe. Refer to Module Installation on page 2--2 for module installation instructions.

Power on the logic analyzer mainframe and allow a 30-minute warm-up period before continuing with any procedures in this section.

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Performance Verification

Module Self Tests and

Power-On Diagnostics

During power-on, the installed modules perform an internal self test to verify basic functionality. No external test equipment is required. The self tests require only a few seconds per module to complete. The front-panel ARM’Dand TRIG’D indicators blink during the self test. After testing completes, the front panel indicators have the following states:

H READY — Green (on)

H ACCESSED — off

H ARM’D — off

H TRIG’D — off

Next, the power-on diagnostics are run. If any self tests or power-on diagnostics fail, the instrument displays the Calibration and Diagnostics property sheet.

NOTE. If any diagnostics fail, you may need to run the self calibration before attempting to service the logic analyzer module. This may be especially true after you install the logic analyzer module in the mainframe for the first time. The Self Calibration procedure is listed under Self Calibration beginning on page 5--5.

Logic Analyzer Module

Functional Verification

Procedure

The following procedure checks the basic functionality of the logic analyzer module. You can perform this procedure with individual modules or with merged modules. Functional verification consists of running the extended diagnostics.

NOTE. Running the extended diagnostics invalidates any acquired data. If you want to save any of the acquired data, do so before running the extended diagnostics.

Perform the following steps to complete the functional verification procedures:

1. Disconnect any probes connected to the logic analyzer module.

2. In the logic analyzer application, go to the System menu and select

Calibration and Diagnostics.

3. Click the Extended Diagnostics tab.

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4. Select the top level test and click the Run button.

The diagnostics will perform each one of the tests listed in the menu under the module selection. All tests that displayed an Unknown status will change to a Pass or Fail status depending on the outcome of the tests.

5. Scroll through the test results and verify all tests pass.

NOTE. If the extended diagnostics fail, run the self calibration procedures as described under Self Calibration beginning on page 5--5 for the logic analyzer module under test and then rerun the extended diagnostics.

Probe Functional

Verification

There are two ways of verifying probe functionality. One way is to connect the probes from the logic analyzer module to a signal source, adjust the appropriate threshold voltage levels, and then verify that the logic analyzer acquires the data in a listing or waveform window.

Alternately, you can perform the performance verification procedures which will verify that the logic analyzer and the attached probes meet or exceed the advertised specifications. The performance verification procedures are covered in the remainder of this chapter.

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Performance Verification

Performance Verification Instructions

This section contains information to verify the performance of the logic analyzer module. Testing is performed using the performance verification software and the performance verification fixture.

As a general rule, these tests should be done once a year.

Prerequisites

The performance verification procedures in this section comprise an extensive, valid confirmation of performance and functionality when the following requirements are met:

H The performance verification software must be loaded on the hard disk.

Refer to Software Installation on page 2--7.

H The logic analyzer module must be installed in a mainframe and operating

for at least 30 minutes at an ambient temperature between +20 _C and +30 _C.

H The TLACAL2 test fixture and other related test equipment must be

installed, connected, and operating for at least 30 minutes at an ambient temperature between +20 _C and +30 _C.

H The logic analyzer module and the TLACAL2 test fixture must have been

last adjusted at an ambient temperature between +20 _C and +30 _C.

H The logic analyzer and TLACAL2 test fixture must be in an operating

environment within the limits described in the Specifications chapter of this manual.

H When verifying the performance of merged modules consisting of different

types of individual modules, the merged module can be tested without separation. The performance verification software runs independent of the logic analyzer application and does not recognize configuration settings.

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H If you are using P686x probes or P6880 probes, you must use the thick board

elastomers (available in the 020-2452-xx accessory kit). Refer to the

Operating Basics chapter of the P68xx Logic Analyzer Probe Instruction Manual for instructions on installing or changing the elastomers.

TLA7AXX Logic Analyzer Module Service Manual

Performance Verification

Procedure Overview

When using the performance verification software, you will connect external test equipment and probes to the logic analyzer module in response to prompts on the screen. The software automatically selects the module settings and determines the results of each test.

The results of the tests are recorded in a temporary file and are available upon test completion for completing test records.

NOTE. Before testing an instrument following repair, you must first complete the adjustment procedure.

Table 4--2 lists the specifications as checked (n)intheSpecifications chapter for the TLA7Axx logic analyzer modules and the TLA7Axx performance verification software checks used to verify those specifications. In addition to the software test listed in the table, some specifications are verified by the built-in diagnostics. By running all tests and diagnostics, you will verify the performance of the logic analyzer module and probes.

Table 4- 2: Performance verification tests

Specification Test method

Threshold accuracy Verified by the Thresholds test. Certified by

running Certification procedure; refer to Logic Analyzer Module Certification beginning on page 4--30.

Channel-to-channel skew Verified indirectly by the Setup and Hold

window size procedure under Setup and Hold

Internal sampling period Verified indirectly by Pulse Width procedure

and time base Accuracy procedure

Minimum recognizable word (across all channels)

Setup and hold window size (data and qualifiers)

Maximum synchronous clock rate Diagnostics verify the clock detection/sampling

Counters and timers Verified by diagnostics

Trigger state sequence rate Verified indirectly by the at-speed diagnostics

Verified indirectly by the Setup and Hold window size and by the Internal Sampling Period

Verified directly by Setup and Hold procedure (P6880 probe only)

circuitry. Bandwidth is verified by Setup and Hold procedures and by the Pulse Width procedure

and the Internal Sampling Period

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Performance Verification

analy

Performance Verification Procedures

Table 4--3 provides a summary of the performance verification procedures. The procedures are listed by groups and include individual procedures. Some of these procedures are optional and are recommended for performing a thorough performance verification. Others are the minimum required to verify the advertised specifications of the logic analyzer module. Each group requires different equipment setups.

Table 4- 3: TLA7Axx performance verification procedures

Procedure by groups Notes

Probe+PIC Procedure Optional procedure; digital multimeter

Probe Gain and Offset

Module+MIC Procedures Optional procedures; digital multimeter

Input Resistance

Digital Gain and Offset

required;verifies probe onl

required

Analog Gain and Offset

Module+Probe Gain and Offset Procedures Required procedures; digital multimeter

Threshold

Analog Gain and Offset

Module+Probe Timing Procedures Required procedures

Pulse Width

Timebase

Analog Outputs to Oscilloscope Optional procedure. TDS694C oscilloscope

Setup and Hold Procedure Can only be verified with P6860 high density

Setup and Hold

Certifiable parameter. This procedure can be run separate from the performance verification procedures. Select Certification button from main window in the software. The Certification instructions are listed on page 4- 30.

required

logi

zer probe

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Performance Verification

Use the tables and illustrations to set up and execute the procedures. The procedures assume that you have already installed the performance verification software on the logic analyzer mainframe. The procedures also assume that you will only perform the procedures selected in each group.

The procedures will vary depending on the type of probes that you have connected to the logic analyzer module and on the number of channels on your logic analyzer module.

Figure 4--3 shows the locations of connectors and test points on the performance verification fixture. You may need to refer to this illustration when connecting probes and cables to the fixture. You should also refer to the label on top of the test fixture.

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Performance Verification

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Figure 4- 3: TLACAL2 test fixture connections

TLA7AXX Logic Analyzer Module Service Manual

Performance Verification

Probe+PIC Procedure

This procedure verifies probe gain and offset circuitry in the individual probes. This procedure is not dependent on any previous procedures. Use this procedure to verify the functionality of the probes. The procedure is optional and is not required to verify any module specifications.

The following procedure assumes that you will be testing one probe at a time without performing any other procedures.

Equipment Setups. It is assumed that the logic analyzer mainframe is already connected to the TLACAL2 test fixture and that the performance verification software is already installed on the hard disk of the logic analyzer. The following procedures describe the specific connections from the probes and to the test fixture.

CAUTION. If you have any P6041 cables connected from the logic analyzer to the TLACAL2 test fixture, always disconnect one end of each P6041 cable before powering down the test fixture.

Always power down the test fixture before connecting or disconnecting ribbon cables. Failure to do so can damage the test fixture, the PIC, or the MICs.

1. Power down the TLACAL2 test fixture before connecting the ribbon cables and the (PIC).

CAUTION. To avoid damaging the test fixture and the PICs through static discharge, always wear a grounded antistatic wrist strap. Avoid handling individual components of the test fixture without static protection.

2. Connect one of the ribbon cables to the MIC0/PIC connector (J141) on the test fixture.

3. Connect the PIC to the other end of the ribbon cable.

4. Connect any one of the coaxial cables from the TV (test voltage) connectors

on the test fixture to the TV connector on the PIC.

5. Connect the multimeter leads to the DMM test points (J390) on the test fixture. Connect the positive lead to the + connector and the negative (ground) lead to the -- connector.

6. Connect the probe to be tested to the PIC.

7. If you are adjusting a P6810 probe:

a. Connect the lead sets to the P6810 GAIN & OFFSET Data connections

at J100, J101, J110, and J111 on the test fixture.

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Performance Verification

b. Connect the clock/qualifier leads to the SNGL square pins at J220. Make

sure that you connect the ground side or the “-- ” side to the square pins with the GND label.

8. If you are testing a P686x probe, connect the probe heads to the P6860/80 GAIN & OFFSET connections at J120 and J130 on the test fixture. If you are testing a P6880 probe, connect the probe heads at J120, J121, J130, and J131 on the test fixture.

NOTE. Make sure that the alignment pin on the P686x or P6880 probe head is aligned with the hole on the test fixture. Tighten the probe head screws by alternating between them until they are finger tight (no more than 1 in-lbs of torque).

9. Power on the test fixture, logic analyzer mainframe, and allow all test equipment to warm up for 30 minutes before continuing.

Start the Software. Complete the following steps to start the performance verification software and to run the verification procedures:

1. Exit the TLA application on the logic analyzer.

2. Double-click the TLA7Axx Performance Verification icon on the desktop to

open the application (see Figure 4--2 on page 4--5).

3. Click the Verification button to start the software. A Verification dialog box similar to Figure 4--4 appears.

4. Select the probe type near the bottom of the dialog box.

5. Select the Probe Gain & Offset procedure (the default setting is not checked)

and clear any other procedures.

NOTE. The software will perform all selected procedures in the listed sequence. To limit the test to specific procedures, clear any procedures that you do not want to run.

6. Click the Next button at the bottom of the dialog box to begin the procedure.

A list of connection instructions displays for the current procedure.

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Performance Verification

Figure 4- 4: Default Verification dialog box

7. Verify that your connections match those of the instructions. Then click the Next button to begin the procedure.

The software will begin the verification procedures and display a list of test results in the window.

8. After the procedure finishes, click the Next button to open the Finish dialog box where you can save the results to a file. Enter a file name and click the Save button. You can use the Save dialog to save the file to a folder of your choice or use the default location.

9. If you are testing more than one probe, disconnect the first probe and connect the next probe. There is no need to power down the test fixture while changing probes.

10. Click the Back button to return to the instructions dialog.

11. Click the Next button to test the next probe.

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Performance Verification

12. After completing the last probe, you can exit the application or return to the main window to perform other procedures.

CAUTION. Power down the test fixture before disconnecting the PIC from the test fixture. Failure to do so can damage the test fixture or the PIC.

Module+MIC Procedures

These procedures verify the input resistance, the digital gain and offset, and the analog gain and offset parameters of the logic analyzer probe input sections. These procedures are performed without the logic analyzer probes. The procedures are optional and do not verify any advertised specifications. However, they are helpful in verifying the logic analyzer functionality and for troubleshooting purposes.

Equipment Setups. It is assumed that the logic analyzer is already connected to the TLACAL2 test fixture and that the performance verification software is already installed on the hard disk of the logic analyzer. It is also assumed that the logic analyzer module is installed in the logic analyzer mainframe. The following procedures describe the specific connections from the logic analyzer module to the MICs and to the TLAC AL2 test fixture.

CAUTION. If you have any P6041cables connected from the logic analyzer to the TLACAL2 test fixture, always disconnect one end of each P6041 cable before powering down the test fixture.

Always power down the test fixture before connecting or disconnecting ribbon cables. Failure to do so can damage the test fixture, the PIC, or the MICs.

1. Power down the TLACAL2 test fixture before connecting the ribbon cables and the MICs.

4- 18

CAUTION. To avoid damaging the test fixture, the PIC, or the MICs through static discharge, always wear a grounded antistatic wrist strap. Avoid handling individual components of the test fixture without static protection.

2. Connect the four ribbon cables to the ribbon cable connectors on the test fixture.

3. Disconnect the PIC if it is connected to the ribbon cable.

4. Connect a MIC to each of the ribbon cables.

5. Connect any one of the coaxial cables from the CS (current source)

connectors on the test fixture to the CS connector on the MIC.

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6. Connect any one of the coaxial cables from the TV (test voltage) connectors on the test fixture to the TV connector on the MIC.

7. Connect the multimeter leads to the DMM test points (J390) on the test fixture. Connect the positive lead to the + connector and the negative (ground) lead to the -- connector.

8. Connect a P6041 cable from each of the Analog Output BNC connectors to the corresponding connector on the front of the test fixture (if necessary, refer to the label on the test fixture for the connection locations).

9. Connect the ribbon cables with the MICs to the appropriate connector on the logic analyzer module.

10. Power on the test fixture and the logic analyzer and allow a 30 minute warm--up period.

Start the Software. Complete the following steps to start the software:

1. Exit the TLA application on the logic analyzer.

2. Double-click the TLA7Axx Performance Verification icon on the desktop.

An application window similar to Figure 4--2 on page 4--5 appears.

3. If you have more than one logic analyzer module in your mainframe, select the logic analyzer module to be verified from the list in the window.

4. Click the Verification button to start the software. A Verification dialog box similar to Figure 4--4 on page 4--17 appears.

5. Select Input Resistance, Digital Gain and Offset, and Analog Gain and Offset and clear any other procedures.

NOTE. The software will perform all selected procedures without interruption. To limit the test to specific procedures, clear any procedures that you do not want to run.

6. Click the Next button at the bottom of the dialog box to begin the procedure.

A list of connection instructions displays for the current procedure.

7. Verify that your connections match those of the instructions. Then click the Next button to begin the procedures.

The software will begin the verification procedures and display a list of results in the window.

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Performance Verification

9. Click the Finish button to finish the procedure and return to the startup window.

CAUTION. Always disconnect one end of each P6041 cable before powering down the TLACAL2 test fixture. Failure to do so can damage the test fixture.

10. Disconnect one end of each P6041 cable before powering down the TLACAL2 test fixture.

Module+Probe Gain and

Offset Procedures

These procedures verify the analog gain and offset parameters of the logic analyzer module. These procedures require you to connect the logic analyzer probes to the test fixture; the actual connections depend on the type of probe and the number of channels of your logic analyzer module. The procedures also verify the Threshold specifications of the logic analyzer module; this is a certifiable parameter.

Equipment Setups. It is assumed that the logic analyzer is already connected to the TLACAL2 test fixture and that the performance verification software is installed on the hard disk of the logic analyzer. It is also assumed that the logic analyzer module is installed in the logic analyzer mainframe. The following procedures describe the specific connections from the logic analyzer module to the probes and to the TLACAL2 test fixture.

CAUTION. Always power down the TLACAL2 test fixture before connecting or disconnecting the ribbon cables. Failure to do so can damage the test fixture, the PIC, or the MICs.

There is no need to power down the test fixture if you are only connecting probes, the P6041 cables, or the digital multimeter to the test fixture.

1. Connect a P6041 cable from each of the Analog Output BNC connectors to the corresponding connector on the front of the test fixture (if necessary, refer to the label on the test fixture for the connection locations).

4- 20

2. Connect the multimeter leads to the DMM test points (J390) on the test fixture. Connect the positive lead to the + connector and the negative (ground) lead to the -- connector.

TLA7AXX Logic Analyzer Module Service Manual

Performance Verification

3. Connect a logic analyzer probe from the logic analyzer C0/C1/C2/C3 input connector (or the C3/C2/A3/A2 connector for 34- or 68-channel modules) to the appropriate connectors on the test fixture as described in the following steps.

4. If you are using a P6810 probe:

a. Connect the lead sets to the P6810 GAIN & OFFSET Data connections

at J100, J101, J110, and J111 on the test fixture.

b. Connect the clock/qualifier leads to the SNGL square pins at J220. Make

sure that you connect the ground side or the “-- ” side to the square pins with the GND label.

5. If you are using a P686x probe, connect the probe heads to the P6860/80 GAIN & OFFSET connections at J120 and J130 on the test fixture. If you are testing a P6880 probe, connect the probe heads at J120, J121, J130, and J131 on the test fixture.

6. Power on the test fixture, logic analyzer, and the other test equipment. Allow all test equipment to warm up for 30 minutes before continuing the procedure.

Start the Software. Complete the following steps to start the software and to run the procedures:

1. Exit the TLA application on the logic analyzer.

2. Double-click the TLA7Axx Performance Verification icon on the desktop.

An application window similar to Figure 4--2 on page 4--5 appears.

3. If you have more than one logic analyzer module in your mainframe, select the logic analyzer module from the list in the window.

4. Click the Verification button to start the software. A Verification dialog box similar to Figure 4--4 on page 4--17 appears.

5. Select the probe type near the bottom of the dialog box.

6. Verify that Threshold and Analog Gain and Offset are selected under

Module+Probe Gain & Offset Procedures. Clear all other procedures in the dialog box.

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Performance Verification

NOTE. The software will perform all selected procedures in the listed sequence. To limit the test to specific procedures, clear any procedures that you do not want to run. If you want to run all of the selected procedures, you will need to play close attention to the connection instructions as they appear on the screen.

7. Click the Next button at the bottom of the dialog box to begin the procedure.

A list of connection instructions displays for the procedure.

NOTE. Some of the connection information may vary depending on the configuration of your logic analyzer module. The connection information in the window should track your logic analyzer module; the printed instructions in this section may differ because they assume you are testing a 136-channel module.

8. Verify that your connections match those of the instructions. Then click the Next button to begin the procedure.

The software will begin the procedures and display a list of results in the window.

9. After the first set of procedures are done, click the Next button to display the instructions for the next step. In most cases you only need to connect a different probe to the test fixture.

10. After changing the connections, click the Next button to continue the procedures.

11. Repeat steps 8 through 9 as indicated by the software.

12. After the procedure finishes, click the Next button to open the Finish dialog

box where you can save the results to a file. Enter a file name and click the Save button. You can use the Save dialog to save the file to a folder of your choice or use the default location.

13. Click the Finish button to complete the process.

CAUTION. Always disconnect one end of each P6041 cable before powering down the TLACAL2 test fixture. Failure to do so can damage the test fixture.

14. Disconnect one end of each P6041 cable before powering down the TLACAL2 test fixture.

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Module+Probe Timing

Procedures

These procedure verify the minimum pulse width specification, the accuracy of the time base, and the analog output path.

NOTE. The Analog Output to Oscilloscope procedure is an optional procedure. You can only perform this procedure if you have a TDS694C oscilloscope connected to the analog outputs of the logic analyzer module; no other oscilloscopes can be used.

CAUTION. If you have any P6041cables connected from the logic analyzer to the TLACAL2 test fixture, always disconnect one end of each P6041 cable before powering down the test fixture.

Always power down the test fixture before connecting or disconnecting ribbon cables. Failure to do so can damage the test fixture, the PIC, or the MICs.

1. Connect a probe to each probe connector on the logic analyzer module.

2. Refer to Table 4--4 on page 4--24 and to Figure 4--5 on page 4--25 to connect

the probe from the logic analyzer C0/C1/C2/C3 input connector (or the C3/C2/A3/A2 connector if you have a 34- or 68-channel module) to the appropriate connectors on the test fixture.

3. If you are using a P6810 probe, make sure that you connect the ground or low side of the lead sets to the GND side of the connectors on the test fixture. Connect the clock/qualifier leads to the DESKEW REF connector; make sure that you connect the ground side or the “-- ” side to the square pins with the GND label. The single ground lead does not need to be connected.

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Performance Verification

Table 4- 4: Module+Probe Timing procedure probe connections

Probe TLACAL2 test fixture connections

P6810 P6810 TIMING

(J881, J882, J883, J884 data connectors J880 Deskew Ref connector)

P686x P6860 DESKEW AND MIN PULSE

(J610, J611 data connectors J612 deskew ref connector)

P6880 P6880 TIMING

(J581, J582, J583, J584 data connectors, J680 Deskew Ref connector)

4. If you are going to perform the Analog Output to Oscilloscope procedure, connect the BNC-to-BNC cable from each of the Analog Output BNC connectors on the logic analyzer module to the corresponding inputs on the oscilloscope.

5. Power on the test fixture, logic analyzer, and oscilloscope and allow all test equipment to warm up for 30 minutes before continuing the procedure.

Start the Software. Complete the following steps to start the software and to run the procedures:

1. Exit the TLA application on the logic analyzer.

2. Double-click the TLA7Axx Performance Verification icon on the desktop.

An application window similar to Figure 4--2 on page 4--5 appears.

3. If you have more than one logic analyzer module in your mainframe, select the logic analyzer module from the list in the window.

4. Click the Verification button to start the software. A Verification dialog box similar to Figure 4--4 on page 4--17 appears.

5. Select the probe type near the bottom of the dialog box.

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Figure 4- 5: Module+Probe timing procedure probe connections

6. Verify that Pulse Width and Timebase are selected under Module+Probe Timing Procedures.

7. If you want to perform the analog output procedure, select the Analog Output to Oscilloscope (it is not checked).

8. Clear all other procedures in the dialog box.

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NOTE. The software will perform all selected procedures without interruption. To limit the test to specific procedures, clear any procedures that you do not want to run. If you want to run all of the selected procedures, you will need to play close attention to the connection instructions as they are displayed on the screen.

9. Click the Next button at the bottom of the dialog box to begin the procedure.

A list of connection instructions displays for the first procedure.

10. Verify that your connections match those of the instructions. Then click the Next button to begin the procedure.

The software will begin the procedures and display a list of results in the window.

NOTE. The pulse width test may show failures at the initial threshold settings. However, the test will automatically rerun at other threshold settings where it looks for an overall “pass” at a threshold. You can view the overall pass/fail result at the top of the results for the pulse width test.

11. After the first set of procedures are done, click the Next button to display the instructions for the next step. In most cases you only need to connect a different probe to the test fixture.

12. After changing the connections, click the Next button to continue the procedures.

13. Repeat steps 8 through 9 as indicated by the software.

14. When the software is ready to start the Analog Output to Oscilloscope

procedure, a dialog appears on the screen. This dialog gives you three choices about pausing the procedure. Select one of the options to either pause on failures, pause on every step, or do not pause on any steps (default selection). Then click the Next button to continue.

NOTE. Selecting one of the pause options allows you to manually check the oscilloscope display for pass or fail information. You will not be able to change the pause options until the entire procedure is complete.

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15. After the procedure finishes, click the Next button to open the Finish dialog box where you can save the results to a file. Enter a file name and click the Save button. You can use the Save dialog to save the file to a folder of your choice or use the default location.

16. Click the Finish button to complete the process.

Setup and Hold Procedure

This procedure verifies the setup and hold specification of the logic analyzer module. This procedure can only be verified with the P686x probes. The procedure requires several iterations of connecting and disconnecting probes to the TLACAL2 test fixture.

Equipment Setups Using P686x Probes. It is assumed that the logic analyzer is already connected to the TLACAL2 test fixture and that the performance verification software is installed on the hard disk of the logic analyzer. It is also assumed that the logic analyzer module is installed in the logic analyzer mainframe. The following procedures describe the specific connections from the logic analyzer module to the P686x probes and the TLACAL2 test fixture.

You must start the Performance Verification software in order for the electronic equipment setup instructions to display. (At what point after the PV software begins to run does the customer see the equipment setup instructions?) The system will determine your hardware and adjust the equipment setup instructions accordingly.

NOTE. Make sure that the alignment pin on the P6860 probe head is aligned with the hole on the test fixture. Tighten the probe head screws by alternating between them until they are finger tight (no more than 1 in-lbs of torque).

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Figure 4- 6: P6864 Setup & Hold procedure connections

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Start the Software. Complete the following steps to start the software and to run the procedures:

1. Exit the TLA application on the logic analyzer.

2. Double-click the TLA7Axx Performance Verification icon on the desktop.

An application window similar to Figure 4--2 on page 4--5 appears.

3. If you have more than one logic analyzer module in your mainframe, select the logic analyzer module from the list in the window.

4. Click the Verification button to start the software. A Verification dialog box similar to Figure 4--4 on page 4--17 appears.

5. Verify that Setup and Hold is selected under Setup and Hold Procedures.

6. Clear all other procedures in the dialog box.

7. Click the Next button at the bottom of the dialog box to begin the procedure.

A list of connection instructions displays for the procedure.

8. Verify that your connections match those of the instructions. Then click the Next button to begin the procedure.

The software will begin the procedures and display a list of results in the window.

9. After the first set of procedures are done, click the Next button to display the instructions for the next step. Move the probes on the test fixture as indicated by the instructions.

10. After changing the connections, click the Next button to continue the procedures.

11. Repeat steps 8 through 9 as indicated by the software.

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12. After the procedure finishes, click the Next button to open the Finish dialog box where you can save the results to a file. Enter a file name and click the Save button. You can use the Save dialog to save the file to a folder of your choice or use the default location.

13. Click the Finish button to complete the process.

Logic Analyzer Module Certification

This section describes the procedures to certify the logic analyzer. You can certify the logic analyzer without completing the main performance verification procedures. Table 4--5 lists the certifiable parameters for the logic analyzer.

Table 4- 5: Logic analyzer certification test

Performance verification test name Specification tested

1. Thresholds

Certifiable parameter

Threshold accuracy

Equipment Setups

To certify the logic analyzer module, use the performance verification software and click the Certification button. Perform the required procedure and then print the results to obtain a copy of the software-generated calibration data report.

NOTE. The certification procedures have the same prerequisites as the performance verification procedures. Refer to Prerequisites on page 4--10 for a detailed list of prerequisites.

These procedures require the same setups as described for the Performance Verification procedures. It is assumed that the logic analyzer is already connected to the TLACAL2 test fixture and that the performance verification software is installed on the hard disk of the logic analyzer. It is also assumed that the logic analyzer module is installed in the logic analyzer mainframe. The following procedures describe the specific connections from the logic analyzer module to the probes and the TLACAL2 test fixture.

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CAUTION. If you have any P6041cables connected from the logic analyzer to the TLACAL2 test fixture, always disconnect one end of each P6041 cable before powering down the test fixture.

Always power down the test fixture before connecting or disconnecting ribbon cables. Failure to do so can damage the test fixture, the PIC, or the MICs.

However, there is no need to power down the test fixture if you are only connecting probes, the P6041 cables, or the digital multimeter.

2. Connect the multimeter leads to the DMM test points (J390) on the test fixture. Connect the positive lead to the + connector and the negative (ground) lead to the -- connector.

3. Connect a logic analyzer probe from the logic analyzer C0/C1/C2/C3 input connector (or the C3/C2/A3/A2 connector if you have a 34- or 68-channel module) to the appropriate connectors on the test fixture.

4. If you are using a P6810 probe:

a. Connect the lead sets to the P6810 GAIN & OFFSET Data connections

at J100, J101, J110, and J111 on the test fixture.

b. Connect the clock/qualifier leads to the SNGL square pins at J220. Make

sure that you connect the ground side or the “-- ” side to the square pins with the GND label.

5. If you are using a P686x probe, connect the probe heads to the P6860/80 GAIN & OFFSET connections at J120 and J130 on the test fixture. If you are using a P6880 probe, connect the probe heads to J120, J121, J130, and J131 on the test fixture.

NOTE. Make sure that the alignment pin on the P686x probe head is aligned with the hole on the test fixture. Tighten the probe head screws by alternating between them until they are finger tight (no more than 1 in-lbs of torque).

6. Power on the test fixture, logic analyzer, and other test equipment. Allow all test equipment to warm up for 30 minutes before continuing.

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Start the Software

Complete the following steps to start the software and to run the procedures:

1. Exit the TLA application on the logic analyzer.

2. Double-click the TLA7Axx Performance Verification icon on the desktop.

An application window similar to Figure 4--2 on page 4--5 appears.

3. If you have more than one logic analyzer module in your mainframe, select the logic analyzer module from the list in the window.

4. Click the Certification button to start the software. A Certification dialog box similar to Figure 4--7 appears.

5. Select the probe type near the bottom of the dialog box.

The Threshold Certification Procedure is selected by default.

6. Click the Next button at the bottom of the dialog box to begin the procedure.

A list of connection instructions displays for the procedure.

7. Verify that your connections match those of the instructions. Then click the Next button to begin the certification procedure.

The software will begin the procedures and display a list of results in the window.

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Figure 4- 7: Default Certification procedure dialog box

8. After the first set of procedures are done, click the Next button to display the instructions for the next step. In most cases you only need to connect a different probe to the test fixture.

9. After changing the connections, click the Next button to continue the tests.

10. Repeat steps 8 through 9 as indicated by the software.

11. After the procedure finishes, click the Next button to open the Finish dialog

box where you can save the results to a file. Enter a file name and click the Save button. You can use the Save dialog to save the file to a folder of your choice or use the default location.

12. Click the Finish button to complete the process.

13. Locate the file that you saved in step 11 and print the file for your records.

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CAUTION. Always disconnect one end of each P6041 cable before powering down the TLACAL2 test fixture. Failure to do so can damage the test fixture.

14. Disconnect one end of each P6041 cable before powering down the TLACAL2 test fixture.

15. Power down the TLACAL2 test fixture and then disconnect the remaining test equipment.

This completes the certification procedures.

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Tektronix TLA7ABx, TLA7AAx Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

WARRANTY

Table of Contents

List of Figures

List of Tables

General Safety Summary

Service Safety Summary

Preface

Manual Structure

Manual Conventions

Related Manuals

Contacting Tektronix

Introduction

Adjustment and Certification Interval

Strategy for Servicing

Service Offerings

Specifications

Logic Analyzer Module Description

TLACAL2 Performance Verification and Adjustment Test Fixture Description

Characteristic Tables

Operating Information

Installation

Software Installation

Operating Information

Merged Modules

Theory of Operation

Block Level Description

Local Processor Unit (LPU) Board

Acquisition Board

Probes

Merged Modules

Performance Verification

Summary V erification

Test Equipment

Test Equipment Setup

Functional Verification

Performance Verification Instructions

Performance Verification Procedures

Logic Analyzer Module Certification