Tektronix TLA7AB4, TLA7AA1, TLA7AA2, TLA7AA3, TLA7AA4 Performance Verification

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Tektronix Logic Analyzer Series

ZZZ

Product Speciﬁcations & Performance Veriﬁcation

Technical Reference Manual

This document applies to TLA System Software Version 5.6 or above

www.tektronix.com

077-1763-03

Copyright © Tektronix. All rights reserved. Licensed software products are owned by Tektronix or its subsidiaries or suppliers, and are protected by national copyright laws and international treaty provisions.

Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. Speciﬁcations and price change privileges reserved.

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

MagniVu and iView are registered trademarks of Tektronix, Inc.

Contacting Tektronix

Tektronix, Inc. 14200 SW Karl Braun Drive P.O. B o x 5 0 0 Beaverton, OR 97077 USA

For product information, sales, service, and technical support:

In North America, call 1-800-833-9200. Worl dwid e, vis it www.tektronix.com to ﬁnd contacts in your area.

Warranty 2

Tektronix warrants that this product will be free from defects in materials and workmanship for a period of one (1) year from the date of shipment. If any such product proves defective during this warranty period, Tektronix, at its option, either will repair the defective product w ithout charge for parts and labor, or will provide a replacement in exchange for the defective product. Parts, modules and replacement products used by Tektronix for warranty work may be n the property of Tektronix.

ew or reconditioned to like new performance. All replaced parts, modules and products become

In order to o the warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country in which the Tektronix service center is located. C ustomer shall be responsible for paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.

This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a) to repair damage result b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any damage or malfunction caused by the use of non-Tektronix supplies; or d) to service a product that has been modiﬁed or integrated with other products when the effect of such modiﬁcation or integration increases the time or difﬁculty of servicing the product.

THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THE PRODUCT IN LIEU OF A NY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

TRONIX’ RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE

TEK AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

btain service under this warranty, Customer must notify Tektronix of the defect before the expiration of

ing from attempts by personnel other than Tektronix representatives to install, repair or service the product;

Ta ble of Contents

Preface ............................................................................................................... v

Related Documentation ....................................................................................... v

Speciﬁcations and Characteristics ................. ................................ ............................... 1

Characteri

Atmospheric Characteristics for the Tektronix Logic Analyzer Family...... ........................... 2

TLA7000 System Speciﬁcations.................................................................................. 3

TLA7012 Portable Mainframe Speciﬁcations ................................ .................................. . 9

TLA7016 Benchtop Mainframe Characteristics ....... ................................ ........................ 14

TLA7PC1 Controller Speciﬁcations............................................................................. 19

TL708EX

TLA700 System Speciﬁcations .................... .................................. ............................ 24

TLA715 Dual Monitor Portable Mainframe Speciﬁcations................................................... 29

Benchtop and Expansion Mainframe Speciﬁcations........................................................... 34

TLA721 Dual Monitor Benchtop Controller Speciﬁcations ................ ................................ .. 38

TLA600 Series Speciﬁcations...................... ................................ .............................. 41

Axx/TLANAx Series Logic Analyzer Module Speciﬁcations .. .................................. .... 52

TLA7

TLA7Lx/Mx/Nx/Px/Qx Module Speciﬁcations.......... ................................ ...................... 62

TLA7PG2 Module Speciﬁcations ............................................................................... 68

DSO Module Speciﬁcations .......................... .................................. .......................... 71

External Oscilloscope (iView) Characteristics ................................. ................................ 76

Performance Veriﬁcation Procedures............................................................................ 78

mmary Veriﬁcation ........................................................................................ 78

Test Equipment................................................................................................ 78

Functional Veriﬁcation ..... ................................ ................................ .................. 79

Certiﬁcation ......... .................................. ................................ ........................ 81

Performance Veriﬁcation Procedures ............................... ................................ ........ 81

Calibration Data Report........................................... .................................. .............. 83

TLA7012 and TLA7016 Test Record ............ ................................ .......................... 83

System Clock Test Data............................ .................................. ........................ 83

stic Tables .......................................................................................... 1

TekLink 8-Port Hub Characteristics ................................................................ 22

TLA Product Speciﬁcations & Performance Veriﬁcation i

Table of Contents

List of Figure

Figure 1: Dimensions of the TLA7012 Portable mainframe ................................................. 13

Figure 2: Dimensions of the TLA7016 Benchtop mainframe.............. .................................. 18

Figure 3: Dimensions of the TLA7016 Benchtop mainframe with rackmount option..................... 18

Figure 4: Dimensions of the TLA7PC1 Benchtop PC Controller............................................ 21

Figure 5: Dimensions of TLA715 Portable mainframe ....................................................... 33

Figure 6: Dimensions of the benchtop and expansion mainframe ........................................... 36

Figure 7: Dimensions of the benchtop and expansion mainframe with rackmount option................ 37

Figure 8: Dimensions of the TLA600 series logic analyzer .................... .............................. 51

List of Tables

Table 1: Atmospheric characteristics............................................................................. 2

Table 2: TLA7000 Backplane interface.......................................................................... 3

Table 3: System trigger and external signal input latencies (Typical) ........................................ 4

Table 4: System trigger and external signal output latencies (Typical)............................ ........... 5

Table 5: Intermodule latencies for LA source (Typical)........................................................ 6

Table 6: TLA7000 External signal interface .................................................................... 7

Table 7: TLA7012 Internal controller... ................................ .................................. ....... 9

Table 8: TLA7012 Display system .............. ................................ ................................ 10

Table 9: TLA7012 Front-panel interface ....................................................................... 11

Table 10: TLA7012 Rear-panel interface....................................................................... 11

Table 11: TLA7012 AC power source .......... .................................. .............................. 11

Table 12: TLA7012 Portable mainframe transportation and storage ........................................ 12

Table 13: TLA7012 Cooling . ................................ .................................. .................. 12

Table 14: TLA7012 Mechanical ................................................................................. 13

Table 15: TLA7016 Benchtop mainframe AC power source (Serial numbers B020000 and higher). . . . 14

Table 16: TLA7016 Benchtop mainframe AC power source (Serial numbers B01000 – B019999).. . .. 14

Table 17: TLA7016 Benchtop mainframe transportation and storage..................... .................. 15

Table 18: TLA7016 Benchtop mainframe cooling ............................................................ 15

Table 19: Enhanced monitor ..... ................................ ................................ ................ 16

Table 20: TLA7016 Benchtop mainframe Interface Module front panel characteristics.................. 16

Table 21: TLA7016 Benchtop mainframe mechanical .................................. ...................... 17

Table 22: TLA7PC1 Internal speciﬁcations ...... ................................ .............................. 19

Table 23: External controls and connectors .................................................................... 20

ii TLA Product Speciﬁcations & Performance Veriﬁcation

Table of Contents

Table 24: TLA7P

Table 25: TL708 EX TekLink 8-Port Hub signal switching characteristics ................................ 22

Table 26: TL708EX TekLink 8-Port Hub AC power source characteristics................................ 22

Table 27: TL708EX TekLink 8-Port Hub atmospherics ...................................................... 23

Table 28: TL708EX TekLink 8-Port Hub miscellaneous ..................................................... 23

Table 29: TL708EX TekLink 8-Port Hub mechanical ........................ ................................ 23

Table 30: TLA700 Backplane interface......................................................................... 24

Table 31: TLA700 Backplane latencies................... ................................ ...................... 25

Table 32: TLA700 External signal interface ................................................................... 27

Table 33: TLA715 Internal controller................................... ................................ ........ 29

Table 34: TLA715 display system............................................................................... 30

Table 35: TLA715 front-panel interface ........ ................................ ................................ 31

Table 36: TLA715 rear-panel interface ......................................................................... 31

Table 37: TLA715 AC power source........................ .................................. .................. 31

Table 38: TLA715 cooling ..................... ................................ ................................ .. 32

Table 39: TLA715 mechanical............. ................................ .................................. .... 32

Table 40: Benchtop and expansion mainframe AC power source ........................................... 34

Table 41: Benchtop and expansion mainframe cooling ....... ................................ ................ 34

Table 42: Enhanced monitor ............... ................................ ................................ ...... 35

Table 43: Benchtop and expansion mainframe mechanical................................................... 35

Table 44: TLA721 benchtop controller characteristics........................................................ 38

Table 45: Front panel characteristics ............................................................................ 40

Table 46: TLA600 input parameters with probes.......... ................................ .................... 41

Table 47: TLA600 timing latencies ............................................................................. 41

Table 48: TLA600 external signal interface ............................ ................................ ........ 42

Table 49: TLA600 channel width and depth ................................................................... 43

Table 50: TLA600 clocking ...................................................................................... 44

Table 51: TLA600 trigger system ............................................................................... 45

Table 52: TLA600 MagniVu feature ............................................................................ 47

Table 53: TLA600 Data handling................................................................................ 47

Table 54: TLA600 internal controller............. .................................. ............................ 47

Table 55: TLA600 display system............................................................................... 48

Table 56: TLA600 front-panel interface ........ ................................ ................................ 49

Table 57: TLA600 rear-panel interface ......................................................................... 49

Table 58: TLA600 AC power source........................ .................................. .................. 50

Table 59: TLA600 cooling ..................... ................................ ................................ .. 50

Table 60: TLA600 mechanical characteristics ................................................................. 50

Table 61: TLA7Axx/TLA7NAx input parameters (with probes) ............................................ 52

Table 62: TLA7Axx analog output...... ................................ .................................. ...... 53

Table 63: Channel width and depth...................................... ................................ ........ 53

Table 64: Clocking ........................ ................................ ................................ ........ 53

C1 mechanical................................................................................. 21

TLA Product Speciﬁcations & Performance Veriﬁcation iii

Table of Contents

Table 65: TLA7A

Table 66: MagniVu acquisition . . ..... . ..... . ..... . ... . . . .... . ..... . ..... . ..... . ..... . .... . ..... . ..... . ..... . ... . 60

Table 67: Merged modules ..... ................................ ................................ .................. 60

Table 68: Data placement............................. .................................. .......................... 61

Table 69: NVRAM .......... ................................ ................................ ...................... 61

Table 70: Mechanical ............................................................................................. 61

Table 71: LA

Table 72: LA module clocking............................. ................................ ...................... 62

Table 73: LA module trigger system .................... ................................ ........................ 64

Table 74: LA module MagniVu feature....... ................................ ................................ .. 66

Table 75: LA module data handling..................... .................................. ...................... 66

Table 76: LA module input parameters with probes........................................................... 66

Table 77

Table 78: PG module electrical speciﬁcation, operational mode................... .......................... 68

Table 79: PG module clocking................................................................................... 69

Table 80: PG module event processing ......................................................................... 70

Table 81: PG module inter-module interactions ............................................................... 70

Table 82: PG module merged PG modules ............. ................................ ........................ 70

Tabl

Table 84: DSO module signal acquisition system .... . ..... . ..... . ... . . . .... . ..... . ..... . ..... . ..... ..... . .... 71

Table 85: DSO module timebase system ....................................................................... 73

Table 86: DSO module trigger system .. ................................ ................................ ........ 73

Table 87: DSO module front-panel connectors ................................................................ 75

Table 88: DSO module mechanical ............................................................................. 75

Table 90: TDS1000B, TDS2000B, TDS1000, and TDS2000 Series oscilloscope waveform edge

Table 91: Test equipment................... ................................ ................................ ...... 78

Table 92: Functional veriﬁcation procedures................. ................................ .................. 79

Table 93: Performance veriﬁcation procedures ........ ................................ ........................ 81

: LA module mechanical ..... .................................. ................................ ........ 67

e 83: PG module mechanical...................................... ................................ .......... 70

ble 89: External oscilloscope (Integrated View or iView) characteristics... . ..... . .... . ..... . ..... ..... . 76

alignment ...................................................................................................... 77

xx/TLA7NAx module trigger system ...................................................... 58

module channel width and depth .................... ................................ ............ 62

iv TLA Product Speciﬁcations & Performance Veriﬁcation

Preface

This document lists characteristics and speciﬁcations of the following Tektronix Logic Analyzer Family products:

TLA7000 series mainframes

TLA7PC1 Controller

TL708EX TekLink 8-Port Hub

TLA700 series mainframes

lated Documentation

TLA600 se

TLA7Axx/TLA7Nx series logic analyzer modules

TLA7Lx/Mx/Nx/Px/Qx series logic analyzer modules

TLA7PG2 pattern generation modules

DSO digital storage oscilloscope modules

Other Tektronix Logic Analyzer modules, microprocessor-related products, and individual logic analyzer probes have their own documentation for characteristics and speciﬁcations.

This document also contains performance veriﬁcation procedures for the TLA7000 Series mainframes.

To prevent personal injury or damage consider the following requirements before attempting service:

Read the General Safety Summary and Service Safety Summary found in the

Tektronix Logic Analyzer Family Product Safety & Compliance Instructions

(Tektronix part number 071-2591-xx).

ries logic analyzers

Refer to the individual service manuals for the performance veriﬁcation procedures and adjustment procedures for earlier TLA products.

The following table lists related documentation available for your logic analyzer. The documentation is available on the TLA Documentation CD and on the Tektronix Web site (www.tektronix.com/manuals).

You can also check the release notes on the instrument for additional information. To access the release notes, select Start > All Programs > Tektronix Logic Analyzer > TLA Release Notes.

TLA Product Speciﬁcations & Performance Veriﬁcation v

Preface

Related Docume

Item Purpose Location

TLA Quick Star

Online Help

Installati

Installation Manuals

XYZs of Logic Analyzers

Declassiﬁcation and Securities instructions

Applicat

Product Speciﬁcations & Performance Veriﬁcation Procedures

on Quick Reference Cards

ion notes

ntation

t User Manuals

High-level operational overview

In-depth operation and UI help

High-level

Detailed ﬁrst-time installation information

Logic anal

Data security concerns speciﬁcto sanitizing or removing memory devices from Tektronix products

Collection of l ogic analyzer application speciﬁc notes

TLA Product speciﬁcations and performance veriﬁcation procedures

installation information

yzer basics

TPI.NET Documentation

Field upgrade kits

nal Service Manuals

Optio

Detailed information for controlling the

nalyzer using .NET

logic a

Upgrade information for your logic analyzer

service documentation for modules

Selfand mainframes

vi TLA Product Speciﬁcations & Performance Veriﬁcation

Speciﬁcations and Characteristics

This document lists the speciﬁcations for the Tektronix Logic Analyzer mainframes and other logic analyzer products. Additional speciﬁcation documents ar Web site. For the most current documentation, refer to the Tektronix Web site (http://www.Tektronix.com).

Characteristic Tables

All speciﬁcations are guaranteed unless noted Typical . Typical characteristics describe typical or average performance and provide useful reference information.

e available on the TLA Documentation CD or on the Tektronix

Speciﬁcations that are marked with the indirectly) using performance veriﬁcation procedures.

For mainframes and modules, the performance limits in this speciﬁcation are valid with these conditions:

The logic analyzer must be in an environment with temperature, altitude, humidity, and vibration within the operating limits described in these speciﬁcations.

The logic analyzer must have had a warm-up period of at least 30 minutes.

For modules, the performance limits in this speciﬁcation are valid with these conditions:

The modules must be installed in a Logic Analyzer Mainframe.

The module must have been calibrated/adjusted at an ambient temperature between +20 °C and +30 °C.

The DSO module must have had its signal-path-compensation routine (self calibration or self cal) last executed after at least a 30 minute warm-up period.

After the warm-up period, the DSO module must have had its signal-path-compensation routine last executed at an ambient temperature within ±5 °C of the current ambient temperature.

symbol are checked directly (or

For optimum performance using an external oscilloscope, please consult the documentation for any external oscilloscopes used with your Tektronix Logic Analyzer to determine the warm-up period and signal-path compensation requirements.

TLA Product Speciﬁcations & Performance Veriﬁcation 1

Speciﬁcations and Characteristics

Atmospheric C

haracteristics for the Tektronix Logic Analyzer Family

The following table lists the Atmospheric characteristics of components in the Tektronix Logic Analyzer family.

Table 1: Atm

Characteristic Description

Temperatur

Relative Humidity

tude

Alti

For TLA7012 instruments, the operating temperature is +5 °C to +45 °C, 11 °C/hr maximum gradient, noncondensing (derated 1 °C per 1000 ft above 5000 ft (1524 m) altitude)

TLA7Axx series module operating temperature is +40 °C maximum.

A7Axx series module operating humidity is 5% to 90% up to +30 °C, 75% from +30 to +40 °C, noncondensing. Maximum wet-bulb temperature is +29.4 °C.

TLA7NAx series module operating humidity is 5% to 90% up to +30 °C, 75% from +30 to +40 °C, 45 % from +40 to +50 °C, noncondensing. Maximum wet-bulb temperature is +29.4 °C.

TLA7Axx/TLA7NAx series module nonoperating humidity is 5% to 90% limited by a wet bulb temperature of +40 °C.

ospheric characteristics

Operating (no media in CD or DVD drive)

+5 °C to +50 °C, 15 °C/hr maximum gradient, noncondensing (derated 1 °C per 305 m (1000 ft) above 1524 m (5000 ft) altitude)

Nonoperating (no media in drive)

-20 °C to +60 °C, 15 °C/hr maximum gradient, noncondensing

Operating (no media in drive)

20% to 80% relative humidity, noncondensing. Maximum wet bulb temperature: +29 °C (derates relative humidi

Nonop

8% to 8 humidity to approximately 22% at +50 °C).

Operating

To 3000 m (9843 ft), (derated 1 °C per 305 m (1000 ft) above 1524 m (5000 ft) altitude.

Non

190 m (40,000 ft )

12,

ty to approximately 22% at +50 °C).

erating (no media in drive)

0% relative humidity, noncondensing. Maximum wet bulb temperature: +29 °C (derates relative

operating

2 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7000 System Speciﬁcations

TLA7000 Syste

m Speciﬁcations

The followin

g tables list the speciﬁcations common to the TLA7000 series logic

analyzers.

Table 2: TLA7000 Backplane interface

Characteristic Description

Number of Slots Portable mainframe

Benchtop m

CLK10 Frequency

Relative Time Correlation

Error

(Typical)

Includes typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a "typical" number for the measurement. Assumes standard accessory probes are utilized.

r time intervals longer than 1 ms between modules, add 0.01% of the difference between the absolute time measurements to the relative time correlation

Fo error to account for the inaccuracy of the CLK10 source.

TLA7Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx "MagniVu" data

TLA7Axx/TLA7NAx to TLA7AxxTLA7NAx "MagniVu" data

TLA7Axx/TLA7NAx to TLA7Nx/Px/Qx "MagniVu" data

TLA7Nx/Px/Qx to TLA7Nx/Px/Qx "normal" data using an internal clock

TLA7Axx/TLA7NAx to TLA7Axx "normal" data using an internal clock

TLA7Axx/TLA7NAx to TLA7Nx/Px/Qx "normal" data using an internal clock

TLA7Nx/Px/Qx to TLA7Nx/Px/Qx "normal" data using an external clock

TLA7Axx/TLA7NAx to TLA7Axx/TLA7NAx "normal" data using an e xternal clock

TLA7Axx/TLA7NAx to TLA7Nx/Px/Qx "normal" data using an external clock

ainframe

10 MHz ±100 ppm

2ns

-3 ns

1 TLA7Nx/Px/Qx sample – 0.5 ns

1 TLA7Axx/TLA7NAx sample – 0.5 ns

1 TLA7Nx/Px/Qx sample – 0.5 ns

2ns

4ns

TLA Product Speciﬁcations & Performance Veriﬁcation 3

TLA7000 System Speciﬁcations

Table 3: System

Logic analyzer s ou rce characteristic

External syst

TLA7Nx/Px/Q

TLA7AAx/TL

trigger and external signal input latencies (Typical)

em trigger input to LA probe tip

x modules

A7NAx modules

Same mainframe To expansion frame

–266 ns –202 ns

–626 ns –562 ns

TLA7BBx modules –1202 ns –1143 ns

TLA7Sxx modules

External Signal In to LA probe tip via Signals 3, 4 (TTLTRG 0,1)

–958 ns ±30 ns –1221 ns ±30 ns

TLA7Nx/Px/Qx modules –212 ns + Clk –148 ns + Clk

TLA7AAx/TLA7NAx modules –535 ns + Clk –471 ns + Clk

TLA7BBx modules

TLA7Sxx modules

External Signal In to LA probe tip via Signals 1, 2(ECLTRG 0,1)

–1190 ns + Clk –1118 ns + Clk

–950 ns ±30 ns –1220 ns ±30 ns

TLA7Nx/Px/Qx modules –208 ns + Clk –144 ns + Clk

TLA7AAx/TLA7NAx modules –627 ns + Clk –556 ns + Clk

TLA7BBx modules

TLA7Sxx modules

All system trigger and signal input latencies were measured from a falling edge transition (active true low) with signals in the wired-OR conﬁguration.

In the Waveform window, triggers are always marked immediately except when delayed to the ﬁrst sample. In the Listing window, triggers are always marked on the next sample period following their occurrence.

Clk represents the time to the next master clock at the destination logic analyzer module. With asynchronous clocking this represents the delta time to the next sample clock. With synchronous sampling this represents the time to the next master clock generated by the setup of the clocking state machine and the

plied SUT clocks and qualiﬁcation data.

sup

Signals 1 and 2 (ECLTRG0, 1) are limited to a broadcast mode where only one source can drive the signal node at any one time. The signal source can be used to drive any combination of destinations.

–1186 ns + Clk –1043 ns + Clk

–950 ns ±30 ns –1116 ns ±30 ns

4 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7000 System Speciﬁcations

Table 4: System

Logic analyzer source characteristic

LA probe tip to external system trigger out (skid)

trigger and external signal output latencies (Typical)

Same mainframe To expansion frame

TLA7Nx/Px/Qx modules 376 ns + Smpl 437 ns + Smpl

TLA7AAx/TLA7NAx modules 794 ns + Smpl 854 ns + Smpl

TLA7BBx mod

TLA7Sxx modules

LA probe tip to External Signal Out via Signal 3, 4 (TTLTRG 0,1)

ules

1332 ns + Smpl 1392 ns + Smpl

1170 ns ±30

1230 ns ±30

OR function

TLA7Nx/Px/Qx modules 366 ns + S mpl 428 ns + Smpl

TLA7AAx/TLA7NAx modules 793 ns + S mpl 854 ns + Smpl

TLA7BBx modules

TLA7Sxx modules

1328 ns + Smpl 1390 ns + Smpl

950 ns ±30 ns 1011 ns ±30 ns

AND function

TLA7Nx/Px/Qx modules 379 ns + S mpl 457 ns + Smpl

TLA7AAx/TLA7NAx modules 803 ns + S mpl 881 ns + Smpl

TLA7BBx modules

TLA7Sxx modules

LA probe tip to External Signal Out via Signals 1, 2 (ECLTRG0,1)

1340 ns + Smpl 1418 ns + Smpl

950 ns ±30 ns 1028 ns ±30 ns

TLA7Nx/Px/Qx modules 374 ns + Smpl 444 ns + Smpl

TLA7AAx/TLA7NAx modules 793 ns + Smpl 863 ns + Smpl

TLA7BBx modules

TLA7Sxx modules

SMPL represents the time from the event to the next valid data sample at the probe tip of the LA module. With asynchronous sampling, this represents the delta time to the next sample clock. With MagniVu asynchronous sampling, this represents 500 ps or less. With synchronous sampling, this represents the timetothe next master clock generated by the setup of the clocking state machine, the system-under-test supplied clocks, and the qualiﬁcation data.

Skid is commonly referred to as the system level system trigger and signaling output latency. This is the absolute time from when the event ﬁrst appears at the input probe tips of a module to when the corresponding event that it generates appears at the system trigger or external signal outputs.

All signal output latencies are validated to the rising edge of an active (true) high output.

Signals 1 and 2 (ECLTRG0, 1) are limited to a broadcast mode where only one source can drive the signal node at any one time. The signal source can be used to drive any combination of destinations.

1330 ns + Smpl 1399 ns + Smpl

950 ns ±30 ns 1019 ns ±30 ns

TLA Product Speciﬁcations & Performance Veriﬁcation 5

TLA7000 System Speciﬁcations

Table 5: Interm

odule latencies for LA source (Typical)

Logic analyzer source characteristic Same mainframe Frame to frame

LA to LA intermodule system trigger (TTLTRG7)

LA2: Trigger All Modules, LA1: Do Nothing

TLA7Nx/Px/Qx modules 66 ns + Smpl 128 ns + Smpl

TLA7AAx/TLA7ABx modules 108 ns + Smpl 118 ns + Smpl

TLA7BBx modules

TLA7Sxx modules

LA to LA intermodule ARM (TTLTRG 2, 4 ,5, 6)

82 ns + Smpl 145 ns + Smpl

105 ns ±30 nsl 167 ns ±30 ns

TLA7Nx/Px/Qx modules 108 ns + Smpl + Clk 170 ns + Smpl +Clk

TLA7AAx/TLA7ABx modules 115 ns + Smpl + Clk 180 ns + Smpl + Clk

TLA7BBx modules

TLA7Sxx modules

LA to LA intermodule Signals 1, 2 (ECLTRG 0, 1)

Trigger, Then Set Signal 2; LA1: If Signal 2 Is True, Then Trigger)

(LA2:

Nx/Px/Qx modules

TLA7

AAx/TLA7ABx modules

TLA7

234

TLA7BBx modules

7Sxx modules

TLA

to LA intermodule Signals 3, 4 (TTLTRG0,1)

95 ns + Smpl + Clk 162 ns + Smpl +Clk

85 ns ±30 ns 147 ns ±30 ns

s + Smpl + Clk

116 n

s + Smpl + Clk

118 n

s + Smpl + Clk

95 n

s + Smpl + Clk

178 n

s + Smpl + Clk

192 n

ns + Smpl + Clk

166

130 ns ±30 ns 192 ns ±30 ns

(LA2: Trigger, Then Set Signal 3; LA1: If Signal 3 Is True, Then Trigger)

TLA7Nx/Px/Qx modules 116 ns + Smpl + Clk 128 ns + Smpl + Clk

TLA7AAx/TLA7ABx modules 120 ns + Smpl + Clk 184 ns + Smpl + Clk

TLA7BBx modules

TLA7Sxx modules

Clk represents the time to the next master clock at the destination logic analyzer module. With ascynchronous clocking this represents the delta time to the next sample clock. With synchronous sampling this represents the time to the next master clock generated by the setup of the clocking state machine and the supplied SUT clocks and qualiﬁcation data.

Signals 1 and 2 (ECLTRG0, 1) are limited to a broadcast mode where only one source can drive the signal node at any one time. The signal source can be used to drive any combination of destinations.

91 ns + Smpl + Clk 158 ns + Smpl + Clk

950 ns ±30 ns 1012 ns ±30 ns

6 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7000 System Speciﬁcations

Table 6: TLA700

0 External signal interface

Characteristic Description

System Trigger Input

TTL compatible input via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe)

Input levels 0 V to 3.0 V

Minimum inp

ut voltage

300 mV

swing

Threshold r

ange

0.5 V to 1.5 V

Threshold step size 50 mV

Input destination

Input Mode

System trigger

Falling edge sensitive, latched (active low)

Minimum Pulse Width 12 ns

Active Pe

riod

Accepts s

ystem triggers during valid acquisition periods via real-time

gating, resets system trigger input latch between valid acquisition periods

Input Voltage

0to+5Vp

TTL com

patible input via rear panel mounted BNC connectors (portable

Extern

Maximum

al Signal Input

mainframe) or front panel mounted SMB connectors (benchtop mainframe)

estination

Input D

levels

Input

Minimum input voltage

Signal 1, 2, 3, 4

.0 V

0Vto3

300 mV

swing

Threshold range 0.5 V to 1.5 V

Threshold step size 50 mV

t Mode

Inpu

ut Bandwidth

Inp

Active (true) low, level sensitive

Signal 1, 2 Signal 3, 4

Hz square wave minimum

50 M

Active Period Accepts signals during valid acquisition periods via real-time gating

Maximum Input Voltage 0 V to 5 V peak

System Trigger Output

TTL compatible output via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe)

Source selection System trigger

Source Mode Active (true) low, falling edge latched

Active Period

Outputs system trigger state during valid acquisition period, resets system trigger output to false state between valid acquisitions

Output Levels VOHV

50 Ω back terminated TTL-compatible output

≥4 V into open circuit, ≥2Vinto50Ω to ground

≤ 0.7Vsinking10mA

Output Protection Short-circuit protected (to ground)

eak

Hz square wave minimum

10 M

TLA Product Speciﬁcations & Performance Veriﬁcation 7

TLA7000 System Speciﬁcations

Table 6: TLA7000 External signal interface (cont.)

Characteristic Description

External Signal Output

Source Selection Signal 1, 2

Output Modes

Level Sensitive

Output Levels VOHV

Active Period

Output Protection Short-circuit protected (to ground)

Intermodule Signal Line Bandwidth

The Input Bandwidth speciﬁcation only applies to signals to the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output.

The Output Bandwidth speciﬁcation only applies to signals from the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output.

TTL compatible outputs via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe)

Signal 3, 4

10 MHz clock

User deﬁnable

Active (true) low or active (true) high

50 Ω back terminated TTL output

≥4 V into open circuit, ≥2Vinto50Ω to ground

≤ 0.7Vsinking10mA

Signal 1, 2 Signal 3, 4Output Bandwidth

50 MHz square wave minimum 10 MHz square wave minimum

Outputs signals during valid acquisition periods, resets signals to false state between valid acquisitions Outputs 10 MHz clock continuously

Minimum bandwidth up to which the intermodule signals are speciﬁed to operate correctly

Signal 1, 2 Signal 3, 4

50 MHz square wave minimum 10 MHz square wave minimum

8 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7012 Portable Mainframe Speciﬁcations

TLA7012 Porta

ble M ainframe Speciﬁcations

The followin

g tables describe the speciﬁcations for the TLA7012 Portable

Mainframe.

Table 7: TLA7012 Internal controller

Characteristic D escription

Operating system Microsoft Windows XP Professional

Motherboard

Microprocessor

Chip set Intel 915GM GMCH with an Intel ICH6-M I/O hub. Supports dual channel

Main memory

Cache memory 2 MB Level 2 (L2) write-back cache

RTC, CMOS setup, & PNP NVRAM retention time

ical)

(Typ

Bootable replaceable

ddiskdrive

har

rmatted capacity

nterface

Average seek time Read 9 ms

DVD-RW drive

The AB915GM motherboard is an ATX-family board that meets the FlexATX a Intel Mobil Celeron M or Pentium M processor and an Intel 915GM chipset, integrating video, system monitoring, and Ethernet controllers on a 9.0 X

7.5 inch b

Intel 2 G processor package

memory for higher performance.

Two 200 pin SO DIMM sockets for DDR2-400/533 (PC2-3200/4300) modul

Maximum 2 GB (two modules, Gbit technology), minimum 128 MB

Installed Conﬁguration 1 GB

> 5 years battery life, lithium battery

Sta drive residing on an EIDE interface.

80 GB

Continually subject to change due to the fast-moving PC component en

ATA, native

Standard PC compatible IDE (Integrated Device Electronics) DVD-RW drive residing on an EIDE interface.

Continually subject to change due to the fast-moving PC component environment.

nd microATX form-factor speciﬁcations. It is based around an

oard.

Hz/533 Dothan microprocessor; 479-pin PGA socket for uFC-PGA

es.

ndard PC compatible IDE (Integrated Device Electronics) hard disk

vironment. These storage capacities valid at product introduction.

rite 10 ms

TLA Product Speciﬁcations & Performance Veriﬁcation 9

TLA7012 Portable Mainframe Speciﬁcations

Table 8: TLA701

Characteristic Description

Display selec

External display drive

Internal display

2 Display system

tion

The TLA7012 Portable Mainframe motherboard can drive 3 video displays.

Two DVI conne connectors has both the DVI digital signals and the analog signals while the other connector has only DVI digital signals available.

The third di This connection is via LVDS. This port drives the internal 15-inch display. One of the external connectors and the internal connection are connected t

One VGA, SV

Primary video port with DVI

nly

digital o

Secondary video port with

ital and analog

DVI dig VGA signalling through an adapter

Classiﬁcation Color LCD (NEC TFT NL10276BC30-24D)

Resolution/Refresh rate and area

lor scale

on (Pixels)

Resoluti

640 x 480

1024 x 768

1280 x 1024

1600 x 1200

Resolution (Pixels) Colors Refresh Rates

640 x 480

1024 x 768

1280 x 1

1600 x 1200

Maximum resolution on the analog VGA is 1600 x 1200 with 32-bit color at 75 Hz.

Colo silicon thin ﬁlm transistor liquid crystal display (a-Si TFT LCD) panel structure with driver LSIs for driving the TFT (Thin Film Transistor) arr motherboard via LVDS signaling.

1024 pixels horizontal by 768 pixels vertical (1024X 768) at 60 Hz refresh rate

26 NTSC

024

r LCD module NL10276BC30-24D is composed of the amorphous

ay and a backlight. This LCD display will be driven directly by the

ea of 304 mm (11.7 in) by 228 mm (9 in) of viewing area.

2, 144 colors (6-bit RGB) with a color gamut of 42% at center to

ctors connect to the external world. One of the

splay connector is available only as an internal connection.

o the same video information.

GA, or XGA-compatible analog output port.

Colors Refresh R

256, 16-bit, 32-bit 60, 75, 85

60, 75, 85

256, 16-bit, 32-bit 60, 75, 85

60, 75, 85

60, 75,

ates

10 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7012 Portable Mainframe Speciﬁcations

Table 9: TLA701

2 Front-panel interface

Characteristic Description

Keypad

18 buttons allow user to perform the m ost common tasks required to operate theTLA

Special function knobs

Multi-function Knob Various increment, decrement functions dependent on screen/window

selected.

Vertical position

Vertical scale

Horizontal position

Horizontal scale

Scrolling a

Scales wav

Scrolling

Scales wa

USB Port Front pa

nd positioning dependent on display type.

eform displays only.

and positioning dependent on display type.

veform displays only.

nel (lower Right on Front Panel) 3 each USB 2.0 connectors.

Table 10: TLA7012 Rear-panel interface

Characteristic Description

TekLink interface bus

Input signal characteristics

Output signal characteristics LVDS compatible outputs via rear-panel 40-pin connector

Reference clock characteristics LVDS compatible inputs via rear-panel 40-pin connector

SVGA output ports

External Trigger input Trigger input routed to the system trigger line

External Signal input Signal input routed to one of four internal signals

System Trigger output

External Signal output One of four internal signals routed to the signal output connector. The

USB 2.0 ports Four USB 2.0 connections

GBit LAN port RJ-45 connector 10/100/1000 Mbps

Connector supports Reference Clock (10 MHz), Power On Signaling, Run event, System Trigger, General purpose events

LVDS compatible inputs via rear-panel 40-pin connector

Two DVI connectors

Internal system trigger routed as TTL-compatible output

internal 10 MHz reference clock can be routed to this output.

Table 11: TLA7012 AC power source

Characteristic D escription

Source voltage and frequency 100 V

115 V

to 240 V

RMS

±10%, 400 Hz

RMS

±10%,50Hzto60Hz

RMS

Maximum power consumption 750 W

Steady-state input current 6 A

maximum at 90 VAC

RMS

, 60 Hz or 100 VAC

RMS

, 400 Hz

RMS

Inrush surge current 70 A maximum

Power factor correction

Yes

TLA Product Speciﬁcations & Performance Veriﬁcation 11

TLA7012 Portable Mainframe Speciﬁcations

Table 11: TLA7012 AC power source (cont.)

Characteristic D escription

On/Sleep indicator Green/yellow front panel LED located left of the On/Standby switch

provides visual feedback when the switch is actuated. When the LED is green, the instrument is powered and the processor is not sleeping. When the LED is yellow, the instrument is powered, but the processor is sleeping.

On/Standby switch and indicator Front panel On/Standby switch allows users to turn the instrument on. A

soft power down is implemented so that users can turn the instrument off without going through the Windows shutdown process; the instrument powers down normally.

The power cord provides main power disconnect

Table 12: TLA7012 Portable mainframe transportation and storage

Charact

Transportation Package Material Transportation Package material meets recycling criteria as described

Conﬁguration for Transportation The system can be shipped with or without modules installed. Only

eristic

Descrip

in Envi 063-1290-00) and Environmentally Responsible Packaging Handbook (Tektronix part number 063-1302-00).

modul 60g shock (per Tektronix Standard part number 062-2858-00, Rev B, Class 5 subassembly requirement) can be shipped installed in this mainframe and i

tion

ronmental Guidelines for Package Design (Tektronix part number

es weighing less than 5lbs/slot which have been qualiﬁed to meet

ts standard shipping package.

Table 13: TLA7012 Cooling

Characteristic Description

Cooling system Forced air circulation system with no removable ﬁlters using eight fans

operating in parallel

Pressurization Negative pressurization system in all chambers including modules

Slot activation Installing a module activates cooling for the corresponding occupied slots

by opening the airﬂow shutter mechanism. Optimizes cooling efﬁciency by only applying airﬂow to installed modules.

Air intake Front sides and bottom

Air exhaust Back rear

Cooling clearance 6 inches (152 mm) front, sides, top, and rear. Prevent blockage of airﬂow

to bottom of instrument by placing on a solid, noncompressable surface; can be operated on rear feet.

Fan speed and operation

All fans operational at half their rated potential and speed (12 VDC)

12 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7012 Portable Mainframe Speciﬁcations

Table 14: TLA70

Characteristic D escription

Classiﬁcation The portable mainframe is intended for design and development bench

Overall dimensions

Weight

Shipping conﬁguration 58 lbs (26.30 kg) minimum conﬁguration (no modules), with all standard

Acoustic noise level (Typical) 43 dBA weighted (operator) 41 dBA weighted (bystander)

Construction materials Chassis parts are constructed of aluminum alloy; front panel and trim

Finish type

12 Mechanical

Height (wit

Width

Depth

h feet)

and lab-based applications.

Dimensions are without front feet extended, front cover attached, pouch attached, n

11.6 in (294

17.75 in (450.85 mm)

18.1 in (459.74 mm)

40 lbs 12 oz (18.45 kg) with no modules installed, two dual-wide slot covers, a

5 lbs (2.27 kg) maximum per module slot

accessories

89 lbs 8 o standard accessories (including probes and clips)

peaces are constructed of plastic; circuit boards are constructed of glass.

Tektronix blue body and Tektronix silver-gray trim and front with black pouch

or power cord attached.

.64 mm)

nd empty pouch

z (41.6 kg) full conﬁguration, with two TLA7P4 modules and

, FDD feet, handle, and miscellaneous trim pieces

gure 1: Dimensions of the TLA7012 Portable mainframe

TLA Product Speciﬁcations & Performance Veriﬁcation 13

TLA7016 Benchtop Mainframe Characteristics

TLA7016 Bench

top Mainframe Characteristics

The followin

g tables list the speciﬁcations for the TLA7016 Benchtop Mainframe. The mainframe includes the interface module. The interface module provides the interface between an external controller and the mainframe. All communication between the controller and the mainframe is via GB LAN.

Table 15: TLA7016 Benchtop mainframe AC power source (Serial numbers B020000 and higher)

Characteristic Description

Source voltage & Maximum power consumption

100 V

120 V

115 V

to 120 V

RMS

to 240 V

RMS

, 440 Hz; 1450 W line power

RMS

, 50 Hz to 60 Hz; 1450 W line power

RMS

, 50 Hz to 60 Hz; 1900 W line power

RMS

Inrush surge current 70 A maximum

Steady state input current 17.6 A

10 A

Powerfactorcorrection(Typical)

0.99 at 60 Hz operation and 0.95 at 400 Hz operation

maximum at 108 VAC

RMS

maximum at 207 VAC

RMS

ON/Standby switch and indicator Front Panel On/Standby switch with integral power indicator.

Switch allows users to turn the instrument on. A soft power down is implemented so that users c an turn off the instrument without going through the Windows shutdown process; the instrument powers down normally.

Maximum power consumed by a fully loaded six-module instrument.

Table 16: TLA7016 Benchtop mainframe AC power source (Serial numbers B01000 – B019999)

Characteristic Description

Source voltage 100 V

100 V

Maximum power consumption

1450 W line power (the maximum power consumed by a fully loaded, 6-module instrument)

Fuse rating (Current and voltage ratings and type of fuse used to fuse the source line voltage)

90 V - 132 VAC

RMS

Operation High-power/Low line (159-0379-00)

Safety: UL198G/CSA C22.2

Size: 0.25 in × 1.25 in

Style: Slow acting

Rating: 20 A/250 V

103 V - 250 VAC

RMS

Operation (159-0256-00)

Safety: UL198G/CSA C22.2

Size: 0.25 in × 1.25 in

Style: No. 59/Fast acting

Rating: 15 A/250 V

207 V - 250 VAC

RMS

Operation (159-0381-00)

Safety: IEC 127/Sheet 1

Size: 5 mm × 20 mm

Style: Fast acting "F", high-breaking capacity

Rating: 6.3 A/250 V

RMS

to 240 V

to 120 V

±10%,45Hzto66Hz

RMS

, 360 Hz to 440 Hz

RMS

14 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7016 Benchtop Mainframe Characteristics

Table 16: TLA7016 Benchtop mainframe AC power source (Serial numbers B01000 – B019999) (cont.)

Characteristic Description

Inrush surge current 70 A maximum

Steady state input current 16.5 A

6.3 A

Power factor correction (Typical)

0.99 at 60 Hz operation and 0.95 at 400 Hz operation

maximum at 90 VAC

RMS

maximum at 207 VAC

RMS

ON/Standby switch and indicator Front Panel On/Standby switch with integral power indicator.

Switch allows users to turn the instrument on. A soft power down is implemented so that users can turn off the instrument without going through the Windows shutdown process; the instrument powers down normally.

Table 17: TLA7016 Benchtop mainframe transportation and storage

Characteristic Description

Transportation Package Material Transportation Package material meets recycling criteria as described

in Environmental Guidelines for Package Design (Tektronix part number 063-1290-00) and Environmentally Responsible Packaging Handbook (Tektronix part number 063-1302-01).

Conﬁguration for Transportation The system can be shipped with or without modules installed. Only

modules weighing less than 5lbs/slot which have been qualiﬁed to meet 60g shock (per Tektronix Standard part number 062-2858-00, Rev B, Class 5 ’subassembly’ requirement) can be shipped installed in this mainframe and its standard shipping package.

Table 18: TLA7016 Benchtop mainframe cooling

Characteristic Description

Cooling system Forced air circulation system (positive pressurization) using a single

low-noise centripetal (squirrel cage) fan conﬁguration with no ﬁlters for the power supply and 13 module slots.

Fan speed control

Slot activation Installing a module activates the cooling for the corresponding occupied

Pressurization Positive pressurization system, all chambers including modules

Slot airﬂow direction P2 to P1, bottom of module to top of module

Mainframe air intake Lower fan-pack rear face and bottom

Mainframe air exhaust

D Temperature readout sensitivity (Typical) 100 mV/ °C with 0 °C corresponding to 0 V output

Temperature sense range (Typical) -10 °C to + 90 °C, delta temperature ≤ 50 °C

Clearance 2 in (51 mm), rear, top, and sides

Rear panel switch selects between full speed and variable speed. Slot exhaust temperature and ambient air temperature are monitored such that a constant delta temperature is maintained.

slots by opening the air ﬂow shutter mechanism. Optimizes cooling efﬁciency by only applying airﬂow to modules that are installed.

Top-sides and top-rear back. Top rear-back exhaust redirected to the sides by the fan pack housing to minimize reentry into the intake.

TLA Product Speciﬁcations & Performance Veriﬁcation 15

TLA7016 Benchtop Mainframe Characteristics

Table 18: TLA7016 Benchtop mainframe cooling (cont.)

Characteristic Description

Fan speed readout

RPM = 20 (Tach frequency) or 10 ≥ (+Pulse Width)

where (+Pulse Width) is the positive width of the TACH1 fan output signal measured in seconds

Fan speed range 650 to 2250 RPM

Table 19: Enhanced monitor

Characte

ristic

Voltage readout

Descript

+24 V, -2 +5 V

ion

4V,+12V,-12V,+5V,-5.2V,-2V,+5V

via RS-232

External

if present, and

Standby

Voltage readout accuracy (Typical) ±3% maximum

Current readout Readout of the present current on the +24 V, -24 V, +12 V, -12 V, +5 V,

-2 V, -5.2 V rails via RS-232

Current readout accuracy (Typical) ±5% of maximum power supply I

Provides access for RS-232 host to enhanced monitorRS-232 Connector

Connector levels ±25 VDC maximum, 1 A maximum per pin

Passive monitor c onnector

25-pin connector provides access for monitoring the power supply,

perature, and fan speed.

tem

Table 20: TLA7016 Benchtop mainframe Interface Module front panel characteristics

Characteristic Description

TekL ink interface bus

Input signal characteristics

Output signal characteristics LVDS compatible outputs via rear-panel 40-pin connector

Reference clock characteristics LVDS com patible inputs via rear-panel 40-pin connector

External Trigger input Trigger input routed to the system trigger line

External Signal input Signal input routed to one of four internal signals

System Trigger output

External Signal output One of four internal signals routed to the signal output connector. The

GBit LAN port RJ-45 connector 10/100/1000 Mbps

Connector supports Reference Clock (10 MHz), Power On Signaling, Run event, System Trigger, General purpose events

LVDS compatible inputs via rear-panel 40-pin connector

Internal system trigger routed as TTL-compatible output

internal 10 MHz reference clock can be routed to this output.

16 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7016 Benchtop Mainframe Characteristics

Table 21: TLA70

Characteristic D escription

Classiﬁcation

Overall Dimensions

Interface module dimensions

Weight

Shipping weight 60 lbs 11 oz (26.7 kg) minimum conﬁguration with interface module (no

Siz

Acoustic noise level

ypical)

Construction materials Chassis parts, aluminum alloy

Finish type

16 Benchtop mainframe m echanical

Standard

Height (with feet)

Width

Depth

Rackmount

Height

Width

Depth

Height

Width

Depth

me with interface

Mainfra module and slot ﬁllers

(Typical)

Maximum per slot

Rackmount kit added

erface module

Int

riable fan speed (at

Va 860 RPM)

Full speed fan (switched at rear)

For lab bencht

13.7 in (35 cm) including feet

16.7 in (42.4 cm)

26.5 in (67 c

13.25 in (33.66 cm)

18.9in(4

28.9 in to 33.9 in (73.4 cm to 86.1 c m) in 0.5 in increments, user selectable

10.32 in (262.1 mm)

1.25 in (31.75 mm)

14.75 in

52 lbs 14 dual-slot ﬁller panels

5lbs(2.27kg)

20 lbs (9.1 kg)

r modules), with standard accessories

othe

187 lbs (85 kg) fully conﬁgured instrument with the addition of ﬁve logic analyzer modules and all m odule standard accessories including probes

lips

and c

slot wide

One

.2 dBA weighted (front)

43.8 dBA weighted (back)

66.2 dBA weighted (front)

66.2 dBA weighted (back)

ront panel and trim pieces, plastic

Circuit boards, glass laminate

Mainframes are Tektronix silver g ray with dark gray trim on fan pack and bottom feet support rails.

op or rackmount applications

8cm)

(373.4 mm)

oz. (24 kg) minimum conﬁguration with interface module and 6

TLA Product Speciﬁcations & Performance Veriﬁcation 17

TLA7016 Benchtop Mainframe Characteristics

Figure 2: Dimensions of the TLA7016 Benchtop mainframe

e 3: Dimensions of the TLA7016 Benchtop mainframe with rackmount option

Figur

18 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7PC1 Controller Speciﬁcations

TLA7PC1 Contr

oller Speciﬁcations

Tektronix ha

s released different motherboards for the TLA7PC1 controllers. The

motherboards are indicated by the following serial number ranges.

B010000toB

019999

B020000 to B029999

B030000 to B039999

The following tables list the speciﬁcations for the TLA7PC1 Controllers. The serial number ranges are designated by preﬁxes, such as: B01, B02, and B03.

NOTE. To access the BIOS Setups for TLA7PC1 controllers with serial numbers

B020000

and higher, restart the instrument and hold down the Delete key. For

controllers with serial numbers B010000 to B019999, restart the instrument and holddownfunctionkeyF2.

Table 22: TLA7PC1 Internal speciﬁcations

Characteristic Description

Operating system Microsoft Windows XP Professional

Motherboard

B01

B02

B03

Microprocessor

Chip set

Main memory

Cache memory Level 2 (L2) write-back cache 1 MB

RTC, CMOS setup, & PNP NVRAM retention time (Typical)

B01

B02, B03

B01, B02

B03

B01

B02

B03

B01

B02, B03

ATX-family board, integrating video, system monitoring, IDE and Ethernet controllers on a single board.

AB915GM - Flex-ATX-family board, 9.0 X 8.0 in.

AIMB-760G2 - RoHS compliant, ATX-family board, 12.0 X 9.6 in.

AIMB-762G2 - RoHS compliant, ATX-family board, 12.0 X 9.6 in.

Intel 2 GHz/533 MHz FSB Pentium M, 479-pin PGA socket for uFC-PGA processor package

Intel 3.4 GHz/800 MHz FS B Pentium 4, LGA775 socket

Intel 915G GMCH with an Intel ICH6 PCI Express I/O hub

Intel 945G GMCH with an Intel ICH7R PCI Express I/O hub

Maximum conﬁguration: 4 GB (four 1 GB DIMMs)

Installed conﬁguration: 1 GB (two 512 MB DIMMs)

Two 200-pin SO-DIMM sockets for DDR2-400/533 MHz (PC2-3200/4300)

Two 240-pin DIMM sockets for DDR2-400/533 MHz (PC2-3200/4300) SDRAM

Two 240-pin DIMM sockets for DDR2-533/667 MHz (PC2-4300/5400) SDRAM

>5 years battery life, lithium battery

>3 years battery life, lithium battery

TLA Product Speciﬁcations & Performance Veriﬁcation 19

TLA7PC1 Controller Speciﬁcations

Table 22: TLA7PC1 Internal speciﬁcations (cont.)

Characteristic Description

Hard disk drive

Size 80 GB, continually subject to change due to the fast-moving P C component

Interface SATA, native

Average seek time Read 9 ms

DVD-ROM/CD-RW drive Standard PC compatible IDE DVD/CD-RW drive residing on an EIDE

External display drive

B01

B02, B03

Source voltage and frequency 100 V

Fuse Internal

Maximum power consumption 400 W

Steady-state input current 8 A

Standard PC compatible IDE hard disk drive residing on an EIDE interface.

environment.

Write10ms

interface. The initial drive was a Teac DV-W28E793 with +R/RW and –R/RW.

Continually subject to change due to the fast-moving PC component environment.

Can drive two external video displays via DVI connectors. One DVI port with DVI digital only, other port with DVI digital and analog VGA signaling via an adapter. DVI has maximum resolution of 1600 x 1200 pixels; with 256, 16-bit, or 32-bit colors; and refresh rates of 60 Hz, 75 Hz, or 85 Hz. Analog VGA has maximum resolution of 1600 x 1200 with 32-bit colors at 75 Hz refresh rate.

One VGA, SVGA, or XGA-compatible analog output port, with maximum resolution of 2048 x 1536 pixels at 85 Hz refresh rate

to 240 V

RMS

maximum at 100 VAC

RMS

±10%,50Hzto60Hz

RMS

RMS,5ARMS

maximum at 240 VAC

RMS

Table 23: External controls and connectors

Characteristic Description

USB ports Four USB 2.0 ports

PS2 ports

On/Standby switch Switch used to power on the instrument

I/O Indicators LEDs for power on/off, HDD activity, and fan alarm

CPU reset switch Hardware reset for the PC

Alarm reset switch

Video Ports

LAN Ports

Audio Ports

B01 None

B02

Keyboard and mouse connectors in rear; one common PS2 connector in front

Reset switch for the system fan and over temperature monitor circuitry

B01

B02, B03

One DVI-I connector and one DVI-D connector

One analog SVG A connector

Two RJ45 with integrated green and yellow/amber LEDs located above the USB connectors

Two vertical 3.5 mm audio-jack stack. Line Output (top, lime) capable of driving headphones, Microphone Input (bottom, pink)

20 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7PC1 Controller Speciﬁcations

Table 24: TLA7P

Characteristic Description

Dimensions Height

Weight

Shipping co

Construct

Finish typ

ion materials

C1 mechanical

nﬁguration

Width

Depth

3.5in(88.9mm)

17.1 in (434.3 mm)

24 in (609.6 m

24lbs12oz(

35 lbs (15.9

Chassis pa of plastic; circuit boards are constructed of glass laminate.

Tektronix

rts are constructed of steel allo y and trim peaces are constructed

silver-gray

Figure 4: Dimensions of the TLA7PC1 Benchtop PC Controller

11. 25 k g)

kg)

TLA Product Speciﬁcations & Performance Veriﬁcation 21

TL708EX TekLink 8-Port Hub Characteristics

TL708EX TekLi

Table 25: TL7

Characteristic Description

characteristics (Typical)

TekL ink P o

(Typical)

TekL ink delay (Typical)

TekL ink

(Typical)

TekLink output signal characteristics (Typical)

TekLink AUX_PWR (Typical)

TekLink real-time interface bus Connector supports Reference Clock (10 MHz), Local

08 EX TekLink 8-Port Hub signal switching characteristics

e assembly delay

rt In to Port Out delays

REF_CLK out to Run out

input signal characteristics

nk 8-Port Hub Characteristics

Shielded twisted pairs (EVT0, EVT1, EVT2)

Non-shielded twisted pairs (EVT3, EVT4, EVT5

REF_CLK (E

Typical s

Input destination

Input levels

Outp

put levels

Out

Vod (voltage out differential)

Vos

,EVT6)

VT0) delay

ystem trigger (EVT1) delay

ut destination

9.5 nsTekLink cabl

10.5 ns

5ns

15 ns

REF_CLK

LVDS compatible inputs through the front-panel 40-pin connector

EVT0_IN_POS/NEG to EVT6_IN_POS/NEG

LVDS compatible input

LVDS compatible outputs through the front-panel 40-p

EVT0

LVD

247 mV minimum 454 mV maximum

1.1

1.375 V maximum

3 V power bi-directional diode isolated 1.3 A

4. maximum output available

10/100 LAN connection, Power On Signaling, Run

vent, System Trigger, General purpose events

out leads Run out by 5 ns

in connector

_OUT_POS/NEG to EVT6_OUT_POS/NEG

S compatible output

25 V minimum

Table 26: TL708EX TekLink 8-Port Hub AC power source characteristics

Characteristic Description

Source voltage and frequency 100 V

Maximum power consumption 110 W

Steady state input current 0.9 A

Inrush surge current

Power factor correction

At 120 VAC, 18 A maximum At 230 VAC, 35 A maximum

Yes

to 240 V

RMS

maximum at 120 VAC

RMS

±10%,47 Hz to 63 Hz

at 80 W

RMS

22 TLA Product Speciﬁcations & Performance Veriﬁcation

TL708EX TekLink 8-Port Hub C haracteristics

Table 27: TL708

Characteristic D escription

Temperature

Humidity

Altitude

EX TekLink 8-Port Hub atmospherics

Operating 0 °C to +50 °C, 11 °C/hr maximum gradient, non-condensing (derated

1 °C per 305m (1000 ft) above 1524 m (5000 ft) altitude)

Non-operating

Operating & Non-operat

Operating To 3000 m (9843 ft)

Non-opera

ing

ting

-40 °C to +71 °C, 15 °C/hr maximum gradient, non-condensing

5% to 95% relative humidity, non-condensing 75% above 30 45% above 40 °C

To 12,000 m (40,000 ft)

°C

Table 28: TL708EX TekLink 8-Port Hub miscellaneous

Characteristic Description

Cooling system Forced-air circulation system with no removable ﬁlters using two fans

operating in parallel

Transportation Package Material Transportation Package material meets recycling criteria as described

in Environmental Guidelines for Package Design (Tektronix part number 063-1290-00) and Environmentally Responsible Packaging Handbook (Tektronix part number 063-1302-00).

Cooling clearance 153 mm (6 in) on back for adequate cooling

Table 29: TL708EX TekLink 8-Port Hub mechanical

acteristics

Char

ssiﬁcation

Cla

ensions

Dim

ight

Width

Depth

Weight

hipping weight

Construction material Chassis parts are constructed of aluminum alloy; circuit boards constructed

Finish type Tektronix silver-gray

ription

Desc

table instrument intended for design and development bench and lab

Por based applications

Benchtop Conﬁguration Rackmount Conﬁguration

50.8 mm (2.0 in)

444.5 mm (17.5 in)

7.5 mm (12.5 in)

.7 kg (5 lbs 14 oz) minimum conﬁguration with power cord and accessories

.66 kg (10 lbs 4 oz) minimum conﬁguration

of glass laminate.

44.5 mm (1.75 in)

482.6 mm (19 in)

8.5 mm (11.75 in)

TLA Product Speciﬁcations & Performance Veriﬁcation 23

TLA700 System Speciﬁcations

TLA700 System

Speciﬁcations

The followin

g tables list the speciﬁcations common to the TLA715 and TLA721 logic analyzers. Refer to the individual logic analyzers section for detailed speciﬁcations.

Table 30: TLA700 Backplane interface

Characteristic Description

Slots

CLK10 Frequency

Relative Time Correlation Error

(Typical)

Includes typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a "typical" number for the measurement. Assumes standard accessory probes are utilized.

Portable mainframe

Benchtop mainframe 10 (three slots taken up by the controller module)

Expansion mainframe

TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx "MagniVu" data

TLA7Axx/TLA7NAx to TLA7AxxTLA7NAx "MagniVu" data

TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx "MagniVu" data

TLA7Lx/Mx/Nx/Px/Qx to TLA 7Lx/Mx/Nx/Px/Qx "normal" data using asynchronous sampling

TLA7Axx/TLA7NAx to TLA7Axx "normal" data using asynchronous sampling

TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx "normal" data using asynchronous sampling

TLA7Lx/Mx/Nx/Px/Qx to TLA 7Lx/Mx/Nx/Px/Qx "normal" data using an external clock

TLA7Axx/TLA7NAx to TLA7Axx/TLA7NAx "normal" data using an external clock

TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx "normal" data using an external clock

TLA7Lx/Mx/Nx/Px/Qx "MagniVu" to DSO data

TLA7Axx/TLA7NAx "MagniVu" to DSO data

TLA7Lx/Mx/Nx/Px/Qx to DSO "normal" data using asynchronous sampling

TLA7Axx/TLA7NAx to DSO "normal" data using asynchronous sampling

TLA7Lx/Mx/Nx/Px/Qx to DSO "normal" data using an external clock

TLA7Axx/TLA7NAx to DSO "normal" data using an external clock

DSO to DSO

10 MHz ±100 ppm

2ns

-3 ns

1 TLA7Lx/Mx/Nx/Px/Qx sample – 0 .5 ns

1 TLA7Axx/TLA7NAx sample – 0.5 ns

1 TLA7Lx/Mx/Nx/Px/Qx sample – 0 .5 ns

2ns

4ns

3ns

2ns

1 TLA7Lx/Mx/Nx/Px/Qx sample + 2 ns

1 TLA7Axx/TLA7NAx sample + 2 ns

3ns

2ns

3ns

24 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA700 System Speciﬁcations

For time interv error to account for the inaccuracy of the CLK10 source.

The DSO module time correlation is measured at the maximum sample rate on one channel only.

als longer than 1 μs between modules, add 0.01% of the difference between the absolute time measurements to the relative time correlation

Table 31: TLA700 Backplane latencies

Characteristic Description

System trigger and external signal input latencies2(Typical)

Portable mainframe and benchtop mainframe

External system trigger input to TLA7Lx/Mx/Nx/Px/Qx probe tip

External system trigger input to TLA7Axx probe tip

External signal input to TLA7Lx/Mx/Nx/Px/Qx probe tip via Signal 3, 4

External signal input to TLA7Axx/TLA7NAx probe tip via Signal 3, 4

External signal input to TLA7Lx/Mx/Nx/Px/Qx probe tip via Signal 1, 2

External signal input to TLA7Axx/TLA7NAx probe tip via Signal 1, 2

External system trigger input to DSO probe tip

-266 ns -230 ns

-653 ns -617 ns

-212 ns + Clk -176 ns + Clk

-634 ns + C lk -596 ns + Clk

-636 ns + C lk -615 ns + Clk

-25ns 11ns

System trigger and external signal output latencies1(Typical)

TLA7Lx/Mx/Nx/Px/Qx probe tip to external sy stem trigger out 376 ns + SMPL 412 ns + SMPL

TLA7Axx/TLA7NAx probe tip to external system trigger out 794 ns + SMPL 830 ns + SMPL

TLA7Lx/Mx/Nx/Px/Qx probe tip to external signal out via Signal 3, 4

TLA7Axx/TLA7NAx probe tip to external signal out via Signal 3, 4

TLA7Lx/Mx/Nx/Px/Qx probe tip to external signal out via Signal 1, 2

TLA7Axx/TLA7NAx probe tip to external signal out via Signal 1, 2

DSO probe tip to external system trigger out

DSO Probe tip to external signal out via Signal 3, 4

DSO probe tip to external signal out via Signal 1, 2

OR function

AND function

OR function

AND function

normal function

inverted logic on backplane

normal function

inverted logic on backplane

OR function

AND function

normal function

inverted logic on backplane

366 ns + SMPL

379 ns + SMPL

792 ns + SMPL

800 ns + SMPL

364 ns + SMPL

796 ns + SMPL

68 ns 104 ns

65 ns

75 ns

68 ns

71 ns

Inter-module latencies (Typical)

358 ns + SMPL 394 ns + SMPL

772 ns + SMPL 808 ns + SMPL

66 ns + SMPL 102 ns + SMPL

479 ns + SMPL 515 ns + SMPL

116 ns + SMPL 152 ns + SMPL

360 ns + SMPL 396 ns + SMPL

TLA7Lx/Mx/Nx/Px/Qx to DSO inter-module system trigger

TLA7Axx/TLA7NAx to DSO inter-module system trigger

TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx inter-module system trigger

TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx inter-module system trigger

TLA7Axx/TLA7NAx to TLA7Axx/TLA7NAx inter-module system trigger

TLA7Lx/Mx/Nx/Px/Qx to DSO inter-module ARM

Expansion

402 ns + SMPL

415 ns + SMPL

828 ns + SMPL

836 ns + SMPL

385 ns + SMPL

817 ns + SMPL

101 ns

111 ns

89 ns

92 ns

TLA Product Speciﬁcations & Performance Veriﬁcation 25

TLA700 System Speciﬁcations

Table 31: TLA700 Backplane latencies (cont.)

Characteristic Description

TLA7Axx/TLA7NAx to DSO inter-module ARM

TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx inter-module ARM

TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx inter-module ARM

TLA7Axx/TLA7NAx to TLA7Axx inter-module ARM

TLA7Lx/Mx/Nx/Px/Qx to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 1, 2

156

TLA7Axx/TLA7NAx to TLA7Axx inter-module via Signal 1, 2

TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Q x inter-module via Signal 1, 2

TLA7Lx/Mx/Nx/Px/Q to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 3, 4

TLA7AxxTLA7NAx to TLA7Axx inter-module via Signal 3, 4

TLA7Axx/TLA7NAx to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 3, 4

TLA7Lx/Mx/Nx/Px/Qx to TLA7Axx/TLA7NAx inter-module System Trigger

DSO to TLA7Lx/Mx/Nx/Px/Qx inter-module S ystem Trigger

DSO to TLA7Axx/TLA7NAx inter-module System Trigger

DSO to DSO inter-module System Trigger

TLA7Lx/Mx/Nx/Px/Qx to TLA7Axx/TLA7NAx inter-module ARM

DSO to TLA7Lx/Mx/Nx/Px/Qx inter-module ARM

DSO to TLA7Axx/TLA7NAx inter-module ARM

DSO to DSO inter-module ARM

DSO to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 1, 2

TLA7Lx/Mx/Nx/Px/Qx to TLA7Axx/TLA7NA x inter-module via Signal 1, 2

DSO to TLA7Axx/TLA7NAx inter-module via Signal 1, 2

TLA7Lx/Mx/Nx/Px/Qx to TLA7Axx/TLA7NAx inter-module via Signal 3, 4

DSO to TLA7Lx/Mx/Nx/Px/Qx inter-module via Signal 3, 4

DSO to TLA7Axx/TLA7NAx inter-module via Signal 3, 4

SMPL represents the time from the event at the probe tip inputs to the next valid data sample of the LA module. With Normal asynchronous sampling, this represents the delta time to the next sample clock. With MagniVu asynchronous sampling, this represents 500 ps or less. With synchronous sampling, this represents the time to the next master clock generated by the setup of the clocking state m achine, the system-under-test supplied clocks, and the qualiﬁcation data.

All system trigger and external signal input latencies are measured from a falling-edge transition (active true low) with signals measured in the wired-OR conﬁguration.

All signal output latencies are validated to the rising edge of a n active (true) high output.

"Clk" represents the time to the next master clock at the destination logic analyzer. With asynchronous sampling, this represents the delta time to the next sample clock beyond the minimum asynchronous rate of 4 ns. With the synchronous sampling, this represents the time to the next master clock generated bythe setup of the clock ing state machine and the supplied system under test clocks and qualiﬁcation data.

Signals 1 and 2 are limited to a "broadcast" mode of operation, where only one source is allowed to drive the signal node at any one time. That single source may be utilized to drive any combination of destinations.

779 ns + SMPL 815 ns + SMPL

108 ns + SMPL + Clk 144 ns + SMPL + Clk

479 ns + SMPL + Clk 533 ns + SMPL + Clk

111 ns + SMPL + Clk 147 ns + SMPL + Clk

116 ns + SMPL + Clk 137 ns + SMPL + Clk

156

113 ns + SMPL + Clk 134 ns + SMPL + Clk

534 ns + SMPL + Clk 555 ns + SMPL + Clk

116 ns + SMPL + Clk 152 ns + SMPL + Clk

124 ns + SMPL + Clk 160 ns + SMPL + Clk

545 ns + SMPL + Clk 581 ns + SMPL + Clk

-287 ns + SMPL -251 ns + SMPL

-240 ns -204 ns

-598 ns -562 ns

50 ns 86 ns

-300 ns + SMPL + Clk -264 ns + SMPL + Clk

-192 ns + Clk -156 ns + Clk

-600 ns + Clk -564 ns + Clk

59 ns 95 ns

156

-179 ns + Clk -158 ns + Clk

-294 ns + SMPL + Clk -273 ns + SMPL + Clk

-598ns + Clk -577 ns + Clk

-294 ns + SMPL + Clk -258 ns + SMPL + Clk

-184 ns + Clk -148 ns + Clk

-598 ns + Clk -562 ns + Clk

26 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA700 System Speciﬁcations

Table 32: TLA70

0 External signal interface

Characteristic Description

System Trigger Input

TTL compatible input via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe)

Input Levels

Input destination

Input Mode

TTL compatible input

≥ 2.0 V

≤ 0.8 V

System trig

Falling ed

ge sensitive, latched (active low)

Minimum Pulse Width 12 ns

Active Period Accepts system triggers during valid acquisition periods via real-time

gating, resets system trigger input latch between valid acquisition periods

Maximum Input Voltage 0 to +5 V peak

External Signal Input

TTL compatible input via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe)

Input Destination

Input Levels

Mode

Input

t Bandwidth

Inpu

Signal 1, 2

3, 4

Signal

TTL compatible input

≥ 2.0 V

≤ 0.8 V

Active (true) low, level sensitive

Signal 1, 2 Signal 3, 4

z square wave minimum

50 MH

Active Period Accepts signals during valid acquisition periods via real-time gating

Maximum Input Voltage 0 to +5 V peak

System Trigger Output

TTL compatible output via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe)

Source selection System trigger

Source Mode Active (true) low, falling edge latched

Active Period

Output Levels

Outputs system trigger state during valid acquisition period, resets system

rigger output to false state between valid acquisitions

50 Ω back terminated TTL-compatible output

≥4 V into open circuit

≥2Vinto50Ω to ground

≤ 0.7Vsinking10mA

Output Protection Short-circuit protected (to ground)

ger

z square wave minimum

10 MH

TLA Product Speciﬁcations & Performance Veriﬁcation 27

TLA700 System Speciﬁcations

Table 32: TLA700 External signal interface (cont.)

Characteristic Description

External Signal Output

Source Selection Signal 1, 2

Output Modes Level Sensitive

Output Levels

Active Period

Output Protection Short-circuit protected (to ground)

Intermodule Signal Line Bandwidth

e Input Bandwidth sp eciﬁcation only applies to signals to the modules; it does not apply to signals applied to the External Signal Input and sent back to the

Th External Signal Output.

The Output Bandwidth speciﬁcation only applies to signals from the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output.

TTL compatible outputs via rear panel mounted BNC connectors (portable mainframe) or front panel mounted SMB connectors (benchtop mainframe)

Signal 3, 4

10 MHz clock

User deﬁnable

Active (true) low or active (true) high

50 Ω back terminated TTL output

≥ 4 V into open circuit

≥2Vinto50Ω to ground

≤ 0.7Vsinking10mA

Signal 1, 2 Signal 3, 4Output Bandwidth

50 MHz square wave minimum 10 MHz square wave minimum

Outputs signals during valid acquisition periods, resets signals to false state between valid acquisitions

Outputs 10 MHz clock continuously

Minimum bandwidth up to which the intermodule signals are speciﬁed to operate correctly

Signal 1, 2 Signal 3, 4

50 MHz square wave minimum 10 MHz square wave minimum

28 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA715 Dual Monitor Portable Mainframe Speciﬁcations

TLA715 Dual Mo

nitor Portable Mainframe Speciﬁcations

The followin

g tables describe the speciﬁcations for the TLA715 Dual Monitor

Portable Mainframe.

Table 33: TLA715 Internal controller

Characteristic Description

Operating system Microsoft Windows 2000

Microprocessor

Main memory

Style 144 pin S

Speed

Available conﬁgurations 32, 64, 128, 256 MB per SO DIMM

Installed conﬁgurations

Cache memory 256 KByte Level 2 (L2) write-back cache

Flash BIOS

Real-time clock and CMOS setups NVRAM Real-time clock/calendar, standard and advanced PC CMOS setups; see

RTC, CMOS setup, & P NP NVRAM retention time

pical)

(Ty

Floppy disk drive

ootable replaceable

B hard disk drive

Size 40 GB

Interface ATA -5/enhanced IDE (EIDE)

Average seek time Read, 12 ms

Average latency

I/O data transfer rate 33.3 Mbps maximum (U-DMA mode 2)

Cache buffer 2 MB (30 GB) /512 KB (10 GB)

CD-RW drive Standard PC compatible IDE (Integrated device Electronics) 8x-8x-24x

Intel Pentium PC-AT conﬁguration with an Intel 815E chip-set and a 733 MHz P e

SDRAM

height

133 MHz

512 MB

256 K

BIOS speciﬁcation

> 10 years battery life, lithium battery

andard 3.5 inch 1.44 MB PC compatible high-density, double-sided

St ﬂoppy disk drive, 500 Kb/sec transfer rate

Standard PC compatible IDE (Integrated Device Electronics) hard disk drive residing on an EIDE interface.

Continually subject to change due to the fast-moving PC component environment. These storage capacities valid at product introduction.

7/14 ms

CD-RW drive residing on an IDE interface.

Continually subject to change due to the fast-moving PC component environment.

ntium III processor

O DIMM, 2 sockets, gold plated, 1.25-inch (3.175 cm) maximum

with both sockets loaded

Byte

TLA Product Speciﬁcations & Performance Veriﬁcation 29

TLA715 Dual Monitor Portable Mainframe Speciﬁcations

Table 34: TLA71

Characteristic Description

Classiﬁcation Standard PC graphics-accelerator technology capable of supporting both

Display memory

Display selection

External display drive

Internal display

5 display system

video port with Silicon

n chip)

motio

(Secondary video port

h 815E chip set)

wit

Classiﬁcation TFT (Thin Film Transistor) 26 cm active-matrix color LCD display, CCFL

Resolution

Color scale 262, 144 colors (6-bit RGB) with a color gamut of 42% at center to NTSC

internal color LCD display and two external color VGA, SVGA, or XGA monitors

4MBSDRAMcl

Hardware se defaults to internal color LCD display (indicated by two beeps); automatically switches to external SVGA monitor, if attached (indicated by one beep).

Dual (simultaneous) display of external SVGA monitor and internal color LCD is possible via special CMOS "simulscan" setup, as long as internal and exter current LCD) and display rates (simulscan mode indicated by three beeps).

Four beeps during the BIOS boot indicates a monochrome LCD was found (not supp monitor was found.

Dynamic Display Conﬁguration 1 (DDC1) support for external SVGA monitor

Two VGA, selected via Win2000 display applet.

Resolution (Pixels) Colors Refresh RatesDisplay Size (Primary

640 x 4

800 x 600

1024 x 768

1024

1280 x

1600 x 600

1600 x 1200

Resolution (Pixels) Colors Refresh Rates

640 x 480

800 x 600

4 x 768

102

1280 x 1024

1600 x 1200

cklight, intensity controllable via software

00 X 600, 262, 144 colors with 211.2 mm (8.3 in) by 158.4 mm (6.2 in)

8 of viewing area

ocked up to 100 MHz, no external video memory

nse of external SVGA monitor during BIOS boot sequence;

nal displays operate at same resolution (limited to 800x600 on

orted). Five beeps indicates no recognizable LCD or external

is provided.

SVGA, or XGA-compatible analog output ports. D isplay size is

4K,16.8M

256, 6

265, 64 K, 16.8 M

256, 64 K, 16.8 M

4K,16.8M

256, 6

256, 64 K

256, 64 K, 16.8 M

,64K,16.8M

256

256, 64 K, 16.8 M

256

,85

60, 75

60, 75, 85

75, 85

60,

60, 75, 80

60, 75

30 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA715 Dual Monitor Portable Mainframe Speciﬁcations

Table 35: TLA71

5 front-panel interface

Characteristic D escription

QWERTY Keypad 31-key ASCII to support naming of ﬁles, traces, and keyboard equivalents

of pointing device inputs for menus

HEX Keypad

Special function knobs

Multi-function knob Various increment/decrement functions dependent on screen or window

25-key HEX supporting standard DSO and LA entry functions

type

Integrated pointing device

USB por

Mouse Port

Keyboard Port

Vertical position

Vertical scale

Horizontal position

Horizontal scale

Scrolling

Scales wav

Scrollin

Scales w

Vertica

Front p

PS/2 co

PS/2 c

and positioning dependent on display type

eform displays only

g and positioning dependent on display type

aveform displays only

lly mounted Trackball with two control buttons (SELECT and MENU)

anel (lower left-hand side) dual USB connector

mpatible pointing device port

ompatible keyboard port

Table 36: TLA715 rear-panel interface

Characteristic Description

Parallel interface port 36-pin high-density connector supports Output only, Enhanced Parallel

Port (EPP), or Microsoft high-speed mode (ECP)

Complies with IEEE P1284-C/D2 for bi-directional Parallel Peripheral Interface for Personal Computers (draft) style 1284-C

Serial interface port 9-pin male sub-D connector to support RS-232 serial port

SVGA output Port 1 and Port 2 Two 15-pin sub-D SVGA connectors

PC CardBus32 port Standard Type I, II, III PC-compatible, PC card slot

Complies with PCMC IA 2.1 and JEIDA 4.1

Table 37: TLA715 AC power source

Characteristic Description

Source voltage and frequency 100 V

100 V

Fuse rating 90 V to 250 V operation

(159-0046-00)

90 V to 250 V operation

(159-0381-00)

UL198/CSA C22.2

0.25 in × 1.25 in, Fast Blow, 8 A, 250 V

IEC 127/Sheet 1

5 mm × 20 mm, Fast Blow, 6.3 A, 250 V

RMS

to 240 V

to 120 V

±10%,45Hzto66Hz

RMS

, 360 Hz to 440 Hz

RMS

Maximum power consumption 600 W

Steady-state input current 6 A

maximum at 90 VAC

RMS

, 60 Hz or 100 VAC

RMS

, 400 Hz

RMS

Inrush surge current 70 A maximum

Power factor correction

Yes

TLA Product Speciﬁcations & Performance Veriﬁcation 31

TLA715 Dual Monitor Portable Mainframe Speciﬁcations

Table 37: TLA715 AC power source (cont.)

Characteristic Description

On/Sleep indicator Green/yellow front panel LED located next to On/Standby switch provides

visual feedback when the On/Off switch is actuated. When the LED is green, the instrument is powered and the processor is not sleeping. When the LED is yellow, the instrument is powered, but the processor is sleeping.

On/Standby switch and indicator Front panel On/Standby switch. Users can push the switch to power down

the instrument without going through the Windows shutdown process; the instrument normally powers down.

The power cord provides main power disconnect.

Table 38: TLA715 cooling

Characteristic Description

Cooling system Forced air circulation system with no removable ﬁlters using six fans

ing in parallel

operat

Pressurization Negative pressurization system in all chambers including modules

Slot activation Installing a module activates the cooling for the corresponding occupied

by opening the airﬂow shutter mechanism. Optimizes cooling

slots efﬁciency by only applying airﬂow to installed modules.

take

Air in

Air exhaust Back rear

Cooling clearance 2 inches (51 mm) front, sides, top, and rear. Prevent blockage of airﬂow

speed and operation

Fan

sides and bottom

Front

ottom of instrument by placing on a solid, noncompressable surface;

to b can be operated on rear feet.

All fans operational at half their rated potential and speed (12 VDC)

Table 39: TLA715 mechanical

Characteristic Description

Overall dimensions

Height (with feet)

Width

Depth

Weight

Shipping conﬁguration 60 lbs 13 oz (27.58 kg) minimum conﬁguration (no modules), with all

Acoustic noise level (Typical) 42.7 dBA weighted (operator)

Dimensions are without front feet extended, front cover attached, pouch attached, nor power cord attached.

9.25 in (23.5 cm)

17 in (43.18 cm)

17.5 in (44.45 cm)

30 lbs 12 oz (13.9 kg) with no modules installed, two dual-wide slot covers, and empty pouch

standard accessories

86 lbs 9 oz (39.26 kg) full conﬁguration, with two TLA 7P4 modules and standard accessories (including probes and clips)

37.0 dBA weighted (bystander)

32 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA715 Dual Monitor Portable Mainframe Speciﬁcations

Table 39: TLA715 mechanical (cont.)

Characteristic Description

Construction materials Chassis parts are constructed of aluminum alloy; front panel and trim

peaces are constructed of plastic; circuit boards are constructed of glass.

Finish type

Tektronix blue body and Tektronix silver-gray trim and front with black pouch, FDD feet, handle, and miscellaneous trim pieces

Figure 5: Dimensions of TLA715 Portable mainframe

TLA Product Speciﬁcations & Performance Veriﬁcation 33

Benchtop and Expansion Mainframe Speciﬁcations

Benchtop and E

xpansion Mainframe Speciﬁcations

The followin

g tables list the speciﬁcations for the TLA721 Benchtop mainframe and the TLA7XM expansion mainframe.

Table 40: Benchtop and expansion mainframe AC power source

Characteristic Description

Source Voltage 100 V

100 V

Maximum Power Consumption 1450 W line power (the maximum power consumed by a fully loaded

13-slot instrument)

Fuse Rating (Current and voltage ratings and type of fuse used to fuse the source line voltage)

90 V - 132 VAC

RMS

Operation

High-power/Low Line (159-0379-00)

103 V - 250 VAC

RMS

Operation

(159-0256-00)

Safety: UL198G/CSA C22.2

Size: 0.25 in × 1.25 in

Style: Slow acting

Rating: 20 A/250 V

Safety: UL198G/CSA C22.2

Size: 0.25 in × 1.25 in

Style: No. 59/Fast acting

Rating: 15 A/250 V

207 V - 250 VAC Operation

(159-0381-00)

RMS

Safety: IEC 127/Sheet 1

Size: 5 mm × 20 mm

Style: Fast acting "F", high-breaking capacity

Rating: 6.3 A/250 V

Inrush Surge Current

70 A maximum

Steady State Input Current 16.5 A

6.3 A

PowerFactorCorrection(Typical)

0.99 at 60 Hz operation and 0.95 at 400 Hz operation

ON/Standby Switch and Indicator Front Panel On/Standby switch with integral power indicator

to 240 V

RMS

maximum at 207 VAC

RMS

to 120 V

RMS,

maximum at 90 VAC

±10%,45 Hz to 66 Hz

360 Hz to 440 Hz

RMS

Table 41: Benchtop and expansion mainframe cooling

Characteristic Description

Cooling system Forced air circulation system (positive pressurization) using a single

low-noise centripetal (squirrel cage) fan conﬁguration with no ﬁlters for the power supply and 13 module slots.

Fan speed control

Rear panel switch selects between full speed and variable speed. Slot exhaust temperature and ambient air temperature are monitored such that a constant delta temperature is maintained.

Slot activation Installing a module activates the cooling for the corresponding occupied

slots by opening the air ﬂow shutter mechanism. Optimizes cooling efﬁciency by only applying airﬂow to modules that are installed.

Pressurization Positive pressurization system, all chambers including modules

34 TLA Product Speciﬁcations & Performance Veriﬁcation

Benchtop and Expansion Mainframe Speciﬁcations

Table 41: Benchtop and expansion mainframe cooling (cont.)

Characteristic Description

Slot airﬂow direction P2 to P1, bottom of module to top of module

Mainframe air intake Lower fan-pack rear face and bottom

Mainframe air exhaust

Top-sides and top-rear back. Top rear-back exhaust redirected to the sides by the fan pack housing to minimize reentry into the intake.

Δ Temperature r eadout sensitivity

Temperature sense range

100 mV/ °C with 0 °C corresponding to 0 V output

-10 °C to +90 °C, delta temperature ≤ 50 °C

Clearance 2 in (51 mm), rear, top, and sides

Fan speed readout

RPM = 20 (Tach frequency) or 10 ≥ (+Pulse Width)

where (+Pulse Width) is the positive width of the TACH1 fan output signal measured in seconds

Fan speed range 650 to 2250 RPM

Table 42: Enhanced monitor

Characteristic Description

Voltage readout

+24 V, -24 V, + 12 V, - 12 V, + 5 V, -5.2 V, -2 V, + 5 V +5 V

External

via RS232

Voltage readout accuracy (Typical) ±3% maximum

Current readout Readout of the present current on the +24 V, -24 V, +12 V, -12 V, +5 V,

-2 V, -5.2 V rails via RS232

Current readout accuracy (Typical) ±5% of maximum power supply I

Rear panel connector levels

±25 VDC maximum, 1 A maximum per pin

(Provides access for RS-232 host to enhanced monitor)

if present, and

Standby

Table 43: Benchtop and expansion mainframe mechanical

Characteristic Description

Overall Dimensions

Standard

Rackmount Height

Height

Width

Depth

Width

Depth

13.7 in (346.7 mm) including feet

16.7 in (424.2 mm)

26.5 in (673.1 mm)

13.25 in (336.6 mm)

18.9 in (480.1 mm)

28.9 in to 33.9 in (734.1 mm to 861.1 mm) in 0.5 in increments, user selectable

Benchtop controller dimensions Height

Width

Depth

Expansion module dimensions Height

Width

Depth

10.32 in (262.1 mm)

2.39 in (60.7 mm)

14.75 in (373.4 mm)

10.32 in (262.1 mm)

1.25 in (31.75 mm)

14.75 in (373.4 mm)

TLA Product Speciﬁcations & Performance Veriﬁcation 35

Benchtop and Expansion Mainframe Speciﬁcations

Table 43: Benchtop and expansion mainframe mechanical (cont.)

Characteristic Description

Weight

Size

Acoustic noise level (Typ ical)

Construction materials Chassis parts, aluminum alloy Front panel and trim pieces,

Finish type

Mainframe with benchtop controller and slot ﬁllers (Typical)

Shipping conﬁguration (Typical) 60 lbs 11 oz. (26.7 kg) minimum conﬁguration with controller

Benchtop controller

Expansion module

Maximum per slot

Rackmount kit adder

Benchtop controller Three slots wide

Expansion module

Variable fan speed (at 860 RPM) 43.2 dBA weighted (front)

Full speed fan (switched at rear) 66.2 dBA weighted (front)

58 lbs 11 oz. (26.7 kg)

(only) and all standard accessories (two manuals, ﬁve dual-wide and one single-wide slot ﬁller panels, power cord, empty pouch, front cover, keyboard, software, and cables)

187 lbs (85 kg) fully conﬁgured, same as above with the addition of ﬁve LA modules (four TLA7P4 modules, one TLA7N4 module) and all module standard accessories (probes and clips)

6 lbs 10 oz. (3.0 kg)

3lbs(1.4kg)

5lbs(2.27kg)

20 lbs (9.1 kg)

Single slot wide

43.8 dBA weighted (back)

66.2 dBA weighted (back)

plastic Circuit boards, glass laminate

Mainframes are Tektronix silver gray with dark gray trim on fan pack and bottom feet support rails.

Benchtop controllers are Tektronix silver gray on front lexan and injector/ejector assemblies with a black FDD and PC card ejector buttons.

Figure 6: Dimensions of the benchtop and expansion mainframe

36 TLA Product Speciﬁcations & Performance Veriﬁcation

Benchtop and Expansion Mainframe Speciﬁcations

Figure 7: Dimensions of the benchtop and expansion mainframe with rackmount option

TLA Product Speciﬁcations & Performance Veriﬁcation 37

TLA721 Dual Monitor Benchtop Controller Speciﬁcations

TLA721 Dual Mo

nitor Benchtop Controller Speciﬁcations

The followin

g tables list the speciﬁcations for the TLA721 Dual Monitor

Benchtop Controller.

Table 44: TLA721 benchtop controller characteristics

Characteristic D escription

Operating system Microsoft Windows 2000

Microprocessor

Main memory

Available conﬁgurations 16, 32, 64, 256 MB per SODIMM

Installed conﬁguration 512 MB maximum conﬁguration

Speed

CAS latency

RAS to CAS delay

RAS precharge

DRAM cycle tim e

Cache memory 512 KB, level 2 (L2) write-back cache

Flash BIOS

Real-time clock and CMOS setups NVRAM Real-time clock/calendar. Standard and advanced PC CMOS setups: see

TC, CMOS setup, & PnP NVRAM retention time

(Typical)

Floppy disk drive

Transfer rate

Access time (ave.)

Intel 733 MHz Pentium III conﬁguration with an Intel 815E chip-set

Two 144 pin SODIMM sockets support one or two SDRAM modules.

133 MHz

2, 3

5/7 or 7/9

512 KB

Provides PC plug-and-play services with and without Microsoft Windows

erating system.

Flash based BIOS ﬁeld upgradable via a ﬂoppy disk

Forced recovery jumper is provided

IOS speciﬁcations

attery life is typically > 7 years

Standard 3.5 inch, 1.44 MB, high-density, double-sided, PC-compatible high-density ﬂoppy disk drive

500 Kb per second

194 ms

38 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA721 Dual Monitor Benchtop Controller Speciﬁcations

Table 44: TLA721 benchtop controller characteristics (cont.)

Characteristic D escription

Bootable replaceable hard disk drive

Size 40 GB

Interface ATA-5/Enhanced IDE (EIDE)

Average seek time Read 12 ms

I/O data-transfer rate 33.3 MB/s maximum (U-DMA mode 2)

Average latency

Cache buffer

CD-RW Drive

Applicable formats CD-DA; CE-ROM Mode 1, Mode 2; CD-ROM XA Mode 2 (Form 1, Form

Interface IDE (ATAPI)

Average access time 130 ms

Data-transfer rate (burst sustained)

Display classiﬁcation Standard PC graphics accelerator technology (bitBLT based) residing on

Standard PC compatible IDE (Integrated Device Electronics) hard disk driveresidingonanEIDEinterface

Continually subject to change due to the fast-moving PC component environment.

This storage capacity valid at product introduction.

7/14 ms

512 KB

Standard PC compatible IDE (Integrated device Electronics) 8x-8x-24x CD-RW drive residing on an IDE interface.

Continually subject to change due to the fast-moving PC component environment.

2); Photo CD (single/multi session); Enhanced CD

16.7 MB per second maximum, 1290-3000 KB per second

the Peripheral Component Interconnect (PCI) bus capable of supporting external color VGA, SVGA, or XGA monitors.

TLA Product Speciﬁcations & Performance Veriﬁcation 39

TLA721 Dual Monitor Benchtop Controller Speciﬁcations

Table 44: TLA721 benchtop controller characteristics (cont.)

Characteristic D escription

Display conﬁguration Hardware automatically senses a missing ﬂat panel LCD in the benchtop

mainframe and defaults to the external SVGA monitor output during the BIOS boot sequence (no internal TFT LCD display exists). This is indicated by a single beep during the boot sequence.

Dynamic Display Conﬁguration 1 (DDC1) support for the external monitor is provided.

Display memory

Display drive

Display size

Silicon Motion Chip)

(Secondary video port with 815E Chip set)

4 MB SDRAM is on board the video controller; no external video memory

Two VGA, SVGA, or XGA compatible analog output ports

User selected via Microsoft Windows

Plug and Play support for DDC1 and DDC2 A and B

Resolution (Pixels) Colors Refresh Rates(Primary video port with

640 x 480

800 x 600

1024 x768

1280 x 1024

1600 x 600

1600 x 1200

Resolution (Pixels) Colors Refresh Rates

640 x 480

800 x 600

1024 x768

1280 x 1024

1600 x 1200

256, 64 K, 16.8 M

256, 64 K

256, 64 K, 16.8 M

256

60, 75, 85

60, 75

Table 45: Front panel characteristics

racteristic

Cha

GA output port (SVGA)

ual USB ports

Mouse port

Keyboard port

Parallel interface port (LPT) 36-pin high-density connector supports standard Centronics mode,

Serial interface port (COM) 9-pin male sub-D connector to support an RS232 serial port

PC CardBus32 port Standard Type I and II PC compatible PC card slot

Type I, II, and III PC Card Port Standard Type I, II, and III PC compatible PC card slot

cription

Des

o 15-pin sub-D SVGA connectors

wo USB (Universal Serial Bus) compliant ports

ront panel mounted PS2 compatible mouse port utilizing a mini D IN

F connector

Front panel mounted PS2 compatible keyboard port utilizing a mini DIN connector

Enhanced Parallel Port (EPP), or Microsoft high-speed mode (ECP)

40 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA600 Series Speciﬁcations

TLA600 Series

Speciﬁcations

The followin

g tables list the speciﬁcations for the TLA600 series logic analyzer.

Table 46: TLA600 input parameters with probes

Characteristic Description

Threshold Accuracy

Threshold range and step size

Threshold channel selection 16 threshold groups assigned to channels.

Channel-to-channel skew

Channel-to-channel skew (Typical)

Sample uncertainty

Probe input resistance (Typical) 20 kΩ

Probe input capacitance: P6417, P6434 (Typical)

Probe input capacitance: P6418 (Typical)

Minimum slew rate (Typical) 0.2 V/ns

Maximum operating signal 6.5 V

Probe overdrive: P6417, P6418 P6434

Maximum nondestructive input signal to probe ±15 V

Minimum input pulse width signal (single channel)

(Typical)

Delay time from probe tip to input probe connector

(Typical)

±100 mV

Settable from +5 V to -2 V in 50 mV steps

P6417 and P6418 probes have two threshold settings, one for the clock/qualiﬁer channel and one for the data channels.

P6434 probes have four threshold settings, one for each of the clock/qualiﬁer channels and two for the data c hannels (one per 16 data channels).

≤ 1.6 ns maximum

≤ 1.0 ns

Asynchronous

Sample period

2pF

1.4 pF data channels

2 pF CLK/Qual channels

-3.5 V absolute input voltage minimum

p-p

6.5 V absolute input voltage maximum

±250 mV or ±25% of signal swing minimum required beyond threshold, whichever is greater

±300 mV or ±25% of signal swing minimum required beyond threshold, whichever is greater

±4 V maximum beyond threshold

2ns

7.33 ns

Synchronous

500 ps

Table 47: TLA600 timing latencies

Characteristic Description

System Trigger and External Signal Input Latencies

(Typical)

External System Trigger Input to LA Probe Tip

External Signal Input to LA Probe Tip via Signal 3, 4

External Signal Input to LA Probe Tip via Signal 1, 2

-266 ns

-212 ns + Clk

-208 ns + Clk

TLA Product Speciﬁcations & Performance Veriﬁcation 41

TLA600 Series Speciﬁcations

Table 47: TLA600 timing latencies (cont.)

Characteristic Description

System Trigger and External Signal Output Latencies (Typical)

LA Probe Tip to External System Trigger Out

LA Probe Tip to External Signal Out via Signal 3, 4

LA Probe Tip to External Signal Out via Signal 1, 2

normal function 364 ns + SMPL

inverted logic on backplane

All system trigger and external signal input latencies are measured from a falling-edge transition (active true low) with signals measured in the wired-OR conﬁguration.

"Clk" represents the time to the next master clock at the destination logic analyzer. In the asynchronous (or internal) clock mode, this represents the delta time to the next sample clock beyond the minimum asynchronous rate of 4 ns. In the synchronous (or external) clock mode, this represents the time to the next master clock generated by the setup of the clocking state machine and the supplied system under test clocks and qualiﬁcation data.

Signals 1 and 2 (ECLTRG0, 1) are limited to a "broadcast" mode of operation, where only one source is allowed to drive the signal node at any one time. That single source may be utilized to drive any combination of destinations.

SMPL represents the time from the event at the probe tip inputs to the next valid data sample. With asynchronous sampling, this represents the delta timetothe next sample clock. With MagniVu asynchronous sampling, this represents 500 ps or less. With synchronous sampling, this represents the time to the next

ster clock generated by the setup of the clocking state machine, the system-under-test supplied clocks, and the qualiﬁcation data.

376 ns + SMPL

OR function

AND function

366 ns + SMPL

379 ns + SMPL

364 ns + SMPL

Table 48: TLA600 external signal interface

Characteristic D escription

System Trigger Input

External Signal Input

Input Levels

Input Mode

Minimum Pulse Width 12 ns

Active Period Accepts system triggers during valid acquisition periods via real-time

Maximum Input Voltage 0 to +5 V peak

Input Destination

Input Levels

Input Mode

Input Bandwidth

Active Period Accepts signals during valid acquisition periods via real-time gating

Maximum Input Voltage 0 to +5 V peak

TTL compatible input via rear panel mounted BNC connectors

TTL compatible input

≥2.0 V

≤ 0.8 V

Falling edge sensitive, latched (active low)

gating, resets system trigger input latch between valid acquisition periods

TTL compatible input via rear panel mounted BNC connectors

Signal 1, 2, 3, 4

TTL compatible input

≥2.0 V

≤ 0.8 V

Active (true) low, level sensitive

Signal 1, 2 Signal 3, 4

50 MHz square wave minimum 10 MHz square wave minimum

42 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA600 Series Speciﬁcations

Table 48: TLA600 external signal interface (cont.)

Characteristic D escription

System Trigger Output

Source Mode Active (true) low, falling edge latched

Active Period

Output Levels

Output Protection Short-circuit protected (to ground)

External Signal Output

Source Selection Signal 1, 2, 3, 4, or 10 MHz clock

Output Modes Level Sensitive

Output Levels

Active Period

Output Protection Short-circuit protected (to ground)

The Input Bandwidth speciﬁcation only applies to signals to the modules; it does not apply to signals applied to the External Signal Input and sent back to the External Signal Output.

The Output Bandwidth speciﬁcation only applies to signals from the modules; it d oes not apply to signals applied to the External Signal Input and sent back to the External Signal Output.

TTL compatible output via rear panel mounted BNC connectors

Outputs system trigger state during valid acquisition period, resets system trigger output to false state between valid acquisitions

50 Ω back terminated TTL-compatible output

≥4 V into open circuit

≥2Vinto50Ω to ground

≤ 0.7 V sinking 10 mA

TTL compatible outputs via rear panel mounted BNC connectors

User deﬁnable

Active (true) low or active (true) high

50 Ohm back terminated TTL output

≥ 4 V into open circuit

≥2Vinto50Ω to ground

≤ 0.7 V sinking 10 mA

Signal 1, 2 Signal 3, 4Output B andwidth

50 MHz square wave minimum 10 MHz square wave minimum

Outputs signals during valid acquisition periods, resets signals to false state between valid acquisitions

Outputs 10 MHz clock continuously

Table 49: TLA600 channel width and depth

Characteristic Description

Product

TLA601, TLA611, TLA621

TLA602, TLA612, TLA622

TLA603, TLA613, TLA623

TLA604, TLA614, TLA624

ChannelsNumber of channels

32 data and 2 clock

64 data and 4 clock

96 data, 4 clock, and 2 qualiﬁer

128 data, 4 clock, and 4 qualiﬁer

Product Memory depthAcquisition memory depth

TLA601, TLA602, TLA603, TLA604

TLA611, TLA612, TLA613, TLA 614

TLA621, TLA622, TLA623, TLA 624

64 K or 256 K samples

1Msamples

TLA Product Speciﬁcations & Performance Veriﬁcation 43

TLA600 Series Speciﬁcations

PowerFlex opti

ons

Table 50: TLA600 clocking

Characteristic Description

Asynchronous sampling

Sampling period

Minimum recognizable word2(across all channels)

synchronous sampling

Number of clock channels

Number of qualiﬁer channels

Setup and hold window size (data and qualiﬁers)

(Typical)

Setup and hold window range For each channel, the setup and hold window can be moved from +8.5 ns

Maximum synchronous clock rate

Demux clocking

4 ns to 50 ms in a 1-2-5 sequence

Channel-to-channel skew + s ample uncertainty

Example: for a P6417, P6418, or P 6434 Probe and a 4 ns sample period =

1.6ns+4ns=

Product

TLA601, TLA611, TLA621

TLA602, TLA612, TLA622

TLA603, T

TLA604, TLA614, TLA624

Product

TLA601,

TLA602, TLA612, TLA622

TLA603, TLA613, TLA623

TLA604

um window size = Maximum channel-to-channel skew + (2 x sample

Maxim

5.6 ns

LA613, TLA623

TLA611, TLA621

, TLA614, TLA624

Clock Channels

Qualiﬁer Channels

uncertainty) + 0.4 ns

Maximum setup time = User interface setup time + 0.8 ns

um hold time = User interface hold time + 0.2 ns

Maxim

ples: for a P6417 or a P6418 probe and user interface setup and

Exam hold of 2.0/0.0 typical:

Maximum window size = 1.6 ns + (2 x 500 ps) + 0.4ns = 3.0 ns Maximum

up time = 2.0 ns + 0.8 ns = 2.8 ns

set

Maximum hold time = 0.0 ns + 0.2 ns = 0.2ns

Channel-to-channel skew (typical) + (2 x sample uncertainty)

Example: for P6417 or P6418 Probe = 1 ns + ( 2 x 500 ps) = 2 ns

s) to -7.0 ns (Ts) in 0.5 n s s teps (setup time). Hold tim e follows the setup

(T time by the setup and hold window size.

200 MHz in full speed mode (5 ns minimum between active clock edges)

100 MHz (10 ns minimum between active clock edges)

44 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA600 Series Speciﬁcations

Table 50: TLA600 clocking (cont.)

Characteristic Description

TLA603, TLA613, TLA623

TLA604, TLA614, TLA624

TLA601, TLA611, TLA621

TLA602, TLA612, TLA622

Time between DeMux clock edges4(Typical) 5 ns minimum between Demux clock edges in full-speed mode

Time between DeMux store clock edges4(Typical) 10 ns minimum between Demux master clock edges in full-speed mode

Data Rate4(Typical) 400 MHz (200 MHz option required) half channel.

Clocking state machine

Pipeline delays

is possible to use storage control and only store data when it has changed (transitional storage).

Applies to asynchronous sampling only. Setup and hold window speciﬁcation applies to synchronous sampling only.

Any or all of the clock channels may be enabled. For an enabled clock channel, either the rising, falling, or both edges can be selected as the active

clock edges. The clock channels are stored.

Full and half speed modes are controlled by PowerFlex options and upgrade kits.

All qualiﬁer channels are stored. For custom clocking there are an additional 4 qualiﬁer channels on C2 3:0 regardless of channel width.

Channels multiplex as follows:

A3(7:0) to

A2(7:0) to

A1(7:0) to

A0(7:0) to

D3(7:0)

D2(7:0)

D1(7:0)

D0(7:0)

Channels multiplex as follows:

A3(7:0) to

A2(7:0) to

A1(7:0) to

A0(7:0) to

C3(7:0)

C2(7:0)

D1(7:0) TLA602, TLA612, TLA622

D0(7:0) TLA602, TLA612, TLA622

10 ns minimum between Demux clock edges in half-speed mode

20 ns minimum between Demux master clock edges in half-speed mode

(Requires channels to be multiplexed.)

These multiplexed channels double the memory depth.

Each channel can be programmed with a pipeline delay of 0 through 3 active clock edges.

ble 51: TLA600 trigger system

Characteristic Description

riggering Resources

ord/Range recognizers

6 word recognizers. The word recognizers can be combined to form full

1 width, double bounded, range recognizers. The following selections are available:

16 word recognizers

13 word recognizers

10 word recognizers

7 word recognizers

4 word recognizers

0 range recognizers

1 range recognizer

2 range recognizers

3 range recognizers

4 range recognizers

TLA Product Speciﬁcations & Performance Veriﬁcation 45

TLA600 Series Speciﬁcations

Table 51: TLA600 trigger system (cont.)

Characteristic Description

Range recognizer channel order

Glitch detector

Minimum detectable glitch pulse width (Typical) 2.0 ns (single channel with P6417, P6418, or a P6434 probe)

Setup and hold violation detector

Transition detector

Counter/Timers 2 counter/timers, 51 bits wide, can be clocked up to 250 MHz.

External Signal In

External Trigger In A backplane input signal that causes the main acquisition and the MagniVu

Active trigger resources

Trigger States

rigger State sequence rate

Trigger Machine Actions

Main acquisition trigger Triggers the main acquisition memory

ain trigger position

MagniVu™ acquisition trigger

MagniVu™ trigger position The MagniV trigger position is programmable within 4 ns boundaries and

Increment counter

Start/Stop timer Either of the two counter/timers used as timers can be started or stopped.

Reset counter/timer Either of the two counter/timers can be reset.

From most-signiﬁcant probe group to least-signiﬁcant probe group: C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 CK1 CK0

Missing channels for modules with fewer than 136 channels are omitted.

Each channel group can be enabled to detect a glitch.

Each channel can be enabled to detect a setup and hold violation. The range is from 8 ns before the clock edge to 8 ns after the clock edge. The range can be selected in 0.5 ns increments.

The setup and hold violation of each window can be individually programmed.

Each channel group can be enabled or disabled to detect a transition between the current valid data sample and the previous valid data sample.

This mode can be used to create transitional storage selections where all channels are enabled.

Maximum count is 2

Maximum time is 9.007 X 10

seconds or 104 days.

Counters and timers can be set, reset, or tested and have zero reset latency.

A backplane input signal

acquisition to trigger if they are not already triggered

16 maximum (excluding counter/timers)

Word recognizers are traded off one-by-one as External Signal In, glitch detection, setup and hold detection, or transition detection resources are added.

Same rate as valid data samples received, 250 MHz maximum

Trigger position is programmable to any data sample (4 ns boundaries)

Triggering of MagniV memory is controlled by the main acquisition trigger

separate from the main acquisition memory trigger position.

Either of the two counter/timers used as counters can be increased.

When a counter/timer is used as a timer and is reset, the timer continues from the started or stopped state that it was in prior to the reset.

46 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA600 Series Speciﬁcations

Table 51: TLA600 trigger system (cont.)

Characteristic Description

Signal out

Trigger out A trigger out signal sent to the backplane to trigger other instruments

Storage Control

Global storage Storage is allowed only when a speciﬁc condition is met. This condition

By event

Block storage

Glitch violation storage The acquisition memory can be enabled to store glitch violation information

Setup and hold violation storage

Each use of External Signal In, glitch detector, setup and hold violation detector, or transition detector requires a trade-off of one word recognizer resource.

Any glitch is subject to pulse width variation of up to the channel-to-channel skew speciﬁcation + 0.5 ns.

Any setup value is subject to variation of up to 1.8 ns; any hold value is subject to variation of up to 1.2 ns.

A signal sent to the backplane to be used by other instruments

can use any of the trigger machine resources except for the counter/timers. Storage commands deﬁned in the current trigger state will override the global storage control.

Global storage can be used to start the acquisition with storage initially turned on (default) or turned off.

Storage can be turned on or off; only the current sample can be stored. The event storage control overrides any global storage commands.

When enabled, 31 samples are stored before and after the valid sample.

Not allowed when glitch storage or setup and hold violation is enabled.

with each data sample when asynchronous sampling is used. The probe data storage size is reduced by one half (the other half holds the violation information). The fastest asynchronous sampling rate is reduced to 10 ns.

The acquisition memory can be enabled to store setup and hold violation information with each data sample when synchronous sampling is used. The probe data storage size is reduced by one half (the other half holds the violation information). The maximum clock rate is reduced by half.

Table 52: TLA600 MagniVu feature

Characteristic Description

MagniVu memory depth 2016 samples per channel

MagniVu sampling period Data is asynchronously sampled and stored every 500 ps in a separate

high resolution memory. There are no clocking options.

Table 53: TLA600 Data handling

Characteristic Description

Nonvolatile memory retention time (Typical) Battery is integral to the NVRAM. Battery life is > 10 years.

Table 54: TLA600 internal controller

Characteristic Description

Operating System Microsoft Windows

Microprocessor

Intel Celeron, 566 MHz

TLA Product Speciﬁcations & Performance Veriﬁcation 47

TLA600 Series Speciﬁcations

Table 54: TLA600 internal controller (cont.)

Characteristic Description

Main Memory

Style 168 pin DIMM, 2 Sockets

Speed

Installed Conﬁgurations

Real-Time Clock and CMOS Setups, Plug & Play NVRAM Retention Time

Hard Disk Drive

Size Minimum 10 GB

CD-RW Drive Standard PC compatible IDE (Integrated Device Electronics) 24x-10x-40x

Floppy Disk Drive

SDRAM

100 MHz

Minimum 256 MB loaded in one socket

Maximum 512 MB with both sockets loaded

Battery life is typically > 3 years when the logic analyzer is not connected to line voltage. When connected to line voltage the life of the battery is extended. Lithium battery, CR3032

Standard PC compatible IDE (Integrated Device Electronics) hard disk driveresidingonanEIDEinterface.

Maximum 30 GB

Continually subject to change due to the fast-moving PC component environment.

These storage capacities valid at product introduction.

CD-RW drive residing on an EIDE interface.

Continually subject to change due to the fast-moving PC component environment.

Standard 3.5 inch 1.44 MB PC compatible high-density, double-sided ﬂoppy disk drive.

ble 55: TLA600 display system

Characteristic D escription

Classiﬁcation Standard PC graphics accelerator technology (bitBLT-based); capable of

supporting both internal color LCD display and external color SVGA/XGA

onitor

Display Memory

Size

Display Selection Both front panel and external displays can be used simultaneously, each

External Display Drive

Display Size

DRAM-based frame-buffer memory

2MB

with independent resolutions. Supports Windows dual-monitor capability.

One SVGA/XGA-compatible analog output port

Selected via Windows

Plug and Play support for DDC1 and DDC2 A and B

Resolution (Pixels) Colors

640 x 480

800 x 600

1024 x 768

1280 x 1024

256, 64 K, 16.8 M

256, 64 K, 8 M

48 TLA Product Speciﬁcations & Performance Veriﬁcation

Table 55: TLA600 display system (cont.)

Characteristic D escription

Internal Display

Classiﬁcation Thin F ilm Transistor (TFT)

10.4 inch active-matrix color LCD display; CCFL backlight; intensity controllable via software

Resolution 800 x 600 pixels

Color Scale 262,144 colors (6-bit RGB)

TLA600 Series Speciﬁcations

Table 56:

Characteristic Description

QWERTY ASCII to support naming of ﬁles, traces, and keyboard equivalents of

Special Function Knobs Various functions

TLA600 front-panel interface

pointing device inputs for menus

Table 57: TLA600 rear-panel interface

Characteristic Description

Parallel Interface Port (LPT) 36-pin high-density connector supports standard Centronics mode,

Enhanced Parallel Port (EPP), or Microsoft high-speed mode (ECP)

Serial Interface Port (COM 1) 9-pin male sub-D connector to support RS-232 serial port

Single USB Ports One USB (Universal Serial Bus) compliant port

SVGA Output Port (SVGA OUT) 15-pin sub-D SVGA connector

Mouse Port

Keyboard Port

Type I and II PC Card Port Standard Type I and II PC-compatible PC card slot

Type I, II, and III PC Card Port Standard Type I, II, and III PC-compatible PC card slot

PS/2 compatible mouse port utilizing a mini DIN connector

PS/2 compatible keyboard port utilizing a mini DIN connector

TLA Product Speciﬁcations & Performance Veriﬁcation 49

TLA600 Series Speciﬁcations

Table 58: TLA60

0 AC power source

Characteristic Description

Source Voltage and Frequency 90-250 V

45-66 Hz, continuous range CAT II 100-132 V

RMS,

360-440 Hz,

RMS,

continuous range CAT II

Fuse Rating

Maximum Power Consumption

Steady-State Input Current

Inrush Surge Current

PowerFactorCorrection

90 V - 132 V Operation (2 required

90 V - 250 V Op

)

eration

(2 required)

UL198/CSA C22.2

0.25 in × 1.2

IEC 127/She

5 in, Fast Blow, 8 A, 250 V

1 5 mm × 20 mm, Fast Blow, 6.3 A, 250 V

600 Watts l

70 A maxim

ine power maximum

mum

maxi

RMS

Yes

On/Standby Switch and Indicator Front Panel On/S tandby switch, with indicator.

The power cord provides main power disconnect.

Table 59: TLA600 cooling

Characteristic Description

Cooling System Forced air circulation (negative pressurization) utilizing six fans operating in

parallel

Cooling Clearance 2 in (51 mm), sides and rear; unit should be operated on a ﬂat, unobstructed

surface

Table 60: TLA600 mechanical characteristics

racteristic

Cha

Weight

TLA614, TLA624, TLA613, and TLA623

TLA612, TLA622, TLA611, and TLA621

TLA604 and TLA603

TLA602 and TLA601

cription

Des

cludes empty accessory pouch and front cover

.1 Kg (40 lbs)

8 Kg (39.75 lbs)

17.6 Kg (38.75 lbs)

17.5 Kg (38.5 lbs)

50 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA600 Series Speciﬁcations

Figure 8: Dimensions of the TLA600 series logic analyzer

TLA Product Speciﬁcations & Performance Veriﬁcation 51

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

TLA7Axx/TLAN

Ax Series Logic Analyzer Module

Speciﬁcations

The following tables list the speciﬁcations of the TLA7Axx/TLA7NAx Series Logic Analyzer modules.

Table 61: TL

Characteristic Description

Threshold accuracy

(Certiﬁable parameter)

Threshold range and step size

Threshold channel selection

Channel to channel skew

Channel to channel skew (Typical)

Sample uncertainty

Minimum slew rate (Typical) 0.2 V/ns

Input voltage range -2.5 V to +5 V

Maximum operating voltage swing 6.0 V peak-to-peak

Probe overdrive

Maximum nondestructive input signal to probe ± 15V

Minimum input pulse width (single channel) (Typical)

A7Axx/TLA7NAx input parameters (with probes)

± (35 mV + 1% of the threshold voltage setting)

Settable from +4.5 V to -2.0 V in 5 mV steps

16 threshold groups assigned to channels. Each probe has four threshold settings, one for each of the clock/qualiﬁer channels and one per group of 16 data channels.

≤ 400 ps maximum

When merged, add the following for slave modules:

0.0 ns when data is acquired on the slave modules through local clocks

125 ps when data is acquired on the slave modules using the master module’s clock and merge deskew has been performed.

375 ps when data is acquired on the slave modules using the master module’s clock and merge deskew has NOT been performed.

≤ 300 ps

When merged, add the following for slave modules:

0.0 ns when data is acquired on the slave modules through local clocks

125 ps when data is acquired on the slave modules via the master modules’ clock and merge deskew has been performed.

375 ps when data is acquired on the slave modules via the master module’s clock and merge deskew has NOT been performed.

Asynchronous

Sample period

Single ended probes ± 150 mV or ± 25% of signal swing minimum required beyond threshold,

whichever one is greater

Differential probes

P6860, P6880, P6960, and P6980 probes

P6810 probes 750 ps

pos-Vneg

is ≥ 150 mV

Synchronous

125 ps

p-p

500 ps

52 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

Table 61: TLA7Axx/TLA7NAx input parameters (with probes) (cont.)

Characteristic Description

Delay time from probe tip to input probe connector

(Typical)

P6860, P6960, and P6980 probes 7.7 ns ± 60ps

P6810 and P6880 probes 7.7 ns ± 80ps

Table 62: TLA7Axx analog output

Character

Number of

Attenuat

Bandwidth (Typical) 2GHz

Accuracy (gain and offset) (Typical) ± (50 mV + 2% of signal amplitude)

istic

ion

outputs

Descripti

Four anal the module’s channels can be mapped to the four analog outputs.

10X mode for normal operation 5X mode for small signals (-1.5 V to +2.5 V)

og outputs regardless of the module channel width. Any four of

Table 63: Channel width and depth

Characteristic Description

Number of channels

Acquisition memory depth

TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4

TLA7AA3, TLA7AC3, TLA7NA3 96 data, 6 clock/qualiﬁer

TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA2

TLA7AA1, TLA7NA1

TLA7AAx, TLA7NAx series 32 M per channel, maximum

TLA7ABx series 64 M per channel, maximum

TLA7ACx series

128 data, 8 clock/qualiﬁer

64 data, 4 clock/qualiﬁer

32 data, 2 clock/qualiﬁer

128 M per channel, maximum

Table 64: Clocking

Characteristic Description

Asynchronous sampling

Sampling period

Minimum recognizable word1(across all

channels)

500 ps to 50 ms in a 1-2-5 sequence. Storage control can be used to only store data when it has changed (transitional storage)

2 ns minimum for all channels

1 ns minimum for half channels (using 2:1 Demultiplex mode)

0.5 ns minimum for quarter channels (using 4:1 Demultiplex mode)

Channel-to-channel skew + sample uncertainty

Example for a P6860 high-density probe and a 2 ns sample period:

400 ps + 2 ns = 2.4 ns

TLA Product Speciﬁcations & Performance Veriﬁcation 53

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

Table 64: Clocking (cont.)

Characteristic Description

synchronous sampling

Master clock channels

Merged slave clock channels

(64+4 channel modules and 32+2 channel modules cannot be merged.)

Qualiﬁer channels

Note: Qualiﬁer channels are stored.

Single channel setup and hold window size

(Typical)

Single module setup and hold window size

(data and qualiﬁers)

Single module setup and hold window size (data and qualiﬁers) (Typical)

Setup and hold window range For each channel, the setup and hold window can be moved from +8.0 ns (T

Product

32+2 module

64+4 module

96+6 module

128+8 module

Product

96+6 module

128+8 module

Product

32+2 module

64+4 module

96+6 module

128+8 module

Clock channels

Qualiﬁer channels

500 ps

Maximum window size = Maximum channel-to-channel skew + (2 x sample uncertainty) + 100 ps

Maximum setup time = User interface setup time + 75 ps

Maximum hold time = User interface hold time + 50 ps

Example using a P 6800 series probe and user interface setup and hold of 625/0 typical:

Maximum window size = 400 ps + 250 ps + 100 ps = 750 ps

Maximum setup time = 625 ps + 75 ps = 700 ps

Maximum hold time = 0.0 ps + 50 ps = 50 ps

Typical window size = Typical channel-to-channel skew + (2 x sample uncertainty) +75ps

Example using P6860 probe: 300 ps + 250 ps + 75 ps = 625 ps

typical) to -8.0 ns (Tstypical) in 0.125 ns steps (setup time).

The setup and hold window can be shifted toward the setup region by 0 ns, 4 ns, or 8ns. Witha0nsshift,therange is +8 ns to -8 ns; witha4nsshift,therange is +12 ns to -4 ns; with an 8 ns shift, the range is +16 ns to 0 ns. The sample point selection region is the same setup and hold window. Setup times are speciﬁed as typical ﬁgures. Hold time follows the setup time by the setup and hold window size.

54 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

Table 64: Clocking (cont.)

Characteristic Description

Maximum sync

TLA7Axx series

Maximum synchronous clock r ate

TLA7NAx series

Demultiplex c lo cking

Demultiplex channels (2:1)

TLA7AA3, TLA7AA4, TLA7AB4, TLA7AC3, TLA7AC4, TLA7NA3, TLA7NA4 modules

TLA7AA1, TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA1, TLA7NA2 modules

hronous clock rate

450 MHz in full-speed mode (2.2 ns minimum between active clock edges)

235 MHz in half-speed mode (4.25 ns minimum between active clock edges)

120 MHz in quarter-speed mode (8.3 ns minimum between active clock edges)

800 MHz on half channels

Software controls the selection between full-speed and half-speed modes.

450 MHz in full-speed mode (2.2 ns minimum between active clock edges)

235 MHz in full-speed mode (4.25 ns minimum between active clock edges)

120 MHz in quarter-speed mode (8.3 ns minimum between active clock edges)

Software controls the selection between full-speed and half-speed modes.

Any individual channel can be demultiplexed with its partner channel. If multiplexing is enabled, all of the A and D channels are multiplexed; there is no individual selection. Channels demultiplex as follows:

A3(7:0) to/from

A2(7:0) to/from

A1(7:0) to/from

A0(7:0) to/from

E3(7:0) to/from E1(7:0) TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules

E2(7:0) to/from E0(7:0) TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules

CK3 to/from

CK2 to/from

CK1 to/from

CK0 to/from

A3(7:0) to/from

A2(7:0) to/from

A1(7:0) to/from D1(7:0) TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA2 modules

A0(7:0) to/from D0(7:0) TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA2 modules

D3(7:0)

D2(7:0)

D1(7:0)

D0(7:0)

only

Q2 TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules only

Q3 TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4 modules only

C3(7:0)

C2(7:0)

only

TLA Product Speciﬁcations & Performance Veriﬁcation 55

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

Table 64: Clocking (cont.)

Demultiplex clocking

Demultiplex channels (4:1)

TLA7AA3, TLA7AA4, TLA7AB4, TLA7AC3, TLA7AC4, TLA7NA3, TLA7NA4 modules

TLA7AA1, TLA7AA2, TLA7AB2, TLA7AC2, TLA7NA2, TLA7NA1 modules

Time between Demultiplex clock edges

(Typical)

Source synchronous sam pling (TLA7Axx)

Clocks per module

Clocks with merged modules When merged, the slave modules have two clocks available from the master

Clock groups Four for a single module and for a merged system

Size of clock group valid FIFO Four stages when operated at 235 MHz or below (three stages when operated

Source synchronous clock alignment window Channel-to-channel skew only

Unlike the 2:1 Demultiplex, the channels within a group of four cannot arbitrarily drive the others.

E3(7:0) to E2(7:0), E1(7:0), E0(7:0) TLA7AA4, TLA7AB4, TLA7AC4,

TLA7NA4 modules only

A3(7:0) to

A1(7:0) to

C3(7:0) to

CK3 to CK2, Q3, Q2 TLA7AA4, TLA7AB4, TLA7AC4, TLA7NA4

CK1 to CK0, Q1, Q0

Unlike the 2:1 Demultiplex, the channels within a group of four cannot arbitrarily drive the others.

A1(7:0) to A0(7:0), D1(7:0), D0(7:0) TLA7AA2, TLA7AB2, TLA7AC2

C3(7:0) to C2(7:0), A3(7:0), A2(7:0)

Same limitations as normal synchronous acquisition

Four

module. Including the local clocks, the total is six clocks.

above 235 MHz); this allows four (source synchronous or other) clocks to occur before the clock that completes the Clock Group Valid signal for that group.

A2(7:0), D3(7:0), D2(7:0)

A0(7:0), D1(7:0), D0(7:0)

C2(7:0), C1(7:0), C0(7:0)

modules only

TLA7NA2 modules only

56 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

Table 64: Clocking (cont.)

Demultiplex c lo cking

Source synchronous clock reset The Clock Group Valid FIFO can be reset in one of the two ways:

1. By the overﬂow of a presettable (0-255) 8-bit counter that counts one of the following clocks: 2ns Clock or the master heartbeat clock (synchronous or asynchronous). An active edge places the reset count to its preset value. An active clock edge will clear the Clock Group Valid reset before the clock gets to the FIFO so that no data is lost.

2. By enabling an external reset. In this mode, one of the clock channels must be traded on the master module to act as a level-sensitive reset input. Any one of the clocks can be selected. A polarity selection is available. This mode affects all Clock G roup Complete circuits.

Neither one of the above modes can be intermixed; one or the other must be selected.

Clocking state machine

Pipeline delays

cation only applies with asynchronous clocking. With synchronous sampling, the setup and hold window size applies.

Speciﬁ Any clock channel can be enabled. For enabled clock channels, either the rising, falling, or both edges can be selected as active clock edges; clock channels

are stored.

This is a special mode and has some limitations such as the clocking state machine and trigger state machine only running at 500 MHz.

Channel groups can be programmed with a pipeline delay of 0 through 7 active clock changes.

TLA Product Speciﬁcations & Performance Veriﬁcation 57

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

Table 65: TLA7A

Characteristic Description

Trigger resou

Word recognizers and range recognizers

Range reco

etector (normal asynchronous clock

Glitch d mode)

m detectable glitch pulse width

Minimu

(Typical)

Setup and hold violation detector (normal

ronous clock mode)

synch

nsition detector

Tra

unter/timers

Signal In 1

xx/TLA7NAx module trigger system

rces

gnizer channel order

16, word reco recognizers. The following selections are available:

16 word reco

13 word recognizers

10 word recognizers

7wordrecog

4 word recognizers

From most-signiﬁcant probe group to least-signiﬁcant probe group:

C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 CK1 CK0

Missing channels for modules with fewer than 136 channels are omitted. When merged, the range recognition extends across the modules. The master module contains

Channel

Glitches are subject to pulse width variations of up to ± 125ps

Minimum input pulse width (single channel)

P6860,

P6880, P6980 differential probe:

P6810 general purpose probe:

Any channel can be enabled to detect a setup or hold violation. The range is from

8.0 ns channel setup and hold violation size can be individually programmed.

The range can be shifted towards the positive region by 0 ns, 4 ns, or 8 ns. With a 0nss with an 8 ns shift, the range is +16 ns to 0 ns. The sample point selection region is the same as the setup and hold window.

Any hold value is subject to variation of up to the channel skew speciﬁcation.

16 t

Any channel group can be enabled or disabled to detect a rising transition, a falling transition, or both rising and falling transitions between the current valid data sample an

Maximum count is 2^50-1 (excluding sign bit)

Maximum time is 4.5 X 10

C reset, do nothing, increased, or decreased. Timers can be reset, started, stopped, or not changed. Counters and timers have zero reset latency and one clock terminal c

A backplane input signal.

the most-signiﬁcant groups.

groups can be enabled to detect glitches.

P6960 high density probe:

before the clock edge to 8.0 ns after the clock edge in 0.125 ns steps. The

hift, the range is +8 ns to -8 ns; witha4nsshift,therange is +12 ns to -4 n s;

setup value is subject to variation of up to the channel skew speciﬁcation. Any

ransition detectors.

d the previous valid data sample.

ounter/timers, 51 bits wide, can be clocked up to 500 MHz

ounters can be used as Settable, resettable, and testable ﬂags. Counters can be

ount latency.

gnizers can be combined to form full width, double bounded range

gnizers

nizers

seconds or 52 days

0 range reco

1 range recognizer

2 range recognizers

3 range reco

4 range recognizers

500 ps

750 ps

gnizers

58 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

Table 65: TLA7Axx/TLA7NAx module trigger system (cont.)

Characteristic Description

Signal In 2

Trigger In A backplane input signal that causes the main acquisition and the MagniVu

Active trigger resources

Trigger states 16

Trigger state sequence rate

Trigger

Main acquisition trigger Triggers the main acquisition memory

Main trigger position

MagniVu trigger

MagniVu trigger position

Incre

Star

Res

Reloadable word recognizer (snapshot) Loads the current acquired data sample into the reference value of the word

Storage control

Storage Storage is allowed only if a speciﬁc condition is met. The condition can use any of

By event

Block storage (store stretch) When enabled, 31 samples are stored before and after the valid sample.

machine actions

ment/decrement counter

t/stop timer

et counter/timer

loadable word recognizer latency

ignal Out

rigger Out

A backplane input signal.

acquisition to trigger if they are not already triggered.

16 maximum (excluding counter/timers)

Word recognizers are traded off one-for-one as Signal In 1, Signal In 2, glitch detection, setup and hold detection, or transition detection resources are added.

Same rate as valid data samples received. 500 MHz maximum.

Programmable to any data sample (2 ns boundaries)

Main acquisition machine controls the triggering of the MagniVu memory

Programmable within 2 ns boundaries and separate from the main acquisition

y trigger position

memor

er/timers used as counters can be increased or decreased.

Count

er of the two counter/timers used as timers can be started or stopped.

Eith

her of the two counter/timers can be reset.

Eit

When a counter/timer used as a timer is reset, the timer continues in the started or stopped state that it was prior to the reset.

cognizer via a trigger machine action. All data channels are loaded into their

re respective word recognizer reference register on a one-to-one manner.

8ns

A signal sent to the backplane to be used by other modules

A signal sent to the backplane to trigger other modules

the trigger resources except for counter/timers. Storage commands deﬁned in the current trigger state will override the global storage control.

Storage can be used to start the acquisition with storage initially turned on (default setting) or off.

Storage can b e turned on or off; only the current sample can be stored. Event storage control overrides any global storage commands.

This allows the storage of a group of samples around a valid data sample when storage control is being used. This only has meaning when storage control is used. Block storage is disallowed when glitch storage or setup and hold violation storage is enabled.

TLA Product Speciﬁcations & Performance Veriﬁcation 59

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

Table 65: TLA7Axx/TLA7NAx module trigger system (cont.)

Characteristic Description

Glitch violation storage Glitch violation information can be stored to acquisition memory with each data

sample when asynchronous sampling is used. The acquisition data storage size is reduced by half when this mode is enabled (the other half holds violation information). The fastest asynchronous clock rate is reduced to 4 ns.

Setup and hold violation storage Setup and hold violation information can be stored to acquisition memory with each

data sample when synchronous sampling is used. The acquisition data storage size is reduced by half when this mode is enabled (the other half holds violation information). The maximum synchronous clock rate in this mode is 235 MHz.

Table 66: MagniVu acquisition

Characteristic Description

MagniVu sampling period Data is asynchronously sampled and stored every 125 ps in a separate

MagniVu (high-resolution) memory. The storage speed can be changed by

re to 250 ps, 500 ps, or 1000 ps with no loss in memory depth so

softwa that the high resolution memory covers more time at a lower resolution.

u memory depth

MagniV

Approximately 16 K per channel. The MagniVu memory is separate from the main acquisition memory.

Table 67: Merged modules

Characteristic Description

Number of merged modules 2, 3, 4, or 5 adjacent modules can be merged. Only 102-channel modules

or 136-channel modules can be merged. Merged modules can have unequal channel widths and channel depths.

Number of channels after merging The sum of all channels available on each of the merged modules including

clocks and qualiﬁers. No channels are lost when modules are merged.

Merged system acquisition depth

Number of clock and qualiﬁer channels after merging The qualiﬁer channels on the slave modules can only be used as data

Merged system trigger resources

Merged range signiﬁcance Most signiﬁcant Master, Slave 1, Slave 2

Channel depth is equal to that of the shallowest module.

channels. They cannot in ﬂuence the actual clocking function of the logic analyzer (for example, log strobe generation).

The clock channels on the slave TLA7Axx modules can capture data on those modules for source-synchronous applications. Each slave module contributes four additional clock channels to the merged set. All clock and qualiﬁer channels are stored to acquisition memory.

The same as a single module except for word recognizer width, setup and hold violation detector width, glitch detector width, and transition detector width has increased to equal that of the merged channel width. Range recognizers will increase to the merged channel w idth up to three modules; range recognition is not supported on the two outside slave modules.

60 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7Axx/TLANAx Series Logic Analyzer Module Speciﬁcations

Table 68: Data p

Characteristic D escription

Timestamp cou

lacement

nter resolution and duration

125 ps resolut

3.25 days duration

ion

Table 69: NVRAM

Characteristic D escription

Nonvolatile memory retention time (Typical) The battery life is integral to the NVRAM; battery life is > 10 years.

Table 70: Mechanical

Character

Material

Weight 136-channel module

Shipping weight 7 lb 12 oz. (3.515 kg) for 136-channel module when packaged for domestic

Overa

Mainframe interlock 1.4 ECL keying is implemented

istic

ll dimensions

102-channel module

nel module

68-chan

34-channel module

Height

Width

Length

Descripti

Chassis p constructed of plastic laminated to steel front panel. Circuit boards are constructed of glass laminate.

5lb6oz. (2.438kg)

5lb4oz.

5 lb 0.5 oz. (2.282 kg)

4 lb 15.5 oz. (2.254 kg)

shipm

10.32

2.39 in (61 mm) with merge connector recessed, 0.41 in (10.41 mm) with merge connector extended

14.7

arts are constructed of aluminum alloy. The front panel is

(2.381 kg)

ent

in (262 mm)

in (373 mm)

TLA Product Speciﬁcations & Performance Veriﬁcation 61

TLA7Lx/Mx/Nx/Px/Qx Module Speciﬁcations

TLA7Lx/Mx/Nx

/Px/Qx Module Speciﬁcations

The followin analyzer modules.

Table 71: LA module channel width and depth

Characteristic Description

Product

TLA7N1, TLA7L1, TLA7M1

TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2

LA7L3, TLA7M3

TLA7M2, TLA7M3, TLA7M4

, TLAQP4

ion memory depth

Acquisit

PowerFlex options

TLA7N3, T

TLA7N4, TLA7P4, TLA7Q4, TLA7L4, TLA7M4

Product Memory de

TLA7L1, TLA7L2, TLA7L3, TLA7L4

TLA7M1,

TLA7N1, TLA7N2, TLA7N3, TLA7N4

TLA7P2, TLA7P4

TLA7Q2

g tables list the speciﬁcations of the TLALx/Mx/Nx/Px/Qx logic

ChannelsNumber of channels

32 data and 2 clock

64 data and 4 clock

96 data, 4

128 data, 4 clock, and 4 qualiﬁer

32 K or 128 K samples

512 K sam

64 K or 256 K or 1 M or 4 M samples

16 M samples

64 M sam

clock, and 2 qualiﬁer

pth

ples

Table 72: LA module clocking

cteristic

Chara

Asynchronous sampling

Sampling period

um recognizable word

Minim

channels)

synchronous sampling

Number of clock channels

Number of qualiﬁer channels

(across all

iption

Descr

2 ns to 50 ms in a 1-2-5 sequence

Channel-to-channel skew + sample uncertainty

Example: for a P6417 or a P6418 Probe and a 4 ns sample period = 1.6 ns + 4 ns =5.6ns

Product

TLA7N1, TLA7L1, TLA7M1

TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2

TLA7N3, TLA7L3, TLA7M3

TLA7N4, TLA7P4, TLA7Q4, TLA7L4, TLA7M4

Product

TLA7N1, TLA7L1, TLA7M1

TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2

TLA7N3, TLA7L3, TLA7M3

TLA7N4, TLA7P4, TLA7Q4, TLA7L4, TLA7M4

Clock channels

Qualiﬁer channels

62 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7Lx/Mx/Nx/Px/Qx Module Speciﬁcations

Table 72: LA module clocking (cont.)

Characteristic Description

Setup and hol

d window size (data and

qualiﬁers)

Setup and hold window size (data and qualiﬁers) (Typical)

Setup and hold window range For the TLA7Nx/Px/Qx logic analyzer modules, each channel of the setup and hold

Maximum synchronous clock rate

Demux clocking

TLA7P4, TLA7Q4, TLA7L3, TLA7L4, TLA7M3, TLA7M4

TLA7N1, TLA7N2, TLA7P2, TLA7Q2, TLA7L1, TLA7L2, TLA7M1, TLA7M2

Time between DeMux clock edges4(Typical) 5 ns minimum between DeMux clock edges in full-speed mode 10 ns minimum

Time between DeMux store clock edges

(Typical)

Data Rate (Typical) TLA7N1, TLA7N2, TLA7P2, TLA7Q2, TLA7N3, TLA7N4, TLA7P4, TLA7Q4,

Maximum window size = Maximum channel-to-channel skew + (2 x sample uncertainty) + 0.4 ns Maximum setup time = User interface setup time + 0.8 ns Maximum hold time = User interface hold time + 0.2 ns

Maximum setup time for slave module of merged pair = User Interface setup time + 0.8 ns Maximum hold time for slave module of merged pair = User Interface hold time + 0.7 ns

Examples: for a P6417, P6418, or P6434 probe and user interface setup and hold of 2.0/0.0 typical: Maximum window size = 1.6 ns + (2 x 500 ps) + 0.4ns = 3.0 ns Maximum setup time = 2.0 ns + 0.8 ns = 2.8 ns Maximum hold time = 0.0 ns + 0.2 ns = 0.2ns

Channel-to-channel skew (typical) + (2 x sample uncertainty)

Example: for P6417 or P6418 Probe = 1 ns + (2 x 500 ps) = 2 ns

window can be moved from +8.5 ns (Ts) to -7.0 ns (Ts) in 0.5 ns steps (setup time). Hold time follows the setup time by the setup and hold window size.

For the TLA7Lx and TLAMx logic analyzer modules, the user interface restricts the setup and hold window range to groups rather than individual channels.

200 MHz in full speed mode (5 ns minimum between active clock edges)

100 MHz in half speed mode (10 ns min imum between active clock edges)

Channels multiplex as follows:Demux Channels TLA7N3, TLA7N4,

A3(7:0) to

A2(7:0) to

A1(7:0) to

A0(7:0) to

D3(7:0)

D2(7:0)

D1(7:0)

D0(7:0)

Channels multiplex as follows:

A3(7:0) to

A2(7:0) to

A1(7:0) to

A0(7:0) to

C3(7:0)

C2(7:0)

D1(7:0) TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2 only

D0(7:0) TLA7N2, TLA7P2, TLA7Q2, TLA7L2, TLA7M2 only

between DeMux clock edges in half-speed mode

10 ns minimum between DeMux m aster clock edges in full-speed mode 20 ns minimum between DeMux master clock edges in half-speed mode

400 MHz (200 MHz option required) half channel.

(Requires channels to be multiplexed.)

These multiplexed channels double the memory depth.

TLA Product Speciﬁcations & Performance Veriﬁcation 63

TLA7Lx/Mx/Nx/Px/Qx Module Speciﬁcations

Table 72: LA module clocking (cont.)

Demux clocking

Clocking state machine

Pipeline delays

For the TLA7Nx/Px/Qx logic analyzer modules, each channel can be programmed with a pipeline delay of 0 through 3 active clock edges.

For the TLA7Lx and TLAMx logic analyzer modules, the user interface restricts the programming to groups rather than individual channels.

It is possible to use storage control and only store data when it has changed (transitional storage).

Applies to asynchronous sampling only. Setup and hold window speciﬁcation applies to synchronous sampling only.

Any or all of the clock channels may be enabled. For an enabled clock channel, the rising edge, falling edge, or both edges can be selected as the active clock edges. The clock channels are stored.

Full and half speed modes are controlled by PowerFlex options and upgrade kits.

Table 73: LA module trigger system

Characteristic Description

Triggering Resources

Word/Range recognizers

Range recognizer channel order

Glitch detector

Minimum detectable glitch pulse width

(Typical)

Setup and hold violation detector

Transition detector

16 word recognizers. The word recognizers can be combined to form full width, double bounded, range recognizers. The following selections are available:

16 word recognizers

13 word recognizers

10 word recognizers

7 word recognizers

4 word recognizers

0 range recognizers

1 range recognizer

2 range recognizers

3 range recognizers

4 range recognizers

From most-signiﬁcant probe group to least-signiﬁcant probe group: C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 CK1 CK0

Missing channels for modules with fewer than 136 channels are omitted. When merged, the range recognition extends across all the modules; the master module contains the m ost-signiﬁcant groups.

The master module is to the left (lower-numbered slot) of a merged pair.

The master module is in the center when three modules are merged. Slave module 1 is located to the right of the master module, and slave module 2 is located to the left of the master module.

Each channel group can be enabled to detect a glitch

2.0 ns (single channel with a P6417, P6418, or P6434 probe)

Each channel can be enabled to detect a setup and hold violation. The range is from 8 ns before the clock edge to 8 ns after the clock edge. The range can be selected in 0.5 ns increments.

For the TLA7Lx and TLAMx logic analyzer modules, the user interface restricts the setup and hold violation detector to groups rather than individual channels.

The setup and hold violation of each window can be individually programmed.

Each channel group can be enabled or disabled to detect a transition between the current valid data sample and the previous valid data sample.

64 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7Lx/Mx/Nx/Px/Qx Module Speciﬁcations

Table 73: LA module trigger system (cont.)

Characteristic Description

Counter/Timers 2 counter/timers, 51 bits wide, can be clocked up to 250 MHz. Maximum count is 251.

Maximum time is 9.007 X 10

Counters and timers can be set, reset, or tested and have zero reset latency.

Signal In 1

Signal In 2

A backplane input signal

Trigger In A backplane input signal that causes the main acquisition and the MagniVu

acquisition to trigger if they are not already triggered

Active trigger resources

16 maximum (excluding counter/timers)

Word recognizers are traded off one-by-one as Signal In 1, Signal In 2, glitch detection, setup and hold detection, or transition detection resources are added.

Trigger States

Trigger State sequence rate

r Machine Actions

Trigge

Same rate as valid data samples received, 250 MHz maximum

Main acquisition trigger Triggers the main acquisition memory

Main trigger position

Increment counter

Trigger position is programmable to any data sample (4 ns boundaries)

Either of the two counter/timers used as counters can be increased.

Start/Stop timer Either of the two counter/timers used as timers can be started or stopped.

Reset counter/timer Either of the two counter/timers can be reset.

n a counter/timer is used as a timer and is reset, the timer continues in the

Whe started or stopped state that it was in prior to the reset.

ignal sent to the backplane to be used by other modules

Signal out

igger out

torage Control

lobal storage

rigger out signal sent to the backplane to trigger other modules

torage is allowed only when a speciﬁc condition is met. This condition can use any

S of the trigger machine resources except for the counter/timers. Storage commands deﬁned in the current trigger state will override the global storage control.

Global storage can be used to start the acquisition with storage initially turned on (default) or turned off.

By event

Storage can be turned on or off; only the current sample can be stored. The event storage control overrides any global storage commands.

Block storage

When enabled, 31 samples are stored before and after the valid sample.

Block storage is disallowed when glitch storage or setup and hold violation is enabled.

Glitch violation storage The acquisition memory can be enabled to store glitch violation information with each

data sample when asynchronous sampling is used. The probe data storage size is reduced by one half (the other half holds the violation information). The fastest asynchronous sampling rate is reduced to 10 ns.

Each use of a glitch detector, setup and hold violation detector, or transition detector requires a trade-off of one word recognizer resource.

Any glitch is subject to pulse width variation of up to the channel-to-channel skew speciﬁcation + 0.5 ns.

For TLA7N1, TLA7N2, TLA7N3, TLA7N4, TLA7P2, TLA7P4, TLA7Q2, and TLA7Q4 Logic Analyzer modules, any setup value is subject to variation of up to

1.8 ns; any hold value is subject to variation of up to 1.2 ns. For TLA7L1, TLA7L2, TLA7L3, TLA7L4, TLA7M1, TLA7M2, TLA7M3, and TLA7M4 Logic Analyzer modules, any setup value is subject to variation of up to 1.6 ns; any hold value is subject to variation of up to 1.4 ns.

seconds or 104 days.

TLA Product Speciﬁcations & Performance Veriﬁcation 65

TLA7Lx/Mx/Nx/Px/Qx Module Speciﬁcations

This mode can be

used to create transitional storage selections where all channels are enabled.

Table 74: LA module MagniVu feature

Characteristic D escription

MagniVu memory depth 2016 samples per channel

MagniVu sampling period Data is asynchronously sampled and stored every 500 ps in a separate

high resolution memory.

Table 75: LA module data handling

Characteristic Description

Nonvolatile memory retention time (Typical) Battery is integral to the NVRAM. Battery life is > 10 years.

Table 76: LA module input parameters with probes

Characteristic Description

Threshold Accuracy

Threshold range and step size

Threshold channel selection 16 threshold groups assigned to channels.

Channel-to-channel skew

Channel-to-channel skew (Typical) ≤ 1.0 ns typical (When merged, add 0.3 ns for the slave module.)

Sample uncertainty

Probe input resistance (Typical) 20 kΩ

Probe input capacitance: P6417, P6434 (Typical)

Probe input capacitance: P6418 (Typical)

Minimum slew rate (Typical) 0.2 V/ns

Maximum operating signal 6.5 V

Probe overdrive

P6417, P6418

P6434

Maximum nondestructive input signal to probe ±15 V

±100 mV

Settablefrom+5Vto-2Vin50mVsteps

P6417 and P6418 probes have two threshold settings, one for the clock/qualiﬁer channel and one for the data channels.

P6434 probes have four threshold settings, one for each of the clock/qualiﬁer channels and two for the data channels (one per 16 data channels).

≤ 1.6 ns maximum (When merged, add 0.5 ns for the slave module.)

Asynchronous

Sample period

Synchronous

500 ps

2pF

1.4 pF data channels

2 pF CLK/Qual channels

p-p

-3.5 V absolute input voltage minimum

6.5 V absolute input voltage maximum

±250 mV or ±25% of signal swing minimum required beyond threshold, whichever is greater

±300 mV or ±25% of signal swing minimum required beyond threshold, whichever is greater

±4 V maximum beyond threshold

66 TLA Product Speciﬁcations & Performance Veriﬁcation

TLA7Lx/Mx/Nx/Px/Qx Module Speciﬁcations

Table 76: LA module input parameters with probes (cont.)

Characteristic Description

Minimum input pulse width signal (single channel) (Typical)

Delay time from probe tip to input probe connector (Typical)

2ns

7.33 ns

Table 77: LA module mechanical

Characteristic D escription

Slot width Requires 2 mainframe slots

Weight (Typical) 5 lbs 10 oz. (2.55 kg) for TLA7N4 and TLA7P4

63 kg) for TLA7N4 and TLA7P4 packaged for domestic shipping

8lbs(3.

l dimensions

Overal

Probe cables P6417 length

Mainframe interlock 1.4 ECL keying is implemented

Height

Width

Depth

P6418 length

length

P6434

262 mm (

61 mm (2.39 in)

373 mm (14.7 in)

1.8 m (6 ft)

1.93 m

1.6m(5ft2in)

10.32 in)

(6 ft 4 in)

TLA Product Speciﬁcations & Performance Veriﬁcation 67

TLA7PG2 Module Speciﬁcations

TLA7PG2 Modul

eSpeciﬁcations

The followin

g tables list the speciﬁcations for the pattern generator module. For information on the individual pattern generator probes, refer to TLA7PG2 Pattern Generator Probe Instruction Manual.

Table 78: PG module electrical speciﬁcation, operational mode

Characteristic D escription

Operational mode

Normal

Step Pattern data output is synchronized by the software command

Output pattern

Maximum

Output level: 5 V

Load: 1 MΩ +1pF

Series

Maximu

Output level: 5 V

Load: 1 MΩ +1pF

s termination resistor: 75 Ω

Serie

mum Operating Frequency

Maxi

Pattern length

Data Output Rate

termination resistor: 75 W

m Clock Output Frequency

Pattern data output is synchronized by the internal/external clock input

134 MB/s in Full Channel Mode

268 MB/s in Half Channel Mode

134 MHz

134 MHz in Half Channel Mode

The m level, output pattern and the load condition, including the series termination resistor in the probe. Operating conditions exceeding this frequency may resu

40 t

80 to 524,280 (2

40 to 1,048,572 (2 up

80 to 2,097,144 (2 upgrade)

in Full Channel Mode

aximum operating frequency of the module is a function of the output

lt in damage to the probe.

o 262,140 (2

grade)

- 4) in Full Channel Mode (standard)

- 8) in Half Channel Mode (standard)

- 4) in Full Channel Mode (option 1M or PowerFlex

- 8) in Half Channel Mode (option1M or PowerFlex

68 TLA Product Speciﬁcations & Performance Veriﬁcation

Table 78: PG module electrical speciﬁcation, operational mode (cont.)

Characteristic Description

Number of channels

Sequences

Number of blocks

Number of subsequences

Subsequences

Repeat count

64 channels in Full Channel Mode

32 channels in Half Channel Mode

The pattern memory for the following data channel will be shared with strobe control/internal inhibit control

Probe D data output channel

D0:0

D0:1

D0:2

D0:3

D0:4

D0:5

D0:6

D0:7

Maximum 4,000

Maximum 50

Maximum 256 steps

1 to 65,536 or inﬁnite

TLA7PG2 Module Speciﬁcations

Control

STRB0

STRB1

STRB2

STRB3

Inhibit probe A

Inhibit probe B

Inhibit probe C

Inhibit probe D

Table 79: PG module clocking

aracteristic

Internal clock

Clock Period 2.0000000 s to 7.462865 ns in Full Channel Mode

Period Resolution 8 digits

Frequency Accuracy ± 100 ppm

External clock input

Clock Rate DC to 134 MHz in Full Channel Mode

Polarity Normal or Invert

Range -2.56 V to +2.54 VThreshold

Resolution 20 mV

Input Impedance

Sensitivity

scription

.0000000 s to 3.7313432 ns in Half Channel Mode

DC to 267 MHz in Half Channel Mode

1kΩ terminated to GND

500 mV

p-p

TLA Product Speciﬁcations & Performance Veriﬁcation 69

TLA7PG2 Module Speciﬁcations

Table 80: PG mod

Characteristic Description

Event Action Advance, Jump

Number of Eve

Number of Ev

Event Mode

Event Filter None or 50 ns

ule event processing

nt Inputs

ent Deﬁnitions

for Advance

for Jump

8 External Ev

8(Amaximum

Edge or Level

and Inhibit

ent Inputs (2 per each probe)

of 256 event input patterns can be OR’d to deﬁne an event)

Table 81: PG module inter-module interactions

Characteristic D escription

Signal Input Input from backplane

Selectable from Signal 1, 2, 3, and 4

Used to deﬁne the Event

Signal Output Output to backplane

Selectable from Signal 1, 2, 3, and 4

Speciﬁed as High or Low in each Sequence line

Table 82: PG module merged PG modules

Characteristic Description

Number of modules that can be merged together

External Event Input for merged module For Jump and Advance, only the External Event Input of the leftmost

Five

ule is used. For Inhibit, each module uses its own External Event

mod Input as a source

Table 83: PG module mechanical

Characteristic D escription

Slot width Requires two mainframe slots

Weight(Typical) 2.5 kg (5 lbs. 4 oz.)

Overall dimensions (excluding connectors)

Mainframe interlock 1.4 ECI keying is implemented

Height

Width

Depth

10.32 in (262 mm)

2.39 in (61 mm)

14.7 in (373 mm)

70 TLA Product Speciﬁcations & Performance Veriﬁcation

DSO Module Speciﬁcations

DSO Module Spe

ciﬁcations

The followin

g tables list the speciﬁcations for the DSO Module.

Table 84: DSO module signal acquisition system

Characteristic Description

Accuracy, DC gain

Accuracy,

Analog bandwidth, DC-50 Ω coupled

Bandwidth, analog, selections 20 MHz, 250 MHz, and FULL on each channel

Calculated rise time (Typical)

Typical full-bandwidth rise times are shown in the chart to the right

Crosstalk (channel isolation) ≥300:1 at 100 MHz and ≥100:1 at the rated bandwidth for the channel’s

Digitized bits 8

internal offset

±1.5% for full scale ranges from 20 mV to 100 V

±2.0% for full scale ranges <19.9 mV

Full scale range setting

10 mV - 1 V

1.01 V - 10 V

10.1 V - 100 V

Full scale range setting

10.1 V - 100 V

100 mV - 10 V

50 mV - 99.5 mV

20 mV - 49.8 mV

10 mV - 19.9 mV

Full scale range setting

10.1 V - 100 V

100 mV - 10 V

50 mV - 99.5 mV

20 mV - 49.8 mV

10 mV - 19.9 mV

sensitivity (Full Scale Range) setting, for any two channels having equal sensitivity settings

Offset accuracy

±[(0.2% x offset) + 1.5 mV + (6% x full scale range)]

±[(0.25% x offset) + 15 mV + (6% x full scale range)]

±[(0.25% x offset) + 150 mV + (6% x full scale range)]

Bandwidth

DC - 500 MHz (TLA7E1 and TLA7E2)

DC - 500 MHz (TLA7D1 and TLA7D2)

DC - 1 GHz (TLA7E1 and TLA7E2)

DC - 500 MHz (TLA7D1 and TLA7D2)

DC - 750 MHz (TLA7E1 and TLA7E2)

DC - 500 MHz (TLA7D1 and TLA7D2)

DC - 600 MHz (TLA7E1 and TLA7E2)

DC - 500 MHz (TLA7D1 and TLA7D2)

DC - 500 MHz (TLA7E1 and TLA7E2)

DC - 500 MHz (TLA7D1 and TLA7D2)

TLA7E1 and TLA7E2

900 ps

450 ps

600 ps

750 ps

900 ps

TLA7D1 and TLA7D2

900 ps

TLA Product Speciﬁcations & Performance Veriﬁcation 71

DSO Module Speciﬁcations

Table 84: DSO module signal acquisition system (cont.)

Characteristic Description

Effective bits, real time sampling (Typical)

Input frequency

TLA7E1 and TLA7E2 5 GS/s (each channel)

Frequency limit, upper, 20 MHz bandwidth limited

10.2 MHz

98 MHz

245 MHz

490 MHz

990 MHz

20 MHz

6.2 bits

6.1 bits

6.0 bits

5.7 bits

5.2 bits

(Typical)

Frequency limit, upper, 250 MHz bandwidth limited

250 MHz

(Typical)

Input channels

Input coupling

Product

TLA7E2

TLA7D2

TLA7E1

TLA7D1

DC, AC, or GND

Channels

Input impedance, DC-1 MΩ coupled 1 MΩ ±0.5%inparallelwith10pF±3pF

Input impedance selections

1MΩ or 50 Ω

Input resistance, DC-50 Ω coupled 50 Ω ±1%

Input VSWR, DC-50 W coupled ≤1.3:1 from DC - 500 MHz, ≤1.5:1 from 500 MHz - 1 GHz

Input voltage, maximum, DC-1 M Ω ,AC-1MΩ,or GND coupled

Input voltage, maximum, DC-50 Ω or AC-50 Ω

300 V at 20 dB/decade above 1 M Hz

but no greater than ±420 V peak, Installation category II, derated

RMS

, with peaks ≤ ±25 V

RMS

Coupled

Lower frequency limit, AC coupled (Typical) ≤10 Hz when AC-1 MΩ Coupled; ≤200 kHz when AC-50 Ω Coupled

Random noise

Bandwidth

RMS noise

selection

Range, internal offset

Full

250 MHz

20 MHz

Full scale range

≤(350 μV + 0.5% of the full scale Setting)

≤(165 μV + 0.5% of the full scale Setting)

≤(75 μV + 0.5% of the full scale Setting)

Offset range

setting

Range, sensitivity (full scale range), all channels

10 mV - 1 V

1.01 V - 10 V

10.1 V - 100 V

10 mV to 100 V

±1 V

±10 V

±100 V

TLA7D1 and TLA7D2

2.5 GS/s (each channel)

6.2 bits

6.1 bits

6.0 bits

5.7 bits

N/A

72 TLA Product Speciﬁcations & Performance Veriﬁcation

DSO Module Speciﬁcations

Table 84: DSO module signal acquisition system (cont.)

Characteristic Description

Step response settling errors (Typical)

Net offset is the nominal voltage level at the digitizing oscilloscope input that corresponds to the center of the A/D Converter dynamic range. Offset accuracy is the accuracy of this voltage level.

The limits given are for the ambient temperature range of 0 °C to +30 °C. Reduce the upper bandwidth frequencies by 5 MHz for each °C above +30 °C. The bandwidth must be set to FULL.

Rise time (rounded to the nearest 50 ps) is calculated from the bandwidth when Full Bandwidth is selected. It is deﬁned by the following formula:

Rise Time (ns) = 450 BW (MHz)

GND input coupling disconnects the input connector from the attenuator and connects a ground reference to the input of the attenuator.

The AC Coupled Lower Frequency Limits are reduced by a factor of 10 when 10X passive probes are used.

The sensitivity ranges from 10 mV to 100 V full scale in a 1-2-5 sequence of coarse settings. Between coarse settings, you can adjust the sensitivity witha resolution equal to 1% of the more sensitive coarse setting. For example, between the 500 mV and 1 V ranges, the sensitivity can be set with 5 mV resolution.

The Full Bandwidth settling errors are typically less than the percentages from the table.

The maximum absolute difference between the value at the end of a speciﬁed time interval after the mid-level crossing of the step, and the value one second after the mid-level crossing of the step, expressed as a percentage of the step amplitude. See IEEE std. 1057, Section 4.8.1, Settling Time Parameters.

Full scale range setting

10 mV - 1 V

1.01 V - 10 V

10.1 V - 100 V

± Step response

≤2V

≤20 V

≤200 V

Maximum setting error (%) at

20 ns 100 ns 20 ms

0.5%

1.0%

0.2%

0.5%

0.1%

0.2%

Table 85: DSO module timebase system

Characteristic Description

Range, Extended Real-time Sampling Rate 5 S/s to 10 MS/s in a 1-2.5-5 sequence

Range, Real-time Sampling R ate

Products Limits

TLA7E1 and TLA7E2

25 MS/s to 5 GS/s on all channels simultaneously in a 1-2.5-5 sequence

TLA7D1 and TLA7D2

25 MS/s to 2.5 GS/s on all channels simultaneously in a 1-2.5-5 sequence

Record Length 512, 1024, 2048, 4096, 8192, and 15000

Long Term Sample Rate

±100 ppm over any ≥ 1 ms interval

Table 86: DSO module trigger system

Characteristic Description

Accuracy (Time) for Pulse Glitch or Pulse Width

Triggering

Accuracy (DC) for Edge Trigger Level, DC Coupled

Range (Time) for Pulse Glitch and Pulse Width Triggering

Range, Trigger Level

Time Range Accuracy

2 ns to 500 ns

520 ns to 1 s

± (20% of setting + 0.5 ns)

± (104.5 ns + 0.01% of setting)

±( ( 2% × | Setting) | ) + 0.03 of Full Scale Range + Offset Accuracy) for signals having rise and fall times ≥20 ns

2nsto1s

Source

Range

Any Channel ±100% of full scale range

TLA Product Speciﬁcations & Performance Veriﬁcation 73

DSO Module Speciﬁcations

Table 86: DSO module trigger system (cont.)

Characteristic Description

Range, Trigger Point Position

Resolution, Trigger Level

Resolution, Trigger Position

Sensitivities, Pulse-Type Runt Trigger (Typical) 10% of full scale, from DC to 500 MHz, for vertical settings >100 mV full

Sensitivities, Pulse-Type Trigger Width and Glitch

(Typical)

vity, Edge-Type Trigger, DC Coupled

Sensiti

Sensitivity, Edge-Type Trigger, Not DC Coupled

(Typical)

Time, Minimum Pulse or Rearm, and Minimum Transition Time, for Pulse-Type Triggering (Typical)

Trigger Position Error, Edge Triggering (Typical)

The trigger position errors are typically less than the values given here. These values are for triggering signals having a slew rate at the trigger point of ³5% of full scale/ns.

Minimum: 0%

Maximum: 100%

0.2% of full scale for any Channel source

One Sample Interval at any Sample Rate

scale and ≤10 V full scale at the BNC input

10% of full scale for vertical settings >100 mV full scale and ≤10 V full scale at the BNC input

The minimum signal levels required for stable edge triggering of an acquisition when the trigger source is DC-coupled

Products Trigger

Sensitivity

Source

TLA7E1 and TLA7E2

Any Channel 2.5% of Full Scale Range

from DC to 50 MHz increasing to 10% of Full Scale Range at 1 GHz

TLA7D1 and TLA7D2

Any Channel 2.5% of Full Scale Range

from DC to 50 MHz increasing to 10% of Full Scale Range at 500 MHz

Trigger Coupling Typical Signal Level for Stable Triggering

AC Same as the DC-coupled limits for

frequencies above 60 Hz; attenuates signals below 60 Hz

High Frequency Reject

One and one-half times the DC-coupled limits from DC to 30 kHz; attenuates signals above 30 kHz

Low Frequency Reject

One and one-half times the DC-coupled limits for frequencies above 80 kHz; attenuates signals below 80 kHz

Noise Reject

Three times the DC-coupled limits

For vertical settings >100 mV and £10 V at the BNC input

Pulse Class

Minimum

Minimum Rearm Width

Pulse Width

Glitch

1ns

2 ns + 5% of Glitch Width Setting

Width 1 ns

2 ns + 5% of Width Upper Limit Setting

Acquisition Mode Trigger Position Error

Sample ±(1 Sample Interval + 1 ns)

74 TLA Product Speciﬁcations & Performance Veriﬁcation

DSO Module Speciﬁcations

Table 87: DSO mo

Characteristic Description

Probe Compensator, Output Voltage The Probe

Compensator output voltage in peak-to-peak Volts

dule front-panel connectors

0.5 V (base-top) ± 1% into a ≥ 50 Ω load

Table 88: DSO module mechanical

Characteristic Description

Slot width Requires 2 mainframe slots

Weight (Typical)

Shipping Weight (Typical)

Overall Dimensions Height: 262.05 mm (10.32 in)

Products Weight

TLA7D1 and

TLA7D2 and TLA7E2

Products Weight

TLA7D1 an

TLA7D2 and TLA7E2

Width: 6

Depth: 373.38 mm (14.70 in)

TLA7E1

d TLA7E1

0.66 mm (2.39 in)

2.44 kg (5.38 lbs)

2.55 kg (5.63 lbs)

6.35 kg (14 lbs)

7.71 kg (17 lbs)

TLA Product Speciﬁcations & Performance Veriﬁcation 75

External Oscilloscope (iView) Characteristics

External Osci

lloscope (iView) Characteristics

The followin

g table lists the characteristics for iView (Integrated View) and for the Tektronix logic analyzer mainframe when connected to an external oscilloscope. For detailed information on the individual speciﬁcations of the external oscilloscope, refer to the documentation that accompanies the oscilloscope.

Table 89: External oscilloscope (Integrated View or iView) characteristics

Character

Supporte

TLA application software version

Minimum

Suppor

(For the latest list of supported external oscilloscopes, visit our Web site at www.tektronix.com/la.)

Maximum number of external oscilloscopes One per Tektronix logic analyzer mainframe

iVi

istic

d Tektronix logic analyzer instruments

recommended TLA controller RAM

ted external oscilloscopes as of May, 2008

ew cable length

Descripti

TLA5000 and TLA5000B series

TLA715, T

TLA7012, TLA7016

V5.6 or gr

512 MB

TDS100

TDS1000B and TDS2000B Series

TDS3000, TDS3000B, and TDS3000C Series (TDS3GM or TDS3GV GPIB/R

DPO3000 Series

DPO4000 and MSO4000 Series

TDS50

TDS6000, TDS6000B, and TDS6000C Series

DPO7000 and DPO7000B Series

DPO7

TDS7000 and TDS7000B Series

CSA7000 and CSA7000B Series

TDS6

TDS754C, TDS784C, TDS724D, TDS754D, TDS784D, TDS794D

6.56 ft (2 m)

LA721

eater

0 and TDS2000 Series

S-232 communication module required)

00 and TDS5000B Series

0000 and DSA70000 Series

54C, TDS684C, TDS 694C

76 TLA Product Speciﬁcations & Performance Veriﬁcation

External Oscilloscope (iView) Characteristics

Table 89: External oscilloscope (Integrated View or iView) characteristics (cont.)

Characteristic D escription

Time correlation uncertainty7(Typical at system trigger)

If RAM is less than 256 MB, the record length of the external oscilloscope may be limited to 1 M.

A GPIB extender is needed to connect the iView cable to the oscilloscope. One end of a standard GPIB cable can be used.

If you encounter possible alignment problems with the logic analyzer and oscilloscope waveform edges, refer to Aligning Logic Analyzer and Oscilloscope Waveform Edges. (See page 77, Aligning Logic Analyzer and Oscilloscope Waveform Edges.)

AGPIBtoU

There is a known timing offset between triggers when a TLA logic analyzer is triggered by the oscilloscope. Tektronix is correcting this problem.

When used with a TLA7016 mainframe and an external PC (such as TLA7PC1), the instruments must be physically located close together so that the iView cable can span both instruments. Removing the sleeving from the iView cable assembly increases the spacing distance available between the external PC and the TLA7016 mainframe.

Includes sampling uncertainty, typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a typical number for the measurement.

SB adapter (TEK-USB-488) is required to connect the iView cable to the oscilloscope.

3 ns Logic analyzer triggers external

oscilloscope

(2 ns + logic analyzer sample period + external oscilloscope sample period)

5ns

External oscilloscope triggers logic analyzer

(4 ns + logic analyzer sample period + external oscilloscope sample period)

Alignin

g Logic Analyzer

and Oscilloscope

Waveform Edges

The ﬁrst time that you take an acquisition after changing the horizontal scale setting on TDS1000B, TDS2000B, TDS1000 or TDS2000 series oscilloscopes, the logic analyzer and oscilloscope waveform edges may not be aligned within

sted speciﬁcation. You can realign the waveform positions in the waveform

the li window that contains the oscilloscope data (Menu bar > Data > Time A lignment). Make sure that the external oscilloscope is the data source and then adjust the time offset to align the waveforms. Use the following approximate offsets for various horizontal scale settings. (See Table 90.)

Table 90: TDS1000B, TDS2000B, TDS1000, and TDS2000 Series oscilloscope

eform edge alignment

wav

Horizontal scale Time offset

0ns

250 ns –11 ns

500 ns –18 ns

μs

2.5 μs –50 ns

μs

10 μs –250 ns

25 μs –650 ns

–5 ns

12 ns

–

–120 ns

TLA Product Speciﬁcations & Performance Veriﬁcation 77

Performance Veriﬁcation Procedures

Performance V

Summary Veriﬁcation

eriﬁcation Procedures

This chapter performance veriﬁcation procedures for the TLA7000 series logic analyzer mainframes. Refer to the individual service manuals for performance veriﬁcation procedures for other Tektronix Logic Analyzer products. Generally, you should p erform these procedures once per year or following repairs that affect certiﬁcation.

Functional veriﬁcation procedures verify the basic functionality of the instrument inputs, o diagnostics, extended diagnostics, and manual check procedures. These procedures can be used for incoming inspection purposes.

Certiﬁcation procedures certify the accuracy of an instrument and provide a traceability path to national standards. Certiﬁcation data is recorded on calibration data reports provided with this manual. The calibration data reports are intended to be copied and used for calibration/certiﬁcation procedures.

After completing the performance veriﬁcation procedures or the certiﬁcation procedures, you can ﬁll out a calibration data report to keep on ﬁle with your instrument.

contains procedures for functional veriﬁcation, certiﬁcation, and

utputs, and basic instrument actions. These procedures include power-on

Performance veriﬁcation procedures conﬁrm that a product meets or exceeds the performance requirements for the published speciﬁcations documented in the

ciﬁcations chapter of this manual.

Spe

Test Equipment

ese procedures us e external, traceable signal sources to directly test

Th characteristics that are designated as checked this manual. Always warm up the equipment for 30 minutes before beginning the procedures.

Table 91: Test equipment

Item number and description Minimum requirements Example

1. Benchtop Mainframe TLA7016 Benchtop Mainframe with a logic analyzer module

installed and an external computer with TLA application software installed.

2. Portable Mainframe TLA7012 Portable Mainframe with a logic analyzer module installed

in the Speciﬁcations chapter of

78 TLA Product Speciﬁcations & Performance Veriﬁcation

Performance Veriﬁcation Procedures

Table 91: Test equipment (cont.)

Item number and description Minimum requirements Example

3. Frequency counter

4. Cable, precision

50 Ω coaxial

Frequency accuracy: <0.0025% Frequency range: 1 kHz to 100 MHz

50 Ω , 36 in, male-to-male BNC connectors

Hewlett Packard 5314A

Tektronix part number 012-0482-XX

Functional Veriﬁcation

The following table lists functional veriﬁcation procedures for the benchtop and portabl Installation Manual for installation instructions.

Table 92: Functional veriﬁcation procedures

Instrument Procedure

Benchtop and portable mainframe

e mainframes. If necessary, refer to the TLA7000 Series Logic Analyzer

Power-on and fan operation

-up diagnostics

Power

Extended diagnostics

TLA Mainframe diagnostics

CheckIt Utilities diagnostics

Power-on and Fan

Operation

Extended Diagnostics

Complete the following steps to check the power-on and fan operation of the logic analyzer:

You will need a mainframe with an LA module installed in each mainframe.

ower on the instrument and observe that the On/Standby switch illuminates.

1.P

2. Check that the fans spin without undue noise.

3. If everything is properly connected and operational, you should see the

modules in the System window of the logic analyzer application.

4. If there are no failures indicated in the System window, the power-on diagnostics pass when you power on the mainframe(s).

Do the following steps to run the extended diagnostics:

NOTE. Running the extended diagnostics will invalidate any acquired data. If

you want to save any of the acquired data, do so before running the extended diagnostics.

TLA Product Speciﬁcations & Performance Veriﬁcation 79

Performance Veriﬁcation Procedures

You will need a m

Prerequisites Warm-up time: 30 minutes

Perform the following tests to complete the functional veriﬁcation procedure:

NOTE. Installing a module in the mainframe provides a means of verifying

connectivity and communication between the module and the mainframe. Try using a diff mainframe or to the module.

1. If you hav analyzer application if it did not start by itself.

2. Go to the

3. Verify that all power-on diagnostics pass.

4. Click the Extended Diagnostics tab.

5. Select All Modules, All Tests, and then clicktheRunbuttonontheproperty

sheet.

ainframe with an LA module installed in each mainframe.

erent module and repeat the tests to isolate the problem to the

e not already done so, power on the instrument and start the logic

System menu and select Calibration and Diagnostics.

TLA Mainframe

Diagnostics

CheckIt Utilities

All tests that displayed an "Unknown" status will change to a Pass or Fail status depending on the outcome of the tests.

6. Scroll through the tests and verify that all tests pass.

The TLA Mainframe Diagnostics a re a comprehensive software test that checks the functionality of the mainframes. To run these diagnostics, do the following steps:

1. Quit the logic analyzer application.

2. Click the Windows Start button.

elect All Programs → Tektronix Logic Analyzer → TLA Mainframe

3.S

Diagnostics.

4. Select your instrument from the Connection dialog box (in most cases this will be the [Local] selection).

5. Run the mainframe diagnostics.

CheckIt Utilities is a comprehensive software application used to check and verify the operation of the PC hardware in the portable mainframe. To run the software, you must have either a keyboard, mouse, or other pointing device.

80 TLA Product Speciﬁcations & Performance Veriﬁcation

Performance Veriﬁcation Procedures

Certiﬁcation

NOTE. To check t

the CheckIt Utilities. The test CD needs to contain a ﬁle with a size between 5 MB and 15 MB.

To run CheckIt Utilities, follow these instructions:

1. Quit the logic analyzer application.

2. Click the Windows Start button.

3. Select All Programs → CheckIt Utilities.

4. Run the tes

information on running the software and the individual tests.

The system clock of the controller is checked for accuracy. The instrument is certiﬁable if this parameter meets speciﬁcations. Complete the performance veriﬁcation procedures and record the certiﬁable parameters in a copy of the Calibration Data Report at the end of this chapter.

he DVD drive, you must have a test CD installed before starting

ts. If necessary, refer to the CheckIt Utilities online help for

Perfo

rmance Veriﬁcation Procedures

This section contains procedures to verify that the TLA7012 Portable Mainframe and the TLA7016 Benchtop Mainframe perform as warranted. Verify instrument

ormance whenever the accuracy or function of your instrument is in question.

perf

Tests Performed

Do the following tests to verify the performance of the TLA7012 Portable MainframeandtheTLA7016BenchtopMainframe. (See Table 93.) You will

ed test equipment to complete the performance veriﬁcation procedures. (See

ne Table 91.) If you substitute equipment, always choose instruments that meet or exceed the minimum requirements speciﬁed.

Table 93: Performance veriﬁcation procedures

Parameter Procedure

System clock (CLK 10)

Certiﬁable parameter

10 MHz system clock test

TLA Product Speciﬁcations & Performance Veriﬁcation 81

Performance Veriﬁcation Procedures

Checking the 10 MHz

System Clock (CLK10)

The following p

Equipment required

Prerequisites Warm-up time: 30 minutes

rocedure checks the accuracy of the 10 MHz system clock:

Frequency counter (item 3)

Precision BNC

cable (item 4)

1. Verify that all of the prerequisites above are met for the procedure.

2. Connect the frequency counter to the External Signal Out BNC connector

on the instrument.

3. Go to the System window and select S ystem Conﬁguration from the System menu.

4. In the System Conﬁguration dialog box, select 10 MHz Clock from the list of routable signals in the External Signal Out selection box and click OK.

5. Verify that the output frequency at the External Signal Out connector is 10 MHz ±1 kHz. Record the measurement on a copy of the calibration data

and disconnect the frequency counter.

report

6. In the System Conﬁguration dialog box, reset the External Signal Out signal to Non

82 TLA Product Speciﬁcations & Performance Veriﬁcation

Calibration Data Report

Calibration D

ata Report

Photocopy th instrument.

is table and use it to record the performance test results for your

TLA7012 and TLA7016 Test Record

Instrument model number:

Serial number:

Certiﬁcate number:

Veriﬁcation performed by:

Veriﬁcation date:

System C

Characteristic Speciﬁcation Tolerance Incoming data Outgoing data

Clock frequency

lock Test Data

10 MHz

±1 kHz (9.9990 MHz-10.0010 MHz)

TLA Product Speciﬁcations & Performance Veriﬁcation 83

Tektronix TLA7AB4, TLA7AA1, TLA7AA2, TLA7AA3, TLA7AA4 Performance Verification

Specifications and Main Features

Frequently Asked Questions

User Manual