Tektronix Logic Protocol Analzyer Field Install Instructions

5 Steps to Successful PCI Express Data Capture

Before beginning these procedures, please refer to the Tektronix Logic Protocol Analyzer

Solutions for PCI Express 3.0 Instruction manual (part number 077-0400-xx) to ensure that you

have the proper module and probe type for the link width that you plan to use with your SUT.

CONFIGURE

1

CONNECT

2

P67SA01S,
P67SA04S,
P67SA08S,

or P67SA16S

P67SA01SD

CALIBRATE

TLA7012 Portable mainframe configuration

TLA7016 Benchtop mainframe configuration

3

1. Power on the TLA mainframes and PC, if

Install the TLA Application

software V6.1+. Go to www.tek.com

to download the latest software.

connected (make sure SUT is off or can be reset).

2. Launch TLA application and connect to the desired
TLA instrument (mainframe).

NOTE: The following step is important because the
probe might not be calibrated and may not capture
training sets indicating the link speed, which is done
automatically once the probe is calibrated.

3. In the Setup-SA Window, if using the clock reference
cable, select “Connected at Front Panel.” If using two

TLA7SA08/16
Modules

TLA7SA08/16
Modules

modules, connect the clock reference cable to one
module. Use clock jumper (part number 174-5392-XX)
to connect between both modules.

4. Power on the platform (SUT).

P67SA01SD

5. In the Setup-SA Window, manually select the Link
Rate to match your platform’s current PCle link rate.

6. Configure the SUT for calibration by ensuring the SUT will
operate on Reset with ASPM disabled and operating at PCIe
maximum link speed with minimal traffic, such as, logical idle.

Probe
Solder Down

P6701SD

Probe
Solder Down

P6701SD

SUT

P67SA16

SUT

P67SA16

P67SA08

If you made any changes to your SUT, reset it.

7. In the Setup-SA Window, click the “Calibrate” button.

8. Once calibration has successfully completed,
manually change the link Rate back to “Track Rate.”

9. Reset your SUT so that the TLA will capture the training

P67SA08

P67SA01S,
P67SA04S,
P67SA08S,

or P67SA16S

sets indicating the link speed and width of your SUT.

10. After your SUT has passed its power-on self-tests,
verify that the Setup-SA Window indicators are green for
each lane, indicating successful symbol lock.

NOTES:

*P071292501*

071-2925-01

Tektronix recommends connecting the clock reference cable (part number 872-0594-XX) and enable it in the SUT (see
CALIBRATE step #4), especially if Spread Spectrum or Active State Power Management (ASPM) is enabled. If using the clock
reference cable with two TLA7SA08/SA16 modules, use the SMA-to-SMA clock jumper cable (part number 174-5392-XX).

If you don’t have a 3-pin 100 MHz reference clock on your SUT, connect the clock reference cable directly to your
slot interposer probe.

ACQUIRE

4

Status

Explore the Setup window to modify the setup,

define hardware filters or create a trigger

Click to Open BEV Configuration tab to

enable Flow Control BEV

5

ANALYZE

After acquisition is complete, click “View Summary” to confirm that calibration
was successful and to get an overview of the PCIe protocol elements acquired.
Your screen should show no errors, similar to the screen below.

Click to monitor Acquisition status

Transaction window

displays protocol

layer data

Transaction stitching

Click the View Summary

button for an overview of

the entire acquisition

Training sets (PCIE)

DLLP packets (PCIE)

Errors, PHY layer

ordered sets

Tektronix Logic Protocol Analyzer Solutions

xx

for PCI E xpress 3.0

ZZZ

Instruction Manual

TektronixLogicP rotocolAnalyzer Solutions forPCI Express 3.0

TLA7012/16Mainframes
TLAApplication Software V5.7+
TMS160PCIE3Software
TLA7SAxxLogic Protocol Analyzer Modules
P67SAxxxSerial Analyzer Probes

www.tektronix.com

P077040000*

*

077-0400-00

(full acquisition data analysis viewer)

Bird’s Eye View

For further information, go to www.tek.com and
download “Tektronix Logic Protocol Analyzer
Solutions for PCI Express 3.0, Instruction Manual,
Tek P/N: 077-0400-xx”. Includes design-in
information, such as, probe load models and CAD
layout files.

Listing window

(lane by lane data)