Tektronix Logic Analyzer Solutions for PCI Express 3.0 Primary User

Tektronix Logic Protocol Analyzer Solutions

ZZZ

for PCI Express 3.0

Instruction Manual

TektronixLogic Protocol Analyzer Solutions for PCI Express 3.0

TLA7012/16 Mainframes TLA Application Software V5.8+ TMS160PCIE3 Software TLA7SAxx Logic Protocol Analyzer Modules P67SAxxx Serial Analyzer Probes

www.tektronix.com

P077040003*

077-0400-03

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Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. Speciﬁcations and price change privileges reserved.

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

DPOJET is a registered trademark of Tektronix, Inc.

PCI Express is a registered trademark of PCI-SIG®.

G3PO is a trademark of Corning Gilbert Inc.

October 25

, 2011

Contacting Tektronix

Tektronix, Inc. 14150 SW P.O . B o x 5 00 Beaverton, OR 97077 USA

For product information, sales, service, and technical support:

In Nor World w i de, visit www.tektronix.com to ﬁnd contacts in your area.

Karl Braun Drive

th America, call 1-800-833-9200.

Warranty

Tektronix warrants that this product will be free from defects in materials and workmanship for a period of one (1) year from the date of shipment. If any such product proves defective during this warranty period, Tektronix, at its option, either will repair the defective product without charge for parts and labor, or will provide a replacement in exchange for the defective product. Parts, modules and replacement products used by Tektronix for warranty work may be n the property of Tektronix.

ew or reconditioned to like new performance. All replaced parts, modules and products become

In order to o the warranty period and make suitable a rrangements for the performance of service. Customer shall be responsible for packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country in which the Tektronix service center is located. Customer shall be responsible for paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.

This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a) to repair damage result b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any damage or malfunction caused by the use of non-Tektronix supplies; or d) to service a product that has been modiﬁed or integrated with other products when the effect of such modiﬁcation or integration increases the time or difﬁculty of servicing the product.

TRONIX' RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE

TEK AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

[W2 – 15AUG04]

btain service under this warranty, Customer must notify Tektronix of the defect before the expiration of

ing from attempts by personnel other than Tektronix representatives to install, repair or service the product;

Warranty

Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on the media will be free from defects in materials and workmanship for a period of three (3) months from the date of shipment. If any such medium or encoding proves defective during the warranty period, Tektronix will provide a replacement in exchange for the defective medium. Except as to the media on which this software product is furnished, Tektronix does not warrant that the functions contained in this software product will meet Customer's requirements or that the operation of the programs will be uninterrupted or error-free.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and workmanship within a reasonable time thereafter, Customer may terminate the license for this software product and return this software product and any associated materials for credit or refund.

THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THE PRODUCT IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRO PAYMENT IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, O R CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

[W9b – 15AUG04]

this software product is provided “as is” without warranty of any kind, either express or implied.

NIX' RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER'S

Ta ble of Contents

General Safety Summary ......................................................................................... xi

Service Safety Summary.................. ................................ .................................. ..... xiii

Compliance Information ......................................................................................... xiv

EMC Compliance......... ................................ .................................. ................. xiv

Safety Compliance........................................................................................... xiv

Environmental Considerations ................ ................................ ............................. xvi

Preface ............................................................................................................ xvii

Related Documentation .................................................................................... xvii

Product Description ....... .................................. ................................ ....................... 1

TLA7SA16 x8 Logic Protocol Analyzer Module .................................. ................... 1

TLA7SA08 x4 Logic Protocol Analyzer Module .................................. ................... 1

Midbus Probes...... .................................. ................................ ..................... 2

Slot Interposer Probes ............................... ................................ ..................... 2

Solder-Down Probe ............................ ................................ ........................... 3

Logic Protocol Analyzer Module Controls and Connectors ............... ............................... 4

Front Panel................................ ................................ ................................ . 4

LED Indicators ............................................................................................ 7

Logic Protocol Analyzer and Logic Analyzer Compatibility .... . . . . . . . . . . . . .................... . . . . . . . . . 9

Options and Accessories.......................................................................................... 10

Install Common Hardware........................................................................................ 15

Connecting the Instrument to the SUT ............................ .................................. ............ 16

Clock Cable ................................................................................................... 18

Connecting a Clock Cable .............. ................................ ................................ 18

Connecting a Clock Jumper Cable..................................................................... 18

Connecting a Probe to the Logic Protocol Analyzer Module.............. .............................. 19

Connect the Midbus Probe................................................................................... 19

Handling the Probe Head ....................... .................................. ...................... 20

Connect the Probe........................................................................................ 21

Arranging the Midbus Probe Cables. ................................ ................................ .. 22

Connect the Slot Interposer Probe .......................................................................... 23

Handling the Probe Head ....................... .................................. ...................... 23

Connect the Probe........................................................................................ 23

Connecting a Probe to a x16 Link.......................... ................................ ............ 25

Optional Lane Adapters Installation Overview..................................... .................. 27

Installing the Slot SUT Card Support Bracket . . . . . . . . .................. . . . . . . . . . . ............... . . . . . 28

Connect the Solder Down Probe ............................................................................ 30

Connect to the Logic Protocol Analyzer Module..................................................... 30

P75TLRST Solder Tip........... ................................ .................................. ...... 31

Applying and Removing Power............................................................................. 34

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual i

Table of Contents

Install the TMS

Set Up the Logic Protocol Analyzer Module ............................. ................................ ...... 37

Setup Window ................. ................................ .................................. .................. 38

Open the Setup Window ..................................................................................... 39

Monitoring Signal Activity .... ................................ .................................. ............ 41

Auto Conﬁguration . ................................ ................................ .......................... 42

Link Rate Controls....................................................................................... 43

SUT Reference Clock ........... ................................ ................................ ........ 44

Descramble and Deskew ........ ................................ .................................. ...... 45

Deﬁning a Data Filter.. . . . . . . . . . . . . . . ...................... . . . . . . . . . . . . . . ................... . .. . . . . . . . . . . 45

Maximum Idle Time Detector .......................................................................... 45

Assigning Lanes.. ................................ .................................. ...................... 45

Multimodule Conﬁgurations................................................................................. 47

Probe Calibration .................................................................................................. 48

Calibrate the Probes .................. ................................ ................................ ........ 49

Calibration Results Table Overview ............................. ................................ ...... 50

Probe Recalibration Information ... .................................. ................................ .. 51

Trigger Window ........................... ................................ .................................. ...... 52

Open the Trigger Window ............................. ................................ ...................... 52

Add States, Clauses, Events, and Actions to the Trigger Window .. .................................. .. 53

Delete States, Clauses, Events, and Actions from the Trigger Window .. .............................. 54

Trigger Events........................... ................................ ................................ ...... 54

Create a TLP Event ...................................................................................... 55

Create a DLLP Event.................................................................................... 56

Create a Link Event.............................. ................................ ........................ 57

Create a Sequence Event ................ .................................. .............................. 58

Event Counter, Global Counter, and Timer Overview ................. .............................. 59

Create a Signal-In Event ................................................................................ 60

Trigger Actions ............................................................................................... 60

Acquiring and Viewing Data ..................................................................................... 61

Transaction Window .... ................................ .................................. ........................ 62

Transaction View ....................... .................................. ................................ .... 62

Status Area ............................ ................................ ................................ ........ 63

Packet View ................................................................................................... 63

Examining Transactions...................................... .................................. .............. 64

Physical Layer View.......................................................................................... 64

Using the Transaction Window with the Listing Window ............................................... 65

Bird’s Eye View ................... ................................ ................................ ................ 66

Viewﬁnder ................................................................................................ 66

Location Bar........ ................................ ................................ ...................... 67

Flow Control Visualization Overview...................................................................... 68

160PCIe3 Support Software ................................................................... 35

ii Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Table of Contents

Conﬁgure the Fl

Flow Control Statistics .................................................................................. 69

Summary Proﬁle Window ........................ ................................ ................................ 70

Summary Statistics Tab Notebook Information ............................. .............................. 71

Element Table Information .................................................................................. 72

Create a Custom Element .................. ................................ ................................ .. 74

Listing Window.......... .................................. ................................ ........................ 75

Add Two Sides of a Link to a Single Listing Window . ................................ .................. 76

Change the Data Display in the Listing or Waveform Windows .................... .................... 76

Bus-Speciﬁc Fields ... ................................ ................................ ........................ 77

10-Bit Mode Acquisition.. . . . . . . . . . . . . . ................... . . . . . . . . . . . . . . . .................... . . . . . . . . . . . . .... 78

Change from Binary Listing Symbol Tables to 10-Bit Mode.... .................................. ...... 78

Disassembler Special Messages.................................... .................................. ............ 79

Vendor Deﬁned Message (VDM) Support...................................................................... 81

Probe Dimensions ................................................................................................. 83

Midbus Probe Cable Dimensions .. ................................ ................................ .... 83

P67SA08 Midbus Probe Head Dimensions ........................................................... 84

P67SA08G2 Midbus Probe Head Dimensions ....................................................... 85

P67SA16 Midbus Probe Head Dimensions ........................................................... 86

P67SA16G2 Midbus Probe Head Dimensions ....................................................... 87

Slot Interposer Probe Cable Dimensions .............................................................. 88

P67SA16 Slot Interposer Probe Dimensions...................................... .................... 88

P67SA08S, P67SA04S, and P67SA01S Slot Interposer Probe Dimensions ........ . . . . . . . . . . .... 89

Circuit Board Design........ .................................. ................................ .................... 94

Mechanical Design ........................................................................................... 94

Footprint Dimensions and Keep-Out Area ................................ ............................ 94

Routing Considerations for the Midbus Probe Footprint .......................................... 101

Midbus Probe CAD Symbols for PCB Layout .......................................................... 103

P67SA01SD Probe Solder Tips ........................................................................... 104

TriMode Resistor Solder Tip ......................................................................... 105

Tip Topology ........................................................................................... 105

Soldering the Tips.................. ................................ ................................ .... 106

Reference Clock Cable Three-Pin Connector ............................. .............................. 109

Electrical Design............................................................................................ 111

Measuring Signal Eye ................................................................................. 111

P67SAxx Midbus Probe Circuit Impact ............................................................. 112

P67SA16G2 x8 or P67SA08G2 x4 Midbus Probe Circuit Impact ............... ................ 113

P67SAxx Slot Interposer Probe Circuit Impact..................................... ................ 114

P67SA01SD Solder-Down Probe Circuit Impact .............................. .................... 115

Reference Clock Signal .................................................................................... 117

Recognize the Reference Clock Signal by Connecting to the SUT with a Clock Cable ....... 117

ow Control Visualization......................................... .................... 69

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual iii

Table of Contents

Recognize the C

Midbus Footprint Pin and Probe Input Assignments .................... ................................ .... 119

General Guidelines for Lane Mapping ................................................................... 120

x8 PCI Express Midbus Pin Assignments............... ................................ ............ 121

x4 PCI Express Midbus Pin Assignments............... ................................ ............ 124

P67SA16G2 x8 Midbus Probe Pin Assignments ................................................... 127

P67SA08G2 x4 Midbus Probe Pin Assignments ................................................... 128

Diagnostics ............. .................................. ................................ ........................ 129

Power-On Diagnostics ....................... ................................ .............................. 129

Extended Diagnostics ...................................................................................... 129

Troubleshooting.................................................................................................. 130

General Troubleshooting............. .................................. ................................ .... 130

Probe Troubleshooting ..................... ................................ ................................ 131

Using the P67UHDSMA Probe .......... .................................. .......................... 131

Care and Maintenance .................... .................................. ................................ .... 136

Exterior Inspection ..................... ................................ ................................ .... 136

Inspection and Cleaning...................................... .................................. ............ 137

Module Exterior Cleaning Procedure................................................................ 137

Probe Retention Mechanism Cleaning Procedure.................................................. 137

Probe Cleaning Procedure ............................ ................................ ................ 137

Cleaning the Probe Head.......... ................................ .................................. .. 138

Storing the Probe............................................ ................................ ................ 138

Repackaging Instructions .............................. .................................. .................. 138

Appendix A: TLA Application Software ............. .................................. ...................... 139

Updating the Logic Protocol Analyzer Module Firmware ............................................. 139

Appendix B: File Attachments ....................... .................................. ........................ 141

Probe Electrical Simulation Models.. .................................. ................................ .. 141

Midbus Probe CAD Symbols for PCB Layout .......................................................... 142

Midbus Probe 3D CAD Models........................................................................... 143

Slot Interposer Probe 3D CAD Models .................................................................. 144

DSP Filter Files for Probe Troubleshooting ......... . . . . . . . . . . . . .................... . . . . . . . . . . . . ........ 144

Appendix C: Installing the Midbus Retention M echanism . .............................. .. .. . . . . . . . . . . . . . . 145

Cleaning the Footprint ................... ................................ .................................. 145

Installing the Midbus Retention Mechanism . . . . . ................... . . . . . . . . . . .................... . . . . . . 145

Installing the Retention Mechanism for the P67SA08 or P67SA16 Midbus Probes . . . . . . . .... 146

Appendix D: System Design Review Checklist.............................................................. 151

General Considerations ............................ .................................. ...................... 151

Midbus Probe Conﬁguration .............................................................................. 151

Mechanical Considerations.......... ................................ .................................. .... 151

Electrical Considerations ...................... ................................ ............................ 153

lock Signal Embedded in the Data Stream....................................... 118

iv Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Table of Contents

Appendix E: Rea

Appendix F: Adding Probes to the P67SA01SD Probe Connector ........................................ 159

Appendix G: Solder-Down Probe Bullets..................................................................... 161

Removing the Bullets ...................... ................................ ................................ 161

Inspecting the Bullets and Connectors ................................................................... 163

Installing the Bullets..... . . . . . . . . . . . . . .................... . . . . . . . . . . . . .................. . . . . . . . . . . . . ........ 163

Glossary

Index

rranging Wires in the Probe Connector ................... ................................ 155

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual v

Table of Contents

List of Figure

Figure 1: P67SA16 x8 midbus probe............ .................................. ............................... 2

Figure 2: P67SA08S x8 Slot interposer probe ......... ................................ ......................... 3

Figure 3: P67SA01SD Solder-Down probe ..................................................................... 4

Figure 4: TLA7SA08 logic protocol analyzer front panel ....... ................................ ............. 5

Figure 5: TLA7SA16 logic protocol analyzer front panel ....... ................................ ............. 6

Figure 6: Installing a module. . . .................... . . . . . . . . . . . . .................... . . . . . . . . . . . . .................. 15

Figure 7: Installation overview .................................................................................. 16

Figure 8: Clock cable and clock jumper

Figure 9: Connecting a probe to the retention mechanism.......................... .......................... 21

Figure 10: Arranging the midbus probe cables................................................................. 22

Figure 11: Connecting a slot interposer probe ....................... .................................. ........ 24

Figure 12: Installing an optional slot probe adapter . . . . . . . .................... . . . . . . . . . . . . .................... 27

Figure 13: Slot SUT card s upport bracket conﬁgurations..................................................... 29

Figure 14: Installing the P67SA01SD probe . . . . . . . ................ . . . . . . . . . . . . .................. . . . . . . . . . . .... 31

Figure 15: Connecting the P75TLRST tip to the probe head................................................. 32

Figure 16: Connecting wires to the circuit...................................... ................................ 33

Figure 17: Connecting the tip to the circuit....................................... .............................. 34

Figure 18: Default Setup window ............................................................................... 40

Figure 19: Changes identiﬁed in the Setup window ........................... ................................ 42

Figure 20: Setup window with changes from auto conﬁguration ............................................ 43

Figure 21: Changes from the default channel-lane connections...... ................................ ........ 46

Figure 22: Calibration Dashboard, initial setup .................... . . . . . . . . . . . . .................... . . . . . . . . . . . . 48

Figure 23: Calibration Dashboard, calibrated system ..................... .................................. .. 48

Figure 24: Default Trigger window ............................................................................. 52

Figure 25: Specifying a TLP event .............................................................................. 55

Figure 26: Deﬁning a TLP ....................................................................................... 55

Figure 27: Specify

Figure 28: Deﬁning a DLLP ..................................................................................... 56

Figure 29: Specifying a Link event.................................. .................................. .......... 57

Figure 30: Deﬁning a Link event ...... ................................ .................................. ........ 57

Figure 31: Specifying a symbol sequence ...................................................................... 58

Figure 32: Deﬁning a symbol sequence................................. .................................. ...... 58

Figure 33: Event counter ......................................................................................... 59

Figure 34: Specifying a global counter ......................................................................... 59

Figure 35: Specifying a timer ............ ................................ ................................ ........ 59

Figure 36: Transaction window.................................................................................. 62

Figure 37: Side-by-side Transaction window and Listing window .......................................... 65

Figure 38: BEV with Viewﬁnder and Location Bar ........................................................... 67

cable ................... ................................ .............. 18

ing a DLLP event............................................................................ 56

vi Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Table of Contents

Figure 39: BEV C

Figure 40: Opening the Summary Proﬁle window ............................................................ 70

Figure 41: Summary Proﬁle window............................................................................ 71

Figure 42: Summary Proﬁle window (Summary Statistics Tab Notebook)................................. 72

Figure 43: Deﬁne Packet window for a Custom element in the Summary Proﬁle window ............... 74

Figure 44: Data displayed in the Listing window.............................................................. 75

Figure 45: P67SA08, P67SA08G2, P67SA16, and P67SA16G2 cable length dimensions ....... . . . . . . . . 83

Figure 46: P67SA08 midbus probe head dimensions ..... .................................. .................. 84

Figure 47: P67SA08G2 midbus probe head dimensions...................................................... 85

Figure 48: P67SA16 midbus probe head dimensions ..... .................................. .................. 86

Figure 49: P67SA16G2 midbus probe head dimensions...................................................... 87

Figure 50: P67SA16S, P67SA08S, P67SA04S and P67SA01S Slot Interposer probe cable lengths .. . . 88

Figure 51: P67SA16S Slot Interposer Probe dimensions ..................................................... 89

Figure 52: P67SA08S, P67SA04S, and P67SA01S Slot Interposer probe dimensions.................... 90

Figure 53: PCI Express Compliance Load Board (CLB1).............. ................................ ...... 91

Figure 54: P75TLRST Solder Tip dimensions ..... .................................. .......................... 91

Figure 55: TriMode Resistor Solder Tip dimensions.......................................................... 92

Figure 56: Connecting the P67SA01SD Solder-Down probe ............ .................................. .. 93

Figure 57: x8 midbus footprint dimensions and keep-out area (front side of circuit board) . . ............ 95

Figure 58: x8 midbus footprint dimension and keep-out area (back side of circuit board) .............. . 96

Figure 59: Footprint pad details for x8 and x4 midbus probes ............................................... 96

Figure 60: x4 midbus footprint dimensions and keep-out area (front side of circuit board) . . ............ 97

Figure 61: x4 midbus footprint dimension and keep-out area (back side of circuit board) .............. . 98

Figure 62: P67SA16G2 x8 Midbus footprint dimensions and keep-out area............................... 99

Figure 63: P67SA08G2 x4 Midbus footprint dimensions and keep-out area............................. 100

Figure 64: Recommended trace routing on the primary surface layer................. .................... 102

Figure 65: P67SA08 x4 midbus probe CAD symbol........................................................ 103

Figure 66: P67SA16 x8 midbus probe CAD symbol........................................................ 103

Figure 67: P75TLRST TriMode Long Reach Solder Tip. ................................ .................. 104

Figure 68: TriMode Resistor Solder Tip ...................................................................... 105

Figure 69: Typical wire length from probe tip to circuit .................................................... 106

Figure 70: P75TLRST solder tip with 0.010 inch of tip wire .............. ................................ 107

Figure 71: P75TLRST solder tip with 0.050 inch of tip wire .............. ................................ 107

Figure 72: P75TLRST solder tip with 0.100 inch of tip wire .............. ................................ 108

Figure 73: P75TLRST solder tip with 0.200 inch of tip wire .............. ................................ 108

Figure 74: Reference clock cable connector dimensions ................................................... 110

Figure 75: Signal eye measurements (time versus voltage) ................................................ 111

Figure 76: Probe impact of the P67SAxx midbus probe ........................ ............................ 112

Figure 77: S-parameter data of retention mechanism only ................................................. 113

Figure 78: S-parameter data of retention mechanism plus P67SA16G2 x8 or P67SA08G2 x4 Midbus

probe ......................................................................................................... 114

onﬁguration panel with Flow Control selected ........................................... 69

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual vii

Table of Contents

Figure 79: Prob

Figure 80: S-parameter data of P67SA01SD Solder-Down probe ......................................... 116

Figure 81: Slot interposer probe with a reference clock cable connected ............................. .... 117

Figure 82: P67SA16 x8 midbus probe footprint pin assignments ................. ........................ 119

Figure 83: P67SA08 x4 midbus probe footprint pin assignments ................. ........................ 119

Figure 84: x8 midbus footprint connections for an upstream or downstream conﬁguration ............ 121

Figure 85: x

Figure 86: x8 midbus footprint connections for an upstream and downstream conﬁguration .......... 123

Figure 87: x4 midbus footprint connections for an upstream or downstream conﬁguration ............ 124

Figure 88: x4 midbus footprint connections for an upstream and downstream conﬁguration .......... 125

Figure 89: x4 midbus footprint connections for an upstream and downstream conﬁguration. ......... 126

Figure 90: P67SA16G2 Midbus probe footprint pin assignments ......................................... 127

Figure 9

Figure 92: P67SA08 x4 midbus probe footprint pin assignments ................. ........................ 128

Figure 93: P67SA08G2 x4 midbus footprint connections to module connectors .. ...................... 128

Figure 94: P67UHDSMA probe connected to the inputs of a Tektronix oscilloscope (example 1) . . . . 133

Figure 95: P67UHDSMA probe connected to the inputs of a Tektronix oscilloscope (example 2) . . . . 134

Figure 96: x8 footprint.......................................................................................... 145

Figu

Figure 98: Connecting the P67SA08 midbus probe to the retention mechanism on the circuit board . 148

Figure 99: Installing the retention mechanism ............ . . . . . . . . . . . . . .................... . . . . . . . . . . . . ...... 149

Figure 100: Soldering the anchoring posts to the circuit board (PCB) .. ................................ .. 150

Figure 101: Opening the probe connector .................................................................... 156

Figure 102: Removing the probe sleeve ...................................................................... 156

Figure 104: Removing individual wires ...... ................................ ................................ 157

Figure 105: Inserting additional probe wires ............................... ................................ .. 159

Figure 106: Replaceable bullets and tool ..................................................................... 161

Figure 107: Removing the bullet contacts .................................................................... 162

Figure 108: Inspect the bullet contacts........................................................................ 163

Figure 109: Installing the bullet contacts . ...................... . . . . . . . . . . . . . . ........................ . . . . . . . . 164

1: P67SA16G2 x8 Midbus footprint connections to module connectors........................ 127

re 97: Connecting the P67SA16 midbus probe to the retention mechanism on the circuit board . 147

gure 103: Probe labels.... ................................ ................................ .................... 157

e impact of the P67SAxxS slot probe................. ................................ ...... 115

8 midbus footprint connections in an upstream and downstream conﬁguration ........... 122

viii Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

List of Tables

Table 1: Front panel indicators and connectors ................................................................. 7

Table 2: Status LEDs............................................................................................... 8

Table 3: TLA7SAxx logic protocol analyzer module standard accessories......................... ........ 10

Table 4: P67SA16 and P67SA08 Midbus probes standard accessories ....... .............................. 10

Table 5: P67SA16 and P67SA08 Midbus probes optional accessories...................................... 10

Table 6: P67SAxxS slot probes standard accessories ......................................................... 11

Table 7: P67SAxxS slot probes optional accessories................ .................................. ........ 11

Table 8: P67SA01SD Solder-Down probe

Table 9: P67SA01SD Solder-Down probe optional accessories ............................................. 12

Table 10: P67SA16G2 x8 Midbus probe standard accessories............................................... 12

Table 11: P67SA08G2 x4 Midbus probe standard accessories............................................... 12

Table 12: P67SA16G2 and P67SA08G2 Midbus probes optional accessories ............................. 13

Table 13: TLA7SAxx logic protocol analyzer module and P67SAxxx probes service options . . ........ 13

Table 14: P67UHDSMA standard accessories ................................................................. 13

Table 15: TLA Modules and midbus probes per link.......................................................... 17

Table 16: TLA Modules and slot interposer probes per link ......................... ........................ 17

Table 17: TLA Modules and solder down probes per link.................................................... 17

Table 18: Status indicators in the Setup window............................................................... 41

Table 19: Channel-lane connector colors ... ................................ ................................ .... 46

Table 20: Trigger events .......................................................................................... 54

Table 21: Trigger event recognizer resources .................. .................................. .............. 54

Table 22: Trigger actions ......................................................................................... 60

Table 23: Special characters in the Listing window ... ................................ ........................ 75

Table 24: Logic protocol analyzer disassembly display options ............................................. 77

Table 25: Training sequence messages.......................... ................................ ................ 79

Table 26: Packet framing messages ............................................................................. 79

Table 27: DLLP mess

Table 28: TLP header messages ..... ................................ .................................. .......... 79

Table 29: CRC checking messages ........................ ................................ ...................... 80

Table 30: General acquisition m essages . . . . . . ...................... . . . . . . . . . . . . ...................... . . . . . . . . . . 80

Table 31: Recommended circuit board design criteria ........................................................ 94

Table 32: Trace characterisitics . . . . .................... . . . . . . . . . . . . .................... . . . . . . . . . . . . ............ 101

Table 33: Reference clock cable three-pin connector pin assignments................................ .... 110

Table 34: Reference clock electrical requirements .......................... ................................ 118

Table 35: Failure symptoms and possible causes ............................................................ 130

Table 36: Internal inspection checklist........................................................................ 136

Table 37: Probes and related electrical simulation models ......................... ........................ 141

Table 38: Midbus probe CAD symbols for PCB layout................................... .................. 142

Table of Contents

standard accessories......................... .................... 11

ages............ .................................. ................................ .......... 79

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual ix

Table of Contents

Table 39: Midbu

Table 40: Slot interposer probe 3D CAD models.. ................................ .......................... 144

Table 41: Probes and related DSP ﬁlter ﬁles ....................... ................................ .......... 144

Table 42: P67SA16 x8 Midbus probe retention assembly kit .................. ............................ 147

Table 43: P67SA08 x4 Midbus probe retention assembly kit .................. ............................ 148

Table 44: P67SA16G2 x8 Midbus probe retention assembly kit........................................... 150

Table 45: P6

Table 46: Midbus probe conﬁguration .......................... .................................. ............ 151

Table 47: Midbus probe..................................... ................................ .................... 151

Table 48: Slot interposer probe ................................................................................ 152

Table 49: Reference clock connector.......................................................................... 152

Table 50: Midbus probe..................................... ................................ .................... 153

Tabl e 51

Table 52: Reference clock connector.......................................................................... 154

: Slot interposer probe ...... .................................. ................................ ........ 154

s probe 3D CAD models.. ................................ ................................ .. 143

7SA08G2 x4 Midbus probe retention assembly kit........................................... 150

x Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

General Safety Summary

General Safet

To Avoid Fire or Personal

Injury

ySummary

Review the fo this product or any products connected to it.

To avoid pot

Only qualiﬁed personnel should p erform service procedures.

While using this product, you may need to access other parts of a larger system. Read the safety s ections of the other component manuals for warnings and cautions r

Use proper power cord. Use only the power cord speciﬁed for this product and certiﬁed for the country of use.

Use proper voltage setting. Before applying power, ensure that the line selector is in the proper position for the source being used.

Connect and disconnect properly. Do not connect or disconnect probes or test leads while they are connected to a voltage source.

Ground the product. This product is grounded through the grounding conductor of the power cord. To avoid electric shock, the grounding conductor must be connected to earth ground. Before making connections to the input or output terminals of the product, ensure that the product is properly grounded.

llowing safety precautions to avoid injury and prevent damage to

ential hazards, use this product only as speciﬁed.

elated to operating the system.

Observe all terminal ratings. To avoid ﬁ re or shock hazard, observe all ratings and markings on the product. Consult the product manual for further ratings information before making connections to the product.

The inputs are not rated for connection to mains or Category II, III, or IV circuits.

Connect the probe reference lead to earth ground only.

Do not apply a potential to any terminal, including the common terminal, that exceeds the maximum rating of that terminal.

Power disconnect. The power cord disconnects the product from the power source. Do not block the power cord; it must remain accessible to the user at all times.

Do not operate without covers. Do not operate this product with covers or panels removed.

Do not operate with suspected failures. If you suspect that there is damage to this product, have it inspected by qualiﬁed service personnel.

Avoid exposed circuitry. Do not touch exposed connections and components when power is pre sent.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual xi

General Safety Summary

TermsinThisManual

Symbols and Terms on the

Product

Do not operate i

Do not operate in an explosive atmosphere.

Keep product surfaces clean and dry.

Provide prop

on installing the product so it has proper ventilation.

These terms may appear in this manual:

WARNING.

in injury or loss of life.

CAUTION

damage to this product or other property.

These t

erms may appear on the product:

DANGER indicates an injury hazard immediately accessible as you read the ma

n wet/damp conditions.

er ventilation. Refer to the manual's installation instructions for details

Warning statements identify conditions or practices that could result

. Caution statements identify conditions or practices that could result in

rking.

WARNING indicates an injury hazard not immediately accessible as you

the marking.

read

CAUTION indicates a hazard to property including the product.

The following symbol(s) may appear on the product:

xii Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Service Safety S ummary

Service Safet

y Summary

Only qualiﬁe Safety Summary and the General Safety Summary before performing any service procedures.

Do Not Service Alone. Do not perform internal service or adjustments of this product unless another person capable of rendering ﬁrst aid and resuscitation is present.

Disconnect Power. To avoid electric shock, switch off the instrument power, then disconnect the power cord from the mains power.

UseCareWhenServicingWithPowerOn. Dangerousvoltagesorcurrentsmay exist in disconnect test leads before removing protective panels, soldering, or replacing components.

To avoid electric shock, do not touch exposed connections.

d personnel should perform service procedures. Read this Service

this product. Disconnect power, remove battery (if applicable), and

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual xiii

Compliance Information

Compliance In

EMC C om pliance

EMC Compliance

Australia / New Zealand

Declaration of

Conformity – EMC

formation

This section environmental standards with which the instrument complies.

Meets the intent of Directive 2004/108/EC for Electromagnetic Compatibility when it is used with the product(s) stated in the speciﬁcations table. Refer to the EMC speciﬁcation published for the stated products. May not meet the intent of the directive if used with other products.

European contact.

Tektronix UK, Ltd. Western Peninsula Western Road Bracknell, RG12 1RF United Kingdom

Complies with the EMC provision of the Radiocommunications Act per the following standard, in accordance with ACMA:

CISPR 11:2003. Radiated and Conducted Emissions, Group 1, Class A, in accordance with EN 61326-1:2006.

lists the EMC (electromagnetic compliance), safety, and

Safety Compliance

Equipment Type

Safety Class

Pollution Degree

Description

Test and measuring equipment.

Class 1 – grounded product.

A measure of the contaminants that could occur in the environment around and within a product. Typically the internal environment inside a product is considered to be the same as the external. Products should be used only in the environment for which they are rated.

Pollution Degree 1. No pollution or only dry, nonconductive pollution occurs. Products in this category are generally encapsulated, hermetically sealed, or located in clean rooms.

Pollution Degree 2. Normally only dry, nonconductive pollution occurs. Occasionally a temporary conductivity that is caused by condensation must be expected. This location is a typical ofﬁce/home environment. Temporary condensation occurs only when the product is out of service.

xiv Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Compliance Information

Pollution Degree

Installation (Overvoltage)

Category Descriptions

Pollution Degr that becomes conductive due to condensation. These are sheltered locations where neither temperature nor humidity is controlled. The area is protected from direct sunshine, rain, or direct wind.

Pollution Degree 4. Pollution that generates persistent conductivity through conductive dust, rain, or snow. Typical outdoor locations.

Pollution Degree 2 (as deﬁned in IEC 61010-1). Note: Rated for indoor use only.

Terminals on this product may have different installation (overvoltage) category designations. The installation categories are:

Measurement Category IV. For measurements performed at the source of low-voltage installation.

Measurement Category III. For measurements performed in the building installation.

Measurement Category II. For measurements performed on circuits directly connected to the low-voltage installation.

Measurement Category I. For measurements performed on circuits not directly connected to MAINS.

ee 3. Conductive pollution, or dry, nonconductive pollution

Overvoltage Category

Overvoltage Category I (as deﬁned in IEC 61010-1)

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual xv

Compliance Information

Environmenta

l Considerations

Product End-of-Life

Handling

Restriction of Hazardous

Substances

This section provides information about the environmental impact of the product.

Observe the following guidelines when recycling an instrument or component:

Equipment recycling. Production of this equipment required the extraction and use of natural resources. The equipment may contain substances that could be harmful to end of life. In order to avoid release of such substances into the environment and to reduce the use of natural resources, we encourage you to recycle this product in an appropriate system that will ensure that most of the materials are reused or recycled appropriately.

This product has been classiﬁed as Monitoring and Control equipment, and is outside the scope of the 2002/95/EC RoHS Directive.

the environment or human health if improperly handled at the product’s

This sym Union requirements according to Directives 2002/96/EC and 2006/66/EC on waste electrical and electronic equipment (WEEE) and batteries. For informa Tektronix Web site (www.tektronix.com).

bol indicates that this product complies with the applicable European

tion about recycling options, check the Support/Service section of the

xvi Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Preface

Tektronix Logic Analyzer Solutions for PCI Express 3.0 Primary User

Specifications and Main Features

Frequently Asked Questions

User Manual