Tektronix Package 82 Instruction Manual Addendum Rev. C Instruction Manual

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M INSTRUMENTS

Package 82 Instruction Manual Addendum

INTRODUCTION

This addendum to the Package 82 Instruction Manual is being provided in order to supply you
with the latest information in the least possible time. Please incorporate this information into the
manual where indicated.

59~QO1-02 Rev. $13-90

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ANALYSIS

Once band bending voltage is known, graphs of J?E vs. V,,
C, vs. JIS, and CM vs gS can be generated. Examples are
shown in Figures 4-17 through 4-19. Again, CV curves for
the device are shown in Figure 411.

VFB and 4,, Interpolation

The program determines flatband voltage, Vm , by locating
the VGS point where CH approximately equals C, . V,, is
then interpolated from the closest V, values.

A straight line interpolation from the previous or follow­ing data points is used, and the interpolated V,, and &,
points are computed.

Interface Trap Density vs. Energy from Midgap fDrr vs Ed

Interface trap density is calculated from CIT as shown
below (Nicollian and Brews 322).

C, = oxide capacitance (pF)
A = gate area (cml)
q = electron charge (1.60219 x lo-19C)
1x10-‘1 = units conversion for C,

The results are stored in the Drr column of the array as
calculated.

Interface trap energy from midgap, ET, is computed from
tiS offset by bulk potential, & as follows:

$s - 4. -ET

Where: $SS = band bending (V)

E, = interface trap energy from midgap (eV)

And:

And:

(1 x 10-12) cm

Drr =

Where: CIT

D, - interface trap density (cm-’ eV-I)
C, = quasistatic capacitance (pF)
Gf =

4

= interface trap capacitance (pF)

high-frequency capacitance (pF)

Where: &

- bulk potential (eV)

kT =E thermal energy at room temperature (4.046

x 10-llJ)

q = intrinsic carrier concentration in silicon (1.45

x 10*“cm-3)

N at 90% wW , or NA or NI, if entered by.

Nx =
the user

A typical example of a Dfl vs. ET plot is shown in Figure

420.

4-24

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