Tektronix P7001 /IEEE 488 Instruction Manual

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/|EEE
INTERFACE
021
INSTRUCTION
-0206-00
Serial
MANUAL.
MANUAL
Number
INFORMATION
488
1978
First
Revised
Printing
JUL
DEC 1986
Copyright Contents
form
without the
of
©
1978
this
Tektronix,
publication
written
permission
may
Inc.
not
All
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reproduced
of
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rights
reserved.
in
any
Inc.
Products
by
TEKTRONIX,
registered
is
a
Printed are
Each or
designates
of unique
United
of
Tektronix,
U.S.
and
foreign
TEK,
trademarks
USA.
trademark
Specification
registered
in
reserved.
INSTRUMENT
instrument
stamped
has
the chassis. The
on
the
country
the serial number
each instrument. Those
to
States
have
patents
SCOPE-MOBILE,
a
six
manufactureisidentified
Inc.
of
its
and
Tektronix,
of Tektronix
SERIAL NUMBERS
and/or
and
subsidiaries
pending
price
serial number
first
of
manufacture. The
are
assigned
unique
as
digits.
follows:
covered
are
patents.
and
lnc. TELEQUIPMENT
U.K.
Limited.
change
on
a panel
insert,
number
last
sequentially manufactured
The
country
privileges
tag,
letter
or
five
digits
and
in
are
are the
of
8000000
100000 200000 300000 700000
Tektronix, Tektronix
Tektronix United
Inc.,
Guernsey,
Sony/Tektronix,
Tektronix The
Holland.
Netherlands
Beaverton,
Ltd.,
Kingdom,
Japan
NV,
Heerenveen.
Oregon,
Channel
Ltd.,
USA
islands
London
TABLE
OF
CONTENTS
SECTION
SECTION
SECTION
THE
QUALIFIED
DO
NOT PERFORM OPERATING
IN
DO
SO.
SECTION
SECTION
SECTION
APPENDIX
APPENDIX
APPENDIX
1
2
3
FOLLOWING
PERSONNEL
4
5
6 REPLACEABLE
A
B
C
GENERAL INFORMATION
INSTALLATION
PROGRAMMING INFORMATION
WARNING
SERVICING
ONLY.
ANV
SERVICING
INSTRUCTIONS
MAINTENANCE
DIAGRAMS
DATA
HP
9825
SUPPLEMENTAL INFORMATION
INSTRUCTIONS
TO
AVOID OTHER
UNLESS
SHEETS
PROGRAMMING
YOU
PARTS
FOR
ARE
PERSONAL
THAN
THAT
ARE
QUALIFIED
INFORMATION
BV
USE
INJURV,
CONTAINED
TO
Figure
2—1
waI—‘DWN
WWWL‘ONNN
3—5
3—6
4—1
4—2A 4—2B
4—3
4—4
LIST
OF
Description
Device Address
The
Setting
P7001/IEEE
IEEE
Data
P7001
DPO
Location
Status
HSA
Basic
P7001 P7001
Funct
Component
Funct
Component
488
Transfer
4K
Card
(Timeslots)
Word
Status
Block
Bus Bus
Block
Block
P123
488
Bus
Memory
Address
Readout
of
and Formats
Register
Diagram
Read
Write
Diag.,
Locator
Diag.,
Locator
LIST
ILLUSTRATIONS
Switch
Interface
Connector
Delimiters
Map
Map
Field
Operation
Operation
OF
SW412
Strap Option
Installation
Pin
Assignments
&
Terminators
Words
Bit
MPU/GPIB
and
0
Addresses
Assignments
PIA/P7001
TABLES
Characters
&
Bd
&
Bd
Page 2-1
2 2 2
3
2—4
3 5 3
8
3
9
3—12 3—14 3—15
4—2
4—9
4—9
4—11
4-12
Table
1—1
3—1
3—2
Description
P7001/IEEE
Setting
Query
Commands
Commands
488
Interface
Capability
Page
1-2
3—6
3—7
262531‘
P7001/IEEE
488
INTERFACE
P7001/IEEE
Interface
INTRODUCTION
manuaI
This
Tektronix
terface
DigitaI
P7001/IEEE
is
Processing
tured devices
”IEEE
488
may
imum
4051
a
sends
Standard
Bus
be
A
system
of
Graphic
system
current
is
referred
15
functions
contains
used
to
designed
DigitaI
commonIy
to
configured
devices,
System,
status
readout information
a
Iistener,
system
devices.
receives
it
GENERAL INFORMATION
both
488
Interface,
interconnect
Osci110$cope
to
operate
Interface
known
by
that
and
weII
as
both
as
messages,
to
the
the
as
name.
from
incIudes
as
a
taIker
system
commands
Section
operationaI
Tektronix
P7001
the
(DPO)
in
accordance
for
ProgrammabIe
Genera]
IEEE
488
a
system
”taIkers”
and
data
captured
controIIer
and
data
1
and
maintenance
Part
Processor
with
compatibIe
any
Purpose
controIIer,
and
”Iisteners”.
a
Iistener.
by
or
from
information
021—0206-00.
No.
section
IEEE
Tektronix Standard
of
with
severaI
Instrumentation”.
is
such
a
talker,
system
controIIer
Bus
as
Interface
devices
the
Acquisition
other
the
system
As
a
of
Tektronix
488-1975,
(GPIB),
Iimited
a
Tektronix
DPO
The
the
Unit,
Iisteners.
the
for
and
a
such
DPO
and
in—
IEEE
max-
As
other
This
manufac-
The
to
in
or
IEEE
488
The
by
referencing
PHYSICAL
The
staIIed
necessary
Power
SuppIy
INTERFACE
CAPABILITY
capabiIities
the
applicabIe
CHARACTERISTICS
P7001/IEEE
into
the
operating
via
488
interface sIot
power
the
of
the
Interface
(+5,
P7001
P7001/IEEE
sections
is
of
-5,
Main
Interface
a
the
+15
488
of
duaI
P7001
and
Interface
IEEE
the
card
assemny
Processor
—12VDC)
Board.
defined
are
Standard
designed
section
taken
is
in TabIe
488-1975
to
a
of
from
the
1-1
document.
be
in-
UFO.
AII
P7001
P7001/IEEE
Interface
Table
Interface
Source
Acceptor
Function
Handshake(SH)
Handshake(AH)
TaIker(T)
Listener(L)
Service
Remote—LocaI(RL)
ParaIIeI
Device
Device
Request(SR)
PoII(pP)
CIear(DC)
Trigger(DT)
ControIIer(C)
1—1
P7001/IEEE
IEEE
Std.
488
.10
.11
.12
488
Interface
Section
CapabiIity
Interface
CompIete(SH1)
CompIete(AH1)
No
“TaIk
No
”Listen
CompIete
None(RLfl)
N0ne(PP¢)
None(DCQ)
None(DTg)
None(cg)
CapabiIity
Only”
OnIy”
(SR1)
Mode(T6)
Mode(L4)
1—2
P7001/IEEE
lnterlace
INTRODUCTION
This
Tektronix
section
488
compatible
Address
section
P7001/IEEE
of
and
controllers.
INSTALLATION
The
P7001/IEEE
sor
2—3.
dress
using
the
Before the
and
the
of
Tektronix
a
device.
for
setting
488
instructional
interface
P123
Strap
manual
the
488
Digital
Included
a
Interface
Section
INSTALLATION
contains
Interface,
Processing
are
strap
Option
option
steps
is
installed,
should
assembly
2
operator/user
used
to
instructions
that
listed
on
however,
be
information
interconnect the
Oscilloscope
for
selecting
facilitates
be
may
set
installed
the
Installation
the
as
explained
IEEE
(DPO)
the
P7001
with
use
in
a
Diagram,
Bus
488
in
the
for
Processor
any
Device
the
of
different
P7001
Device
following
the
IEEE
Proces-
Figure
Ad-
paragraphs.
SELECTING
Selecting
switch,
number.
number
SN412
For
must
DEVICE ADDRESS
Device
the
the
MPU/GPIB
with
0n
devices
be
between
_
Address
talk/listen
$0000
and
LSD
is
board
01110
1f
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——OPEN—
accomplished
(shown
in
Figure
capabilities,
(O
‘5
3
2
14
to
P/O MPU/GPIB
‘*
mg
:
5,
by
setting
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such
decimal),
670-4882—OX
MSD
U413
the
a
to
the
as
inclusive.
BOARD
5—bit
unique
DPO,
DIP
binary
this
Figure
@
2—1
Device
Address Switch
2623—02
SW412
2—1
P7001/IEEE
Interface
SELECTING
Each
switches,
(Most
which
that
left
Device
that
corner
Significant
the
bit
are
Address
When
has
of
viously
SETTING
The
with
option
P123
different
may
set
operation
DEVICE
the
of
numbered
numbers
has
pushed
the
been
the
stored
P123
P123
be
for
(pin
ADDRESS
bits
five
1
on
Digit).
are
been
set
in
at
is
set
DPO
memory
selected
CRT.
STRAP
strap
at
Note
Channel
OPTION
option
controllers.
found
both
in
"Standard"
1
jumpered
(Continued)
is
the
Note
read.
a
to the
to
binary
top
Qflflll
location
with
that
7
allows
Section
to
to
set
left
(Least
that
When
SN412
of
a
1;
and
the other
(3
decimal).
button
will
when
memory
the
A
more
3
of
operation adjacent
1
or
Significant
this
rocker
e.g.,
'D'
be
Device
'D'
interface
thorough
this
(jumper
pin
D
by
five
reversed
is
switch
the
if
three
pushed
is
displayed
Address
(Field
to
explanation
manual.
not
pin
-
corresponding
Digit)
from
is
pushed
first
are
two
in
in,
in
the
is
elicited,
0)
will
operate
Figure
installed)
1
indicated
is
5
to the
in switches
the
at
Device
the
lower
be
destroyed.
more
of
use
shows
2-2
rocker
the
on
the
in
top,
on
order
at
bottom,
Address
right-hand
data
any
efficiently
the
of
connector
and
”Optional"
withu»).
right
the the
pre-
strap
Figure
Access
terface
from
To
on
the
avoid
pin1or
left.
be
now
U122
l
Standard
(a)
2—2
If
de—energized
Setting
to
housing
hole
loss
the
the
the
(see
and
when
adjacent
DPO
P123633
I;
Operation
the
jumper
Figure
reach
operating
was
in with
energized
and
a
:2
g
a
a
a
U123
P123
Strap
is
gained
2—3).
longnose
in
the
(above
pin
while
”power—up”
81
a
Option
through
To
"Standard“
pin
sequence
change
pliers
1)
the
jumper
hole in
a
operating
to
mode,
with
the
performed
(b)
Optional
the
left
modes,
re—position
the
jumper
free
was
end
re-positioned,
to
P123
U122
rear
remove
the
extending
activate
fig:
m
of
8
8
U123
the
Eflifl
OperatiozréS23
the
jumper.
be
it
the
placed to
must
change.
may
73
E
03
in—
plug
the
2—2
@
P7001/IEEE
Inlertace
(Behind
SW412
Side
021—0206-00
P700l/IEEE
Panel)
488
Interface
Interface
Installation
Screws
(2)
Cable
012—0630—01
Assy
INSTALLATION/REMOVAL
With
AC
1.
Processor
2.
Tighten
Connect
.
012-0630—01)
screws.
.
Prior
to
terface
Figure
2—3
P7001/IEEE
power
both
either
removal,
off,
and
press
interface
to
end
the
set
installation
488
insert
in
slowly
installation
of
the
interface
the
screws
.
Interface
the
IEEE
AC
power
and
2-3
interface until
488 bus
assembly
the
screws.
cable
at
OFF
to
thumbscrews
Installation
into the
assembly
(Tektronix
and
J1
and
ensure
are
rear is
secure
fully
of the
firmly
seated.
Part
with
the
that
disengaged.
P7001
No.
thumb—
in-
2623-04
P7001/IEEE
IEEE
488
Interface
BUS
CONNECTOR
IEEE
The
shown
as
This
8
interlaced
controller
nector
The
Part
on
24-pin
pin
interface
No.
012-0630—01
or arrangement
double—sided,
and
female
a
Bus
488
Figure
Connector
2-3,
female ribbon
ground
other
lines,
IEEE
and
also includes the
(standard
with
side for
male
a
connecting
SHIELD
and
is
connector
and
488
compatible
signal
side
SRO
ATN IFC
located
is
physically
has
used
is
to
nomenclature.
line
mating
2
to
meter
mate
IEEE
with
additional
NDAC
DAV
NRFD
the
at
attached
attached
rear
to
16
active
interconnect the
device.
connector
488
the
system
Dl04
EOI
cable).
connector
DIOZ
D|03
Figure
components
DI01
panel
the
and
of
MPU/GPIB
signal
DPO
2—4
shows
cable,
This
on
the
interface,
Board.
lines
with
the
Tektronix
connector
the
interface
the
to
a
system con-
bus.
and
is
Figure
2-4
IEEE
488
GND
LOGIC
GND
Bus
GND
GND
‘0
9
GND
11
Connector
8
GND
7
2—4
REN D|O7
DIOB
GND
6
Pin
Assignments
DIOS
DIOG
@
P7001/IEEE
Interface
INTRODUCTION
section
This
general
4051
formats
patible
iarity
nature
Graphic
used
controller.
non-Tektronix
For
with the
Regardless
ation of
an
understanding
for
Programmable
Option“
Section tional
rear
the
In
addition,
in
2
information
of
this
of
this
for
PROGRAMMING
the
of
and
System
to
operate
a
for
as
system
Examples
controllers,
programming
which
DPO,
setting
manual.
controller
use
or
IEEE
of
Instrumentation”.
non—Tektronix
for
section
the
on
use
manual
specific
DPO
the
language
the
of Standard
the
of
strap
with
Section
INFORMATION
contains
type
controller.
under
given
is
DPO
manual,
option,
the
program
are
such
of
being
Operators
488—1975,
controllers,
HP—9825
3
operator/user
of
system
utilizing
Included
control
the
the
system
TEK
HP—9825
in
as
the
utilized,
Manual
”IEEE
the
and
the
corresponding
be
contained
is
read
must
information
the
commands
are
from
any
BASIC
4051
and
HP—9830,
controller
familiarity
and
understood.
in
be
Digital
Appendix
will
Standard
paragraph
both
of
Tektronix
command
and
IEEE
488
language.
famil—
essential.
is
with the
useful,
oper—
as
Interface
entitled
"Strap
instructions
Addi-
II
at
a
com-
will
in
the
GENERAL
INFORMATION
The
P7001/IEEE
compatible
cilloscope
488
bus;
allows
”controllers”,
specific
pendently.
connected
tem tem
functions
captured
cule
(waveforms),
OPERATING
with
use
tions
the
appendix
Power
When
ates
488
bus.
terrupt poll,
TEK
the
by
readout
Most
of
a
for
instructions
to
On/Initialization
a
(through
determined
shown
as
4051".
488
device with
(0P0).
There
listeners
The
responsibility
instruments
both
as
DPO
the
information
commands,
INSTRUCTIONS
the
TEK
4051
other
this
DPO
goes
the
This
condition
in
(i.e.,
operating
Graphic
IEEE
included
manual
through
interface)
by
a
subsequent
Interface
P7001
the
three
are
"talkers”,
and
are
a
talker
waveforms),
the
to
and
internal
instructions
System
488
controllers
here
gives
the
an be
may
programming
be
can
bus
of
different
and
talkers
of
the
to
listen
and
a
listener.
bus.
memory
as
may
and
those
operating
power—on
interrupt
cleared
the
paragraph
used
a
to
interconnect
Tektronix
types
"listeners”.
be
to
selected
controller is
to
or
current
As
a
talk.
As
status
listener,
addresses
included
system
be
for
examples
here
controller.
inferred
the
controller
for
transition,
request
and
the
nature
controller
to
entitled
Digital
of devices
IEEE
Standard
and
de-selected
to
designate
DPO
The
a
talker,
messages,
DPO
the
from
the bus.
are
specifically
Operating
from
a
HP-9825
the
automatically
it
(SRQ)
”Servicing
take
signal
and
a
IEEE
any
Processing
the
on
which
such
in
sends
it
and
receives
comparison
utilized.
controller.
the
on
source
serial
of
status
Interrupts
488
Os-
IEEE
488—1975
inde—
sys-
a
sys-
data
grati—
data
for
instruc-
of
An
gener—
IEEE
in—
the
with
@
3—1
P7001/IEEE
Interface
Power
for
On/Initialization
no
If
some
interface
command
The
a
the
DPO
Word
When
following
Status
for
ment,
of
Status
When
on
line
conduct
with
pond
interrupt
Status
interrupt
other
explained
DPO
must
Status
reason
be
interrupt
SRQ
no
Word
DPO
the
IEEE
the
a
status
of
one
request
Word
cleared.
later
Word
has
decimal
0
l6
issues
488
poll
the
for
=
81
=
82
=
83
=
84
=
85
>
18¢
(Continued)
handling
the
controller
in
is
request
been
status
Meaning:
an
bus.
in
order
following
each
Meaning
instructions
does
This
can
be
this section.
used
to
indicate
(SR0),
or
generated,
words:
may
Interface
2
Interface
interrupt,
The
system to
decimal
of
these
its
controller
release
conditions):
DPO
DPO
DPO
:
DPO
:
HSA
:
:
Error
graph
included
are
not
service the
accomplished
the
to
be
solicited
the
interface
idle
busy
interface
SRQ.
the
hung
has
words
up.
but
CALL
Sweep
(if
occurred
status
powered
was
PROGRAM
Single aborted
entitled
by
controller
with
will
(Both
16
asserts
should
The
(the
has
button
completed.
HSA
(see
"Error
in
the
program,
interrupt,
using
cases
be
interface
self—
is
the
the
POLL
a
respond
return
HP
with
the
programmed
DPO
will issue
corrected.
pushed.
installed).
following
Messages").
or
the
”DCLb“
reason
state-
with
controllers)
SRQ
will
one
decimal
signal
to
res-
an
para-
Error
Four
dicated
receipt
Status
Messages
different
the
to
of
the
Word
error
system
SRQ
will
113
114
115
112
conditions
controller
result
Meaning:
may
by
in
SRQ.
an
of
one
Communication
meaningless
the
If
the
error
Examples
ligible
:
Programming have
range
carry
impossible
it
clude
valid
ory.
:
Internal Error
hardware
mean a
transient
:
Other
error
scribed
exist
the
for
A
status
following
or
data will
is
not
include
commands,
Error
been
received
parameters.
the
out
overflowing
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There
grammed
residing
7168;
Front
Further information
found
P7001
(070-1810—00),
in
A/D
Display
(O70-1610-00),
Status
erator
shows
these
over
where
In
er,
is
and
the
In most
registers
most
it
those
then
used
P7001
the
Converter
the
Generator
and
word
Front
HSA
status
cases,
the
of
is
necessary
cases,
the
"0CTb"
to
set
up
format
Panel
because
operating
the
(five
P7001
the
address
7046;
the
on
Processor
Manual
P7001
Manual
Hardware
the
for
Registers
word.
the
user
the
or
”ADRU”
command,
the
contents
if
the
is
HSA
Processor
7424;
and
Readout
Hardware
registers
Manual
(O70—1809-00),
Readout
(070-1608—00),
A/D
the
does
microprocessor
procedures.
desirable
command
which
of the
(Tektronix
Interface
Signal
Converter,
is
illustrated
not
to is
is
installed)
of
the
Interface,
Signal
involved
the
Manual
the
Averager
have
to
residing
However,
control
used
to
explained selected
DPO.
Averager
in
controlling
Part
P7001
P7001
Manual
Readout
in
learn
there
these
select
in
register.
registers
These
7296;
(if
which
are:
Display
installed),
the
No.
070-1882—00),
&
Sample
Hold Manual
(O70-1609-00),
Front
Panel/Z—Axis
(061-1344—00).
Interface,
Figure
to
in
registers
a
3-5.
operate
the
interface
some
are
the
appropriate
subsequent
and
bit
P7001/IEEE
be
can
A/D
Converter, Generator,
6912.
DPO
may
the
P7001
the
Manual
Display
Figure
set
up
takes
operations
by
bit. regist-
paragraph,
Interface
pro-
be
Gen-
3-6
Address:
6912
Used
Not
14
15
13
LV_J
TYPE
AVERAGING
=SNEEP
1
=POINT
Strappable(P73)
Local
in
0—15
l
5
9
10 11 12
14 15
13
PROGRAM CAL
11
12
OF
MODE(LOCAL)
BCD
2
3
7
6
BUTTONS
1M
\
8
Not Used
in
9
8
4A
V
V
MODE(CPU)
k_______1f_______J
QM
=IDLE =IDLE
91
=AVERAGE
IQ
=HISTOGRAM
11
coal
7
A
6 5
WAVEFORM
flflfll
Qfllfl
fllflfl
169M
4
=A
=8
=C =D
Not
Used
3
Z-M
j
Figure
@
3—6
HSA
Status
Register
Bit
Assignments
3—15
P7001/IEEE
OCT
Commands
Interlace
OCT
The
ations of
and
3-5
octal ers
marks,
the
illegal
string
3—6).
numbers
(i.e.,
the
DPO
to
operation.
variable that is
DPO
The
execution
immediately
OCT
is intended
In
the
Panel
to
Panel
variable
4051
Status
P7001
The
Status
won't
Memory,
following
A$
(Octal)
the
16-bit
The
must
in
the
TEK
4051
assert
Address
the
of
preceded
to
following
Register),
lflfl
11¢
Register
used
is
suppress
commands
Status
octal
be
enclosed in
form
of
will
SRQ
to
The
Register
”OCTb"
by
operate.
TEK
Waveform
PRINT PRINT
example
@1:”ADR @1:”OCT
to
rather that
the
are
Words
form
a
string
suppress
the
controller
octal defined
in
”OCT?”
0r
"ADRb"
an
4051
and
line
A.
may
the
controller.
leading
is
used
in
used
to
the
to
send
DPO
ease
quotation
literal).
the
leading
with
representation
line
to
transfer
the
in
to
the
Note
elsewhere
the
interface
commands.
command
example,
11%
sets
“g7w4fl
”;"Q4fl01fl”
be
used
numeric
the
of
zero
receive octal
or
Status
programming.
If
and
not
marks
zero(s),
a
Status
also
may
the
program.
will
In
set
IQQ
not
most
the
selects
Front
the
that
variable
octal
number.
Register
Note
treated
enclosed in
which
Word
be
cases,
P7001
Panel
contents
in
A.
113,
in
the
be
affected
OCT
address
address
Display source
220,
line
This
represent—
(see
Figures
that
charact-
as
quotation
will
cause
indicating
form
will
7@4Q
of
the
the
is
so
the
of
after
be
which
on
(Front
Front
string
the
a
2gp
21%
22¢
PRINT @1:”ADR PRINT
INPUT
@1:”OCT?“ @1:A$
”:7Q4W
3—16
STD
and
The
and
consists
character
mode.
any
ited
The
combination
with
HOL
Commands
”STOb”
string
argument
comma
a
(Store)
of
the
representing
in
any
(e.g.,
command
command
following
order,
”A,C,D”
used
is
mnemonic
DPO
the
command
the
long as
as
or
to
place
followed
channels
mnemonic
all
adjacent
"D,C,A,B”).
by
to
the
a
DPO
one,
be
placed
can
characters
in
two,
be
A,
P7001/IEEE Interface
the Store
three
in
B,
the
C
or
Store
orDor
are
mode,
four
delim—
”HOLb”
The
follows the
string.
The
“STOb”
the
1
DPO
capture
plug—ins.
B
of
acquisition
mode.
Hold
100 110 120 130
Note
that
example
speed along speed
Manual
ing
mately
insert
depends
which
at
with
and
(Tektronix
”SAMPLE
4.5 approximately
command
rules
same
and
”HOLb"
4
to
input
In
the
following
to
Store
a
of
full
PRINT
FOR
I=1
NEXT
PRINT
time
the
the
on
DPO
the
a
graph
input
showing
signal
Part
&
HOLD
and
milliseconds.
puts
as
the
the
commands
signals
TEK
mode,
waveform,
@1:”STO
I
@1:”HOL
to
lines
20
delay
repetition is
operating.
digitizing
repetition
No.
070—1599-00)
A—D
CONVERTER”.
Therefore,
90
milliseconds
selected
”STOb”
are
through
4051
110
and
“;”A,B”
";”A,B”
required
rate
rates,
DPO
command
used
Vertical
the
example,
and
in
130
lines
line
of
A
more
time
may
starting
Each
lines
of
delay
channels
for
together
line
120
create
sets
the
input
detailed
for
be
4051
110
into
delimiters
to
Amplifier
100
a
Channels
and
110
signal
various
found
on
page
FOR
and
120
the
Hold
in
the
mode,
in the
program
sets
time
A
120
of
and
the
and Time
Channels
and
the
to
B
preceding
the
delay
discussion of
combinations of
the
2-2
the
DPO
under
step
Operators
uses
above
in
LOOP
in
program.
and
character
DPO
to
Base
A
and
permit
the
to
sweep
this,
sweep
head—
the
approxi—
example
SSR Command
The
”SSRb”
gering
can
mnemonic ed
comma
event
the
functions
be
captured
in
quotation
must
In
the
waveforms
SRQ
is
line
controller
and
gin
indicate
@
nature
the
100 110
120 130 200 210 220 300
310
(Single—Sweep—Reset)
from
that
so
Time
the
if
followed
marks,
serve
as
following
(four
to
tell
should
then the
of
single—sweep
INIT
ON
PRINT @1:”SSR
GOTO
POLL
IF
RETURN
PRINT
RETURN
a a
by
as
delimiter
TEK
4051
in
this
the
controller
be
SRQ.
THEN
SRQ
130
N,M;1
M=84
THEN
“SINGLE—SWEEP
one
Base
one,
in
plug—ins two,
”STOb”
the
between
example,
example)
programmed
DPO
The
operation
200
”;”A,B,C,D”
30%
command
four
to
three
and
characters.
after
have
that
conduct
to
will
is
complete.
COMPLETED”
3-17
can
waveforms
set
are
four
or
”HOLb“
the
been has
it
send
a
and
reset
up
of
correctly.
arm
single-shot
character
commands. Once
programmed
captured,
something
a
poll
status
to
determine
to
word
the
string
number
the
report.
of
The
DPO
84
DPO
trig-
events
command
enclos-
again,
of
single-
asserts
The
the
decimal
a
ori-
to
P7001/IEEE
Interlace
X—Y
Display
(as
no
If
set
of
display
Y—T
and
The
display
Generator
explained
display
In
the the
to
In
the
Controlling
Hardware
a
If
in the
led
mands.
source
of
The
and
averages
following
Where:
Note
Commands
mode
of
Status
is
PRINT
OCT
specified,
TEK
of
display
@1:”Y-T
example,
under
mode
following
Y—T
mode
following
(horizontal input
PRINT
Hardware
the
DPO,
it
"HAVb"
destination
be
to
example
PRINT
N
S
is
is
B,
D
is the
the
the
C
that
M
that
a
is
ing) averages
X
represents
Sweep
type
“Sweep”.
source
@1:”X—Y
Signal Averager
(the
command
of
taken,
shows
@N:”HAV
Device
source
D),
or
destination
must
S/D
positive
from
or
equal
(note
of
averaging
and
DPO
the
can
Register
commands),
4051
example,
(vertical
"
the
vs
vertical
"
Signal
HSA)
Averager
may
places
waveform
the
and
chooses
the
”HAVb”
“;”S/D
the
how
Address
of
and;
of
be
followed
decimal
1
the
that
to
to
type
P
7
2”,
or
is
destination
be
controlled
and
using
by
or
the
program
the
Display
(Tektronix
be
controlled
HSA
the
to
between
command
”;M;”
of
the
waveform
the
averaged
by
integer
"Point"
(for
and;
of
averaging,
S
must
not
specified,
arrays
the
using
the
will
Display
input
vs
Generator
input).
(HSA)
Part
with
in
the
be
averaged,
Point
is
X“
DPO,
a
be
and;
be
to
space),
from
averaging),
preceded
may
either
”OCTb”
”X-Yb”
default
Generator
time).
is
No.
the
averaging
and
used:
averaged
waveform,
and;
1
12
to
“bP”
for
the
program
be
the
by
command
addressing
to
”Y—Tb”
and
the
to
of
the
to
set
644—0092-00)
”HAVb”
and
mode,
specifies
Sweep
by
same
(DPO
A, B,
(for
with
Point
a
space).
averaging.
Haveform
“Sweep”
the
and
will
desired.
if
set
Y-T
DPO
the
X—Y
is
"HISb"
selects
the
C
or
number
”b8”
If
default
the
13
bit
commands.
mode.
is
mode
instal-
com-
the
number
The
A,
D
(note
averag-
of
for
the
to
The
togram
Where:
”HISb“
mode
command,
of
operation.
N,
S,
H
is
(note
PRINT
M
D,
destination
the
that
HSA
The
tion
Manual
shown
@N1"HIS
X
and
H
must
must
when
used
(TEK
below,
";"3/D/H
as
are
of
be
be
with
P/N
be
may
";M;"
described
the
Histogram,
followed
Note
strapped
the
061-1344—00)
3-18
by
for
TEK
used
XII
for
a
"CPU"
4051.
for
to
place
”HAVb“
the
DPO
space).
opera-
See
details.
the
command,
Waveform
HSA
HSA
A,
in
B,
the
and;
C
or
His-
D
@
P7001/IEEE
Interface
When
SRQ
In
Panel
The
one
was
any
is
of
lOO 11O
the
Front
an
poll. that
button
information,
the
to
be
must
again.
CALL
RAM
with
or
buttons.
A
sample
Command".)
controller. If
O.
Since
be
serviced
It
button
CALL
buttons.
”CLIO”
the
memory.
The
following
(Note
routine
1OO
llO
Interrupts
of
one
generated,
response
PROGRAM
the
pushed,
PRINT
INPUT
foregoing
and
line
only
one
and
is also
O)
if
it
command.
An
example
PRINT
sample
this
for
INIT
ON
DPO
the
then
the
the
to
the
serial
CALL
”FPI?”
@1:”FPI?”
@1:F
example,
11O
transfers
no
front
level
of
cleared
necessary
illuminated
is
Previous
This
of
the
@1:"CLI
routine
sample
Single—sweep
THEN
SRQ
front
panel
controller
poll
buttons
command
1OO
line
the
panel
interrupt
before to
the
extinguish
and
interrupts
command
”CLIb“
shows
routine
interrupts
ZOOO
PROGRAM
should
decimal
is
was
pushed.
is
used,
sets
decimal
button
is
allowed,
PROGRAM
it
and
has
command
a
way
services
only
as
the
up
number
was
CALL
(clear)
desired
is
CPU
the
no
effect
follows:
service the
to
given
is
CALL
buttons
be
programmed
status
In
order
in
the
DPO
pushed,
all
previous
buttons
the
to
BUSY
on
Front
under
word
to
following
to
output
of
the
F
in
BUSY
CPU
re—enable
lamp
other
any
UPC
Panel
the
1-15
is
conduct
to
83,
indicating
find
out
example:
the button
pushbutton
11O
line
interrupts
become
may
active
lamp
the
be
cleared
DPO
PROGRAM
interrupts.
heading
pushed,
a
which
(F)
will
(PROGRAM
PROG—
status
CALL
”SSR
201O 202O
21OO
211O 212O 213O 214O
22OO
221O
222O
223O
In
the
tines
and
for
223O
serve
the service
@
ZOOO
GOTO
GOSUB F
RETURN
foregoing
PROGRAM
to
subroutines
POLL
RETURN
PRINT INPUT
IF
GOSUB F
F=F-9
PRINT
IF
N,M;1
M=83
F>9
222O
example,
CALL
clear
THEN
@1:"FPI?”
21OO
@le
THEN
@1:”CLI
buttons
22OO
OF
3100,3200,3300,3400,3500,3600,3700,3800,39OO
0F
4000,4100,4200,4300,4400,45OO
1
through
Panel
3-19
31OO
through
15,
PROGRAM
respectively.
to the
Front
the before
lines
returning
45OO
CALL
main
service
are
buttons
program
Lines
for
flow.
subrou—
222O
of
all
P7001/IEEE
DCL
Interface
Command
The
"DCLb"
clears front
In
addition,
firmware
and
sets
command
be
executed
initialization,
all
can
command
panel
interrupts
execution of
DPO
operations
be
also
follows:
as
used
PRINT
performs
a
initializes
with
to
@1:”DCL
the
and
”DCLb”
clear
function of
re—enables
commands
(sets
a
default
service
the
the
the
interface
Q)
to
mode
to
requests
DPO
the
”CLIb“
PROGRAM
DPO
the
(SRQ).
command
to
Address
default
Device
CALL
go
mode.
(i.e.,
buttons).
through
Register,
This
Clear
a
can
Transferring
Waveforms
another
to
Where:
Waveform
may
with
A
is
B
is the
be
the
PRINT
the
following
waveform
waveform
Arrays
transferred
command:
@1:”TAB
source
destination
from
one
(can
DPO
be
(can
memory
A,
also
B,
location
C
or
be
A,
D),
B,
and;
C
(A,
or
B,
D)”
C
D}
or
3-20
@
Acquiring
The
DPO,
In
this
7704A
to
mainframe
In
the
waveform
prompt
simply
changes
the
a
to
carriage
subsequent
transfer
18O
take
reference
zero
reference
and
Scaling
following
subtract
example,
a
it
is
1O
2O 3O 4O
SO
6O
7g
8O
9O
lOO
11O
12O 13O
14O Z=O
ISO
16O
17O
I8O
19O
ZOO
21O 22O
23O
24O 25O 26O 27O 28O 29O
3OO
preceding
DPO
in
user
method
ground
return to
computations).
the
an
average
waveform
DIM
PRINT
FOR NEXT
PRINT PRINT
INPUT
PRINT
FOR NEXT I
PRINT @1:”HOL PRINT
INPUT
FOR
Z=Z+N(I+200)
NEXT I
Z=Z/5O
PRINT
INPUT
W=W—Z
PRINT PRINT INPUT
V=VAL(S$)
M=POS(S$,”V”,1) T$=SEG(S$,M-1,l) M=POS(”munp”,T$,1)
V=V*10+(—3*M)
W=N*(V/102.3)
memory
to to
ground
value.
Data
routine
zero
assumed
is
being
W(512)
@1:”STO
I=1
I
@1:“HOL
”GROUND
A$
@1:”STO
I=1
@1:"DPC?"
@1:w
I=1
@1:"DPB?"
@1:w
@1:”CHL
@1:"SCL?”
@1:S$
example,
location
set
up
stop
the
probe
make
reference
50
of
avoid
(to
an
is
example
reference,
that
used.
"g”B”
3O
to
”;“B”
PROBE,
”;”C”
3O
to
”;”B"
5O
to
“;“BO"
lines
B.
a
ground
the
controller until
(or
plug-in),
the
program
Lines
elements
8O
waveform
end
point
of
and
to
appropriately
the
left
PRESS
1O
through
6O
Line
reference
then
continue
through
the
to
from
the
inaccuracies)
how
to
vertical
RETURN”
5O
displays
waveform.
the
user
he
would
(A$
would
13O
STORE,
4051.
middle
acquire
data
scale the data.
plug—in
"STORE"
a
makes
Lines
of the
which becomes
and
message
Line
the
type
be
not
HOLD,
14O
ground
P7001/IEEE
from
slot
"HOLD”
to
7O
is
necessary
in
a
used
and
then
through
in
in
the
lnierface
the
the
a
The
and
ZOO,
line
210.
plug-in
translate
scale
@
factor.
raw
and
Lines
which
it
data the
is
to
The
transfer
zero
22O
through
stored
a
numerical
array
of
reference
24O
S$.
in
value.
w
now
the
original
value
acquire
Lines
contains
3-21
is
25O
Line
waveform
subtracted
knob
the
through
3OO
multiplies
the
scaled
occurs
from
readout
29O
decode
data.
in
lines
the
raw
the
of
S$
the data
19O
data
vertical
and
the
to
in
P7001/IEEE
Interface
The
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6—021-0206-00
Replacement
or
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Changes
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improvements
ordering
type
Tektronix. number.
or
If
a
parts.
number.
part
Inc.
Change
ELECTRICAL
PARTS
parts
Tektronix
to
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serial
have
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Field Office
information.
SPECIAL
X000
00X
are
become
in
number.
ordered
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if
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available,
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any.
NOTES
first
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INFORMATION
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sometimes
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to
give
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information
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number
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contactyou concerning
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AND
at this serial
added
this serial
after
PARTS
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to
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your
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of this manual.
SYMBOLS
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the
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is
therefore
Part
order:
if
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number
number
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the
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number.
instrument
part.
change
any
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circuit
when
local
your
in
part
In
the
Parts
List.
Because further
utilized
ACTR ACTUATOR ASSY ASSEMBLY CAP CER CKT CIRCUIT COMP CONN CONNECTOR ELCTLT ELEC
INCAND
LED
NONWlR
of
space
Item
Name
where
possible.
CAPACITOR CERAMIC
COMPOSITION
ELECTROLYTIC ELECTRICAL INCANDESCENT LIGHT
NON
an
limitations.
identification. the
EMITTING DIODE
WIREWOUND
ITEM NAME
Name
Item Name
an
is
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Item
US
ABBREVIATIONS
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may
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from
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sometimes
Cataloging
PLSTC QTZ RECP RES
RF
SEL SEMICOND SENS
VAR WW XFMR XTAL
description
appear
by a
as incomplete.
Handbook
PLASTIC
QUARTZ RECEPTACLE RESISTOR RADIO
FREQUENCY SELECTED SEMICONDUCTOR SENSITIVE
VARIABLE
WIREWOUND TRANSFORMER CRYSTAL
H6—1
colon
can
(2),
For
be
6-1
Replaceable
Mfr.
Code
01121
01295
0A713 07263
27014 32159 3h630
50434 56289 59660
72982
80009
81073 90201
91418
Electrical
Parts—021-0206-00
Manufacturer
ALLEN-BRADLEY TEXAS
INSTRUMENTS,
GROUP
MOTOROLA, FAIRCHILD FAIRCHILD NATIONAL WEST-CAP
TYCO
HEWLETT-PACKARD
SPRAGUE
TUSONIX
ERIE
TEKTRONIX, GRAYHILL,
MALLORY
R.
P.
RADIO
MALLORY
INC.,
SEMICONDUCTOR,
CAMERA
SEMICONDUCTOR ARIZONA
FILTERS
DIV.,
ELECTRIC
INC.
TECHNOLOGICAL
INC.
INC.
CAPACITOR
MALLORY
MATERIALS
AND
COMPANY,
CROSS
COMPANY
INDEX—MFR.
INC.,
SEMICONDUCTOR
AND
INSTRUMENT
CORP.
INC.
COMPANY
CO.
PRODUCTS,
DIV.
CO.,
AND
COMPANY,
CO.,
INC.
INC.
SEMICONDUCTOR
DIV.
PROD.
DIV.
OF
CORP.
A
INC.
OF
OF
DIV.
P.R.
CODE
NUMBER
Address
2ND
1201
BOX
P
0
EXPRESSWAY
5005
464
2900 2201 3940 640
87
2155 644
P
561
3029 E.
P.
4242
5012,
MCDOWELL
E
ELLIS
SEMICONDUCTOR
ELVIRA
E.
W.
MONTECITO
PAGE
MARSHALL
N
FORBES
W.
12TH
BOX
500
0
HILLGROVE
WASHINGTON
BOX
0.
W
BRYN
MANUFACTURER
TO
STREET
SOUTH
13500
RD,P0
STREET
ROAD
ROAD
MILL
ST.
BLVD
ST.
AVE.,
372
MAWR
N
CENTRAL
BOX
DR.
PO
STREET
BOX
20923
373
State,
City,
MILWAUKEE,
DALLAS, PHOENIX,
MOUNTAIN
SANTA
TUCSON, PHOENIX,
PALO
NORTH
TUCSON,
ERIE,
BEAVERTON,
LA
TX
CLARA,
AZ
ALTO,
ADAMS,
AZ
PA
GRANGE,
AZ
VIEW,
AZ
16512
INDIANAPOLIS,
CHICAGO,
IL
WI
75222
85036
CA
85706
85019
CA
MA
85705
OR
IL
60646
Zip
53204
CA
95051
94304
01247
97077
60525
IN
9A052
46206
REV
JUL
1982
Replaceable
Electrical Parts—021-0206-00
thNo.
A1
22
01 02 06 09 010 013
014 017 018 019 022
026
027 028 029 04o 041 042
043 044
0100
0111 0112 0113
0114 0115 0116 0117
c118
0119
c120
0123
c125
0209
0210
0211
0212 0213
0214
0215 0216 0219
0220
0225 0310 0311 0312 0313
0317 c321
c322
0323
c324
0325
Tektronix
No.
Pan
670-4882-03
670—4883-03
290—0296-00 283-0024—00
283-0024-00 283-0024-00
283-0000—00
283-0150-00
283-0024—00 283-0108—00 283—0000-00
283-0024-00 283-0024-00
283—0024-00
283—0024-00
283-0024-00
283-0024—00
283—0024—00
283-0024—00
283—0024—00
283-0024—00 283—0000-00 283-0024—00
283-0024-00 283-0024-00
283-0024—00
283—0024-00 283-0024—00 283-0024—00 283—0024-00 283—0024-00
283—0024—00
283-0024400 283-0024-00 283-0024-00 290-0296-00 283-0024-00
283-0024—00
283-0024-00
283-0024—00
283—0024—00 283—0024—00
283-0024-00 283-0024-00
283-0024-00
283-0024—00 283-0024—00
283-0024-00
283—0024-00 283-0024—00
283-0024—00
283-0024-00
283—0024-00 283—0024-00 283-0024—00 283—0024-00
Serial/Model
EH
No1
Dscont Name
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0x2 0x2
CAP.,FXD,ELCTLT:lOOUF,20%,20V CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
CAP.,FXD,CER DI:0.1UF,+80—20%,SOV CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
CAP.,FXD,ELCTLT:lOOUF,20Z,20V
CAP.,FXD,CER
CAP.,FXD,CER
CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
&
Descflpfion
Mfr
Code
80009 80009 670—4883-03
56289 72982 72982 72982 59660 59660
72982 56289 59660 72982 72982 72982
72982 72982 72982 72982 72982 72982
72982 59660 72982 72982 8121N08325U01042 72982 72982
72982 72982 72982 8121N083ZSU01042 72982 72982 72982
72982 72982 72982 8121N083Z5U01042 56289 72982 72982
72982 72982 72982 72982 72982 72982
72982 72982
72982
72982 72982 8121N083ZSU01042 72982
72982 8121N08325U01OAZ 72982 72982 72932 72982 72982
MfrPan
670—4882-03
150D107X0020S2
8121N0832500104z
8121N08325U01042
8121008325001042 831-519-Z5U-102P 835-5158651J
8121N0832500104z
272013
831-519-250-102P
8121N083ZSU01042
3121N0832500104z 8121808325001042
8121N08325U0104Z
8121808325001042
8121N08325U01042
8121N083zsuo1o4z 8121808325001042 8121808325001042
8121N0832500104z
831—519—250-1029
8121N0832500104z
8121N083Z5U01042
8121Nos3z500104z
8121N083ZSU01042
8121N083zsuo104z
8121N08325U01042
8121N083zsuo104z
8121N08325U01042
8121N083zsuo104z 8121N08325001o4z
1500107x002082 8121008325001042
8121N083ZSU01042
8121808325001042 8121N0832500104z 8121N083zsuo104z 8121808325001042
8121N083Z5UOIOAZ
8121008325001042
8121N083ZSU01042
8121808325001042 8121N0832500104z 8121N08325001042
8121N083Z5001042
8121008325001042 8121N0832500104z
8121808325001042 8121N08325001o4z 8121808325001042
Number
REV
JUL
1982
6-3
Replaceable
Electrical Pans—021-0206-00
Tektronix
No.
Part
No.
Ckl
0412
0413
041a
283-0203—00
283=0024~00
283m0052—OO
0415 283e0331-00
0415 0417
0420
0425
290—0536-00 283—0003-00
283~0203—00
283-0203-00
08310 152-0168-00
CRAIS
CR419
1315
020 021
813 R16 817 818 820 821
R22 824 828 838 315-0102—00 839
R42
800 8100 8120 8121 8122 8123
R124 R216
8220
8311
8313
8318
8319 R324 R325
8411.
R415
8418
814012
U1
U2
03
U4 U5 U6
U7 US U9
152-0322-00
152-0322—00
108-0317-00
151-0190-00 151-0188-00
315—0181~00
315-0102-00
315—0181-00 RES.
315=0103-00
31590472—00
315=0102-00
315-0181-00
315-0102—00 315-0102—00
315—0102-00 315—0102-00
315—0103-00
315-0910-00
315—0102—00
315-0102—00
315-0102-00
315-0302-=00
315—0302—00
315-0102-00 315-0102-00
315-0102—00
315-0102-00 315-0620-00
315-0620-00
315—0102—00 315—0102—00
315-0821-00 315-0821-00 315-0103-00
260—1827-00
156-0145—00
156=0145=00
156—0145—00
156‘0145-00
156-0653-00
156-0653-00
156-0653-00
156-0653-00 156-01h5-00
Serial/Model
Eff
No.
Dscont
&
Name
CAP.
,FXD,CER CAP.,FXD,CER CAP.,FXD,CER
CAP,
,FXD,CER
CAP.
,FXD,ELCTLT:10UF,ZOZ,25V CAP.,FXD,CER
CAP.,FX'D,CER CAP.,FXD,CER
SEMICOND SEMICOND SEMICOND
COIL,RF:FIXED,15UH
TRANSISTOR:SILICON,NPN IRANSISTOR:SILICON,PNP
DEVICE:ZENER,O.4W,12V,SZ DEVICE:SILICON,15V,HOT DEVICE:SILICON,15V,HOT
88s.,81m,c11888:180
RES.,FXD,CMPSN:1K
,FXDfiCMPSNdSO
888.
,FXD,CMPSN:10K RES.,FXD,CMPSN:4.7K RES.,FXD,CMPSN:1K
RES.,FX'.D,CMPSN:180 RES.,FXD,CMPSN:1K
888,880,08888118
RES.,FXD,CMPSN:1K
888.
,FXD,CMPSN:1K RESD,FXD,CMPSN:1K
888.
,FXD,CMPSN:10K RES.,FXD,CMPSN:91 RES.,FX.D,CMPSN:1K RES.,FXD,CMPSN:1K RES.
,FXD,CMPSN:1K
888.
,FXD,CMPSN:3K
888.
,FXD,CMPSN:3K RES.,FXD,CMPSN:1K RES.,FXD,CMPSN:IK RES.,FXD,CMPSN:1K
888,,81m,08888:11<
RES.,FXD,CMPSN:62
RES.,FXD,CMPSN:62
RES.
,FXD,CMPSN:1K
RES.-,FXD,CMPSN:1K RES.,FXD,CMPSN:820 OHM,SZ,O.25W RES.,FXD,CMPSN:820 OHM,SZ,O.25W RES.,FXD,CMPSN:1OK
SWITCH,ROCKER:5,SPST
MICROCIRCUIT,DI:QUAD MICROCIRCUIT,DI:QUAD MICROCIRCUIT,DI:QUAD MICROCIRCUIT,DI:QUAD
MICROCKT,INTFC:QUAD MICROCKT,INTFC:QUAD
MICROCKT,INTFC:QUAD MICROCKT,INTFC:QUAD
MICROCIRCUIT,DI:QUAD
Descrlption
DI:0.47UF,ZOZ,50V
01:0.108,+80-207.,50v 01:10588,1z,500v 01:4398,2z,100v
DI:0.0lUF,+80—ZOZ,ISOV
DI:0.h7UF,202,50V
01:0.4708,202,5ov
0HM,52,0.25W
0HM,SZ,0.25W
01m,5z,0.25w
01m,5z,0.2sw
OHM,SZ,O.25W
0HM,52,0.25W
0118,5z,0.25w
01m,5z,0.2sw
OHM,52,0.25W
01m,5z,o.2sw
0HM,SZ,O.25W
01m,5z,0.25w
OHM,SZ,0.25W
088,5z,0.25w
0181,5z,0.258 01m,5z,0.25w
01m,5z,0.2sw
0m,5z,0.2sw
0HM,SZ,O.25W
0818,520258
Ol-lM,SZ,0.25W OHM,SZ,0.25W OHM,SZ,0.25W OHM,SZ,O.25W
011M,sz,o.25w
OHH,SZ,0.25W
01m,5z,0.25w
01m,5z,0.2sw
2-INPUT
2-INPUT
2-INPUT
Z-INPUT UNIFIED UNIFIED
UNIFIED UNIFIED
2-INPUT
BUS XCVR
BUS XCVR
BUS XCVR
BUS XCVR
Pos
POS POS POS
POS
CARRIER CARRIER
NAND
NAND
NAND
NAND
NAND
BFR BFR
BFR
BFR
BFR
Mfr
Code
72982 72982 72982 72982 90201 91418
72982 72982
04713 50434 50434
32159
07263 04713
01121 01121 01121 01121 01121 01121
01121 01121 01121 01121 01121 01121
01121 01121 01121 01121 01121 01121
01121 01121 01121 01121 01121 01121
01121 01121 01121 01121 01121 01121
81073
80009 80009
80009
80009 80009 80009
80009 80009 80009
Part
Number
Mfr
8131N075E474M
8121808325001042
OBAISAICOGOlOSOF 805—5051841306 'I‘DClOéMOZSFL
SP1032151=4R9
8131N075EA74M
8131807584748
SZG35009K4
5082-2672 5082-2672
715018
3032677 SPS6868K
081815 081025 081815 081035
084.725
081025
081815 081025 081025 081025 081025 081025
081035 089105 081025 081025 081025 083025
083025 081025 081025 081025 081025 086205
086205 081025
081025
088215 088215 081035
7683053
158—0145—00
156—0145=00
156=0145-00
156-0145—00
156-0653000 156-0653-00
156-0653-00 156-0653-00
156-0145—00
6-»4
REV
JUL 1982
Replaceable
Electrical
Parts—021-0206-00
thNo.
U10
U11 U12 U13 U14
01s
U16 U17 U18 U19
U20 021
022
U23
024 025
U26 U27
U28
029 040
U41
042
U43
U44
04s
0113
0114 0115
U116
U117 U118 U119 U120
U121
0122
U123 U125
0212
U213 U214
0215
0210 0217
U218
0219
U220 U225
0310
U311
U312 U313 U314 U315
U316
0317
U318
Tektronix
N0.
Pan
156-0058—00
156-0129-00 156-0030-00 156-0043-00
156—0041-00 156—0030-00
156-0041-00 156-0072-00 156-0043-00 156-0047-00 156-0058-00
156—0061—00
156-0058-00
156-0385-00
156-0222—00
156-0222-00
156-0222—00
156-0427-00
156—0427—00
156—0427-00 156-0716—00
156-0716-00 156-0716-00 156-0716-00
156-0145-00
156-0072—00 160—0180-00
160-0179-00
160—0178—00
156-0061-00
156-0916-00 156-0535-00 156-0531-00 156-0531-00 156-0427-00
156-0427—00
156-0427-00 156-0849-00
160—0177-00
160-0176-00 160-0175-00 160-0174-00
156-0078—00
156-0058-00 156-0385-00 156-0535-00 156-0426-00 156-0849-00
156—0402-00
156-0139-00
156-0285—00 156-0382—00 156—0382-00
156-0382-00
156-0464-00 156-0464-00
156—0535—00
Serial/Model
Efi
N0.
Dscont
&
Name
Descnpfion
MICROCIRCUIT,DI:HEX.INVERTER MICROCIRCUIT,DI:QUAD MICROCIRCUIT,DI:QUAD MICROCIRCUIT,DI:QUAD MICROCIRCUIT,DI:DUAL MICROCIRCUIT,DI:QUAD
MICROCIRCUIT,DI:DUAL
MICROCIRCUIT,DI:MONOSTAELE
MICROCIRCUIT,DI:QUAD HICROCIRCUIT,DI:TPL MICROCIRCUIT,DI:HEX.INVERTER MICROCIRCUIT,DI:SGL,BCD
2-INPUT 2-INPUT 2-INPUT
D-TYPE
2—INPUT
D-TYPE
2—INPUT
3-INPUT
TO
MICROCIRCUIT,DI:HEX.INVERTER
MICROCIRCUIT,DI:HEX.INVERTER MICROCIRCUIT,DI:HEX.LATCH MICROCIRCUIT,DI:HEX.LATCH MICROCIRCUIT,DI:HEX.LATCH MICROCIRCUIT,DI:PERIPHERAL
MICROCIRCUIT,DI:PERIPHERAL MICROCIRCUIT,DI:PERIPHERAL
8
MICROCIRCUIT,DI:RAM,128 MICROCIRCUIT,DI:RAM,128 MICROCIRCUIT,DI:RAM,128 MICROCIRCUIT,DI:RAM,128
MICROCIRCUIT,DI:QUAD
MICROCIRCUIT,DI:MONOSTAELE
MICROCIRCUIT,DI:1024 MICROCIRCUIT,DI:1024 MICROCIRCUIT,DI:1024 MICROCIRCUIT,DI:SGL,BCD
MICROCIRCUIT,DI:EIGHT MICROCIRCUIT,DI:TRI-STATE MICROCIRCUIT,DI:QUAD MICROCIRCUIT,DI:QUAD
x
8
X
a
x
X
8
2-INPUT
x
s
STATIC,PRGM
0
x
STATIC,PRGM
3
x
STATIC,PRGM
TO
2-INP
HEX
UNIFIED
UNIFIED MICROCIRCUIT,DlzPERIPHERAL MICROCIRCUIT,DI:PERIPHERAL
MICROCIRCUIT,DI:PERIPHERAL MICROCIRCUIT,DI:QUAD
MICROCIRCUIT,DI:1024
MICROCIRCUIT,DI:1024
MICROCIRCUIT,DI:1024 MICROCIRCUIT,DI:1024
MICROCIRCUIT,DI:1
INTERFACE
x
X
X
X
16
0F
a
8 8 8
STATIC,PRGM STATIC,PRGM STATIC,PRGM STATIC,PRGM
DECODER-DEMUX
MICROCIRCUIT,DI:HEX.INVERTER HICROCIRCUIT,DI:HEX.INVERTER MICROCIRCUIT,DI:TRI-STATE
MICROCIRCUIT,DI:MICROPROCESSOR
MICROCIRCUIT,DI:QUAD
HEX
INTERFACE
MICROCIRCUIT,LI:TIMER MICROCIRCUIT,LI:DUAL MICROCIRCUIT,LI:VOLTAGE MICROCIRCUIT,DI:QUAD MICROCIRCUIT,DI:QUAD MICROCIRCUIT,DI:QUAD
MICROCIRCUIT,DI:DUAL MICROCIRCUIT,DI:DUAL MICROCIRCUIT,DI:TRI-STATE
LINE DRIVER
REGULATOR
2-INPUT 2-INPUT
2—INPUT
4-INPUT
4-INPUT
HEX
GATE
GATE
NAND
POS
NOR
GATE
FLIP-FLOP
GATE
NAND
FLIP-FLOP
NOR GATE
NAND GATE
0000052
NAND
DECODER
BFR
BUS
XSVR
BUS
XSVR
GATE
GATE
DIP 01295
ADPTR
BFR
DIP
MV,TTL,14
P05
POS
050
INTERFACE ADPTR
INTERFACE INTERFACE ADPTR
STATIC STATIC STATIC STATIC
POS
MV,TTL,14
DEC
3-STATE
BUFF
BUS XCVR
BUS XCVR
INTERFACE ADPTR
INTERFACE ADPTR
INTERFACE ADPTR
BUFF
NAND GATE
NAND NAND GATE
NAND
NAND GATE
BUFF
Mfr
Code
80009 80009 01295 80009 27014 01295
27014
MfrPan
156-0058-00 156-0129-00
SN7400(N
156-0043-00
DM7474N
SN7400(N
DM7474N
SN74121(N 80009 80009 80009 01295
80009
80009 30009
00009 80009
04713
04713
04713
04713 04713
04713
04713
80009 01295 80009 80009 30009 01295
80009 27014 27014 27014 04713
04713
04713 80009
156-0043—00
156-0047-00
156-0058-00
SN7442<N
156-0058—00
156-0385-00
156-0222-00
156-0222-00
156-0222—00
M06820(L
MC6820(L MC6820(L
MCM68108 MCM68108 MCM68105 MCM6810$
156-0145-00
5N74121(N 160-0180—00
160-0179-00 160-0178-00
SN7442(N
156—0916-00
DM8097M DM8833N DM8833N
MC6820(L MC6820<L
MC6820(L
156-0849-00 80009 160-0177-00 80009
80009 80009
80009
80009
80009 27014
04713 80009
27014
01295
27014 LM340T-12
01295 01295 01295
07263 07263 74L520PC 27014
160-0176-00
160-0175-00
160-0174-00
156—0078—00
156-0058-00 156-0385-00
DM8097M
MC6SOOS
156-0849-00
LMSSSCN
SN75150P
SN74LSOO(N SN74LSOO(N SN74LSOO(N
74LSZOPC
DM8097M
Number
OR
J)
OR
J)
OR
J)
on
J)
0R
P)
P)
00
OR
F)
OR
J)
OR
J)
0R
P)
OR
P)
OR
P)
OR
OR OR
OR
DC
OR
00
J) J) J)
REV
JUL 1982
6-5
Replaceable
Electrical
Pans—02141206430
Tektronix
No.
W
0319
11320
U321 11322 11323
U324
U325
11413
U414 U418 156-0323—00
0420
Y416
No.
Part
156-0145—00
lseeoszs-oo
156°0138°00
156-0383—00 156»0480=OO
156°0849-00
156-0849-00 156-0041-00 156-0718-00
156—0206-00
158-0056-00
Serial/Model
N0.
&
Name
MICROCIRCUIT,DI:QUAD
mcxocmcuu,01:1111:5st
MICROCIRCUIT,LI:CORE MICROCIRCUIT,DI:QUAD
mcaocmcuummmn
MICROCIRCUIT,DI:QUAD
MICROCIRCUIT,DI:QUAD
uxcxocmcumnnnuu
MICROCIRCUIT,DI:TRIPLE
mcaocmcuu,01:111:x.
MICROCIRCUIT,DI:DUAL
UNIT,QTZ:4MHZ,0.003Z,SEERIES
xm,
Description
2-INPUT
LINE
2-»111110'1
2—mpur
INTERFACE
INTERFACE
11-11111:
INVERTER
SCH/SINK
max
RECEIVER
FLIP-FLOP
3-INP
31211
11mm
905
11111-1?
NOR
cm
AND
am:
BUS XSVR
XSVR
BUS
PCS-NOR GATES
DRVR
MEM
PR
Mfr
Code
80009 27014 01295 80009 01295 80009
80009
27014 80009 01295 01295
34630
Mfr
Part
Number
156-0145-00
DM8097M SN7SLSQN
156=0383-00
SNMLSOBW
156—0849-00
156-0849-00
01174741:
156-0718—00
5117450411
SN75325<N
150—6070
OR
OR
J)
J)
643
REV
JUL
1982
REPLACEABLE
Section
021-0205.oo
6-
PARTS
Replacement
Tektronix.
lnc.
Changes
accommodate
and to
give developed important.
when information number.
improved
serial
If
a
part
part,
representative
number.
Change
manual.
in
the
description
Name Name can
by
sometimes
may
identification.
utilized
be
FIGURE
in
Items
numbers
to
ORDERING
parts
Office
Field
Tektronix
to improved
the benefit
you
in
our
engineering
ordering
in
your
number.
have
you
your
will
contact
information.
List.
Parts
colon
a
the
where
this
section
illustrations.
the
available
are
representative.
or
instruments
components
of
the
parts.
Part
order:
modification
and
has been
ordered
local Tektronix,
concerning
you
if
any,
NAME
ITEM
Item
an
Because
it).
as
appear
Federal
US.
possible.
INDEX
AND
referenced
are
MECHANICAL
INFORMATION
from
or
through
your
are
as they
circuit
latest
department.
include the
to
number.
number
replaced
lnc.
is
located at
is
Name
of
space
incomplete.
Cataloging
NUMBERS
sometimes
become
instrument
any
separated
limitations.
figure
by
available.
improvements
It is
therefore
following
if
applicable.
with
a new
Office
Field
change
the
rear
from
further
For
Handbook
and
made
type
in
of
an
local
part
this
the
Item
Item
HES-1
index
PARTS
INDENTATION
This
mechanical
in
the
2
Detail Attaching
it
items
Followingisan
description
345
Part of
Parts Attaching
mounts.
parts
relationships. used
to
or
or or
the
1
Assembly Attaching
Attaching
item
lndented
indentation.
Attaching specified.
parts
column.
and/or
Component
for
“"
Assembly
END
parts
Assembly
for
parts
END
""
of Detail Part
parts
END ATTACHING
Parts
always
while the
are
must
of.
part
be
purchased separately.
ATTACHING
Detail
ATTACHINGPARTS
for
detail
list
example
and/or
Parts
appear
included
and
SYSTEM
is
indented
of
Name
and/or
PARTS
Component
Part
Detail
0/
PARTS
in
the
are
parts
to
the
indentation
&
Description
Component
""
Part
indentation
same
indented
the
with.
unless otherwise
indicate item
system
the
to
right.
next
higher
as
a
ACTR ADPTR ADAPTER ALIGN ALIGNMENT
AL
ASSEM ASSEMBLED ASSY ATTEN AWG AMERICAN WIRE BD BRKT BRACKET BRS BRASS BRZ BRONZE BSHG CAB CABINET CAP CAPACITOR CER CERAMIC CHAS CHASSIS CKT CIRCUIT COMP COMPOSITION CONN COV COVER CPLG CRT DEG DEGREE DWR
INCH
SIZE
NUMBER ACTUATOR
ALUMINUM
ASSEMBLY ATTENUATOR
BOARD
BUSHING
CONNECTOR
COUPLING CATHODE
DRAWER
RAY
GAGE
TUBE
ABBREVIATIONS
ELCTRN ELEC ELCTLT ELEM EPL ELECTRICAL EOPT
EXT
FIL
FLEX
FLH FLTR
FR
FSTNR FT FOOT FXD
GSKT
HDL
HEX HEX HEX
HLCPS HELICAL HLEXT
HV
IC
ID
IDENT IMPLR
ELECTRON ELECTRICAL ELECTROLVTIC
.
ELEMENT
EQUIPMENT EXTERNAL FILLISTER HEAD FLEXIBLE FLAT HEAD FILTER FRAMEorFRONT FASTENER
FIXED GASKET HANDLE HEXAGON HEXAGONAL
HD
HEXAGONAL SOCKET
SOC
HELICAL HIGH INTEGRATED INSIDE IDENTIFICATION IMPELLER
VOLTAGE
DIAMETER
PARTS LIST
HEAD
COMPRESSION EXTENSION
CIRCUIT
IN
INCAND INSUL
mm,
LPHLDR MACH MECH MTG NIP NON
oeo
OD OVH
BRZ
PH pL PLSTC PN PNH PWR RCPT RES RGD RLF RTNR SCH SCOPE SCR
INCH INCANDESCENT INSULATOR INTERNAL LAMPHOLDER MACHINE MECHANICAL MOUNTING SLFLKG
WIRE
NIPPLE NOT ORDER OUTSIDE OVAL PHDSPHOR PLAIN PLASTIC PART NUMBER PAN POWER
RECEPTACLE RESISTOR RIGID RELIEF RETAINER SOCKET OSCILLOSCOPE SCREW
WIRE
HEAD
or
HEAD
ev
WOUND
DESCRIPTION
DIAMETER
BRONZE
PLATE
HEAD
SE SECT SEMICOND SHLD SHLDR SKT 5L
SLVG SPR
so
SST STL
sw
T
TERM THD THK TNSN TPG TRH
v
VAR
w
wSHR
XFMR XSTR
END
SINGLE
SECTION SEMICONDUCTOR SHIELD SHOULDERED SOCKET SLIDE SELF-LOCKING SLEEVING SPRING SQUARE STAINLESS STEEL SWITCH TUBE TERMINAL THREAD THICK TENSION TAPPINC TRUSS HEAD VOLTAGE VARIABLE WITH WASHER TRANSFORMER TRANSISTOR
STEEL
Repmceame 021-0206-00
hfifr.
Code
04919 05820 06540
08261 09922 22526
70868
77900
70189
00009
93907
TK0435
Manufacturer
COMPONENT
E0
NITE OIV SPECTRA-STRIP
BURNOY CORP
00 00
ONPHENOL
R
AN
SHOKEPROOF
OIV
ILLINOIS
SHAKEPRODF
TEXTRONIX
TEXTRON
CONCOR
LENIS
MechanMaIPans—
CROSS
MFG
SERVICE
G
AND
NOKEFIELO
ONATON ELECTRONIC
CORP
PONT E
I
PONT CONNECTOR SYSTEMS
OPEROTIONS
F
ALLIED
OF
SCREN
CO
ILLINOIS
TOOL
DIVISION
INC
INC
OIV
ENGINEERING
0N ELTRO CO
BE NENOURS
TOOL
NORKS
CO
INC
INDEX
INC
ONO
WORKS
-
HRRONORE
INC
CO
MFR.
Address
1
60
446
7100
RICHARDS
30
33
SOINT
ST
4900
P0BOX
600
4114
CODE
COMPONENT
RUOUBON
BLAKE ST
LflHPSON
OVE
HUNTER
FRONKLIN
E
CHARLES
CHARLES
H
S
GRIFFITH
500
OVE
18TH
S
PEORIO
NUMBER
PORK
R0
AVE
LONE
ST
R0
R000
OR
MANUFACTURER
TO
(fity.
NEST
NAKEFIELO
NEH HOVEN
GOROEN GROVE
NORNOLK CT
CAMP
OONBURY
ELGIN
ELGIN
BEAVERTON
ROCKFORD
CHICOGO
State.
BRIOGENOTER
NO
01880
CT
06515
CD
06852
PO
HILL
17011
CT
06810
60120
IL
60120
IL
OR
97077
61101
IL
60609
IL
Zip
(Made
MO
92642
02379
6-8
REV
DEC
1986
a
Fig.
Index No.
1-1
-2
-3
-4
-5
-6
Tektronix
No.
Part
380-0499-00
211-0008-00
211—0504-00
134-0067-00
214-1573-00 380-0511-00
-7 210-0586-00
-8 211-0097-00
211-0009—00
-9
-1O
385-3778-00
-11
211-0101-00
198-3057-00
-12
~13
----------
~14
211-0115-00
129-0561-00
-15
386-3370—01
-16
131-0993—00
-17
131-0608-00
-18
136—0623-00
-19
—20
136-0260-02
—21
136-0289-02 136-0514-00
-22
~23
136-0252-07
214—0579—00
-24
-25
----------
—26
210—0586-00
-27 211-0097-00
214—1967-00
-28
136—0634-00
-29
136-0578-00
-30
-31 129-0466-00
211—0116-00
-32
-33 129-0662-00
-34
211-0116-00
-35
-------
—35
131—0608—00 136-0579—00
-37
136—0623—00
-38
136-0252-07
-39
-4O
136-0260-02
136—0269—02
-41
-42 214-0579-00
175-0830-00
-43
—44
352—0165—00
131-0707-00
-45
070-2623-00
012—0630—01
012—0630-03
Serial/Assembly
Effective
8010100 8010274
8010273
No.
Dscont
Qty 12345
1
H50
HALF,CONN:FRDNT,NYLON
(ATTACHING
8
SCREN,NACHINE:4-4O
4
SCREN,NACHINE:6-32
ATTACHINO
(END
1
BUTTON,PLUO:O.5
THUNOSCREN:6—32
2
1
“SO
HALF,CDNN:REAR,ALUNINUN
(ATTACHINO
2
NUT,PL,ASSEN
2
SCREN,NACHINE:4—4D
2
SCREN,NACHINE:4-40
ATTACHING
(END
1
SUPPORT,CKT
(ATTACHING
2
SCREN,NACHINE:4—4D
ATTACHING
(END
1
NIRE
1
2
2
1
1
54
4 13 14
2
3
5
1
1
1
13
2
2
4
4
1
42
4
3
6
8
20
2
AR
2
15
1
1
1
SET,ELEC:
EXT BOARD
(ATTACHING
SCR,ASSEN
SPACER,POST:1.213
Ex
ATTACHING
(END .CKT BOARD ASSY
.PLATE,CONN HTG:REAR,N/HARDNARE
.BUS,CONDUCTDR:SHUNT
.TERNINAL,PIN:D.355
.SKT,PL—IN ELEK:CNPNT,4O .SKT,PL—IN
.SKT,PL-IN .SKT,PL-IN
.SDCKET,PIN .TERN,TEST .NICRDCIRCUIT:(SEE .(ATTACHING PARTS) .NUT,PL,ASSEN .SCREN,NACHINE:4—40
ATTACHING
.(END
.HEAT
SINK,DIODE:(2)0.15
.SKT,PL-IN
.5XT,PL—IN
SPACER,POST:0.575
(ATTACHING
SCR,ASSEN
ATTACNINO
(END
SPACER,POST:1.188
X
(ATTACHING
SCR,ASSEN
ATTACHING
(END CKT
BOARD
.TERNINAL,PIN:O.365
.SKT,PL—IN .SKT,PL—IN ELEX:CNPNT,4O .SOCKET,PIN
.SKT,PL-IN .SKT,PL-IN
.TERR,TEST
CA8LE,SP,ELEC:7,26
HLDR,TERN
CONTACT,ELEC:22-25
STANDARD
NANUAL,TECH:INSTR CA8LE,INTCON:2.0N CA8LE,INTCON:2.0N
ACCESSORIES
8.
Name
PARTS)
PARTS)
HOLE,GRAY
X
PARTS)
HAz4—4O
PARTS)
80:0PIB
PARTS)
PARTS)
ASSY:NPU/OPIB(SEE
PARTS)
NSHRz4-4O
PARTS)
INCLUDES:
ELEK:NICRDCKT,16 OIP,LON ELEK:MICROCIRCUIT,14 ELEK:NICROCIRCUIT,8
CONN:N/0
POINT:BRSCDPL
NAz4-4O
PARTS)
ELEK:NICROCIRCUIT,20 ELEK:NICROCIRCUIT,24
PARTS)
NSHRz4-4O
PARTS)
PARTS)
NSHRz4—4O
PARTS)
ASSY:PIA/7001(SEE
ELEK:NICRDCIRCUIT.24
CDNN:N/0 DINPLE ELEK:NICROCKT,16 ELEK:NICROCIRCUIT,14
POINT:BRS
CONN18
NIRE,BLACK
Description
X
O.25,PNH,STL
X
O.250,PNH,STL
PLASTIC
0.25,STL
A1
0.025
DIP,LON
REPL)
0.25,STL
DIA
HOLES,AL
EA
END,AL,0.188
A2
0.025
DIP,LON
DIP,LDN
PL
OD,SST
CD
DEG,STL
REPL)
BRZ
OLD
PROFILE
DIP
DIP
CO
DIP
DIP,LON
REPL)
8RZ GLD
OIP,LDN
PROFILE
DIP
JKT,R8N
OLD
8E
PL
PL
CL
PL
00
PL
CL
PL
0.656,0.312
X
X
O.312,PNH,STL
X
O.25,PNH,STL
INTERFACE
X
0.25,FLH,100
X
O.312,PNH,BR5,NP,POZ
L,4-4O INT/EXT,AL,O.188
ASSEMBLY,8LACK
X
L
DINPLE
U312
X
X
0.312,PNH,STL
L,4-40,NYLON,0.375
X
0.312,PNH,8RS,NP,POZ
L,4-4O
X
O.312,PNH,BRS,NP,POZ
X
L
CD
ANG,STRD,PVC
ANG,8RS,CU
L
L
Repwceame 021-0206-00
Mfr.
Code
80009
93907
TKO435
80009 06540 6130—55-0632 80009
78189
TKO435
93907
80009
TKO435
80009
77900
H
80009 129-0661-00
,
80009 22526
22526 48293-036 09922 09922 09922 DILB14P-108T 09922 22526 75060-012 80009
78189
TXD435
05820 289-A8
PF
HE
PF
09922 09922 80009
77900
80009
77900
22526 48283-036 09922 OIL824P-108
09922
22526 75050-012
09922 09922 DILB14P-108T 80009 214-0579—00 08261 111-2699-972 80009 22525
80009 070—2623-00 04919 2024-2 74858
MechaMcm
Mfr.
Part
380-0499-00
BY
ORDER
BY
ORDER
134—0057-00
380-0511-00
211-041800-00
ORDER BY DESCR
ORDERBYDESCR
386-3778-00
ORDERBYDESCR
198—3057-00
BY
ORDER
386—3370-01
65474-005
DILB4OP-108 DILB15P~108T
DILBBP-108
214-0579-00
211-041800-00
ORDER BY DESCR
DILBZOP-108
DIL824P-108
129-0466—00
BY
ORDER
129-0662—00
ORDERBYDESCR
DILB4OP—108
DIL81SP-1OBT
352-0165—00
47439—000
AC30147-102
Pafls-
No.
DESCR
DESCR
OESCR
DESCR
REV
DEC
1986
Replaceable
021-0206-00
&
Fig.
Index No.
1-
Tektronix
Part
012-0530-01
012—0630-03
Mechanical
No.
8010100
8100796
Parts-
Seria|lAssembly
Effective
Dscont
8100795
No.
12345
Qty
1
C118LE,INTCON:2.0H
[OPTION
1
CABLE,INTCON:2.0I
(OPTION
Name8.Description
31
31
L
ONLY)
L
ONLY)
Mfr,
Code
04919
74868
Mfr.
Part
2024—2
DC30147-102
No.
6—1
0
REV DEC
1986
IQ.
.—
mxvroumo
021
—0206-00
M06800
70°C;
L
or
(0
to
M668000
(—40
to
85°C;
L
Suffix
P
Suffix)
only)
MICROPROCESSING
MC6800
The
central control function
with
TTL,
+5.0-voIt
one
only
bus
interface.
The MC6800
its 16-bit
with
well sing
3<state,
as
applications
Eight‘Bit
O
Bi-Directional
0
Sixteen-Bit
O
72
Instructions
Seven
0
Addressing
Extended,
Variable
0
O
Vectored
O
Maskable
0
Separate
In
Stack
0
Six Internal
Program
0
Direct
Memory
Capability
0
Clock
Rates
.
Halt
Bus
and
Simple
0
is
a
MC6800,
the
power
is
capable
address
making
realizable.
Parallel
Processing
Data
Address
Variable
Modes
Implied
Stack
Length
Restart
Interrupt
Non-Maskable
Registers
Counter,
Addressing
as
High
Interface
Instruction
Single
monolithic 8-bit
Motorola’s
for
all
with
as
of
addressing
The
memory
65K
and
8-bit data
Bytes
lines.
direct
Bus
Bus
supply,
Length
Direct, Relative,
and
Accumulator
Vector
Interrupt
Two
Stack
Accumulators,
Pointer
(DMA) and
1
MHz
as
.
Without
TTL
Execution
UNIT
(MPU)
microprocessor
M6800
M6800
no
addressing
of
family.
system
external
65K
bus
Addressing
Immediate,
Internal
and
Condition
Multiple
Capability
forming
Compatible
parts,
TTL devices
of
bytes
is
bidirectional
and
multiproces-
Registers
Index
Code
Processor
the
requires
for
memory
Indexed,
Saved
Register,
Register
MOS
(N-CHANNEL,SILICON-GATE)
as
MICROPROCESSOR
L
SUFHX
FACKAGE
CASE 715
NOT SHOWN:
PLAST'C
PSUFFIX
PACKAGE
711
CASE
CERAWC
M6800
MCBBOO
Microprocessor
1
II
I]
Bus
Data
Bus
Address
w€g€€g¢n:g;§a
Read
Only
Memory
Random
Access
Memory
Interface
Adapter
Interface
Adapter
FAMILY
7
=
Modem
Input/
Output
Control
—>
‘—
Control
,
MCBSOO
Data
'
Data
and
.
.
MICROPROCESSOR
BLOCK
DIAGRAM
Bus
t
.
“I
Registers Buffers»
,
“:
I
Address
‘iT-V‘i‘Buffers",_v"V'
T
Address.
Registers
and
V'
'
II
II
Bus
'
f
MC6800
ELECTRICALCHARACTERISTICS
Characteristic
High Voltage
lnput
Low
Input
Clock
Input
Three—State
Output
Output
Power
Capacitance
Frequency
Clock
“Except
g(V’Capacitances
Voltage Logic
VCC
Input
Input
lnpm
=
max)
Current
V)
Overshoot/Undershoot
=
0.4
0
Current
5.25
to
5.25
(Off
2.4
to
State)
V,
V,Vcc=0.0
V,VCC=max)
Leakage
(Vin
(Vin=0to
(Vin
High Voltage
“Load “Load “Load
“Load
Low
=
—205
=
—145
=
~100
Voltage
=
1.6
uAdC,
uAdc,
,uAdc,
mAdc,
VCC VCC
VCC
VCC
=
=
= =
min)
min) min) min)
Dissipation
#
(Vin=0,TA=25°C,f=1.O
of
Operation
1)
(Figure
Timing
Time
Cycle
Pulse Width
Clock
(Measured
Total
Rise and
(Measured
Delay
(Measured
Overshoot
at
VCC
(212
(1)1
and
Up
Times
Fall
between
TimeorClock
at
VOV
Duration
IRQ and
NMI, periodically
are
Time
MHZ)
V)
0.3
~
+
V53
Separation
=
V35
which
require sampled
0.3Vand
+
0.5 V)
High Low
3
rather
kn
=
(VCC
5.0
1
V
5%,
V55
=
Logic VIH
(1)192
$1,492
Level
Level
Logic‘
o1,<1>2
DO-D7
A0—A15,R/W
D0»D7
A0-A15,R/W,VMA
BA
(1)192
TSC DBE
DO—D7
Logic
Inputs
A0—A15,R/W,VMA
$1
(1)2
(D1332
V)
0.3
VCC
pullup
than
FIGURE
load
100%
resistors
tested.
'—
1
for
CLOCK
wire-OR
0,
TA
Symbol
VIHC
VILC
V03
VOH
VOL
PW¢H
t4", t¢f
TIMlNG
=
70°C
0
to
VlL
'in
ITSl
PD
Cin
cout
f
tcyc
tut
td
tog
capability
WAVEFORM
unless
Min
+
2.0
V55
Veg—0.3
0.3
V35
—0.1
Vss
0.5
VCC
~
0.5
V55
~
+ 2.4
V53
+
2.4
V55
+ 2.4
V53
»
80
——
0.1
1.0
430 450
940
5.0
0
0
at
optimum
otherwise
0.600
operation.
noted.)
Typ
~
-—
~
1.0
v
2.0
_
H
~
120
7.0 10
6.5
~
——
Max
VCC
VCC+0.1
+
0.8
V55
VSS+0.3
+
0.5
VCC
+
0.5
V35
2.5
100
10
100
-—
+
0.4
VSS
1.2
160
15
10
12.5
8.5
12
1.0
10
4500
4500
——
50
9100
40
Unit
Vdc
Vdc
Vdc
[JAdC
pAdc
Vdc
Vdc
W
pF
pF
MHz
,
us
ns
ns
ns
ns
ns
VOV
Overshoot
Vos
V
I
H
V
05
Vos
V
I
Vos
cmin
Lcmax
1
q)
C
—‘
tos-’
Undersh
oot
$2
Id),
V
+
2
VSS
0.5
3
Clock
Overlap
t¢f
measurement point
tOS
,
——
MC6800
MAXIMUM RATINGS
Supply Voltage
Voltage
Input
_
Operating
Storage Thermal
Temperature
Temperature
Resistance
Rating
Range
Range
Symbol
VCC
Vin
TA
Tstg
GJA
Value
~O.3
__0_3
0to+70
—55
Unit
+7.0
to
+70
to
+150
to
7O
Vdc
Vdc
0
C
°C
oC/W
This
device
inputs against
electric
or
ages
normal
precautions
of
tion
any
voltages
to
contains
damage
fields;
voltage
this
high impedance
circuitry
due
however,
be
higher
taken
than
to
to
high it
to
maximum
circuit.
protect
is
advised
avoid
static
the
volt~
that
applica—
rated
READ/WRITE TIMING
Address
Delay
Read
=
tut
Time
Data
Hold
Time
Time
Time
Contro|s*
Control Control
State State
Bus
Enable
Bus
Enable
Bus
Enable
information
Access Time
+
tDSR)
“AD
(Read)
Time
Time
(Address, R/W,
DBE
for
(Write)
Setup
Rise and
Delay Enable Delay
Down Delay
Rise
Peripheral
ttacc
Data
Setup
Data Hold
Input
Output
Address Hold
Enable
High
Data
Delay
Processor
Processor Processor
Bus
Available Three Three Data
Data Data
*Additional
Figures
Characteristic
Input
Time
Fall
Time
During
(Figure
Fall
and
is
in
given
2
VMA)
Time
3)
Times
Figures
FIGURE
and
451
(Figure
3,
Up
12
2
=
f
1.0
Time
3)
through
READ
Load Circuit of
MHz,
(Figure
16
of
DATA FROM
3)
the
6.
Figure
Symbol
{AD
tacc
tDSR
tH
tH
tAH
tEH
tDDW
tpcs
tPCr:
tpcf
tBA tTSE tTSD
tDBE
tDBED
‘DBErr tDBEf
Characteristics
Family
MEMORYORPERIPHERALS
Min
——
100
10
10
50 75
450
200
—-
_
150
300
——
H
see
pages
Typ
220
-
25
165
——
17
through
Max Unit
300
540
H
-—
225
——
100
300
40
700
——
25
20.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns ns ns
ns
ns
Address
From
From
Peripherals
or
MPU
VMA
Data
Memory
R/W
a2
of
Start
Cycle
$1
/
0.3
Vcc
0.3
v
v
V
0.3
tr
V
2.4
V
0,4
V
2.4
tDSFl
Valid
Data
mm
Data
Not Valid
0.8
V
MOTOROLA
Semiconductor
A-3
Products
Inc.
“—4
MC6800
Address
From
Data
From
DBE
$1
(1)2
R/W
MPU
VMA
MPU
=¢2
/—
VCC
0.3
FIGURE 3
of
Start
0.3
V
tr
Cycle
V
WRITE
IN
MEMORY
PERIPHERALS
OR
Data
VaIId
tDEED
tDEE
2.0
DBE
Data From
4E
MPU
(:52
v
v
0.8
~—tDBEf
Z
——
«IDBEr
V
.4
2
V
4
0
H—JDDw——
Data Not
VaIid
F—fi
§—______a
Valid
Data
q—tH
W
m
——
—-
TYPICAL
IDH IOL
Vcc
TA
:40?)
=1,8
= 530
22590
4
mA
V
versus
pA max
max
FIGURE
SOU
500
400
(n5)
TIME
300
DELAY
200
DATA
CAPACITIVE
@
V
2.4
@
0.4V
OUTPUT
BUS
LOADING
DELAY
ADDRESS
600
500
400
(ns)
TIME
300
DELAY
200
FIGURE 5
=—I45p.A
IDH
IOL=1.5
=
VCC
TA=25°C
OUTPUT
max@0.4V
mA
V
5.0
TYPICAL
DELAY
max@ 2.4
READ/WRITE,
versus
V
CAPACITIVE
V
Address,
VMA,
AND
LOADING
100
200 300
LOAD
CL,
®
includes
CL
CAPACITANCE
stray
400
(pF)
MOTOROLA
100
capacitance
500
600
Semiconductor
A-4
200
LOAD
CL,
Products
300
DAPACITANCE
Inc.
CL
inciudes
400
(pF)
capacitance
stray
500 600
MC6800
FIGURE
Test
C
R
Point
_
130
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17
A7
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A6
A5
14
15
Program Counter
Index
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A
AccumuIator
B
Condition
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Register
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A2
11
12
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A1
9
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A12
A13
A14
A15
24
25
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Decode
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and
22
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23
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=
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1,21
M
28
27
26
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05
29
DS
04
MOTOROLA
Data
Buffer
32
31
30
132
133
33
D1
D0
Semiconductor
A-5
Products
Inc.
MC6800
Proper
operation
trol
and
timing
functions
and that other
determine the
Clocks Phase One
for
used
are
the
at
Address
address
ble
of
the
output
This
permits
Data
It
bus.
memory
output
130
and
HER
in
the
In
the
instruction,
Memory lines
will be
a
voltage
Vcc
Bus
bus. The
driving
is
the
Bus (DO-D7)
is
bidirectional, and
buffers
pF.
When
machine
halt
mode,
Bus Available
Address
in
Transition of
last
250nsof
operation,
the
ThreeState
address lines and high
impedance
=
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and
will
V.
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be
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T80 applications,
$1
the
high on
clock~must
low
state
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bus
address
it
can
of data
brought
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in
address directly
device,
destruction
Read/Write
the
signals
MPU
standby
Control
impedance)
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standard
one
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peripheral
to
address
utilized
PIA
TTL
high
peripherals
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in
Read
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state,
going
state.
in
be
the
Memory
bus.Innormal
for
AClA. This
and
and
load
signal.
TTL load
devices
enabling
MPU
of
signals
of
state
and
two-phase
level.
(A0-A15)
outputs
standard
one
turned
off,
MPU
peripheral
capable
this
input
will
be
the
be
will
the
three-state
RaTt
the
phase
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line
Control
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the
state.
Valid
low.
forced
own
the
be
the
to
Eight pins
transferring
of
halted.
machine
at
one.
must
(TSC)
This
Memory
enable
requires
provided
signal
to
lines
processor.
Phase
Two
non—overlapping
-—
Sixteen
are
TTL load
is
it
be usedinDMA
pins
three-state
essentially
are
data
devices.Italso
driving
a
line
is in
This
will
will be
zero,
mode.
must
To
go
—This
state
one
the
and
insure
high
line
will
low
input
stop
at
not
input
to
Address
The
data
(Data
bus
Bus
the Three-State Control
the
leading edge
be held
for
this function
be
then
memory.
be
(R/W)
of this
high
off
in
held
will
occur
——
and
(high)
or
signal
will
turn
when
Also,
This
state.
and
Address (VMA)~This
that there
operation,
peripheral
signal
90
pF
may
of
in
the
high
to
the
state
in
the MPU.
operate
available for
Since
this
This TTL
memory
Write
(low)
is
Read
Read/Write
the
processor
output
90
pF.
is
a
this
interfaces
is
three‘state.
not
be
directly
the
devices
is
valid
driven
MPU
that certain
accomplish
be
monitored
((151, (1)2)
clock that
used
are
drivers
bus
and
130
an
open
applications.
used
for
and
to
has
standard
state,
is
level
the
at
a
one
all
other
occur
single
one
causes
go
occur
and
is
not
into the off
Clock
700nsafter
Bus Available
affected
for
Enable).
line
Phase One
state
properly.
other
is
MPU
for
only
compatible
whether
The
state.
(high).
Three-State
the
to
is
capable
output
address
signal
such
One
by
SIGNAL
con-
specific
Two
pins
~
runs
for
capa-
When
pF.
circuit.
the
data
from
three-state
TTL
load
all
activity
sensitive.
end of
Valid
level,
thFee-state
the
during
instruction
cycle.
all
of
the
ln
DMA
should
Clock.
and
the
The
devices
a
dynamic
4.5
us
output
normal
off
(high
halted,
of
driving
indicates
the
on
should
the
as
standard
active
this
DESCRIPTION
to
the
the
an
or
by
be
(1)2
to
or
the
it
be
Data Bus Enable
control
bus drivers when
patible;
the
bus
that another
Memory held
normally the stopped
occur
is
WAIT drivers
normally
WAIT
I
of
signal
howeverinnormal
phase
two
low.
high
if
the
Access
be
state
and
the
WAIT
will
device
in
PETE
drivers
Bus Available (BA)
in
instruction. At
will
go
inactive level.
by
state
=
0)
nonmaskable
or
driving
one
Interrupt Request
that
requests
machine.
the current
nizes
the
in
Condition
the
begin
an
Counter, stored
the
interrupt
that
so
cycle,
vectoring
FFF8
causes
in
memory.
The
be
serviced.
is
Halt
The
the
to should
of
interrupts.
RES-e7
from
a
failure
is
detected
the
gin
routine
All
the
the
restart,
memory
the
by
interrupt
be
can
or
an
The
instruction that
request.
interrupt Accumulators,
on
away
request
further
no
a
16bit
address
and FFFQ. An
MPU
the
Halt
line
Interrupts
low.
TRO
has
however
chip;
be
used
This
power
initial
an
on
restart
initialize
to
higher
the
will be used
program
mask
interrupted
(DBE)
for
the
in
the
clock.
During
be
disabled
control the data
(DMA)
low
the
indicating
the
that
line
state
their
to
the
occurrence
standard
interrupt
processor
At
that
Code
sequence.
stack.
the
by
interrupts
address
which
to
be
must
a
high
for
input
down
start-up
the
input,
sequence.
the
address
order
last
to
counter.
is
bit
set
PRO.
by
MPU
data
high
state.
operation,
an
internally.
applications,
The
state;
that
address bus
is
in
the
result of
a
as
such
time,
off
state
The
processor
interrupt.
TTL
load and 30
(FRO)
sequence
will
is
being
time,
Register
The
and
Condition
Next
setting
may
will
be
is
located
address
branch
in
the
will be
impedance
3
k9
a
wire‘OR
is
used
to
condition,
of
the this This
processor
lines
(FFFE, FFFF)
two
load
the
During
and
must
This
MPU
Bus
when
the
low
is
input
bus
and
This
input
it
would
read
When
such
bus
DBE
Available
activated,
microprocessor
is
available. This
state
or
the execution
all
three-state
and
other
is
removed from the
of
maskable
a
This
output
pF.
This level
be
generated
wait
until it
executed before
if
the
not
Index
the
interrupt
occur.
loaded
loaded
an
latched
interrupt
the
set,
Register, Program
Code
MPU
At the
that
in
memory at
interrupt
for
state
internally
is
the
to
high
pullup
external
reset
and
resistor
optimum
and
resulting processor.
will
will
from
will
program
the
be
signal
start
be
restart
reset
the
its
forced
that
before
three-state
the
will
enable the
is
TTL
be
driven
cycle,
is
it
as
should
signal
will
it
the
processor
outputs
(mask
is
sensitive
completes
mask
machine
Register
will
respond
mask bit
end
points
locations
these
locations
interrupts to
device
the
start
from
a
If
a
high
MPU
execution
condition.
reset
high.
locations
is
addressed
routine,
the
com—
the data
desired
in
Direct
will
go
has
will
of
output
their
to
capable
input
within
the
it
recog<
bit
will
are
high
of
the
to
routine
while
internal
to
VCC
control
MPU
power
level
be
to
of
For
the
MPU
by
be
to
a
bit
to
a
a
in
®
MOTOROLA
Semiconductor
Products
Inc.
MC6800
Figure
after
restart.
clock
periods
high
prior
first
the appear
the
on
higher
counter.
lower
the
counter.
gram
Non-Maskable
this
input
generated
me—sf
instruction
KIWI—l
signal.
Register
9
shows
Reset
after
the
to
restart
the address
order
Following,
order
requests
within
signal,
that
The
has
effect
no
initialization of the
the
must
reaches
VCC
leading edge
memory
lines. bits
eight
the
next
bits
eight
Interrupt
a
that
non-mask~interrupt
the
processor.
the
processor
is
being
executed
interrupt
on
W.
be held low
4.75
of
vector
This
location
be
stored
to
address
be
to
(NMI)
As with
will
before
bit
in
FIGURE
mask
microprocessor
least
for
at
If
on
Reset
the
volts.
$2,
address (FFFE)
should
into the
FFFF
should contain
stored into
A
low-going
sequence
the
complete
the
the
m
it
recognizes
Condition
-—
9
INITIALIZATION
eight
goes
(151
next
will
contain
program
the
pro-
edge
on
be
current
the
Code
The Index
and
Condition
Register, Program
Code
stack.Atthe end of the
loaded
that
points
in
memory
these locations
at
masflfle
NMI
the
chip;
used
be
Inputs
sampled
are
routine
locations
interrupt
has
a
however
for
wire-OR
Wand
during
the
on
high
$1
instruction.
is
10
flow chart
Figure
and
paths
1
the
gives
MPU AFTER RESTART
OF
a
interrupt
memory
Register
a
to
vectoring
FFFC
causes
routine
impedance
3
a
k9
and
are
W
(152
following
vectors
for
map
Counter,
stored
are
16-bit
a
cycle,
and
the
in
memory.
address
FFFD.
MPU
pullup
An
to
resistor internal
external resistor
optimum
hardware
and
describing
of
interrupt
control of
interrupt
will
start
completion
the
the
the
microprocessor.
vectors.
Accumulators,
away
address
is
which
address
branch
to
to
VCC
interrupts.
lines
the
interrupt
decision
major
the
on
will
be
located
loaded
a
non
to
should
that
of
an
Table
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interrupt
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l
1.
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ll
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-
Address
FFFE+FFFF
-
Instruction
=
Out
Contents
Loaded
of
~
into
MPU
————~_
MOTOROLA
Semiconductor
A-7
Products
Inc.
MC6800
Yes
V
A
FIGURE 10
Start
FFFE,
MPU
Reset
Sequence
FFFF
FLOW
CHART
The
registers
Program
(16‘bits)
address.
Stack
contains
that
in
an
normally
MPU
available
Counter
register
Pointer
external
random
a
A
has
for
the
three
use
that
The
address
16-bit by
The
points
stack
the
program
of
push-down/pop-up
Read/Write
access
registers
programmer
counter
the
to
pointer
the
next
stack.
current
is
a
two
available
memory
and
three
(Figure
is
a
byte
This
MPU
8-bit
11).
two
byte
program
register
location
stack
that
I
F
h
Etc
ns me
Execute
instruction
REGISTERS
is
may
V
t
ll
l
t.
'On
have
any
applications
stack
when
Index
is
that for
the
Accumulators
lators
that
arithmetic
location
power
Register
used
to
Indexed
are
logic
Interrupt
NM'
FFFC FFFD
that
store
used
l
require
is
mode
—~
unit
V
Execute
Routine
ll
(address)
the stack
lost,
The
index
data
of
memory
MPU
The
hold
to
(ALU).
lRO
FFF8 FFF9
v
that
storage
register
a
sixteen bit
or
contains
operands
is
convenient.
of
information
be
must
is
a
two memory
addressing.
two
and
In
non—volatile.
register
byte
address
8-bit
accumu-
from
results
those
in
the
an
®
MOTOROLA
Semiconductor
11-8
Products
Inc-
MC6800
FIGURE
-—
11
PROGRAMMING
MODEL
OF
MICROPROCESSING UNIT
THE
7
ACCA
7
ACCB
15
IX
15
PC
15
SP
7
1
l
1
H
c
Register
Counter
Pointer
COdes
(From
Bit
A
B
7)
Accumulator
O
Accumulator
0
Index
0
Program
0
Stack
O
N
$23,323"
c
z
v
L
Carry
Overflow
Zero
Negative
Interrupt
Bit
Half
Carry
(From
3)
SP=Stack
CC
ACCB
ACCA
iXH
lXL
PCH
PCL
=
Condition
=
Accumulator
=
Accumulator
=
Index
2
Index
=
Program
=
Program
FIGURE 12~SAVING THE STATUS
Pointer
Codes (Also called
B
A
Register,
Register,
Higher
Lower Counter, Counter,
Order
Order8Bits Higher Lower
Order
Order
the
8
Bits
8
8
Processor
Bits
Bits
Status
Byte)
OF THE
m-2
m-1
m+1 m+2
MICROPROCESSOR
i
I
Before
IN
THE
STACK
m—9
m—8
m-7
m—6
m—5
m—4
m—3
m-2
m-‘l
m+1
m+2
After
MOTOROLA
Semiconductor Products
A-9
Inc.
M
06800
Condition
indicates Negative
(C),
and
COndition Code
for
the
interrupt
Code
Figure
status
results
the
(N),
half
conditional
mask
Register
12
within the
MPU
MC6800 has
The
Included
rotate, interrupt thru
are
load,
and
6).
MPU
The
M06800
address modes
the
that
mode
coding
modes
7
along
is
I
of
MHz,
addressing and
addressing
in
Table
time
quency
Accumulator
only
addressing,
specified.
These
Immediate
is
operand except
and
containedinthe
LDS
and
third
bytes
Code
Register
of
an
Zero
(2),
from
carry
Register
branch
and
the
(I).
The
b7)
order
bit
(b6
shows
stack.
INSTRUCTION
a
and decimal
binary
conditional
store,
stack
manipulation
ADDRESSING
eight-bit
that
within the
given
Addressing
be
can
a
function
for
a
particular
with the
in
machine
these
times would
(ACCX)
either
accumulator
are
one-byte
LDX which have
of
the
The
condition code
Arithmetic
Overflow
bit
are
3
used
Logic
(V),
(H):
as
Carry
These bits
testable
instructions.
of
unused
bits
are ones.
of
saving
the
SET
72
of
set
different
arithmetic,
unconditional
or
instructions
MODES
microprocessing
used
by
a
of
instruction.
associated instruction
Addressing
second
instruction.
programmer,
both the
instruction
cycles.
be
A
or
instructions.
In
immediate
byte
the
operand
The MPU
type
A
summary
With
microseconds.
——
In
accumulator
of
register
Unit
operation:
from
bit
of-
the
conditions
is
Bit
4
the
the Condition
microprocessor
instructions.
logical,
shift,
branch,
(Tables
has
unit
of
can
seven
with
the
instruction
of
the
be
found
execution
fre»
clock
a
accumulator
B
addressing,
the
in
the
instruction
second
the
addresses
location
this
for
execution.
7
the
Direct
operand
instruction.
address zero
through
by
storing
it
should
whenitfetches
These
Addressing
is
Direct
lowest
the
255.
in
data
be
random
a
twoorthree-byte
are
In
direct
contained
addressing
256
bytes
Enhanced execution
these locations.
access
the
addressing,
in
the
allows
in
the
In
memory.
immediate
instructions.
the
second
the
user
machine
times
most
configurations,
These
instruction
address
byte
to
directly
locations
i.e.,
achieved
are
two-byte
are
of
of
the
instructions.
In
Extended
address used
as
The
third
eightbits
lute
2
address
Indexed
containedinthe
the index
to
carry index
The
modified
so
ter two-byte
Implied
the
instruction
register,
Relative
is
contained
the
to
carry allows
+129
byte
Addressing
containedinthe
the
of
higher
of
byte
address
the
in
memory.
Addressing
eight«bits
second
register's
is
then added
register.
This
address
is
there
no change
instructions.
Addressing
gives
These
etc).
Addressing
in
the
second
user
to
of
counter's
is
the
program
borrow
or
the
bytes
instructions.
the
These
——
to
result
is
——
the
are
then added
address
present
extended
second
byte
of the address instruction for
the
operand.
are
In
indexed
of
byte
lowest
eight
the
higher
is
then
in
held
a
the
to
In
the
address
one—byte
In
relative
of
byte
lowest
to
data
within
instruction.
addressing,
the
of
of
is
used
This
three—byte
addressing,
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TABLE
OPERATIONS MNEMONIC
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4
I
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V
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o 0
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o
s
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significant
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Register
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exit the
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0
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R
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o
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I
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If
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set,
state.
I?
:
of
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(See
Special Operations)
NonMaskabIe
a
A.
bytes?
A-l3
M
C6800
TABLE
7
INSTRUCTION
ADDRESSING MODES
(TimesinMachine
AND
Cycles)
ASSOCIATED
EXECUTION TIMES
ABA ADC ADD AND ASL ASFI
BCC
BCS
BEA BGE BGT BHI BIT BLE BLS BLT
BMI
BNE BPL BRA BSR BVC BVS
CBA CLC CLI CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOFI
OpevandI
(Dual
xx
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0103:»).
no»-
a.
INC INS
INX
JMP JSR
LDA LDS
LDX
LSR NEG NOF’ ORA PSH PUL ROL ROR RTI HTS SBA SBC
SEC
SEI SEV STA
STS
STX SUB SWI TAB TAP TBA TPA TST TSX TSX WAI
OperandI
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4:
5C 6C
7:
8C
9C
101:
11:
1121:
131:
1,141:
15:
16C
171:
.18:
19:
I261:
ASSIGNMENT
PIN
O
VSS'
A
Halt
$1
IRQ:
VMA
N—MI
BA
Vcc.
A0
A1
A2
I
A3
A4
A5
A6
A7
A8
A9
A10
A11
Reset
TSC
N.C.
DBE
N.C.
R/W
D4
05 05
707
A15
A14
A13
A12
V53
¢2
DO
D1
02 03
NOTE:
:1
J
J
:I
:I
:1
:I
J
:I
:I
3
3.129
:1
3
:1
I]
I]
3
3
3
40‘
39
38
37
36
35
34
33" 32 31'.
'30,;
28
27
26
25
24
23,
22
21‘.
Interrupt
Instrucfion
the
WAI
a
is
time
instruction.
12
being
cycles
executed,
Then
end
from
is
It
“fl“
I
:(LD
4
I
of
the
foltowing
except
cycles.
2471..
1
1111111101
SNEATIN-G
MILLIMETEHS INCHES
MAX
MIN
a
50.29 51.31 1.980
14.88 15.82
2.54
4.19
0.38 0.53 0.015
1.40 0.030 0.055
0.76
zgr—xL-Im-nunwzbg
2.54
830
1.78
0.76
0.20 0.33 0.008
2.54 4.19 0.100 0.165
14.60
15.37 100
0.51
1.52
.
.
2
I
,
I]
I’LANEGJ
MIN
MAX
2.020
0.615
0.585
0.100 0.185
0.021
0.100
030
0.030
0.070
0.013
0.575
0.605
0.020
100
0.060
,___
L
NOTE:
PACKAGE
See PIastic
I.
LEADS,TRUE
0.25
mm
PLANE),AT
CONDITION.
CASE
(CERAMIC)
Page
Package
'
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MAX.
DIMENSIONS“
715-02
165 for
dimensions.
~
POSITIONED
DIA
SEATING
(AT
MAT'L_
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~
'
.
WITHIN
'
'
®
MOTOROLA
Semiconductor
A-l4
Products
Inc.
MC6800
Table
tion
present
Address
each
This
Address
and
cycle
information
results
ing
pected
IMMEDIATE
ADC EOR
(13%:
233
BIT SBC
CMP
SUB
CPX
tgi
DIRECT
ADC
EOR
(13%:
233
BIT
SEC
CMP
SUB
CPX
t8:
STA
STS STX
INDEXED
JMP
ADC
EOR
2,38
5%?
BIT
SEC
CMP
SUB
CPX
tgi
8
provides
on
line
(VMA),
for
the
each
detailed
a
Address
and
instruction.
is
useful
during debug
Mode Cycle
Instructions
Cycles
Bus,
the
in
of
2
3
3
4
4
5
4
5
6
SUMMARY
description
Data
Bus,
Read/Write
comparing
both software
VMA
Line
#
1
1
1
2
1
1
1
2
1
3
1
1
1
2
1
3
1 1
1
2
1
3
1
4
1
1
1
2
0
3
1
4
1
1
1
2
3
0
1
4
1
5
1
1
1
2
0
3
0
4
1
1
1
2
0
3
0
4
1
5
1
1
1
2
0
3
0 Index
4
1
5
1
6
CYCLE BY
OF
informa-
of
the
Valid
Memory
line
(R/W)
with
actual
and hard-
TABLE
8——OPERATION SUMMARY
Code Address
Op
Code Address
Op
Code Address
Op
Code Address
Op
Code Address
Op
Code Address
Op
Code
Op
Address
Op
Op
Address
Operand
Address
of
Code
Address
Code Address
of
Address
OpCodeAddmg
Code
Op
Destination
Destination
Op
Op
Address of
Address of
Address
Op
Op
Index
Index
Op
on
Index
Index
Index
0p
Op Index
Index
Index
Address
Code Address
Code
Address
of
Code Address
Code
Address
Register
Register
Code
Address
Code Address
Register
Register
Register Code Address
Code Address
Register
Register
Register
Register
dur-
ex-
Address
+
+
+
4-
Operand
+
Operand
+
+
Address
Address
+
Operand
Operand
Operand
+
Plus
+
Plus Offset Iw/o
Plus Offset
+
Plus
Offset
Plus
Plus Offset
Bus
1
1
2
1
1
1
1
1
1
+
1
Offset
1
1
Offset
CYCLE
ware
as
is
categorized
Number
with
the
execute the
table.)
(w/o
Carry)
Carry)
(w/o
Carry)
1
+
OPERATION
the control
in
Cycles
same
the
groups
per
Addressing
same
R/W Line
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
of
in
program
according
instruction.
Mode
manner;
Code
Op
Operand
OD
Code
Operand
Operand
Code
Op
Address of
Operand
Code
Op
Address of
Operand
Operand
OpCode
Destination
Irrelevant
Data
from
Code
Op
Address of
Irrelevant
Register
Register
Code
Op
Offset
Irrelevant
Irrelevant
Code
Op
Offset
Irrelevant
Irrelevant
Operand
Code
Op
Offset
Irrelevant
Irrelevant Data
Operand
Operand
is
executed.
to
Addressing
(In
and
exceptions
Data
Data
Data
(High
Data (Low
Operand
Data
Operand
Data
(High
Data (Low
Address
(Note
Data
Accumulator
Operand
Data (Note
Data
(High
Data (Low
Data (Note
(Note
Data
Data (Note
Data (Note
Data
(Note
Data
(Note
Data
(High
Data (Low
The
general,
Number of
are
Bus
Order
Order
Order
Order
1)
1)
Order
Byte)
Order
Byte)
1)
1)
1)
1)
1)
1)
Order
Byte)
Order
information
Mode
and
instructions
Cycles
indicated
Byte)
Byte)
Byte)
Byte)
Byte)
in
M
®
MOTOROLA
Semiconductor
A-l5
Products
Inc.
MC6800
Address
and
INDEXED
STA
ASL
LSR
REE
SE:
Egg/I
$815
INC
STS STX
JSR
EXTENDED
JMP
ADC EOR
233 8%:
BIT
SEC
CMP
SUB
CPX
t3;
A
STA
B
STA
LSR
ASL
CE);
fig?
Egg/I $8113
INC
Mode
Instructions
(Continued)
Cycles
6
7
7
8
3
4
5
5
6
Cycle
#
1
2
3
4
5
6
1
2
3
4
5
6
7
1
2
3
4
5
6
7
2
3
4
5
6
8
TABLE 8OPERATION
VMA
Line
1
1
0
0
0
1
1
1
0
0
1
0
1/0
(Note
3)
1
1
0
0
0
1
1
1
1
1
0
1
1
0
7
0
0
1
1
1
2
1
3
1
1
1
2
1
3
1
4
1
1
1
2
1
3
1
4
1
5
1
1
1
2
1
3
0
4
1
5
1
1
1
2
1
3
1
4
0
5
1/0
6
(Note
3)
Code Address
Op
Code
Op
Index
Index
Index
Index
Code
Op
Code
Op
Index
Index
Index
Index
Index
Op
Op
Index
Index
Indgx
Index
Index
Op
Op
Index
Stack
Stack
Stack
Index
Index
Op
Op
Op
Op
Op
Op
Address
Op
Op
Op
Address
Address of
Op
Op
Op
Operand
Operand
Op
Op
Op
Address
Address
Address of
Address
Address
Register
Register
Register
Register
Plus
Plus Offset
Plus
Address
Address
Register
Register
Register
Register
Register
Plus
Plus
Plus Offset
Plus
Code Address
Code Address
Register
Register
Register
Register
Register
Code
Plus Offset (w/o Carry)
Plus
Plus Offset
Plus Offset
Address
Code Address
Register
Pointer
—~
Pointer
Pointer
Register
Register
Code
Plus Offset
Address
Code Address +
Code Address
Address
Code
Code Address
Code Address
of
Operand
Address
Code
Code Address
Code Address
of
Operand Operand
Code Address
Address
Code
Code Address
Destination Address
Destination
Address
Code
Address
Code
Address
Code
of
Operand
of
Operand
Operand
SUMMARY
Bus
1
+
Offset (w/o
Offset
1
+
Offset
Offset
Offset
1
+
Offset
1
+
1
2
1
+
2
1
+
+ 2
1
+
+
2
+
1
+
+ 2
Address
1
+
2
+
(Continued)
R/W Line
1
1
1
1
1
O
1
1
1
1
1
1
(w/o
Carry)
Carry)
0
1
1
1
1
1
0
1
+
0
1
1
1
0
0
1
1
(w/o
Carry)
1
1
1
1
1
1
1
1
‘l
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
Code
Op
Offset
Irrelevant
Irrelevant
Irrelevant Data (Note
Operand
Code
Op
Offset
Irrelevant
Irrelevant Data (Note
Current
Irrelevant
New
Code
Op
Offset
Irrelevant
Irrelevant Data
Irrelevant Data
Operand
Operand
Code
Op
Offset
Irrelevant
Return Return
Irrelevant Data
Irrelevant
Irrelevant Data
Op
Jump Jump
Op
Address of
Address
Operand
Op
Address of
Address of
Operand
Operand
Op
Destination
Destination
Irrelevant
Data
Op Address of
Address
Current
Irrelevant
New
Data Bus
Data (Note
Data (Note
Data
(Note
Data
Data
Data
'
Data
(Note
Operand
Operand
Data (Note
(Note
(Note
Data
(High
(LOW
Data
(Note
Data
Address
Address
(Low
(High
(Note
Data
(Note
(Note
Code
Address
Address
(High
(Low Order
Code
Operand
of
Operand
Data
Code
Operand
Operand
Data
(High
(Low Order
Data
Code
Address
Address (Low
(Note
Data
from Accumulator
Code
Operand
of
Operand
Data
Data
(Note
Data
Operand
Operand
1)
1)
1)
1)
1)
1)
(Note
1)
1)
1)
Order
Order
1)
Order
Order
I)
1)
1)
Order
(High
(Low
(High
(Low
Order
(High
1)
(High
(Low
1)
(Note
3)
Byte)
Byte)
Byte)
Byte)
Order
Order
Order
Order
Byte)
Byte)
Order
Order
Order
Order
3)
Byte)
Byte)
Byte)
Byte)
Byte)
Byte)
Byte)
Byte)
Byte)
Byte)
A—l6
MC68OO
Address
and
Instructions
EXTENDED
STS STX
(Continued)
JSR
INHERENT
ABA DAA SEC ASL DEC ASR CBA LSR CLC NEG CLI CLR ROL TPA CLV ROR
COM
sen
INC
SEV TAB TAP
NOP TBA
TST
SBA
DES
PNESX
INX
PSH
PUL
TSX
TXS
HTS
Mode Cycle
Cycles
#
1
2
3
6
4
5
6
1
2
3
4
5
9
6
7
8
9
1
2
2
1
4
2
3
4 0
1
4
2
3
4
1 1
2
4
3
4
1
2
4
3
4
1
2
4
3
4
1
2
3
5
4
TABLE 8
VMA
Line Address
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
O
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
OPERATION
Code Address
Op
Code Address
Op
Code Address
Op
Address
Address
Address
Code Address
Op
Code
Op
Code
Op
Subroutine
Stack
Pointer
Stack
Pointer
Stack
Pointer
Code Address
Op
Code
Op
Code Address
Op
Code Address
Op
Code Address
Op
Code
Op
Previous
New
Register
Code
Op
Code Address
Op
Pointer
Stack
Stack
Pointer
Code Address
Op
Code
Op
Stack
Pointer
Stack
Pointer
Code Address
Op
Code Address
Op
Pointer
Stack
New
Index
Code Address
Op
Code Address
Op
Index
Register
New Stack
Code
Op
Code Address
Op
Stack
Pointer
Stack
Pointer
Stack
Pointer
of
Operand
of
Operand
of
Operand
Address
Address
Starting
Address
Address
Register
Address
Address
Register
Pointer
Address
Contents
+
+
+ 2
SUMMARY (Continued)
Bus
1
+
2
+
1
+
1 1
+
+ 2
Line
Address
1
2
+ 2
2
+
+1
1
+
Contents
1 1
+
1 1
1
+
1 1
1 1
+
1
+
1
+
1
R/W
1
Op
1
Address of
1
Address
1
Irrelevant
O
Operand
O
Operand
1
Op Address of
1
Address
1
Op
0
Return
0
Return
1
Irrelevant
1
Irrelevant
1
Address of
1
Op
1
Op
1
Op
1
Op
1
Irrelevant
1
Irrelevant
1
Op
Op
0
Accumulator Accumulator
1
Op
1
Op
1
Irrelevant Data (Note
Operand
1
Op
Op
1
Irrelevant Data
1
Irrelevant
1
Op
1
Op
1
Irrelevant
1
Irrelevant
1
Op
1
Irrelevant
1
Irrelevant
1
Address of Next Order
Address of Order
Code
Operand
of
Operand
Data
Data
Data
Code
Subroutine
of
Subroutine
CodeofNext
Address (Low
Address
Data
Data
Subroutine
Code
Code
of
Next Instruction
Code
Code
of Next
Data
Data
Code
Code
of Next
Code
Code
of Next
Data
Code
Code
of Next
Data
Code
Code
of Next
Data
Data
Code
Data
Data (Note
Byte)
Next
Byte)
Data Bus
(High
(Low
(Note
Order
(High
(Low Order
Instruction
(High
(Note
(Note
Instruction
(Note
(Note
Instruction
Data
Data
Instruction
from Stack
Instruction
(Note
(Note
Instruction
(Note
Instruction
Instruction
1)
(High
(LOW
Order
Order
1)
1)
(Low
1)
1)
1)
1)
1)
2)
1)
Order Order
Byte)
Byte)
.
Order
Order
Byte)
Byte)
Order
(High
(Low
Byte)
Byte)
Byte)
Byte)
Byte)
-——-—————_~
®
MOTOROLA
Semiconductor
A—l7
Products
Inc.
MC6800
Address
and
INHERENT
WAI
RTI
SWI
RELATIVE
\BHI
BCC
SE?)
at:
BGE
BLT
BM)
BGT
BSR
1.
Note
2.
Note Note 3.
4. While
Note
Mode
Instructions
(Continued)
BNE
3;:
BVC BVS
If
device
Depending
is
Data
ignored
For
TST,
the
Address
low;
which
bus
on
VMA=0
MPU
Bus,
Cycles
9 5
1O
12
4
8
is
addressed
capacitance,
MPU.
the
by
and
is
waiting
R/W,
Cycle
#
_1
2
3
4
6
7
8
9
1
2
3
4
5
6
7
8
9
1O
1 .1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
1
2
3
4
5
6
7
8
during
Operand
for the
and Data
TABLE
VMA
Line
1
1
1
1
1
1
1
1
1
1
1
O
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0 Branch
1
1
0
1
1
0
0
0
this
data from
does
data interrupt,
Bus
are
——
8
OPERATION SUMMARY
Address
Code
Code
Code
Code
Address
Address
Pointer Pointer
Pointer
Pointer Pointer
Pointer
Address
Address
1
-
—-
2
3
4
5
6
Op
Op
Stack
Stack
Stack
Stack
Stack
Stack Pointer
Stack
Op
Op
Bus
1
+
(Note 4)
1
+
(Continued)
Stack Pointer
Pointer
Pointer Pointer
+
+ 2
+
3
Stack
Stack
Stack
1 1
Stack Pointer+4
Stack Pointer
Stack
Stack
Code
Op
Code
Op Stack
Stack
Stack
Stack Pointer
Stack
Stack Pointer
Stack
Stack
Vector
Vector
Code
Op
Code
Op
Code
Op
+
5
Pointer+6
7
+
Pointer
Address
1
+
Address
Pointer
~
#
Address
Address
Address
1
2
3
5
6
7
(Hex)
FFFA
FFFB (Hex)
1
+
+ 2
Pointer
Pointer
Pointer~4 0
Pointer Pointer
Address
Address
Address
Code
Code
Address of
Address
Address
1 1
+
Main
Program
Op
Op
Return
Stack Pointer 0
Address
VMA,
high
1
~
2
of Main
then the
may
will
impedance
Program
Data
be retained
high indicating
go
state.
Bus will
go
the
on
the
Stack
Stack
Return Subroutine
cycle
uses
the
previous cycle
not
Bus
all in
Pointer
Pointer
Address
change.
Available
the
R/W Line
1
Code
Op
1
Code
Op
0
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0
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the
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following
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VMA
is
®
MOTOROLA
Semiconductor
A-l8
Products
Inc-
M06820
(0
to
70°C;
L
or
M068200
L
{-40
to
85°C;
Suffix only)
P
Suffix)
PERIPHERAL
MC6820
The
of
means processing
peripherals
to
and
most
The
MPU
can
four control operation
8—Bit
Two Bidirectional
Two
Two
Four
0
Handshake
O
High-Impedance
0
Program
CMOS
interfacing
Unit
control
four
peripheral
functional
during
be
programmed
control/interrupt
modes.
of
Bidirectional
Programmable Programmable
Individually-Controlled
Peripheral
as
Operation
Lines
Controlled
Drive
Peripheral
(MPU).
through
lines. No
devices.
system
This
the
interface.
Control
Capability
INTERFACE ADAPTER
Interface
peripheral
This device
8—bit
two
external
configuration
initialization.
to
as
act
lines
Data
8—Bit
may
a
high
Bus
Buses
allows
Control
Data Direction
Control
Logic
3-State
Outputs
for
and
Interrupt
Side
on
Adapter
equipment
is
capable
bidirectional
logic
the PIA
of
Each
an
input
be
programmed
degree
for
Communication
for Interface
Registers
Registers
Interrupt
and
Input
Direct
and
Interrupt
A
Peripheral
provides
to
of
peripheral
is
required
is
of
the
peripheral
or
output,
of
flexibility
to
Input
Output
Transistor
Disable
Lines
(PIA)
the
MC6800
the interfacing
programmed
for
Peripherals
Lines;
for
interfacing to
each
and
one
in
the
with
the
Two Usable
Peripheral
Drive
Capability
data
data
of
Peripheral
universal
Micro‘
MPU
the
buses
the
by
lines
of the
several
over-all
MPU
M
OS
(NCHANNEL,SILICON-GATE)
PERIPHERAL
ADAPTER
NOT SHOWN:
PSUFFIX
PLASTIC
CASE
INTERFACE
L
SUFFIX
CERAMIC
PACKAGE
CASE 715
PACKAGE
711
M6800
MCGBOO
Microprocessor
II
Address
Bus
Data
Bus
MICROCOMPUTER
BLOCK
I
it
DIAGRAM
Read
Memory
Random
Access
Memory
MC6820
Interface
,
Adapter
Interface
Adapter
Only
FAMILY
Modem
Data
Memory Address
and
Control
Interru
Bus
9
MC6820
<—>
—>
(
PERIPHERAL
BLOCK
i
..
'
i
'
Data
»
A
Bus
Buffers
.
.
,
L
Selection
'and
.<
"
Control
v
-
INTERFACE
DIAGRAM
_
ADAPTER
V.
A
Buffets.
and
Data
Register
AV
B
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..
and
.
'='<—>
_
,V.
‘1‘»
-
Pegzhfal
PerEIJpheraI
ata
M06820
ELECTRICAL
High Voltage
lnput
Low
Input
Leakage
Input
=
0
(Vin
Three-State
=
0.4to2.4
(Vin
High
Input
Input
Output
Output
Output
Output
Output
Power
lnput
Output
Peripheral
Delay Time,
Delay Time,
Rise
Delay Time,
Delay
(VlH
Low
(VIL
High
“Load “Load
Low
“Load
High
(VOH
=
(V0
Darlington
Low
(VOL
Leakage
(VOH
Dissipation
Capacitance
=
(v;n
Capacitance
=
(Vin
(Figure 2,
(Figure
and
Time
Delay
(Figure
(Figures 4,
Time,
(VCC
Time,
Delay
(Figure 6,
Time,
Delay
(Figure
Time,
Delay
(Figure
and
Rise
Delay
Time,
(Figure
Interrupt
Reset Low
=
2.4 Vdc)
=
0.4 Vdc)
=
=
=
=
1.5
=
=
0,
0,
Data
Fall
Fall
Release
CHARACTERISTICS
Voltage
Current
Vdc)
5.25
to
(Off
State)
Input
Vdc)
Current
Current
Voltage
-205
—100
Voltage
1.6
mAdc,
Current
Vdc)
2.4
Vdc,
Base)
Current
0.4 Vdc)
2.4 Vdc)
TA
TA
Setup
Enable
3)
Enable
2)
Times
from
3)
Enable
5)
Enable
30%
Enable
7)
Peripheral
5)
Enable
6)
Time
CBi
7)
pAdc,
pAdc,
(Sourcing)
the
(Sinking)
Current
=
25°C,
=
25°C,
negative
negative
for
CA1
negative
negative
VCC,
positive
positive
for
active
Enable Enable
Enable
current
(Off
=
f
‘R/W,
=
f
Time
CA1
active
Figure
Data
C81 and C82
transition
Timem
Time*
(Figure
9)
Characteristic
R/waFet,
R80,
Current
Width<25
Pulse Pulse Width
Pulse Width<25
for
State)
1.0 MHz)
__
Reset,
1.0 MHz)
(Figure
transition
transition
CA2
and
transition
transition
transition
4; Figure
transition
valid
driving
R80,
1)
CB2
to
other
CA2
to
CA2
to
input
CA2
to
Peripheral
to
Peripheral
to
12 Load
CB2
to
negative
transitionto082
input
CB2
positive
to
Fifi—ET
and
(Figure
=
(VCC
R81,
<25
than
PAO-PA7,
CSO,
R81,
negative
positive
signals
positive
C)
negative
positive
signals
V
5.0
cso,
DO—D7,
MS)
us)
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transition
transition
(Figure
transition
8)
i5%,
V55
Other
Other
C31,E§§,
CBl,
PBO-PB7,
PAO-PA7,
PAO~PA7,
Other
Other
e.g.,
PBO-PB7,
W,
CS2, CA1,
WERTQB
transition
transition
3)
transition
valid
Data
PAO—PA7,VCA2
transition
7)
=
Enable
Inputs
Enable
Inputs
CA1,
Enable
DO—D7
Outputs
00—07
Outputs
W
Enable
00.07
CA2,
PBO-PB7
Valid
0,
CB2
CA2
CA2
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C82
CB1
TA
= O
Symbol
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ITSl
llH
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an
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th
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lin
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70°C
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+
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-
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F
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10
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20
12.5
10
7.5
5.0 10
1.0
1.0
1.0
2.0
1.0
2.0
1.0
1.0
1.0
2.0
16
Unit
Vdc
+
0.4
+
0.8
Vdc
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“Ada
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mAdc
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pF
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us
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us
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line
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high
minimum
a
MOTOROLA
of
1.0
before
us
addressing
Semiconductor
the
PIA.
Products
Inc.
A—20
MC6820
MAXIMUM
Supply Voltage
Voltage
lnput
Operating
Storage Thermal
BUS
READ
Enable
Enable
Enable
Setup
Data
Data
Address
Rise and
WRITE
Enable
Enable Pulse
Enable
Setup Data
Data Hold
Address
Rise
Temperature
Temperature
Resistance
TIMING
(Figures
Cycle Pulse
Pulse
Time,
Time
Delay Hold
Time
Hold
Fall
(Figures
Cycle
Pulse
Time,
Setup
Time
Hold
Fall
and
FIGURE
RATINGS
Rating
Range
Range
CHARACTERISTICS
10
12)
and
Time
High
Width,
Low
Width,
Address and
Time
Time
11
Time
Width,
Width,
Address and
Time
Time
Time for
for
Enable
12)
and
High Low
Enable
1
PERIPHERAL
R/W
R/W
(Read
Characteristic
validtoEnable
input
valid
Enable
to
input
DATA
Mode)
positive
positive
SETUP
Symbol
VCC
Vin
TA
Tstg
GJA
transition
transition
TIME
Value
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N03
0to+70
——55
82.5
Unit
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to
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to
+150
to
Vdc
Vdc
0C
0C
OC/W
Symbol
tcch
PWEH
PWEL
tAS
tDDR
tH
tAH
tEf
tEr,
tcch
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tDSW
tH
(AH
tErI
tEf
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device
This
inputs
ages
normal
tion
voltages
Min
1.0
against electric
or
precautions
of
any
to
contains
voltage
this
Typ
0.45
0.43
160
——
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10
~
1.0
0.45
0.43
160
195
1O
10
FIGURE 2—-CA2
CRA-S=CRA-3
Mode,-
~
circuitry
fields;
high
due
however,
be
higher
impedance
damage
-
-—
~
-
-—
-
DELAY TIME
=1,
to
taken
than
Max
~
25
320
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25
25
——
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~
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to
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protect
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um
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rated
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us
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ns
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FAO~PA7 PBO-PB7
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r
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v
V
2.4
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CA2
MOTOROLA
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FIGURE Mode;
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V
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f,
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V
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the
previous
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part
E
was
pulse.
deselected
during
*i
V
2.4
Products
Inc.
M06820
FIGURE 4
Enable
PAO-PA7
CA2
-—
(Write
‘cmos-
tho
(Write
PERIPHERAL
CRA-5
Mode;
0.4
v
FIGURE
Mode;
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previous
6
CRB—5
part
E
if:
2-4
0.4
CBZ
pulse.
CMOS
=
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=
ORB-3
was
DATA
-----
V
v
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deselected
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=1,
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TIME
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450%
CRB-4
during
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=
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0)
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the
FIGURE
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5
(Write
Enable
PERIPHERAL
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Mode;
\
DATA AND
=
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2.4
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r;
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pulse.
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transition
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X
v
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CB2
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FIGURE
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Mode;
Enable
t
C81
/
2‘4
positive
7
CRB-5
V
‘tcez
C
82
"Assumes
any
part
previous
0.4
FIGURE
Enable
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CS,
Bus
R/W
FIGURE
BUS
10
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tAS
8
RELEASE
IRO
V
2.4
READ TIMING
Information
F’WEH
V
2'4
tEr
tDDR
V
2.0
V
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TIME
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2.4
CHARACTERISTICS
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from
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4
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4
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a
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.
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9
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WRITE TIMING
Information
"‘PWEH
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<—
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V
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v
__..____...__.__._
MOTOROLA
Semiconductor
1-1-22
Products
Inc.
MC6820
(DO-D7,
Point
Test
for
130
pF
C:
=
30pFfor
R=
11.7
=
24
The PIA bit bi-directional register
enable line and
line,
tion
with
have
complete
in
lized select
PIA
lines
data
MPU
state except
Read/Write
is
selected for
PIA timing
other
of
the
the
MC6800
PIA
MPU
the
Bus.
Data the
input
the
PIA
high
on
data
to
the
proper
m
all
register
be
can
system
for
kfl
for
k9
interfaces
select
the
conjunction
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of
the
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the
and devices
signals
that
when
the
line
Enable
signal
is
E
pulse.
(.52
Read/Write
control
to
A
low
buffers
the
on
the
Read/Write line
the
bus. The
address
The
bits
used
asa
operation.
Load
PAO-PA7,
00—07
PAOAPA7,
DO.D7
PAO-PA7,
data
lines,
two
reset
MC6800
control
with
allow
PIA.
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remain
MPU
in
is
the
Read
a
operation.
(E)
is
that
referenced
This
signal
Clock.
(R/Wl
the
state
and
E
signal
PIA
and
active
in
the
power~on
A
the
CA2,
5.0
BL:
MMD6150
°"
MMD
or
CA2,
CA2 and
M06800
three
PBO‘PB7,
PBO-PB7,
PBO<PB7,
to
bus,
interrupt
line.
These
VMA
output,
PIA.
the
over
MPU
an
(DO‘D7)
Data
the
transfer
bus
data
in
performs
Read
The
supplied
the
high‘impedance
a
(high)
enable
to
the
to
leading
will
normally
This
output
directionofdata
PIA Read/Write
the
on
is
data
transferred
if
the
device
the PIA for
sets
up
the
to
enable
Re—set
a
logical
and
buffers
output
low
PIA
reset
C82)
V
k
2-5
EQUIV-
7000
Equiv.
CBZ
and
CB2
PIA
MPU
select
chip
request
lines,
signals,
permit
VlVlA
address line
—-
The
of
data
drivers
PIA
read
state
pulse,
PIA.
the
and
be
is
signal
transfers
from
has
been
are
pulse
is
line
zero
a
as
master
FIGURE 12
BUS TIMING TEST
Polnt
Test
100
Load
(IRQ
5.0
pF
I
INTERFACE SIGNALS
with
an eight-
lines,
two
read/write
in
conjunc—
MPU
the
should
be
a
into
bi—directional
between
three-
are
(off)
operation.
when
the
is
the
E,
Timing
of
trailing
derivative of
a
generated
on
line
enables
MPU
the
selected.
transfer
a
are
reset
when
present.
to
This
during
enabled
E
used
(low).
to
uti
chip
the
state
The
PIA
only
all
edges
by
the
to
A
of
reset
line
Data
Enable
be
deselected
inactive
select
the
internal
that
the
Interrupt Request
the circuitry.
the
tied
flag low.
interrupt
in
interrupt
plished by
sequentially
each
LOADS
B
Only)
V
3k
FOR MPU
PIA
Chip
signals are
and
high
transfers
and
stable
state.
PIA
Register
lines
PIA. These
is
to
The
register
duration of
Interrupt
MPU
chip).
together
Each
bits
Each
PIA
the
Servicing
PIA
The
interrupt
(CMOS
Polnt
Test
o——]
Select
used
to
must
m
are
Read/Write
for
the
when
Select (R80
used
are
€ontrol
be
written
and
theEpulse
Request
either
lines
These
This
permits
in
a
WHITE
that
can
bit
flag
line.
Also
which
from
a
peripheral
an
software
a
reads and
for
interruptlflag
flags
C81 and
(C80,
select
the
be
low
then
performed
signals.
duration
of
any
select
to
lines
two
Registers
read.
or
select lines
chip
while
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lines
(IRQA
directly
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are
all
wire«OR
cause
is
configuration.
the
associated with
four
interrupt
be
may
interrupt
routine
tests
bits
cleared
are
of the
are to
or through interrupt
interrupt
used
device. by
C
Load
Load)
pF
130
63—2)
These
C50
PIA.
for
selection
under the
The
chip
E
the
chip
and
RS1)
various
the
in
used
select
in
the
and
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and
IRQB)
drain"
has
two
a
enable
W
to
MPU
the
that,
onaprioritized
the
two
that
are
(zeroed)
C81
and
of
control of the
select
The
pulse.
selects
The
registers
conjunction
a
particular
should
read
write
or
The
act to
load
(no
request
internal
particular
bits
inhibit
may
control
set.
a
as
be
three
input
must
device.
the
lines
must
device
in
are
two
register
inside
register
stable
cycle.
active
interrupt
priority
device
linestobe
interrupt
line
to
peripheral
provided
are
a
particular
be
accom-
basis,
registers
result of
be
is
the
with
for
low
on
go
in
an
———————
®
MOTOROLA
Semiconductor
A-23
Products
Inc.
M06820
lFlQA
DO
D1
DZ
03
D4
05
D6
D7
38
33
32
31
30
29
28
27
26
4
H
<———>
<—>
H
<—>
EXPANDED
Control
RegisterA
(CRA)
Bus
Data
Buffers
-
(DBB)
Bus
|nput
Register
(BIR)
|—-—'———J—}—1/
<
Output
,
;
m
*5
E51
Output
Register
(ORA)
BLOCK
Bus
DIAGRAM
A
——J\
Interrupt
Control
Direction
Data
Register
(DORA)
v
Peripheral
InterAface
Status
A
A
<~——40
39
H
H
H
H
<—>
CA1
CA2
2
”0
3 PA1
PA2
4
5
PA3
FAA
6
7
PAS
8
PAS PA?
9
H
V
VSS
cc
Enable
=P'
Pin
:
cso
CS1
C82
R50
RS1
R/W
Reset
IRQB
20
l”
1
22
24
23
36
35
37
21
25 34
—> —> —>
—>
‘—‘>
———-<>-
—-——>‘
=
I
Chip
Select
and
R/W
Control
:
:>
>
Output
Register
(ORB)
Control
Register
(CRB)
8
>
Peripheral
Interface
B
A
Direction
Data
a
Register
(DDR8)
interrupt
C°”t'°'
Status
B
3
<——>1o
H11
<—>
H13
<—->
H
H16 H17
‘————-
H19
PBO
P81
12
P82
P83
14
P84
15
P85
P136
PB7
CB1
18
CB2
_______.
MOTOROLA
Semiconductor
A—24
Products
Inc-
MC6820
MPU
Read
Peripherai
data
register.
be
cannot during
interrupt
these
The PIA and eral
Section
peripheral
or
output.
enabled
E
an
control
lines
four
interrupt/Control
devices.
A
data
This
corresponding
which
are
Direction
data
Data
to act
MPU
pullup
standard
The
lines
written
responding
in
Output
Peripheral lines
properly
is
greater
less
output
reach
a
on
respective
Section
data
to act
PAO-PA7.
differ
to
Register
line
to
act
Operation,
as
inputs
Data Bus
resistor
TTL
data
that
are
into
data Register
Data
are
programmed
if
than
than
0.8
lines
full
voltage
Read
operation
bit of
B
in
lines
either
as
However,
from
After
to
pulse.
lines
used
are
provides
Peripheral
lines
can
is
accomplished
Data
be
outputs.
causes
as
an
input.
the
appears
lines.
these
on
load.
in
Output
programmed
the
register
line
A”
the
voltage
2.0
volt
for
such
that
causes
Output
Peripheral
B
the
Section
inputs
those
driving
Data
being
be
set
E
The
(CA1, CA2,
as
interrupt
8‘bit
two
lines
Data
be
Direction
During
data
on peripheral
directly
In
lines
Register
will
while
a
A
may
operation
as
outputs.
on
volts
a
logic
the
voltage
the
differ
to
Register
Data
of
or
outputs
the
output
lines
until
of
the
the
is
used
Operation
cleared,
pulse
inputs
PIA
bi-directional
for
interfacing
(PAO—PA7)
programmed
by
setting
Register
A
the
the
in
“0”
corresponding
MPU
an
on
input
represents
will
A
be
to
outputs.
a
cause
results
”0”
be
read
when
This
the
for
data
peripheral
a
logic
”0”
output.
on
transferred
from
that contained
A.
(PBO-PB7)
PIA
the
can
in
a
buffers
PAO-PA7.
the
corresponding
bit
interrupt
PIA
to
C81,
flag
is
deselected
condition the
When
C82).
least
at
one
E
PERIPHERAL INTERFACE
buses
data
to
periph-
Eachofthe
as
to act
bit
bit
a
lines
the
mode
maximum
a
appear
"high"
in
by
the
data
“1”
these lines does
similar
driving
They
an
input
in
“1”
a
for
those
the Data
of
peripheral
Read
Peripheral
programmed
corresponding
internal
the
of
the data
on
A
logical
the
on
”low”.
a
MPU
an
"Read
corresponding
will
be
data
output
Loading
into the
The
be
programmed
MPU
in
peripheral
manner
these
have three-
the
lines
one
”1"
cor-
Data
read lines
and
the
not
the
to
lines
must
pulse edge sense
the the of the
edge sense
interrupt
occur
of
the
interrupt input
network.Ifthe
interrupt
LINES
state capability,
when
state addition,
read
be
even
outputs,
may volts
Interrupt Input
CA1
flags signals
Peripheral
CA2
a
peripheral
patible
resistor
function
Register
Peripheral
may
peripheral
high
ard
TTL
ampere switch.
NOTE:
CBi, to
prevent
register
Reset clear
the
dataonthe
properly
if
the
voltages are
these
also be
and
to
used
directly
CB1
of the control
is
also
Control
be
can
programmed
control
standard
with
this line
on
of
this
A.
Control
be
also
programmed
control
input
impedance
As
TTL.
and
may
at
1.5volts
line
This
is
It
setting
when
inactive,
undesired
recommended
Reset
CB2) should
going
any
from
interrupt
circuit
will be
flag
pin.
input
allowing
peripheral
peripheral
from
those
lines
are
compatible
are
a
as
source
drive the base
(CA1
input
registers.
programmed
(CA2)The
output.
TTL;
represents
signal
(C82)
output.
an
output
also be used
to
directly
is
programmed
held
be
of
corresponding
goes
read of the
a
interrupt
the
has
set
them
data
below
and
only
to act
line
to
and
that
in
a
to
flags.
it
inactive
signal
flag
been
the
on
enter
to
line
data
lines
programmed
2.0 with
of
up
of
——
CB1)
lines
The active
the
by
as
an
As
an
output,
as
an
input
standard TTL
one
is
programmed
Peripheral
~
as
act
As
an
is
compatible
is
compatible
as a
source
drive
the
by
the
control
1
logic
state
interrupt
inactive
an
data
to
enabled and
been
conditioned,
active
a
high
an
as
PBO-PB7
for
a
the
transition
impedance
as
“high”.
edge
condition
to
has
properly
next
is
used
lines
volts
standard
1
to
milliampere transistor
a
Peripheral Input
the
set
that
transition
control
two
peripheral
control
interrupt input
line
this
the
internal
with
Control
an
interrupt input
this
input,
with
with standard
of
to
up
base of
Control
registers
a
transistor
Register
lines
flags
may
in
(CA1,
the
when Reset
state. Subsequent
active
the
edge
input.
will
outputs
As
and
TTL
ati.5
switch.
lines
interrupt
for
these
registers.
line
or
is
com-
pullup
load. The
Control
line
C82
line
has
stand-
1
mil|i<
CA2,
is
active
control
be
used
In
as
or
B.
to to
-—~———-——
®
MOTOROLA
Semiconductor Products
A-25
Inc.
MC6820
INTERNAL CONTROLS
are
data
six
locations
bus:
Registers,
two
and
within
Peripheral
two
There
MPU
Direction of these locationsiscontrolled
in
together
in
Table
R51
0
0
0
1
‘I
1 1
=
X
Don’t
with
1.
R80
0
O
1
0
O
Care
bit
TABLE
ORA-2
X
X
X
X
2
the Control
‘I
INTERNAL ADDRESSING
Control
CR
Bit
8-2
X
X
X
1
0
X
Register
1
0
INITIALIZATION
A
low This
ters.
inputs, figured
and
during
Details
and
Control
DATA
The
control peripheral
“0"
configures
input;
an
the direction
line has
reset
will
set
all
interrupts
the
possible
of
Register are
DIRECTION
Data
two
line.
data
the
“1" results
a
the
PAO-PA7,
disabled.
restart
program
configurations
as
REGISTERS
Direction
of
data
A
Data
corresponding
in
an
the
Control
by
Peripheral
Data
Control
Peripheral
Data
Control
effect
PBO—PB7,
follows.
Registers
through Direction
output.
PIA
Registers,
Registers.
the R80
Register,
Location
Direction
Register
Direction
Register
of
zeroing
The
which
of
(DDRA
each
peripheral
accessible
two
and RSI
Selected
Register
Register
A
Register
Register
8
all
and CB2
CA2
PIA
must
follows the
Data Direction
the
and
allow
the
corresponding
Register
data
the
to
Data
Selection
inputs
shown
as
A
A
B
B
PIA
regis-
be
con—
reset.
DDRBI
MPU
bit
set
line
CONTROL
The
MPU
control allow the
status two the applied. and control control
CRA
CR8
as
Bit
Data
2
selection
Data
signals are
Interrupt
The
four
to
at
as
signals when
cannot
reset indirectly
the
appropriate
REGISTERS
Control
two
control
to
lines
MPU
the
of the
registers
proper
Bits 6
modified
are
lines
words
TABLE
7
IROAI
IROA2
7
IRQBI IROBZ
Direction
in
each
of either
Direction
applied
Flags
interrupt
the four
on
lines
those
be
set
the
CA2,
CAI,
enable the
to
interrupt
be
may
select
chip
and
7
by
CA1, CA2,
is
shown
2
CONTROL
5
6
CA2 Control
5
6
CB2 Control
Access
Control
a
Register
R80
to
(CRA-6,
flag
Interrupt
are
programmed
directly
a
by
section.
Registers
operation
written
of
external
in
I
I
register
Peripheral
bits
from
Read
(CRA
CBI
flags.
and
the
CBI
Table
I
4
I
4
Control
when
and R81.
ORA-7,
are
and
the
Peripheral
and
(CRA
of
and
082.
interrupt
Bits
read
or
register
two
registers
interrupts
C82.
or
2.
WORD
3
DDRA CA1
Access
3
DDRB CB1
Access
(CRA—2
Bit
(CRA
Interface
the
proper
CRB—6,
by
set
Peripheral
be
to
MPU
CR
and
the four
In
lines
0
through
the
by
select
The
FORMAT
2
1
2
and
and
Register
register
and
active
inputs.
Data
Data
Operation
B)
allow
the
peripheral
addition
and
are
occurring
they
monitor
5
of
the
MPU when
signals
read
are
only
on
formatofthe
1
I
0
Control
I
0
Control
CR
B-2)
-
allows
CR8)
the
or
select
CRB-7)
transitions of
These
and
lines
bits
are
on
Control
Bus
B)
CR
ORA-1
(one-1)
NOieSI
TABLE
CRA-O
(CRB-O)
0
0
1
1 1
4,
O
1
0
1.
T
indicates
I,
indicates
The
Interrupt
ORB-7
and
If
CRA—O
IROA
high,
MOTOROLA
3 -—CONTROL OF INTERRUPT
Interrupt Input
CA1
(CB1)
IActive Set
positive
negative
is
cleared
(CRB—O)
(IRQB)
flag
IACIive
IActive
IActive
transition
transition
bit
by
is low
occurs
ORA—7
an
when
after
(low
(high
is
MPU
an
Set
Set
Set
to
to
cleared
Reed
interrupt
CRA—O
high)
Semiconductor
A-26
INPUTS
Interrupt Flag
ORA-7
(one-7)
high
on
(CB1)
on
high
(081)
on I
high
(CBI)
high
on
(C81)
low)
by
an
B
of
the
Data
occurs
(ORB-0)
is
CA1
CA1
of
I
of CA1
I
of CA1
CA1
T
of
MPU
Register
(Interrupt
written
Read
CB1
AND
MPU
Interrupt
Request
IRQA
Disabled mains
high
low
Goes
interrupt
(ORB—7)
flag
goes
Disabled mains
high
low
Goes
interrupt
(ORB—7)
of
disabled)
a
"one".
to
the
A
and
flag
goes
Data
Products
(IROB)
IRO
when
bit
high
m
when the
bit
high
Register,
is
later
Inc.
re—
the
ORA-7
re-
ORA-7
brought
MC6820
Control
of
CRB-O, CRA-‘l,
the
control
of input
lines
CAT
CA1 and C81
B-1)
CR
and
registers
and
C81.
ORA-5
(ORB-5)
O
0
0
0
Notes:
Interrupt Input
—-
The
used
are
1.
2.
3 The
4.
to
CRA—O
Bits
TABLE 4CONTROL OF CA2 AND
ORA—4
(ORB-4)
O
0
1
1
T
indicates
indicates
l
Interrupt
cleared
If
ORA-3
high,
two
control
CRA—3
(ORB-3)
by
(ORB-3)
IROA
Lines
lowest
and
O
1
0
1
positive
negative
flag
MPU
an
(IRQB)
the
CRB-O
transition
bit
ORA-6
is
(CRA-O,
order
interrupt
Interrupt
CA2
1
l
T
T
transition
Read
low
when
occurs
bits
are
CRAS (CREE)
Input
(CBZ)
Active
Active
Active
Active
to
(low
high)
to
(high
is
cleared
of
after
by
theBData
interrupt
an
CRA.3
used
respectively.
transition
(Table
CBZ AS
is
low
Interrupt Flag
ORA-6
Set
high
Set
high
Set
high
Set
high
low)
MPU
an
Register.
occurs
(CRB«3)
enable the
to
of
Bits
the
CRA-l
3).
INTERRUPT INPUTS
(CHE-6)
of
CA2
on
i
(CBZ)
of
CA2
on
i
(C82)
of
T
CA2
on
(CB2)
T
of
CA2
on
(CBZ)
of
A
the
Data
disabled)
a
"one".
to
Read
(Interrupt
is
written
MPU
interrupt
interrupt
MPU
IROA
Disabled mains
Goes
interrupt
(ORB-6) Disabled
mains
Goes
interruptflag
(CRB-6)
Register
and
CRB<I
and
input
Interrupt
Request
(IRQB)
~—
high
low
flag
goes
high
low
goes
and
is
later
signals
signals
l—R-O
re-
when the
bitCRA~6
high
IRO
re~
when the
bitCRA'S
high
ORB-6
brought
IROA and
determine the
CA1
and
is
IROB,
active
C81
M
ORB—5 ORB—4
1
1
1
O
O
i
MOTOROLA
®
CRB-a
0
1
0
TABLE 5
——
CONTROL
ORB-5
OF CBZ
is
high
Cleared Set
Low
the
on
E
first
the
MPU Write “B"
positive
pulse
transition
following
Data
operation.
Low
the
on
positive
the
Write
first
"B"
E
Data
pulse
transition
after
Register
tion.
Low
result
Register
Always high. MPU
results
“zero",
ORB-3
when
of
MPU
an
“'38
high
as
Will
be
in
cleared
clearing
Write Control
goes
WriteinControl
long
as
Register
Semiconductor
A-27
AS
Register
an
opera-
low
ORB-3
when
ORB-3
AN
MPU
as
“8"
OUTPUT
CB2
of
an
of
a
is
an
to
the
when
High
is
ORB-7
of
tion
the
High
on
the first
"E"
pulse
the
part
Always
low.Willgohighon
in
Control
changes
when
High
of
result Control
set
081
the
"E"
which
deselected.
was
low
as
Register
CRB»3
ORB-3
an
Register
interrupt flag
by an
signal.
positive
pulse
long
MPU
Products
active
following
occurred
as
an
”one".
to
goes
Write
"B".
transi-
edge
while
ORB—3
MPUWrite
“8"
that
as a
high
into
Inc.
bit
of
an
is
MC6820
Control
of
(ORA-3, ORA-4,
Bits
control
bits
input
and
4,
3,
CA2
the
determine
an
or
PIN
output
ASSIGNMENT
CA2
CRA~5,
5
of the
and
if
ORA-5
and
C82
Peripheral
control
lines
signal.
O
0
ORB-4,
If
CRB-3,
two
C82
Peripheral
control
the
control
ORA-4 CRA-3 Cleared
1
1
1 1
1 1
Control
and
registers are
Control
will
be
ORA-5
bit
TABLE
0
1
~
0
Control
1
Always highaslong
is
MPU
”A" that
a
Lines
used
These
interrupt
to
C885)
lines.
an
(ORB-5)
CONTROL OF CA-2
6
-
CRA-S
Low
after
on
an
negative
MPU
operation.
Low
after
on
an
negative
MPU
operation.
result
high.
Write
an
Register
Will
to
clears
CRA-3
when
Low
of
”zero".
Read
Read
MPU
be
Control
is
high
transition
“A"
transition
“A”
goes
Write
"A".
as
cleared
Register
CRA—S
is
CA1
(CB2)
control mode,
(Tables
low
CA2
low,
(CB1) (Table 4).
becomes
peripheral
CA2
5
ASANOUTPUT
CA2
E
of
Data
E
of
Data
3
as
to
ORA-3
on an
to
PACKAGE
is
(CB2)
an
output
data
have
C82
and
and
6).
when the
High
is
CRA—7
tion
High
the
during
Always low. WritetoControl
that
High a
Control
set
CA1
of
the
the
on
first
"E"
deselect.
a
low
Will
90
changes
when
result
of
Register”A".
DlMENSlONS
an
When
transfers.
Set
interrupt
by
signal.
negative
pulse
as
long
high
ORA-3
ORA-3
an
interrupt
CRA-5
signal
slightly
active
an
which
ORA-3
as
on
Register
to
goes
MPU
that
different
flag
transi-
edge
occurs
MPU
an
”one".
high
Write
input
(ORB-5)
may
When
bit
of
is
“A"
as
to
line similar
is
in
be
the
high,
used
CA2
output
characteristics
to
to
1EV°
P23
E
2
3CPA1
C
PA2 IRQB
4
PA3
5
:
I:
6
PA4
C
7
PAS
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FAG
8
c
PA7
9
1OCPBO
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11:
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P82
12
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715-02
(CERAMIC)
40 SEE PAGE 165 FOR
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37
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35
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33
32
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DIMENSIONS
715-02
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LEADSTRUE
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PLANE)
CONDITION
In
Data
Note:
j
POSITIONEO
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..,.Y.:,..,_;
165
Page
Package
MILLIMETERS
MIN
29.97 30.99 1.180
14.88
3.05
0.38
0.76
2.54
0.78
0.20
2.54
14.88
0.51
..
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