Tektronix P6960,P6962,P6964,P6980,P6982,P6960HCD,P6960HS User Manual

P6900 Series High-Density Logic Analyzer Probes

ZZZ

with D-Max™ Probing Technology

Instruction Manual

Warning

The servicing instructions ar only. To avoid personal injury, do not perform any servicing unless you are qualiﬁed to do s prior to performing service.

e for use by qualiﬁed personnel

o. Refer to all safety summaries

www.tektronix.com

P077152806*

077-1528-06

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TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

Contacting Tektronix

Tektronix, Inc. 14150 SW Karl Braun Drive P.O . B o x 5 00 Beaverto USA

For product information, sales, service, and technical support:

n, OR 97077

In North America, call 1-800-833-9200. World wide, v i sit www.tektronix.com to ﬁnd contacts in your area.

Warranty

Tektronix warrants that this product will be free from defects in materials and workmanship for a period of one (1) year from the date of shipment. If any such product proves defective during this warranty period, Tektronix, at its option, either will repair the defective product without charge for parts and labor, or will provide a replacement in exchange for the defective product. Parts, modules and replacement products used by Tektronix for warranty work may be n the property of Tektronix.

ew or reconditioned to like new performance. All replaced parts, modules and products become

In order to o the warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges p repaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country in which the Tektronix service center is located. Customer shall be responsible for paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations.

This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a) to repair damage result b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any damage or malfunction caused by the use of non-Tektronix supplies; or d) to service a product that has been modiﬁed or integrated with other products when the effect of such modiﬁcation or integration increases the time or difﬁculty of servicing the product.

THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THE PRODUCT IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

TRONIX' RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE

TEK AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE O F THE POSSIBILITY OF SUCH DAMAGES.

[W2 – 15AUG04]

btain service under this warranty, Customer must notify Tektronix of the defect before the expiration of

ing from attempts by personnel other than Tektronix representatives to install, repair or service the product;

Table of Contents

Preface ............................................................................................................... v

Related documentation......... ................................ ................................ ............... v

Environmental considerations ............................................................................... vi

Commonly us

Operating basics ................. .................................. ................................ ................. 1

Product description ... .................................. ................................ ....................... 1

Connect the probes to the logic analyzer......................................... .......................... 10

Connect the probes to the target system.................................................................... 11

Dress the probe cables........................................................................................ 19

Store th

Reference ................. ................................ .................................. ........................ 21

Probe and target system interface design information .................................................... 21

Board design .................................................................................................. 27

Probe footprint dimensions ........ .................................. ................................ ........ 35

Other design considerations ................................................................................. 36

epinoutdeﬁnition and channel assignment . ... ... . .. . ... ... . .. . ... ... ... . .. . ... ... ... . .. . ... ... . .. . . 37

Prob

Speciﬁcations ................ ................................ ................................ ...................... 53

Mechanical and electrical speciﬁcations ................................................................... 53

Maintenance........................................................................................................ 55

Probe calibration .............................................................................................. 55

Perform the functional check .......................... ................................ ...................... 55

spect and clean the probes................................................................................. 55

Service strategy ....... .................................. ................................ ...................... 56

Legacy probe and attachment support ............................ ................................ .......... 56

Repackaging instructions .......................... ................................ .......................... 57

Replaceable parts .................................................................................................. 59

Parts ordering information................................................................................... 59

Replaceable parts list ....................... ................................ .................................. 60

Index

ed terms ......... ................................ ................................ .............. vi

e probe heads................. .................................. ................................ ...... 20

P6900 Series Logic Analyzer Probes Instruction Manual i

Table of Contents

List of Figure

Figure i: Differential input amplitude ... ... . .. . ... ... . .. . ... ... . .. . ... ... . ... ... ... . ... ... . .. . ... ... . .. . ... ... . vii

Figure ii: Flying lead set......................................................................................... vii

Figure iii: Probe example. ... ... . ... ... ... . .. . ... ... . .. . ... ... ... . ... ... ... . .. . ... ... . .. . ... ... . .. . ... ... . .. . ... . viii

Figure 1: P6960 High-Density probe with D-Max probing technology............. ......................... 2

Figure 2: P6960HS High-Density probe with D-Max probing technology .................................. 3

Figure 3: P6962 High-Density probe with D-Max probing technology............. ......................... 4

Figure 4: P6964 High-Density probe with D-Max probing technology............. ......................... 6

Figure 5: P6980 High-Density Differe

Figure 6: P6982 High-Density Differential probe with D-Max probing technology .............. ......... 8

Figure 7: Connecting the probes to the logic analyzer .......... ................................ .............. 10

Figure 8: Replacing the wires on the retention posts ...................... ................................ .... 11

Figure 9: Installing the retention posts in the PCB . . .. . ... ... . .. . ... ... . .. . ... ... . .. . ... ... ... . ... ... ... . .. . .. 12

Figure 10: Soldering the retention posts in the PCB ........ ................................ .................. 13

Figure 11: Installing the alternate retention assembly ... . ... ... ... . ... ... ... . ... ... ... . ... ... ... . .. . ... ... . .. . 14

Figure 12: Proper handling of the interface clip ............................................................... 15

Figure 13: Connecting the probes to the target system............ .................................. .......... 16

Figure 14: Using the ﬂying lead set to connect to the target system................. ........................ 18

Figure 15: Proper dressing of the probe cables ................ ................................ ................ 19

Figure 16: Protecting the probe heads........................................................................... 20

Figure 17: P6960, P6960HS, P6980, and P6982 probe dimensions ......................................... 27

Figure 18: P6962 and P6964 probe dimensions................................................................ 28

Figure 19: Retention post dimensions........................................................................... 29

Figure 20: Keepout area ................ ................................ .................................. ........ 29

Figure 21: Side-by-side layout................................................................................... 30

Figure 22: End-to-end layout ........ .................................. ................................ .......... 30

Figure 23: Alternate retention assembly dimensions ................................ .......................... 30

Figure 24: Keepout

Figure 25: Side-by-side layout................................................................................... 31

Figure 26: End-to-end layout ........ .................................. ................................ .......... 32

Figure 27: Signal routing on the target system................................................................. 32

Figure 28: High-Density probe load model................... .................................. ................ 34

Figure 29: Probe footprint dimensions on the PCB............................................ ................ 35

Figure 30: Optional Via-in-pad placement recommendation ................................................. 36

Figure 31: P6960/P6960HS single-ended PCB footprint pinout detail...................................... 37

Figure 32: P6962 single-ended PCB footprint pinout detail.................................................. 39

Figure 33: P6964 single-ended PCB footprint pinout detail.................................................. 41

Figure 34: P6980 differential PCB footprint pinout detail.......... .................................. ........ 44

Figure 35: P6982 differential PCB footprint pinout detail.......... .................................. ........ 48

ntial probe with D-Max probing technology ............ ........... 7

area .................... ................................ .................................. .... 31

ii P6900 Series Logic Analyzer Probes Instruction Manual

Table of Contents

Figure 36: Repl

Figure 37: P6960 High-Density probe accessories ........ .................................. .................. 61

Figure 38: P6960HS High-Density probe accessories ........................................................ 62

Figure 39: P6962 High-Density probe accessories ........ .................................. .................. 63

Figure 40: P6964 High-Density probe accessories ........ .................................. .................. 64

Figure 41: P6980 High-Density Differential probe accessories.......... ................................ .... 65

Figure 42: P

Figure 43: Optional accessories.......................................... ................................ ........ 67

acing the cLGA clip ...................... ................................ ...................... 56

6982 High-Density Differential probe accessories.... ................................ .......... 66

P6900 Series Logic Analyzer Probes Instruction Manual iii

Table of Contents

List of Tables

Table 1: Logic analyzer clock and qualiﬁer availability . . .. . ... ... . .. . ... ... . .. . ... ... ... . ... ... ... . .. . ... ... 22

Table 2 : 2X D

Table 3: 4X Demultiplexing source-to-destination channel assignments . ... . .. . ... ... . .. . ... ... . ... ... ... . 25

Table 4: Channel assignment for P6960/P6960HS single-ended data, differential clock logic analyzer

probes ............ .................................. ................................ ............................ 37

Table 5: Channel assignment for a P6962 single-ended data, differential clock logic analyzer probe . .. 40

Table 6: Channel assignment for a P6964 single-ended data, differential clock logic analyzer probe . .. 42

Table 7: C

102-channel logic analyzer module..................... ................................ .................... 44

Table 8: Channel assignment for a P6980 differential clock and data logic analyzer probe to a 68- or

34-channel logic analyzer module .......................................................................... 46

Table 9: Channel assignment for a P6982 differential clock and data logic analyzer probe to a 136- or

102-channel logic analyzer module..................... ................................ .................... 48

10: Channel assignment for a P6982 differential clock and data logic analyzer probe to a 68- or

Table

34-channel logic analyzer module .......................................................................... 50

Table 11: Mechanical and electrical speciﬁcations .................... .................................. ...... 53

Table 12: Environmental speciﬁcations......................................................................... 54

Table 13: Parts list column descriptions .......................... .................................. ............ 60

Table 14: P6960 replaceable parts list..................................... ................................ ...... 61

le 15: P6960HS replaceable parts list..... .................................. ................................ 62

Tab

Table 16: P6962 replaceable parts list..................................... ................................ ...... 63

Table 17: P6964 replaceable parts list..................................... ................................ ...... 64

Table 18: P6980 replaceable parts list..................................... ................................ ...... 65

Table 19: P6982 replaceable parts list..................................... ................................ ...... 66

Table 20: P6900 Series Probes optional accessories........................................................... 67

emultiplexing source-to-destination c hannel assignments . ... ... . ... ... ... . ... ... . .. . ... ... . 24

hannel assignment for a P6980 differential clock and data logic analyzer probe to a 136- or

iv P6900 Series Logic Analyzer Probes Instruction Manual

Preface

Related documentation

Item Purpose

TLA Quick Start User Manuals

Online Help

Installation Reference Sheets High-level installation information

lation Manuals

Instal

XYZs of Logic Analyzers

Declassiﬁcation and Securities instructions Data security concerns speciﬁc to sanitizing

Application notes

Product Speciﬁcations & Performance Veriﬁcation Procedures

TPI.NET Documentation

Field upgrade kits

ptional Service Manuals

High-lev

In-dept

Detailed ﬁrst-time installation information

Logic a

or removing memory devices from Tektronix prod

Coll speciﬁc notes

TLA Product speciﬁcations and performance veriﬁcation procedures

Detailed information for controlling the logic an

S mainframes

el operational overview

h operation and UI help

nalyzer basics

ucts

ection of logic analyzer application

alyzer using .NET

grade information for your logic analyzer

elf-service documentation for modules and

P6900 Series Logic Analyzer Probes Instruction Manual v

Preface

Environmental considerations

This section provides information about the environmental impact of the product.

Product end-of-life

handling

Restriction of hazardous

substances

Commonly used terms

Observe the f

Equipment recycling. Production of this equipment required the extraction and use of natural resources. The equipment may contain substances that could be harmful to the environment or human health if improperly handled at the product’s end of life. In order to avoid release of such substances into the environment and to reduce t in an appropriate system that will ensure that most of the materials are reused or recycled appropriately.

This pr accessory, and is not required to comply with the substance restrictions of the recast RoHS Directive 2011/65/EU until July 22, 2017.

ollowing guidelines when recycling an instrument or component:

he use of natural resources, we encourage you to recycle this product

This symbol indicates that this product complies with the applicable European Union re on waste electrical and electronic equipment (WEEE) and batteries. For information about recycling options, check the Support/Service section of the Tekt r on

oduct is classiﬁed as an industrial monitoring and control instrument

quirements according to Directives 2002/96/EC and 2006/66/EC

ixWebsite(www.tektronix.com).

cLGA

Compression Footprint

Refer to the following list of commonly used terms throughout the manual.

cronym for compression Land Grid Array, a connector that provides an

An a electrical connection between a PCB and the probe input circuitry.

A connectorless, solderless contact between your PCB and the P6900 Series

obes. Connection is obtained by applying pressure between your PCB and

pr the p robe through a cLGA c-spring.

vi P6900 Series Logic Analyzer Probes Instruction Manual

Preface

Differential Input

Amplitude Deﬁnition

For differenti Vmin-Vmax) must be greater than or equal to 150 mV.

Figure i: Differential input amplitude

al signals, the magnitude of the difference voltage Vmax-Vmin (and

D-Max probing technology

Flying Lead Set

Trademark name that describes the technology used in the P6900 Series high-density logic analyzer probes.

A lead set designed to attach to a P6960 Probe to provide general-purpose probing capability. (See Figure ii.)

Figure ii: Flying lead set

P6900 Series Logic Analyzer Probes Instruction Manual vii

Preface

Functional Check

Procedure

Keepout Area

Module

Module End

PCB

Probe

Functional che conﬁrming that the probes recognize signal activity at the probe tips.

An area on a printed circuit board in which component, trace, and/or via placement may be restri

The unit that plugs into a mainframe that provides instrument capabilities such as logic analysis.

The end of the probe that plugs into the module unit.

An acronym for Printed Circuit Board; also known as Etched Circuit Board (ECB).

The device connects a module with a target system. (See Figure iii.)

ck procedures verify the basic functionality of the probes by

cted.

Figure iii: Probe example

obe Adapter

Probe Head

SMT KlipChip

viii P6900 Series Logic Analyzer Probes Instruction Manual

A device that connects the LA module probe to a target system.

The end of the probe that connects to the target system or probe adapter.

An interface device for attaching logic analyzer probes to components with a maximum lead diameter of 2.413 mm (0.095 in) and stackable on lead centers of 1.27 mm (0.050 in).

Operating basics

Product description

This section provides a brief description of the Tektronix P6900 Series High-Density Logic Analyzer Probes, information on attaching color-coded probe labels, and p the target system.

The P6900 Series Probes connect TLA7ACx Series Logic Analyzer modules to a target system.

The P6960, P6960HS, P6962, and P6964 probes consist of 32 single-ended channels and two (2) differential channels in one probe head.

The P6980 probe consists of 34 channels in two probe heads, with each head containing 17 differential channels.

The P6982 probe consists of 17 differential channels in one probe head.

robe and adapter connection instructions from the logic analyzer to

Probe labels

If you purchase probes for the logic analyzer module, you will need to apply the

-coded labels. You will ﬁnd instructions on how to attach the labels to the

color probes on a color reference card that is included with the probes:

0 High Density Logic Analyzer Probe Labeling and Installation

P696 Instructions

62 High Density Logic Analyzer Probe Labeling and Installation

P69 Instructions

964 High Density Logic Analyzer Probe Optimized for 4X Demultiplexing

P6 Labeling and Installation Instructions

980 High Density Differential Logic Analyzer Probe Labeling and

P6 Installation Instructions

6982 High Density Differential Logic Analyzer Optimized for 2X

P Demultiplexing Probe Labeling and Installation Instructions

P6900 Series Logic Analyzer Probes Instruction Manual 1

Operating basics

P6960 High-Density Probe

The P6960 Probe probing technology. (See Figure 2.) The probe consists of one probe head that has 34 channels (32 data and 2 clock/qual).

Figure 1: P6960 High-Density probe with D-Max probing technology

The following list details the capabilities and qualities of the P6960 Probe:

Differential or single-ended clock and qualiﬁcation inputs

is a 34-channel, high-density connectorless probe with D-Max

ingle-ended data inputs

cLGA contact eliminates the need for a built-in connector

Footprint supports direct signal pass-through

Supports PCB thickness of 1.27 mm to 6.35 mm (0.050 in to 0.250 in)

Consists of one independent probe head of 34 channels (32 data and 2 clock/quals)

Narrow 34-channel probe head makes for easier placement and layout

2X mode, (for example, 1:2 demultiplexing) uses one-half of the p robe head

4X mode, (for example, 1:4 demultiplexing) uses one-quarter of the probe head

Color-coded keyed attachment

–2.5 V to +5 V input operating range

–2.0 V to +4.5 V threshold range

300 mV minimum single-ended signal amplitude

150 mV amplitude each side minimum differential signal

Minimal loading of 0.5 pF at 20 kΩ to ground

2 P6900 Series Logic Analyzer Probes Instruction Manual

Operating basics

P6960HS High-Density

Probe

Operationinno

Any common mode voltage is acceptable so long as the maximum positive voltage does n exceed –2.5 V (clock only)

NOTE. Yo u c an ﬁnd more information about the P6960 probe routing and pinout

in the Signal Routing section. (See Figure 27 on page 32.)

The P6960HS Probe is a 34-channel, high-sensitive, high-density connectorless probe with D-Max probing technology. It has twice the voltage sensitivity compared with the standard P6960 probe. (SeeFigure2.) Theprobeconsistsofa probe head with 34 channels (32 data and 2 clock/qual).

rmal or inverted polarity is acceptable (clock only)

ot exceed +5 V and the maximum negative voltage does not

Figure 2: P6960HS High-Density probe with D-Max probing technology

The following list details the capabilities and qualities of the P6960HS Probe:

Differential or single-ended clock and qualiﬁcation inputs

Single-ended data inputs

cLGA contact eliminates the need for a built-in connector

Footprint supports direct signal pass-through

Supports PCB thickness of 1.27 mm to 6.35 mm (0.050 in to 0.250 in)

Consists of one independent probe head of 34 channels (32 data and 2 clock/quals)

Narrow 34-channel probe head makes for ea sier placement and layout

2X mode, (for example, 1 :2 demultiplexing) uses one-half of the probe head

P6900 Series Logic Analyzer Probes Instruction Manual 3

Operating basics

P6962 High-Density Probe

4X mode, (for ex head

Color-coded keyed attachment

–1.25 V to +2.5 V input operating range

–1.0 V to +2.25 V threshold range

100 mV minimum single-ended signal amplitude

50 mV amplitude each side minimum differen

Minimal loading of 0.5 pF at 20 kΩ to ground

Operation in normal or inverted polarity is acceptable (clock only)

Any common mode voltage is acceptable so long as the maximum positive voltage does not exceed +2.5 V and the maximum negative voltage does not exceed –1.25 V (clock only)

NOTE. You c an ﬁnd more information about the P6960HS probe routing and

pinout in the Signal Routing section. (See Figure 27 on page 32.)

The P6962 Probe is a 34-channel, high-density connectorless probe with D-Max probing technology. (See Figure 3.) The probe consists of one probe head that has 34 channels (32 data and 2 clock/qual), distributed over 2 module-end connectors.

ample, 1:4 demultiplexing) uses one-quarter of the probe

tial signal

Figure 3: P6962 High-Density probe with D-Max probing technology

The following list details the capabilities and qualities of the P6962 Probe:

Differential or single-ended clock and qualiﬁcation inputs

Single-ended data inputs

cLGA contact eliminates the need for a built-in connector

4 P6900 Series Logic Analyzer Probes Instruction Manual

Operating basics

Footprint supp

Supports PCB thickness of 1.27 mm to 6.35 mm (0.050 in to 0.250 in)

Consists of one independent probe head of 34 channels (32 data and 2 clock/quals)

Narrow 34-channel probe head makes for ea sier placement and layout

Optimized for 4X mode (1:4 demultiplexing) to minimize board real estate

Color-coded keyed attachment

–2.5 V to +5 V input operating range

–2.0 V to +

300 mV minimum single-ended signal amplitude

150 mV amplitude each side minimum differential signal

Minimal loading of 0.5 pF at 20 kΩ to ground

Operation in normal or inverted polarity is acceptable (clock only)

Any common mode voltage is acceptable so long as the maximum positive voltage does not exceed +5 V and the maximum negative voltage does not exceed –2.5 V (clock only)

orts direct signal pass-through

4.5 V threshold range

NOTE. Yo u c an ﬁnd more information about the P6962 probe routing and pinout

in the P6962 Single-ended Probe with D-Max probing technology section. (See

ure 32 on page 39.)

Fig

P6900 Series Logic Analyzer Probes Instruction Manual 5

Operating basics

P6964 High-Density Probe

The P6964 Probe probing technology. (See Figure 4.) The probe consists of one probe head that has 34 channels (32 data and 2 clock/qual), distributed over 4 module-end connectors.

is a 34-channel, high-density connectorless probe with D-Max

Figure 4: P6964 High-Density probe with D-Max probing technology

The following list details the capabilities and qualities of the P6964 Probe:

Differential or single-ended clock and qualiﬁcation inputs

Single-ended data inputs

cLGA contact eliminates the need for a built-in connector

Footprint supports direct signal pass-through

Supports PCB thickness of 1.27 mm to 6.35 mm (0.050 in to 0.250 in)

Consists of one independent probe head of 34 channels (32 data and 2 clock/quals)

Narrow 34-channel probe head makes for easier placement and layout

Optimized for 4X mode (1:4 demultiplexing) to minimize board real estate

Color-coded keyed attachment

–2.5 V to +5 V input operating range

–2.0 V to +4.5 V threshold range

300 mV minimum single-ended signal amplitude

150 mV amplitude each side minimum differential signal

6 P6900 Series Logic Analyzer Probes Instruction Manual

Operating basics

P6980 High-Density

Differential Probe

Minimal loadin

Operation in normal or inverted polarity is acceptable (clock only)

Any common mode voltage is acceptable so long as the maximum positive voltage does not exceed +5 V and the maximum negative voltage does not exceed –2.5

NOTE. Yo u c an ﬁnd more information about the P6964 probe routing and pinout

in the Signal Routing section. (See Figure 27 on page 32.)

The P6980 Probe is a 34-channel, high-density connectorless differential probe with D-Max probing technology. (See Figure 5.) The probe consists of two independent probe heads of 17 channels each (16 data and 1 clock/qual).

gof0.5pFat20kΩ to ground

V (clock only)

Figure 5: P6980 High-Density Differential probe with D-Max probing technology

The following list details the capabilities and qualities of the P6980 Probe:

Differential data, clock and qualiﬁcation inputs (single-ended signals may be probed if negative input is grounded)

cLGA contact eliminates the need for a built-in connector

Footprint supports direct signal pass-through

Supports PCB thickness of 1.27 mm to 6.35 mm (0.050 in to 0.250 in)

Consists of two probe heads supporting 17 channels each, for a total of 34 channels

2X mode (1:2 demultiplexing) and 4X mode (1:4 demultiplexing), use one probe head to minimize required board real estate

P6900 Series Logic Analyzer Probes Instruction Manual 7

Operating basics

P6982 High-Density

Differential Probe

Color-coded ke

–2.5 V to +5 V input operating range

–2.0 V to +4.5 V threshold range

300 mV minimum single-ended signal amplitude (5 V maximum)

150 mV each side minimum differential signal amplitude (2.5 V maximum)

Minimal loading of 0.5 pF at 20 kΩ to ground

Operation in normal or inverted polarity is acceptable

Any common mode voltage is acceptable so long as the maximum positive voltage does not exceed +5 V and the maximum negative voltage does not exceed –2.5 V

NOTE. You ca n ﬁnd more information about the P6980 probe routing and pinout

in the Signal Routing section. (See Figure 27 on page 32.)

The P6982 Probe is a 17-channel, high-density connectorless differential probe with D-Max probing technology. (See Figure 6.) The probe consists of one probe head of 17 differential channels (16 data and 1 clock/qual).

yed attachment

Figure 6: P6982 High-Density D ifferential probe with D-Max probing technology

The following list details the capabilities and qualities of the P6982 Probe:

Differential data, clock and qualiﬁcation inputs (single-ended signals may be probed if negative input is grounded)

cLGA contact eliminates the need for a built-in connector

Footprint supports direct signal pass-through

Supports PCB thickness of 1.27 mm to 6.35 mm (0.050 in to 0.250 in)

8 P6900 Series Logic Analyzer Probes Instruction Manual

Operating basics

Consists of one

Optimized for 2X mode (1:2 demultiplexing) to minimize required board real estate

Color-coded keyed attachment

–2.5 V to +5 V input operating range

–2.0 V to +4.5 V threshold range

300 mV minimum single-ended signal amplitude (5 V maximum)

150 mV each side minimum differential signal amplitude (2.5 V maximum)

Minimal l

Operation in normal or inverted polarity is acceptable

Any common mode voltage is acceptable so long as the maximum positive voltage does not exceed +5 V and the maximum negative voltage does not exceed

NOTE. Yo u c an ﬁnd more information about the P6982 probe routing and pinout

in the Signal Routing section. (See Figure 27 on page 32.)

–2.5 V

probe head supporting 17 channels

oading of 0.5 pF at 20 kΩ to ground

P6900 Series Logic Analyzer Probes Instruction Manual 9

Operating basics

Connect the pr

obes to the logic analyzer

Connect the probes to the logic analyzer according to the following steps. (See Figure 7.)

1. Identify the beveled edges of the connector inside the m odule end of the probe.

2. Align the beveled edges of the connector to its mating connector on the logic

analyzer module and press into place.

3. Use care to evenly tighten both screws on the module end of the probe until they are snug. First slightly tighten both screws, then snug each screw to 4 in-lbs (max).

NOTE. All

analyzer when it is powered on. In addition, all P6900 series Logic Analyzer probes connect to the logic analyzer in exactly the same manner.

P6900 series Logic Analyzer probes can be connected to the logic

Figure 7: Connecting the probes to the logic analyzer

10 P6900 Series Logic Analyzer Probes Instruction M anual

Operating basics

Connect the pr

obes to the tar get system

Retention posts

Use the correct retention

post wire

You can connect the P6900 Series Probes to the target system without turning off the power to the target system. The target system must have either the probe retent procedures for both methods are described here.

The retention posts are mounted on a plastic carrier for easy installation to your circuit bo thicker PCBs.

If the PCB is ≤ .120 in thick, use the wire that comes preattached to the posts. If the PCB i

The longer wires are embedded in the protective foam of the retention post kit. Make su > .120 in thick. Install the longer wires on the retention posts according to the following steps. (See Figure 8.)

1. Remove the old wire by pulling the side of the wire over the retaining tab and lifting the wire away from the post.

2. Place the new wire in the slot side without the tab, and then wrap the wire over the tab side until it engages in the slot (you will feel or hear a slight click).

ion posts or the alternate retention assembly installed. Installation

ard. Two lengths of wires are shipped with the posts to allow use with

s > .120 in thick, use the longer wire that is included with the posts.

re that you use the longer wires included in the kit when the PCB is

Figure 8: Replacing the wires on the retention posts

P6900 Series Logic Analyzer Probes Instruction Manual 11

Operating basics

Install the retention posts

To install the r

1. On the retention post/carrier assembly, locate the black retention post (the post with the k (See Figure 9.)

2. Press the re

NOTE. The following two steps – bending and soldering the wires to the circuit

board – are the two most important steps in assuring that the probe retaining posts are correctly mounted. Bending the wires before soldering them helps prevent long-term cold solder ﬂow.

3. Press down on the carrie r and bend the post wires out to anchor the posts to the PCB. Ensure the assembly is perpendicular to the PCB when bending and soldering the post w ires.

The bend point in the retaining wire should be as close to the circuit board surface as possible. Grip the wire with a pair of needle-nose pliers about 1/8-in (not the pliers) act as the fulcrum point for bending the wire. This method pulls the probe mounting posts tightly against the circuit board surface.

etention posts on the PCB, do the following:

eying pin) and align it to the keying pin hole on the PCB.

tention posts into the holes on the footprint on the PCB.

ch above the circuit board surface and let the side of the through-hole

Figure 9: Installing the retention posts in the PCB

12 P6900 Series Logic Analyzer Probes Instruction M anual

Operating basics

4. Solder the post soldered from the top or bottom of the circuit board, but it is best to solder the bottom to avoid the heat-sinking effects of the posts on top.

Figure 1

5. Pull off

NOTE. The posts may have a small amount of movement after you solder them to

the circuit board. This is normal and accounted for in the post design.

0: Soldering the retention posts in the PCB

s to the PCB. (See Figure 10 on page 13.) The posts can be

the carrier from the posts.

Clean the compression

footprints

The probe should mate ﬁrmly to the board when the two screws are tightened to the mounting posts. The screws have a mechanical stop on them to prevent overtightening the probe to the board.

After a probe has been installed and removed, there may be slightly more play in the posts. This is also normal and accounted for in the probe design.

CAUTION. To avoid electrical damage, always power off your target system before

cleaning the compression footprint.

Before you connect the probe to the target system, clean the compression footprints on the board, according to the following steps:

1. Use a lint-free, clean-room cloth lightly moistened with electronic/reagent grade isopropyl alcohol, and gently wipe the footprint surface.

2. Remove any remaining lint using a nitrogen air gun or clean, oil-free dry air.

P6900 Series Logic Analyzer Probes Instruction Manual 13

Operating basics

Alternate retention

assembly

Thealternater footprint to help stabilize the probe. Install the alternate retention assembly on the circuit board according to the following steps. (See Figure 11.)

1. Locate the correct footprint. If you intend to use multiple probes, your PCB has multiple footprints. Be careful to select the correct one.

2. Clean the compression footprint as described above.

3. Align the re

retention assembly lines up with the keying pin hole on the footprint.

4. Insert the

NOTE. The following two steps are important to ensure that the retention assembly

is correctly mounted and that the probe makes proper contact with the PCB.

5. Hold the retention assembly so that it is ﬁrmly ﬂush with the surface of the footprint, and the four anchoring posts extend through the circuit board to the opposite side.

6. Using a pair of needle-nose pliers, grasp one of the posts. Using the circuit board hole as a fulcrum, bend the post outward so that it is ﬂush with the PCB surface, anchoring the assembly to the PCB. Bend the other three posts in the same manner.

etention assembly provides a housing around the connector

tention assembly over the footprint so that the keying pin on the

retention assembly into the holes in the footprint on the PCB.

7. Solder the anchoring posts to the PCB.

Figure 11: Installing the alternate retention assembly

14 P6900 Series Logic Analyzer Probes Instruction M anual

Operating basics

Handling the cLGA

Interface Clips (probe

heads)

Always handle t following points in mind when you handle the clips:

Always handle avoid the contacts in the center. Do not touch the contacts with ﬁngers, tools, wipes, or any other devices. (See Figure 12.)

he cLGA interface clips in the probe heads with care. Keep the

the cLGA interface clips by the outer edges, being careful to

Figure 12: Proper handling of the interface clip

Do not expose the connector to liquids or dry chemicals.

If the board pad array needs to be cleaned, only use isopropyl alcohol and lint-free cloth as described above.

Immediately following cleaning, or immediately prior to placement of connector to circuit board, the board pad array and connector contact array should be blown off with clean, oil-free dry air or nitrogen to remove loose

bris. First start the blowing process by aiming away from the array areas,

de and t hen sweep across the pad and contact arrays in a repeated motion to remove loose debris.

Place the connector onto the board pad array using the bosses or locator pins for alignment. Take care to prevent incidental contact with other surfaces or edges in the connector contact array area prior to board placement.

Always store the probe head in the protective cover when not in use. (See Figure16onpage20.)

P6900 Series Logic Analyzer Probes Instruction Manual 15

Operating basics

Connect the probe

Connect the pro

1. Align the black screw on the probe to the black post on the PCB. If you are connecting th on the probe to the silver side of the retention assembly.

bes using the following steps. (See Figure 13.)

e probe to the alternate retention assembly, align the silver screw

Figure 13: Connecting the probes to the target system

2. Start both screws in the posts, and tighten them evenly to ensure that the probe approaches and mates squarely to the PCB. If access is limited, use the adjustment tool that came with your probe. The probe is completely fastened to the PCB when the screws stop in the posts.

3. Verify that all of the channels are functional. You can ﬁnd more information on any channel that appears to be nonfunctional in the following section. (See

age 17, Troubleshoot the probe connections to the DUT.)

16 P6900 Series Logic Analyzer Probes Instruction M anual

Operating basics

Troubleshoot the probe connections to the D UT

The most obviou seeing incorrect data in the logic analyzer acquisition. However, the nature of the incorrect data has a very consistent characteristic; the data from multiple channels go to a logic low and stay there. Intermittent bad data, or a single dead channel are not failures typically associated with probe mounting post installation problems.

1. Slightly move the probe head to either side, or press down on the probe head while making new acquisitions. If good data is now being acquired, then the probe mounting is most likely the cause.

2. If good data is not acquired, then remove the probe and check the posts for too much play. If there is signiﬁcant play, then the probe mounting is most likely th

3. If the posts have minimal play and you cannot see a gap between the bottom of the po from one logic analyzer probe location to another.

4. If the p inspect the cLGA interface clip on the probe for any damage or missing c-spring metal contacts.

If there is damage to the interface clip, or if any c-spring metal contacts are missing, replace the cLGA interface clip. (See page 56, Replace the cLGA Clip.)

s symptom of a problem with the mounting post installation is

ecause.

sts and the circuit board surface, then move the probe with bad data

roblem follows the probe, then the probe is the problem. Visually

5. If the problem does not follow the probe, it is either the logic analyzer or the probe connection at its previous location. Move the probe back to the original location to be certain that it was not a connection problem at the logic analyzer end.

6. Place another probe in the mounting posts of the original probe. If the new probe acquires data, then the old probe is probably at fault.

P6900 Series Logic Analyzer Probes Instruction Manual 17

Operating basics

Connect the ﬂying lead set

The ﬂying lead s foryourprobe. Theﬂying lead set allows you to connect to individual test points on your PCB. However, for general-purpose probing, the P6810 probe is recommended for best performance.

Connect the probe to the target system by performing the steps that follow. (See Figure 14.) You can connect the probe leads to the target system without turning off the power to the target system.

1. Connect the probe leads to the s quare pins on the PCB.

2. Connect the negative input to ground on the PCB.

3. Connect the leadset to the probe.

et, Tektronix part number 196-3494-xx, is an optional accessory

Figure 14: Using the ﬂying lead set to connect to the target system

18 P6900 Series Logic Analyzer Probes Instruction M anual

Dress the probe cables

Operating basics

Use the Velcro cable managers to combine the cables together or to help relieve strain on the probe connections.

Hang the probe cables so that you relieve the tension on the probes at the retention posts. (See Figure 15.)

Figure 15: Proper dressing of the probe cables

P6900 Series Logic Analyzer Probes Instruction Manual 19

Operating basics

Store the prob

eheads

To protect the interface clip, it is important to properly store the probe heads when the probes are not in use. (See Figure 16.)

Gently slide the probe cover over the probe end and store the probe.

Figure 16: Protecting the probe heads

20 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

This section provides reference information for the P6900 Series High-Density Probes with D-Max probing technology.

Probe and target system interface design information

Once you have determined which probe is required, use the following information to design t topics are in this section:

he appropriate connector into your target system board. The following

Signal ﬁxturing

considerations

Signal ﬁx

Signal connections (signal names and footprints)

Mechanical considerations

Electrical considerations

This section contains the following information to consider for signal ﬁxturing:

Clocks

Merged modules and source sync hronous clocking

Demultiplexing multiplexed buses

2X and 4X high resolution timing modes (Internal 2X and 4X)

Probing analog signals

Range recognition

Clocks and qualiﬁers. Every logic analyzer has some special purpose input channels. Inputs designated as clocks can cause the analyzer to store data. Qualiﬁer channels can be logically ANDed and ORed with clocks to further deﬁne

hen the analyzer should latch data from the system under test. Routing the

w appropriate signals from your design to these inputs ensures that the logic analyzer can acquire data correctly. Unused clocks can be used as qualiﬁer signals.

turing considerations

and qualiﬁers

Depending on the channel width, each TLA7ACx Series logic analyzer module will have a different set of clock and qualiﬁer channels. The following table shows the clock and qualiﬁer channel availability for each module. (See Table 1 on page 22.)

P6900 Series Logic Analyzer Probes Instruction Manual 21

Reference

Table 1: Logic a

TLA7ACx Module Clock Inputs Qualiﬁer Inputs

TLA7AC2

TLA7AC3

TLA7AC4

nalyzer clock and qualiﬁer availability

CLK:0 CLK:1 CLK:2 CLK:3 QUAL:0 QUAL:1 QUAL:2 QUAL:3

All clock and qualiﬁer channels are stored. The analyzer always stores the logic state of these channels every time it latches data.

Since clock and qualiﬁer channels are stored in the analyzer memory, there is no need to double probe these signals for timing analysis. When switching from state to timing analysis modes, all of the clock and qualiﬁer signals will be visible. This allows you to route signals not needed for clocking to the unused clock and quali

ﬁer channels.

It is a good practice to take advantage of the unused clock and qualiﬁer channels to incre

ase your options for when you will latch data. Routing several clocks and strobes in your design to the analyzer clock inputs will provide you with a greater ﬂexibility in the logic analyzer clocking setup menus.

As an example, look at a microprocessor w ith a master clock, data strobe, and an address strobe. Routing all three of these signals to analyzer clock inputs will enable you to latch data on the processor master clock, only when data is strobed, or only when address is strobed. Some forethought in signal routing can greatly expand the ways in which you can latch and analyze data.

A microprocessor also provides a good example of signals that can be useful as qualiﬁers. There are often signals that indicate data reads versus data writes

W), signals that show when alternate bus masters have control of the processor

(R/ buses (DMA), and signals that show when various memory devices are being used (ChipSel). All of these signals are good candidates for assignment to qualiﬁer channels.

By logically ANDing the clock with one of these qualiﬁers you can program the analyzer to store only data reads or data writes. Using the DMA signal as a qualiﬁer provides a means of ﬁltering out alternate bus master cycles. Chip selects can limit data latching to speciﬁc memory banks, I/O ports, or peripheral devices.

Merged module sets and source synchronous clocking. TLA7ACx analyzer modules that are 102-channels or 136-channels wide can be merged together to act as a single logic analyzer with a larger channel count. Up to ﬁve modules can be merged to provide up to a 680-channel analyzer. A unique feature of the TLA7ACx module is that it supports source synchronous clocking. Combining these two capabilities provide some additional considerations for signal routing.

22 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Source sync hro system clock and the data bus by requiring the sending device to drive an actual clock or strobe signal along with the data that is very tightly coupled with it in terms of skew. The receiving device then uses this strobe to capture the data.

A variant of this scheme is being applied to large microprocessor buses, where the bus is split into smaller, more easily managed groups that each have their own dedicated strobe. Although the timing relationship between a particular clock and its associated data group is very tight, the timing between the different groups can vary great

Many source synchronous designs use wide buses. It is not uncommon to require asetofme probing larger source synchronous systems. While all of the modules in a merged set can use their clock inputs independently if needed, remember that there are a maximum of four clock inputs on a 136-channel wide module.

To see the importance of this we will once again use a microprocessor system as an example. Tektronix logic analyzer processor has a 32-bit address bus and a 64-bit data bus. The data bus is split into four 16-bit subgroups that have independent source synchronous clocks. For the logic analyzer to correctly

re data from this system it will need ﬁve clock inputs, one for the address

acqui bus and one each for the four 16 –bit data bus subgroups.

quire both buses, the analyzer would need at least 96 channels (32 address

To ac and 64 data). However, a single 102 channel card does not have the required ﬁve clock inputs. By merging two 102-channel modules into a set you can obtain the needed number of clock inputs. Route the address bus to one module in the set and route the data bus, along with its four source synchronous clocks, to the second module in the set.

nous clocking is a method that manages the skew between the

ly and changes depending on which device has control of the bus.

rged logic analyzer modules to provide the channel count needed in

P6900 Series Logic Analyzer Probes Instruction Manual 23

Reference

Demultiplexin

g multiplexed buses. TLA7ACx modules support both 2X and 4X

demultiplexing. TLA7NAx modules support 2X demultiplexing. Each signal on a dual or quad multiplexed bus can be demultiplexed into its own logic analyzer channel. Refer to the following tables to determine the correct channel groups to use.

Table 2: 2X Demultiplexing source-to-destination channel assignments

Destination channels receiving target system test data

TLA7AC4/

Source

A3:7-0 D3:7-0 D3:7-0

A2:7-0 D2:7-0 D2:7-0

A1:7-0 D1:7-0 D1:7-0 D1:7-0

A0:7-0 D0:7-0 D0:7-0 D0:7-0

C3:7-0 C1:7-0 C1:7-0

C2:7-0 C0:7-0 C0:7-0

E3:7-0 E1:7-0

E2:7-0 E0:7-0

CLK:0 QUAL:1 QUAL:1

CLK:1 QUAL:0 QUAL:0

CLK:2 QUAL:3

CLK:3 QUAL:2

TLA7NA4

TLA7AC3/ TLA7NA3

———

TLA7AC2 /TLA7NA2

C3:7-0 C3:7-0

C2:7-0 C2:7-0

——

TLA7AA1/ TLA7NA1 TLA7AB4 TLA7AB2

—

D3:7-0

D2:7-0

D1:7-0 D1:7-0

D0:7-0 D0:7-0

C1:7-0

C0:7-0

E1:7-0

E0:7-0

QUAL:1

QUAL:0

QUAL:3

QUAL:2

C3:7-0

C2:7-0

—

24 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Table 3: 4X Demu

Source TLA7AA4 TLA7AA3 TLA7AA2 TLA7AA1 TLA7AB4 TLA7AB2

C3:7-0 C2:7-0

A1:7-0 A0:7-0

A3:7-0 A2:7-0

E3:7-0 E2:7-0

CLK:3 CLK:2

CLK:1 CLK:0

ltiplexing source-to-destination channel assignments

Destination c

C1:7-0 C0:7-0

D1:7-0 D0:7-0

D3:7-0 D2:7-0

E1:7-0 E0:7-0

QUAL:3 QUAL:2

QUAL:1 QUAL:0

hannels receiving target system test data

C2:7-0 C1:7-0 C0:7-0

A0:7-0 D1:7-0 D0:7-0

A2:7-0 D3:7-0 D2:7-0

———

CLK:0 QUAL:1 QUAL:0

A3:7-0 A2:7-0 C2:7-0

A0:7-0 D1:7-0 D0:7-0

——

A3:7-0 A2:7-0 C2:7-0

—

C2:7-0 C1:7-0 C0:7-0

A0:7-0 D1:7-0 D0:7-0

A2:7-0 D3:7-0 D2:7-0

E2:7-0 E1:7-0 E0:7-0

CLK:2 QUAL:3 QUAL:2

CLK:0 QUAL:1 QUAL:0

A3:7-0 A2:7-0 C2:7-0

A0:7-0 D1:7-0 D0:7-0

—

When demultiplexing data there is no need to connect the destination channels to the mu

ltiplexed bus. Data from the source channels are routed to the destination channels internal to the logic analyzer. You can ﬁnd more information about the mapping of source channels to destination channels in the Demultiplexing Multiplexed Buses section. (See page 24.)

Demultiplexing affects only the main memory for the destination channels. This means that the MagniVu memory is ﬁlled with data from whatever is connected to the demultiplexing destination channel probe inputs. This provides an opportunity to acquire high resolution MagniVu data on a few extra channels. Connecting the

ultiplexing destination channels to other signals will allow viewing of their

dem activity in the MagniVu memory but not the main memory.

2X and 4X high resolution timing modes. The 2X high resolution timing mode provides double the normal 500 MHz sample rate on one-half of the channels. By trading half of the analyzer's channels, the remaining channels can be sampled

t a 1 GHz rate with double the memory depth. Likewise, 4X high resolution

a timing mode provides quadruple the normal 500 MHz sample rate on one-fourth of the channels. By trading three-fourths of the analyzer's channels, the remaining channels can be sampled at a 2 GHz rate with quadruple the memory depth.

P6900 Series Logic Analyzer Probes Instruction Manual 25

Reference

Both of the high routing. (See Table 2.) (See Table 3.) By taking care to assign critical signals to the demultiplexing source channels, you can o btain extra timing resolution where it is most needed. Since demultiplexing affects only the main memory you will still have the MagniVu data available for all of the signals that are disconnected from the main memory when you switch to the high resolution timing m odes.

Analog signals probing. The TLA7ACx module provides visibility of analog signals with Analog mux. Analog mux routes the actual signal seen by each channel's probe through a high bandwidth path to an analog multiplexer inside of the logic analyzer module. From the logic analyzer interface, you can route any input channel to one of four output connectors on the m odule. By connecting the analy characteristics of any signal probed by the logic analyzer.

Sometim Signals such as A/D Converter inputs, D/A Converter outputs, low voltage power supplies, termination voltages, and oscillator outputs are just a few examples. Routing these signals to unused logic analyzer inputs provides a quick method of viewing their activity without ever picking up an oscilloscope probe.

Take care to ensure that such signals are voltage limited and will not exceed the maximum nondestructive input voltage for the logic analyzer probes of ±15 Vpeak.

zer analog outputs to your oscilloscope, you can see the analog

es it is convenient to have analog signals accessible for easier probing.

resolution timing modes use the same demultiplexing channel

Range recognition. When using range recognizers, the probe groups and probe channels must be in hardware order. Probe groups must be used from the most-signiﬁcant probe group to the least-signiﬁcant probe group based on the following order:

C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 CK1 CK0

Probe channels must be from the most-signiﬁcant channel to the least-signiﬁcant channel based on the following order:

76543210

The above examples assumes a 136-channel LA module. The missing channels in LA modules with fewer than 136 channels are ignored. With merged modules, range recognition extends across the ﬁrst three modules: the master module contains the most-signiﬁcant channels.

26 P6900 Series Logic Analyzer Probes Instruction M anual

Board design

Reference

This section provides information that helps you design your PCB mechanically and electrically for use with the P6900 Series Probes.

Probe dimensions

The following ﬁgures show the dimensions for the P6960, P6960HS, P6980, and P6982 probes.

Figure 17: P6960, P6960HS, P6980, and P6982 probe dimensions

P6900 Series Logic Analyzer Probes Instruction Manual 27

Reference

Figure 18: P6962 and P6964 probe dimensions

28 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Retention post dimensions

and keepout area

You can attach t Figure 19.) You can alternately attach the probes to the PC board retention assembly. (See Figure 23 on page 30.)

Both mounting methods hold the probe securely to the board, and ensure a reliable electrical and mechanical connection and pin-to-pad alignment to your design. Board thicknesses that are supported include 1.27 mm (0.050 in) to 6.35 mm (0.250 in). The dimensions of the retention posts are shown in the following ﬁgure. (See Figure 19.)

All dimensions are per standard IPC tolerance, which is ±0.004 in.

CAUTION. To avoid solder creep, bend the post wires out after you insert the posts

in the boa from the top or bottom of the circuit board.

he probes to the PC board using two retention posts. (See

rd, and then solder the post wires. You can solder the retention wires

Figure 19: Retention post dimensions

The following ﬁgure shows the keepout area required for the retention posts. (See Figure 20.) Vias must be placed outside of the keepout area. Any traces routed on the top layer of the board must stay outside of the keepout area. Traces may be

ted on inner layers of the board through the keepout area.

rou

Figure 20: Keepout area

P6900 Series Logic Analyzer Probes Instruction Manual 29

Reference

Side-by-side and

end-to-end layout

dimensions

The following ﬁ (See Figure 21.)

Figure 21: Side-by-side layout

The following ﬁgure shows the dimensions for an end-to-end footprint layout. (See Figure 22.)

gure shows the dimensions for side-by-side footprint layout.

Figure 22: End-to-end layout

Alternate retention

assembly dimensions

and keepout area

The alternate retention assembly provides a housing around the connector footprint to help stabilize the probe. The following ﬁgure shows the dimensions of the assembly. (See Figure 23.)

All dimensions are per standard IPC tolerance, which is ±0.004 in.

CAUTION. To avoid solder creep, bend the assembly wires out after you insert the

wires in the board, and then solder the wires.

Figure 23: Alternate retention assembly dimensions

30 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

The following ﬁ assembly. (See Figure 24.)

Figure 24: Keepout area

NOTE. Tektronix has provided a 3D CAD solid model ﬁle (named

dmax_socket_assembly.stp) for the plastic retention assembly. It also includes footpri To access the attached ﬁle, open the PDF ﬁleandclickonthepaperclipiconon theleftsideofthedocumentviewer.

nt information for your circuit board. The ﬁle is attached to this PDF ﬁle.

gure shows the keepout area required for the alternate retention

Side-by-side and

Eend-to-end layout

dimensions

The following ﬁgure shows the dimensions for side-by-side footprint layout. (See Figure 25.)

Figure 25: Side-by-side layout

The following ﬁgure shows the dimensions for an end-to-end footprint layout. (See Figure 26.)

P6900 Series Logic Analyzer Probes Instruction Manual 31

Reference

Figure 26: End-to-end layout

Signal routing

The following ﬁgure shows examples of pass-through signal routing for a single-ended data conﬁguration and a differential data conﬁguration. (See Figure 27

Figure 27: Signal routing on the target system

s section provides information on c ompression footprint requirements and

Mechanical considerations

32 P6900 Series Logic Analyzer Probes Instruction M anual

Thi physical attachment requirements.

e PCB holes, in general, do not have an impact upon the integrity of your

Th signals when the signals routed around the holes have the corresponding return current plane immediately below the signal trace for the entire signal path from driver to receiver.

NOTE. For optimum signal integrity, there should be a continuous, uninterrupted

ground return plane along the entire signal path.

Reference

Electrical considerations

Physical attac

Series Probe interconnects are designed to accommodate PCB thickness ranging from1.27mmto6.35mm(0.050into0.250in). Toaccommodatethisrange, there are two wire lengths in the design:

For board thicknesses of 0.050 in to 0.120 in, use the standard wire that comes mounted to the post in the retention kit included with each probe.

For board thicknesses of 0.120 in to 0.250 in, use the long wire supplied w ith the probe (also included in the retention kit, embedded in foam).

(See page 11, Use the correct retention post wires.)

This sect P6900 Series Probes.

The lowor slower in a typical 25 Ω source impedance environment (50 Ω runs with a pass-through connection). For source impedance outside this range, and/or rise and fall times faster than 1 ns, use the high-frequency model to determine if a signiﬁcant difference is obtained in the modeling result.

The compression land pattern pad is not part of the load model. Make sure that you include the compression land pad in the modeling.

hment requirements for the P6900 Series Probes. The P6900

ion provides information on transmission lines and load models for the

frequency model is typically adequate for rise and fall times of 1 ns

smission lines. Due to the high performance nature of the interconnect,

Tran

ensure that stubs, which are greater than 1/4 length of the signal rise time, are modeled as transmission lines.

P6900 Series probes load model. The following electrical model includes a low-frequency and high-frequency model of the High-Density Single-Ended and

gh-Density Differential Probes. (See Figure 28.) For the Differential Probes,

Hi the load model is applied to both the + side and the – side of the signal.

P6900 Series Logic Analyzer Probes Instruction Manual 33

Reference

Figure 28: High-Density probe load model

The differential load for the P6960 and P6964 clock inputs and the P6980 and P6982 probes can be modeled by attaching the single line model to each side (+ and –) of the differential signal. The + and – sides of the differential signal are well insulated in the probe head up to and including the differential input stage.

34 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Probe footpri

nt dimensions

Use the probe footprint dimensions in the following ﬁgure to lay out your circuit board pads and holes for attaching the retention posts. If you are using the alternate re except the overall length and width.(SeeFigure23onpage30.)Padﬁnishes that are supported include immersion gold, immersion silver, and hot air solder level.

All dimensions are per standard IPC tolerance, which is ±0.004 in.

NOTE. Tektronix recommends using immersion gold surface ﬁnish for best

performance.

Tektronix also recommends that the probe attachment holes ﬂoat or remain unconnected to a ground plane. This prevents overheating the ground plane and promotes quicker soldering of the retention posts to your PCB. The probe retention posts are designed to allow you to solder the retention posts from either side of

tention assembly, all dimensions remain the same as shown below,

your PCB.

Figure 29: Probe footprint dimensions on the PCB

NOTE. You must maintain a solder mask web between the pads when traces are

routed between pads on the same layer. The solder mask must not encroach onto the pads within the pad dimensions. (See Figure 20 on page 29.)

P6900 Series Logic Analyzer Probes Instruction Manual 35

Reference

Other design c

Via-in-pad

onsiderations

Traditional layout techniques require vias to be located next to a pad and a signal routed to the pad, causing a stub and more PCB b oard area to be used for the connection. effects of the logic analyzer probing that you design into the circuit board.

Using viaminimize the stub length of the signals on your board, thus providing the smallest intrusion to your signals. It also enables you to minimize the board area that is used for the probe footprint and maintain the best electrical performance of your design.

The following ﬁgure shows a footprint example where two pads use vias. (See Figure 30.) Detail A describes the recommended position of the via with respect to the pad.

All dimensions are per standard IPC tolerance, which is ±0.004 in.

Many new digital designs require you to minimize the electrical

in-pad to route signals to the pads on the circuit board allows you to

Figure 30: Optional Via-in-pad placement recommendation

36 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Probe pinout d

eﬁnition and channel assignment

This section contains probe pinout deﬁnitions and channel assignment tables for the P6900 Series Probes.

P6960/P6960HS

Single-ended probes with

D-Max probing technology

The following ﬁgure shows the pad assignments, pad numbers, and signal names for the PCB footprint of the P6960/P6960HS single-ended data, differential clock logic analyzer probes. (See Figure 31.) The P6960/P6960HS probes have 32 data channels, one clock, and one qualiﬁer for each footprint.

Figure 31: P6960/P6960HS single-ended PCB footprint pinout detail

The listing of channel mapping to a logic analyzer module for P6960/P6960HS single-ended data, differential clock logic analyzer probes is as follows. (See Table 4.)

Table 4: Channel assignment for P6960/P6960HS single-ended data, differential c lock logic analyzer probes

136-channel module

Land pattern

Pin number

A1 D0 E2:0 A2:0 A0:0

A2 D1 E2:1 A2:1 A0:1

A4 D4 E2:4 A2:4 A0:4

A5 D5 E2:5 A2:5 A0:5

A10 D10 E3:2 A3:2 A1:2

A11 D11 E3:3 A3:3 A1:3

A12

A13 D14 E3:6 A3:6 A1:6

A14 D15 E3:7 A3:7 A1:7

A15

A16 D18 E1:5 D3:5 D1:5

Signal name Probe 4 Probe 3 Probe2 Probe1 Probe2 Probe1

GND GND GND GND GND GND GND

CK1+ Q3+ CK0+ CK1+ CK3+ CK1+ CK3+

CK1– Q3– CK0– CK1– CK3– CK1– CK3–

GND GND GND GND GND GND GND

only 136- and 102-channel modules

C2:0

C2:1

C2:4

C2:5

C3:2

C3:3

C3:6

C3:7

C1:5

68-channel module only

A0:0

A0:1

A0:4

A0:5

A1:2

A1:3

A1:6

A1:7

D1:5 A3:5

68- and 34-channel modules

C2:0

C2:1

C2:4

C2:5

C3:2

C3:3

C3:6

C3:7

P6900 Series Logic Analyzer Probes Instruction Manual 37

Reference

Table 4: Channel assignment for P6960/P6960HS single-ended data, differential clock logic analyzer probes (cont.)

136-channel module

Land pattern

Pin number

A17 D19 E1:4 D3:4 D1:4

A18

A19 D22 E1:1 D3:1 D1:1

A20 D23 E1:0 D3:0 D1:0

A21

A22 D24 E0:7 D2:7 D0:7

A23 D25 E0:6 D2:6 D0:6

A24

A25 D28 E0:3 D2:3 D0:3

A26 D29 E0:2 D2:2 D0:2

A27

B2 D2 E2:2 A2:2 A0:2

B3 D3 E2:3 A2:3 A0:3

B5 D6 E2:6 A2:6 A0:6

B6 D7 E2:7 A2:7 A0:7

B8 D8 E3:0 A3:0 A1:0

B9 D9 E3:1 A3:1 A1:1

B10

B11 D12 E3:4 A3:4 A1:4

B12 D13 E3:5 A3:5 A1:5

B13

B14 D16 E1:7 D3:7 D1:7

B15 D17 E1:6 D3:6 D1:6

B16

B17 D20 E1:3 D3:3 D1:3

B18 D21 E1:2 D3:2 D1:2

B19

B20

B21

B22

Signal name Probe 4 Probe 3 Probe 2 Probe 1 Probe 2 Probe 1

GND GND GND GND GND GND GND

CK2- Q2- Q0- CK2- Q1- CK2- CK0-

CK2+ Q2+ Q0+ CK2+ Q1+ C K2+ CK0+

GND GND GND GND GND GND GND

only 136- and 102-channel modules

C1:4

C1:1

C1:0

C0:7

C0:6

C0:3

C0:2

C2:2

C2:3

C2:6

C2:7

C3:0

C3:1

C3:4

C3:5

C1:7

C1:6

C1:3

C1:2

68-channel module only

D1:4 A3:4

D1:1 A3:1

D1:0 A3:0

D0:7 A2:7

D0:6 A2:6

D0:3 A2:3

D0:2 A2:2

A0:2

A0:3

A0:6

A0:7

A1:0

A1:1

A1:4

A1:5

D1:7 A3:7

D1:6 A3:6

D1:3 A3:3

D1:2 A3:2

68- and 34-channel modules

C2:2

C2:3

C2:6

C2:7

C3:0

C3:1

C3:4

C3:5

38 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Table 4: Channel assignment for P6960/P6 960HS single-ended data, differential clock logic analyzer probes (cont.)

136-channel module

Land pattern

Pin number

B23 D26 E0:5 D2:5 D0:5

B24 D27 E0:4 D2:4 D0:4

B25

B26 D30 E0:1 D2:1 D0:1

B27 D31 E0:0 D2:0 D0:0

P6962 s

Signal name Probe 4 Probe 3 Probe2 Probe1 Probe2 Probe1

GND GND GND GND GND GND GND

ingle-ended probe

with D-Max probing

technology

only 136- and 102-channel modules

The following ﬁgure shows the pad assignments, pad numbers, and signal names for the PCB footprint of the P6962 single-ended data, differential clock logic analyzer probe. (See Figure 31.) The P6962 probe has 32 data channels and

locks for each footprint.

two c

C0:5

C0:4

C0:1

C0:0

68-channel module only

D0:5 A2:5

D0:4 A2:4

D0:1 A2:1

D0:0 A2:0

68- and 34-channel modules

Figure 32: P6962 single-ended PCB footprint pinout detail

P6900 Series Logic Analyzer Probes Instruction Manual 39

Reference

The following t

able lists the channel mapping to a logic analyzer module for a

P6962 single-ended data, differential clock logic analyzer probe.

Table 5: Channel assignment for a P6962 single-ended data, differential clock logic analyzer probe

Pin number

A10

A11

A12

A13

A14

A15

A16 E3:5 A1:5

A18

A19 E3:1 A1:1

A20 E3:0 A1:0

A21

A22 E2:7 A0:7

A23 E2:6 A0:6

A24

A25 E2:3 A0:3

A26 E2:2 A0:2

A27

C and E group probe

C2:0

C2:1

GND GND

C2:4

C2:5

GND GND

CK+ CK+

CK- CK-

GND GND

C3:2

C3:3

GND GND

C3:6

C3:7

GND GND

3:4

GND GND

C2:2

C2:3

GND GND

C2:6

C2:7

GND GND

A0-A3 group probe

A2:0

A2:1

A2:4

A2:5

A3:2

A3:3

A3:6

A3:7

1:4

A2:2

A2:3

A2:6

A2:7

40 P6900 Series Logic Analyzer Probes Instruction M anual

Table 5: Channel assignment for a P6962 single-ended data, differential clock logic analyzer probe (cont.)

Reference

Pin number

B10

B11

B12

B13

B14 E3:7 A1:7

B15 E3:6 A1:6

B16

B17 E3:3 A1:3

B18 E3:2 A1:2

B19

B20

B21

B22

B23 E2:5 A0:5

B24 E2:4 A0:4

B25

B26 E2:1 A0:1

B27 E2:0 A0:0

C and E group probe

C3:0

C3:1

GND GND

C3:4

C3:5

GND GND

CK- CK-

CK+ CK+

GND GND

A0-A3 group probe

A3:0

A3:1

A3:4

A3:5

P6964 single-ended probe

with D-Max probing

technology

The following ﬁgure shows the pad assignments, pad numbers, and signal names for the PCB footprint of the P6964 single-ended data, differential clock logic analyzer probe. (See Figure 33.) The P6964 probe has 32 data channels and two clocks for each footprint.

Figure 33: P6964 single-ended PCB footprint pinout detail

P6900 Series Logic Analyzer Probes Instruction Manual 41

Reference

The following t

able lists the channel mapping to a logic analyzer module for a

P6964 single-ended data, differential clock logic analyzer probe.

Table 6: Channel assignment for a P6964 single-ended data, differential clock logic analyzer probe

Pin number Signal name 136 Channel

A1 D0

A2 D1

A4 D2

A5 D3

A10 D4

A11 D5

A12

A13 D6

A14 D7

A15

A16 D8 A3:7

A18

A19 D10 A3:5

A20 D11 A3:4

A21

A22 D12 A3:3

A23 D13 A3:2

A24

A25 D14 A3:1

A26 D15 A3:0

A27

B2 D16 E3:0

B3 D17 E3:1

B5 D18 E3:2

B6 D19 E3:3

GND GND

CK1+ CK3+

CK1- CK3-

GND GND

C3:7

C3:6

C3:5

C3:4

C3:3

C3:2

C3:1

C3:0

3:6

42 P6900 Series Logic Analyzer Probes Instruction M anual

Table 6: Channel assignment for a P6964 single-ended data, differential clock logic analyzer probe (cont.)

Pin number Signal name 136 Channel

B8 D20 E3:4

B9 D21 E3:5

B10

B11 D22 E3:6

B12 D23 E3:7

B13

B14 D24 A1:0

B15 D25 A1:1

B16

B17 D26 A1:2

B18 D27 A1:3

B19

B20

B21

B22

B23 D28 A1:4

B24 D29 A1:5

B25

B26 D30 A1:6

B27 D31 A1:7

GND GND

CK2- CK1-

CK2+ CK1+

GND GND

Reference

P6900 Series Logic Analyzer Probes Instruction Manual 43

Reference

P6980 differential probe

with D-Max probing

technology

The following ﬁ for the PCB footprint of the P6980 differential data and clock logic analyzer probe. (See Figure 34.) The P6980 probe has 16 data c hannels, and one clock or qualiﬁer

gure shows the pad assignments, pad numbers, and signal names

for each footprint. There are two footprints associated with one P6980 probe.

Figure 34: P6980 differential PCB footprint pinout detail

The following table lists the channel mapping to a 136 channel or 102 channel logic analyzer module for the P6980 differential data and clock logic analyzer probe.

Table 7: Channel assignment for a P6980 differential clock and data logic analyzer probe to a 136- or 102-channel logic analyzer module

136-channel module only 136- and 102-channel modules

Land pattern Probe 4 Probe 3 Probe 2 Probe 1

Pin number

A1 D0+ E2:0+ E0:0+ A2:0+ D2:0+ A0:0+ D0:0+

A2 D0- E2:0- E0:0- A2:0- D2:0- A0:0- D0:0-

A4 D2+ E2:2+ E0:2+ A2:2+ D2:2+ A0:2+ D0:2+

A5 D2- E2:2- E0:2- A2:2- D2:2- A0:2- D0:2-

A7 D4+ E2:4+ E0:4+ A2:4+ D2:4+ A0:4+ D0:4+

A8 D4- E2:4- E0:4- A2:4- D2:4- A0:4- D0:4-

A10 D6+ E2:6+ E0:6+ A2:6+ D2:6+ A0:6+ D0:6+

A11 D6- E2:6- E0:6- A2:6- D2:6- A0:6- D0:6-

A12

A13

A14

A15

A16 D8+ E3:0+ E1:0+ A3:0+ D3:0+ A1:0+ D1:0+

A17 D8- E3:0- E1:0- A3:0- D3:0- A1:0- D1:0-

A18

A19 D10+ E3:2+ E1:2+ A3:2+ D3:2+ A1:2+ D1:2+

Signal name Head1 Head2 Head1 Head2 Head1 Head2 Head1 Head2

C2:0+ C0:0+

C2:0- C0:0-

GND GND GND GND GND GND GND GND GND

C2:2+ C0:2+

C2:2- C0:2-

GND GND GND GND GND GND GND GND GND

C2:4+ C0:4+

C2:4- C0:4-

GND GND GND GND GND GND GND GND GND

C2:6+ C0:6+

C2:6- C0:6-

GND GND GND GND GND GND GND GND GND

NC NC NC NC NC NC

GND GND GND GND GND GND GND GND GND

NC NC

C3:0+ C1:0+

C3:0- C1:0-

C3:2+ C1:2+

44 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Table 7: Channel assignment for a P6980 differential clock and data logic analyzer probe to a 136- or 102-channel logic analyzer modu

Land pattern Probe 4 Probe 3 Probe 2 Probe 1

Pin number

A20 D10- E3:2- E1:2- A3:2- D3:2- A1:2- D1:2-

A21

A22 D12+ E3:4+ E1:4+ A3:4+ D3:4+ A1:4+ D1:4+

A23 D12- E3:4- E1:4- A3:4- D3:4- A1:4- D1:4-

A24

A25 D14+ E3:6+ E1:6+ A3:6+ D3:6+ A1:6+ D1:6+

A26 D14- E3:6- E1:6- A3:6- D3:6- A1:6- D1:6-

A27

B2 D1- E2:1- E0:1- A2:1- D2:1- A0:1- D0:1-

B3 D1+ E2:1+ E0:1+ A2:1+ D2:1+ A0:1+ D0:1+

B5 D3- E2:3- E0:3- A2:3- D2:3- A0:3- D0:3-

B6 D3+ E2:3+ E0:3+ A2:3+ D2:3+ A0:3+ D0:3+

B8 D5- E2:5- E0:5- A2:5- D2:5- A0:5- D0:5-

B9 D5+ E2:5+ E0:5+ A2:5+ D2:5+ A0:5+ D0:5+

B10

B11 D7- E2:7- E0:7- A2:7- D2:7- A0:7- D0:7-

B12 D7+ E2:7+ E0:7+ A2:7+ D2:7+ A0:7+ D0:7+

B13

B14

B15

B16

B17 D9- E3:1- E1:1- A3:1- D3:1- A1:1- D1:1-

B18 D9+ E3:1+ E1:1+ A3:1+ D3:1+ A1:1+ D1:1+

B19

B20 D11- E3:3- E1:3- A3:3- D3:3- A1:3- D1:3-

B21 D11+ E3:3+ E1:3+ A3:3+ D3:3+ A1:3+ D1:3+

B22

B23 D13- E3:5- E1:5- A3:5- D3:5- A1:5- D1:5-

B24 D13+ E3:5+ E1:5+ A3:5+ D3:5+ A1:5+ D1:5+

le (cont.)

136-channel module only 136- and 102

Signal name Head1 Head2 Head1 Head2 Head1 Head2 Head1 Head2

GND GND GND GND GND GND GND GND GND

CK- Q3- Q2- C K0- Q0- CK1- CK2- CK3- Q1-

CK+ Q3+ Q2+ CK0+ Q0+ CK1+ CK2+ CK3+ Q1+

GND GND GND GND GND GND GND GND GND

-channel modules

C3:2- C1:2-

C3:4+ C1:4+

C3:4- C1:4-

C3:6+ C1:6+

C3:6- C1:6-

C2:

2:3-

2:3+

C2:5- C0:5-

C2:5+ C0:5+

C2:7- C0:7-

C2:7+ C0:7+

C3:1- C1:1-

C3:1+ C1:1+

C3:3- C1:3-

C3:3+ C1:3+

C3:5- C1:5-

C3:5+ C1:5+

C0:

0:3-

0:3+

P6900 Series Logic Analyzer Probes Instruction Manual 45

Reference

Table 7: Channel assignment for a P6980 differential clock and data logic analyzer probe to a 136- or 102-channel logic analyzer modu

Land pattern Probe 4 Probe 3 Probe 2 Probe 1

Pin number

B25

B26 D15- E3:7- E1:7- A3:7- D3:7- A1:7- D1:7-

B27 D15+ E3:7+ E1:7+ A3:7+ D3:7+ A1:7+ D1:7+

le (cont.)

136-channel module only 136- and 102

Signal name Head1 Head2 Head1 Head2 Head1 Head2 Head1 Head2

GND GND GND GND GND GND GND GND GND

-channel modules

C3:7- C1:7-

C3:7+ C1:7+

The following table lists the channel mapping to a 68 channel or 34 channel logic analyzer module for the P6980 differential data and clock logic analyzer probe.

Table 8: Channel assignment for a P6980 differential clock and data logic analyzer probe to a 68- or 34-channel logic analyzer module

attern

Land p

umber

Pin n

A1 D0+ A0:0+ D0:0+

A2 D0- A0:0- D0:0-

A4 D2+ A0:2+ D0:2+

A5 D2- A0:2- D0:2-

A7 D4+ A0:4+ D0:4+

A8 D4- A0:4- D0:4-

A10 D6+ A0:6+ D0:6+

A11 D6- A0:6- D0:6-

A12

A13

A14

A15

A16 D8+ A1:0+ D1:0+

A17 D8- A1:0- D1:0-

A18

A19 D10+ A1:2+ D1:2+

A20 D10- A1:2- D1:2-

A21

A22 D12+ A1:4+ D1:4+

al name

Sign

GND GND GND GND GND

NC NC

GND GND GND GND GND

annel module only for Probe 2

68-ch

Head

d 34-channel modules for Probe 1

68- an

Head

C2:0

C2:

:2+

2:2-

C2:4+

C2:4-

C2:6+

C2:6-

NC NC

C3:0+

C3:0-

C3:2+

C3:2-

C3:4+

Head

A2:0+

A2:0-

A2:2+

A2:2-

A2:4+

A2:4-

A2:6+

A2:6-

A3:0+

A3:0-

A3:2+

A3:2-

A3:4+

46 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Table 8: Channel assignment for a P6980 differential clock and data logic analyzer probe to a 68- or 34-channel logic analyzer modu

le (cont.)

Land patter

Pin number Signal name Head1 Head2 Head1 Head2

A23 D12- A1:4- D1:4-

A24

A25 D14+ A1:6+ D1:6+

A26 D14- A1:6- D1:6-

A27

B2 D1- A0:1- D0:1-

B3 D1+ A0:1+ D0:1+

B5 D3- A0:3- D0:3-

B6 D3+ A0:3+ D0:3+

B8 D5- A0:5- D0:5-

B9 D5+ A0:5+ D0:5+

B10

B11 D7- A0:7- D0:7-

B12 D7+ A0:7+ D0:7+

B13

B14

B15

B16

B17 D9- A1:1- D1:1-

B18 D9+ A1:1+ D1:1+

B19

B20 D11- A1:3- D1:3-

B21 D11+ A1:3+ D1:3+

B22

B23 D13- A1:5- D1:5-

B24 D13+ A1:5+ D1:5+

B25

B26 D15- A1:7- D1:7-

B27 D15+ A1:7+ D1:7+

GND GND GND GND GND

CK- CK1- CK2- CK3- CK0-

CK+ CK1+ CK2+ CK3+ CK0+

GND GND GND GND GND

68-channel

module only for Probe 2

68- and 34-c

C3:4-

C3:6+

C3:6-

C2:1-

C2:1+

C2:3

C2:

:5-

2:5+

C2:7-

C2:7+

C3:1-

C3:1+

C3:3-

C3:3+

C3:5-

C3:5+

C3:7-

C3:7+

hannel modules for Probe 1

A3:4-

A3:6+

A3:6-

A2:1-

A2:1+

A2:3-

A2:3+

A2:5-

A2:5+

A2:7-

A2:7+

A3:1-

A3:1+

A3:3-

A3:3+

A3:5-

A3:5+

A3:7-

A3:7+

P6900 Series Logic Analyzer Probes Instruction Manual 47

Reference

P6982 differential probe

with D-Max probing

technology

The following ﬁ for the PCB footprint of the P6982 differential data and clock logic analyzer probe. The P6982 probe has 16 data channels, and one clock or qualiﬁer for

gure shows the pad assignments, pad numbers, and signal names

each footprint.

Figure 35: P6982 differential PCB footprint pinout detail

The following table lists the channel mapping to a 136 channel or 102 channel logic analyzer module for the P6982 differential data and clock logic analyzer probe.

Table 9: Channel assignment for a P6982 differential clock and data logic analyzer probe to a 136- or 102-channel logic analyzer module

136-channel

Land pattern

Pin number Signal name Probe 4 Probe 3 Probe 2 Probe 1

A1 D0+ E2:0+ A2:0+ A0:0+

A2 D0- E2:0- A2:0- A0:0-

A4 D2+ E2:2+ A2:2+ A0:2+

A5 D2- E2:2- A2:2- A0:2-

A7 D4+ E2:4+ A2:4+ A0:4+

A8 D4- E2:4- A2:4- A0:4-

A10 D6+ E2:6+ A2:6+ A0:6+

A11 D6- E2:6- A2:6- A0:6-

A12

A13

A14

A15

A16 D8+ E3:0+ A3:0+ A1:0+

A17 D8- E3:0- A3:0- A1:0-

A18

A19 D10+ E3:2+ A3:2+ A1:2+

A20 D10- E3:2- A3:2- A1:2-

A21

GND GND GND GND GND

NC NC NC NC NC

GND GND GND GND GND

module only 136- and 102-channel modules

C2:0+

C2:0-

C2:2+

C2:2-

C2:4+

C2:4-

C2:6+

C2:6-

C3:0+

C3:0-

C3:2+

C3:2-

48 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Table 9: Channel assignment for a P6982 differential clock and data logic analyzer probe to a 136- or 102-channel logic

le (cont.)

136-channel module only 136- and 102

GND GND GND GND GND

CK- Q3- CK0- CK1- CK3-

CK+ Q3+ CK0+ CK1+ CK3+

GND GND GND GND GND

-channel modules

C3:4+

C3:4-

C3:6+

C3:6-

C2:1-

C2:1

C2:

:3+

2:5-

2:5+

C2:7-

C2:7+

C3:1-

C3:1+

C3:3-

C3:3+

C3:5-

C3:5+

C3:7-

C3:7+

analyzer modu

Land patter

Pin number Signal name Probe 4 Probe 3 Probe 2 Probe 1

A22 D12+ E3:4+ A3:4+ A1:4+

A23 D12- E3:4- A3:4- A1:4-

A24

A25 D14+ E3:6+ A3:6+ A1:6+

A26 D14- E3:6- A3:6- A1:6-

A27

B2 D1- E2:1- A2:1- A0:1-

B3 D1+ E2:1+ A2:1+ A0:1+

B5 D3- E2:3- A2:3- A0:3-

B6 D3+ E2:3+ A2:3+ A0:3+

B8 D5- E2:5- A2:5- A0:5-

B9 D5+ E2:5+ A2:5+ A0:5+

B10

B11 D7- E2:7- A2:7- A0:7-

B12 D7+ E2:7+ A2:7+ A0:7+

B13

B14

B15

B16

B17 D9- E3:1- A3:1- A1:1-

B18 D9+ E3:1+ A3:1+ A1:1+

B19

B20 D11- E3:3- A3:3- A1:3-

B21 D11+ E3:3+ A3:3+ A1:3+

B22

B23 D13- E3:5- A3:5- A1:5-

B24 D13+ E3:5+ A3:5+ A1:5+

B25

B26 D15- E3:7- A3:7- A1:7-

B27 D15+ E3:7+ A3:7+ A1:7+

P6900 Series Logic Analyzer Probes Instruction Manual 49

Reference

The following t

able lists the channel mapping to a 68 channel or 34 channel logic

analyzer module for the P6982 differential data and clock logic analyzer probe.

Table 10: Channel assignment for a

P6982 differential clock and data logic analyzer probe to a 68- or 34-channel

logic analyzer module

Pin number Signal name 68-channel module only for Probe 2 68- and 34-channel modules for Probe 1

A1 D0+ A0:0+

A2 D0- A0:0-

A4 D2+ A0:2+

A5 D2- A0:2-

A7 D4+ A0:4+

A8 D4- A0:4-

A10 D6+ A0:6+

A11 D6- A0:6-

A12

A13

A14

A15

A16 D8+ A1:0+

A17 D8- A1:0-

A18

A19 D10+ A1:2+

A20 D10- A1:2-

A21

A22 D12+ A1:4+

A23 D12- A1:4-

A24

A25 D14+ A1:6+

A26 D14- A1:6-

A27

B2 D1- A0:1-

B3 D1+ A0:1+

B5 D3- A0:3-

B6 D3+ A0:3+

GND GND GND

NC NC NC

GND GND GND

C2:0+

C2:0-

C2:2+

C2:2-

C2:4+

C2:4-

C2:6+

C2:6-

C3:0+

C3:0-

C3:2+

C3:2-

C3:4+

C3:4-

C3:6+

C3:6-

C2:1-

C2:1+

C2:3-

C2:3+

50 P6900 Series Logic Analyzer Probes Instruction M anual

Reference

Table 10: Channel assignment for a P6982 differential clock and data logic analyzer probe to a 68- or 34-channel logic analyzer modu

le (cont.)

Pin number Signal name 68-channel

B8 D5- A0:5-

B9 D5+ A0:5+

B10

B11 D7- A0:7-

B12 D7+ A0:7+

B13

B14

B15

B16

B17 D9- A1:1-

B18 D9+ A1:1+

B19

B20 D11- A1:3-

B21 D11+ A1:3+

B22

B23 D13- A1:5-

B24 D13+ A1:5+

B25

B26 D15- A1:7-

B27 D15+ A1:7+

GND GND GND

CK- CK1- CK3-

CK+ CK1+ CK3+

GND GND GND

module only for Probe 2

68- and 34-c

C2:5-

C2:5+

C2:7-

C2:7+

C3:1

:3-

:3+

3:5-

C3:5+

C3:7-

C3:7+

hannel modules for Probe 1

P6900 Series Logic Analyzer Probes Instruction Manual 51

Reference

52 P6900 Series Logic Analyzer Probes Instruction M anual

Speciﬁcations

Mechanical an

d electrical speciﬁcations

The following table lists the m echanical and electrical speciﬁcations for the P6900 Series Probes. The electrical speciﬁcations apply when the probe is connected between a co

mpatible logic analyzer and a target system. (See Table 11.)

Refer to the Tektronix Logic Analyzer Family Product Speciﬁcations document (Tektroni

x part number 071-1344-xx) available on the Tektronix Logic Analyzer Family Product Documentation CD or downloadable from the Tektronix Web site for a complete list of speciﬁcations, including overall system speciﬁcations.

Table 11: Mechanical and e lectrical speciﬁcations

Characteristic P6960, P6962, P6964 P6960HS P6980, P6982

Threshold accuracy

Input resistance

Input capacitance 0.5 pF 0.5 pF 0.5 pF

Minimum digital signal swing (TLA7AAx/TLA7ACx)

Minimum digital signal swing (TLA7BBx)

Maximum nondestructive input signal to probe

Delay from probe tip to module input connector

Probe length

Operating range

±(35 mV ±1% of setting) ±(35 mV ±1% of setting) ±(35 mV ±1% of setting)

20 kΩ ±1% 11.7 kΩ ±1% 20 kΩ ±1%

300 mV single-ended 150 mV single-ended

200 mV single-ended 100 mV single-ended

±15 V ±7.5 V ±15 V

7.70 ns ±60 ps 7.70 ns ±60 ps 7.70 ns ±60 ps

1.8 m (6 ft) 1.8 m (6 ft) 1.8 m (6 ft)

+5 V to –2.5 V +2.5 V to –1.25 V + 5 V to –2.5 V

150 mV differential each side

100 mV differential each side

NOTE. Because the length of the probes are electrically similar, they can be

interchanged without problems.

P6900 Series Logic Analyzer Probes Instruction Manual 53

Speciﬁcations

The following t

able shows the environmental speciﬁcations for the probes.

Table 12: Environmental speciﬁcations

Characteristic P6900

Temperature

Operating 0 °C to +50 °C ( 0 ° F to +122 °F)

Nonoperating

Humidity

Altitude

Operating 9843 ft (3,000 m)

Nonoperating

Electrostatic immunity 6 kV

-51 °C to +71 °C (-60 °F to +160 °F)

10 °C to 30 °C (+50 °F to +86 °F) 95% relative humidity

30 °C to 40 °C (+86 °F to +104 °F) 75% relative humidity

40 °C to 50 °C (+104 °F to +122 °F) 45% relative humidity

40,000 ft (12,192 m)

54 P6900 Series Logic Analyzer Probes Instruction M anual

Maintenance

The P6900 Series High-Density Logic Analyzer Probes do not require scheduled or periodic maintenance. Refer to the Functional Check section below to verify the basic functionality of the probes.

Probe calib

ration

To co n ﬁrm that the probes meet or exceed the performance requirements for published speciﬁcations with a compatible logic analyzer module, you must return the probes

Perform the functional check

Connect t verify that the acquired data is displayed in either the listing or waveform windows.

Inspect and clean the probes

CAUTION. To prevent damage during the probe connection process, do n ot touch

posed edge of the interface clip. Do not drag the contacts against a hard

the ex edge or corner.

intain a reliable electrical contact, keep the probes free of dirt, dust, and

To m a contaminants. Remove dirt and dust with a s oft brush. Avoid brushing or rubbing the c-spring contacts. For more extensive cleaning, use only a damp cloth. Never use abrasive cleaners or organic solvents.

to your local Tektronix service center.

he logic analyzer probes to a signal source, start an acquisition, and

P6900 Series Logic Analyzer Probes Instruction Manual 55

Maintenance

Service strat

Replace the cLGA Clip

egy

The P6900 Series Probes use replaceable c-spring cLGA clips. If a probe failure other than the cLGA clip occurs, return the entire probe to your Tektronix service center for re

For replacement part number information, refer to the Replaceable Parts List. To replace the clip, do the following:

1. Gently pull one side of the clip a way from the probe head, as shown in the following ﬁgure, and then remove the entire clip.

2. Align the new clip to the probe head and gently snap it into place.

3. Test the probe to conﬁrm that all channels are functional.

pair.

Figure 36: Replacing the cLGA clip

Legacy probe and attachment support

Nexus Technology, a Tektronix Partner, sells accessories that allow you to use the P6960 probe with legacy attachment connectors as well as utilize the P6960 probe footprint with select P68xx and P64xx probe products.

Please contact Nexus Technology directly for more information.

Contact Information:

Nexus Technology

Phone: 877-595-8116

Fax: 877-595-8118

56 P6900 Series Logic Analyzer Probes Instruction M anual

Repackaging instructions

Use the original packaging, if possible, to return or store the probes. If the original packaging is not available, use a corrugated cardboard shipping carton. Add cushioning material to prevent the probes from moving inside the shipping container.

Enclose the following information when shipping the probe to a Tektronix Service Center.

Maintenance

Owner's address

Name and phone number of a contact person

Type of probe

Reason for return

Full des

cription of the service required

P6900 Series Logic Analyzer Probes Instruction Manual 57

Maintenance

58 P6900 Series Logic Analyzer Probes Instruction M anual

Replaceable parts

This chapter contains a list of the replaceable c omponents for the P6900 Series Probes. Use this list to identify and order replacement parts.

Parts ordering information

Replacement parts are available through your local Tektronix ﬁeld ofﬁce or representative.

Changes to Tektronix products are sometimes made to accommodate improved components as they become available and to give you the beneﬁt of the latest improvements. Therefore, when ordering parts, it is important to include the followin

If you order a part that has been replaced with a different or improved part, your local Tektronix ﬁeld ofﬁce or representative will contact you concerning any change in part number.

ginformationinyourorder.

Part number

Instrument type or model number

Instrument serial number

Instrument modiﬁcation number, if applicable

P6900 Series Logic Analyzer Probes Instruction Manual 59

Replaceable parts

Replaceable parts list

The P6900 Series Probes contain only the cLGA clip as a replaceable part. If probe failure occurs, return the entire probe to your Tektronix service representative for repair.

Refer to the following list for replaceable items:

Table 13: Parts list column descriptions

Column Column name Descriptio

2 Tektronix part number Use this part number when

3 and 4

Figure & in

Serial n

Qty

Name & description

dex number

umber

Items in this section reference numbers to the exploded view illustrations that follow.

ordering replacement parts from Tekt

Column t the serial number at which the part was ﬁrst effective. Column serial number at which the part was discontinued. No entrie good for all serial numbers.

This i of parts used.

An ite from the description by a colon (:). Because of space limi may sometimes appear as incomplete. Use the U.S. Fede H6-1 for further item name identiﬁcation.

ﬁgure and index

ronix.

hree indicates

four indicate the

s indicates the part is

ndicates the quantity

m name is separated

tations, an item name

ral Catalog handbook

Abbreviations conform to American National Standard ANSI Y1.1-1972.

60 P6900 Series Logic Analyzer Probes Instruction M anual

Replaceable parts

Table 14: P6960

Figure & index number

(See Figure 37.)-1

-2 020-2622-XX 1

-3 200-4893-XX 1

replaceable parts list

Tektronix part number

010-6960-12 1

020-2908-XX 1

346-0300-XX 1

003-1890-XX 1

071-1539-XX 1

335-1208-XX 1

Serial no. effective

Serial no. discont'd Qty Name & description

P6960 PROBE (INCLUDES SHEET OF LABELS)

COMPONENT KIT, CLGA INTERFACE CLIP PREINSTALLED ON THE PROBE; 1 EA, P6900 SERIES PROBE, SAFETY CONTROLLED

COVER,PROTECTIVE; BLACK VINYL (PLASTISOL) WITH STATIC-DISSIPATIVE ADDITIVE

P6900 RETENTION ASSEMBLY KIT, QTY 2

STRAP,VELCRO;ONE WRAP,BLACK,0.500W X 8.00L,QTY 2 BAGGED & LABELED

TOOL,HAND; USED TO TIGHTEN PROBE HEAD TO DUT

MANUAL,TECH; TRIFOLD,INSTALLATION/LABELING INSTRUCTIONS FOR P6960

P6960 PROBE, SHEET OF LABELS

Figure 37: P6960 High-Density probe accessories

P6900 Series Logic Analyzer Probes Instruction Manual 61

Replaceable parts

Table 15: P6960

Figure & index number

(See Figure 38.)-1

-2 020-2622-XX 1

-3 200-4893-XX 1

HS replaceable parts list

Tektronix part number

010-0825-10 1

020-2908-XX 1

346-0300-XX 1

003-1890-XX 1

071-1539-XX 1

335-3009-XX 1

Serial no. effective

Serial no. discont'd Qty Name & description

P6960HS PROBE (INCLUDES SHEET OF LABELS)

COMPONENT KIT, CLGA INTERFACE CLIP PREINSTALLED ON THE PROBE; 1 EA, P6900 SERIES PROBE, SAFETY CONTROLLED

COVER,PROTECTIVE; BLACK VINYL (PLASTISOL) WITH STATIC-DISSIPATIVE ADDITIVE

P6900 RETENTION ASSEMBLY KIT, QTY 2

STRAP,VELCRO;ONE WRAP,BLACK,0.500W X 8.00L,QTY 2 BAGGED & LABELED

TOOL,HAND; USED TO TIGHTEN PROBE HEAD TO DUT

MANUAL,TECH; TRIFOLD,INSTALLATION/LABELING INSTRUCTIONS FOR P6960

P6960 PROBE, SHEET OF LABELS

Figure 38: P6960HS High-Density probe accessories

62 P6900 Series Logic Analyzer Probes Instruction M anual

Replaceable parts

Table 16: P6962

Figure & index number

39--1 010-6962-10 1

-2 020-2622-XX 1

-3 200-4893-XX 1

replaceable parts list

Tektronix part number

020-2908-XX 1

346-0300-XX 1

003-1890-XX 1

071-2153-XX 1

335-1772-XX 1

Serial no. effective

Serial no. discont'd Qty Name & description

P6962 PROBE (INCLUDES SHEET OF LABELS)

COMPONENT KIT, CLGA INTERFACE CLIP PREINSTALLED ON THE PROBE; 1 EA, P6900 SERIES PROBE, SAFETY CONTROLLED

COVER,PROTECTIVE; BLACK VINYL (PLASTISOL) WITH STATIC-DISSIPATIVE ADDITIVE

P6900 RETENTION ASSEMBLY KIT, QTY 2

STRAP,VELCRO;ONE WRAP,BLACK,0.500W X 8.00L,QTY 2 BAGGED & LABELED

TOOL,HAND; USED TO TIGHTEN PROBE HEAD TO DUT

MANUAL,TECH; QUADFOLD,INSTALLATION/LABELING INSTRUCTIONS FOR P6962

P6962 PROBE, SHEET OF LABELS

Figure 39: P6962 High-Density probe accessories

P6900 Series Logic Analyzer Probes Instruction Manual 63

Replaceable parts

Table 17: P6964

Figure & index number

40--1 010-6964-11 1

-2 020-2622-XX 1

-3 200-4893-XX 1

replaceable parts list

Tektronix part number

020-2908-XX 1

346-0300-XX 1

003-1890-XX 1

071-1685-XX 1

335-1315-XX 1

Serial no. effective

Serial no. discont'd Qty Name & description

P6964 PROBE (INCLUDES SHEET OF LABELS)

COMPONENT KIT, CLGA INTERFACE CLIP PREINSTALLED ON THE PROBE; 1 EA, P6900 SERIES PROBE, SAFETY CONTROLLED

COVER,PROTECTIVE; BLACK VINYL (PLASTISOL) WITH STATIC-DISSIPATIVE ADDITIVE

P6900 RETENTION ASSEMBLY KIT, QTY 2

STRAP,VELCRO;ONE WRAP,BLACK,0.500W X 8.00L,QTY 2 BAGGED & LABELED

TOOL,HAND; USED TO TIGHTEN PROBE HEAD TO DUT

MANUAL,TECH; TRIFOLD,INSTALLATION/LABELING INSTRUCTIONS FOR P6964

P6964 PROBE, SHEET OF LABELS

re 40: P6964 High-Density probe accessories

Figu

64 P6900 Series Logic Analyzer Probes Instruction M anual

Replaceable parts

Table 18: P6980

Figure & index number

41--1 010-6980-12 1

-2 020-2622-XX 2

-3 200-4893-XX 2

replaceable parts list

Tektronix part number

020-2908-XX 1

346-0300-00 1

003-1890-XX 1

071-1542-XX 1

335-1209-XX 1

Serial no. effective

Serial no. discont'd Qty Name & description

P6980 PROBE SET (INCLUDES SHEET OF LABELS)

COMPONENT KIT, CLGA INTERFACE CLIP PREINSTALLED ON THE PROBE; 1 EA, P6900 SERIES PROBE, SAFETY CONTROLLED

COVER,PROTECTIVE; BLACK VINYL (PLASTISOL) WITH STATIC-DISSIPATIVE ADDITIVE

P6900 RETENTION ASSEMBLY KIT, QTY 2

STRAP,VELCRO;ONE WRAP,BLACK,0.500W X 8.00L,QTY 2 BAGGED & LABELED

TOOL,HAND; USED TO TIGHTEN PROBE HEAD TO DUT

MANUAL,TECH; TRIFOLD,INSTALLATION/LABELING INSTRUCTIONS FOR P6980

P6980 PROBE, SHEET OF LABELS

Figure 41: P6980 High-Density Differential probe accessories

P6900 Series Logic Analyzer Probes Instruction Manual 65

Replaceable parts

Table 19: P6982

Figure & index number

42--1 010-6982-11 1

-2 020-2622-XX 1

-3 200-4893-XX 1

replaceable parts list

Tektronix part number

020-2908-XX 1

346-0300-XX 1

003-1890-XX 1

071-1684-XX 1

335-1313-XX 1

Serial no. effective

Serial no. discont'd Qty Name & description

P6982 PROBE SET (INCLUDES SHEET OF LABELS)

COMPONENT KIT, CLGA INTERFACE CLIP PREINSTALLED ON THE PROBE; 1 EA, P6900 SERIES PROBE, SAFETY CONTROLLED

COVER,PROTECTIVE; BLACK VINYL (PLASTISOL) WITH STATIC-DISSIPATIVE ADDITIVE

P6900 RETENTION ASSEMBLY KIT, QTY 2

STRAP,VELCRO;ONE WRAP,BLACK,0.500W X 8.00L,QTY 2 BAGGED & LABELED

TOOL,HAND; USED TO TIGHTEN PROBE HEAD TO DUT

MANUAL,TECH; TRIFOLD,INSTALLATION/LABELING INSTRUCTIONS FOR P6982

P6982 PROBE, SHEET OF LABELS

Figure 42: P6982 High-Density Differential probe accessories

66 P6900 Series Logic Analyzer Probes Instruction M anual

Replaceable parts

Table 20: P6900

Figure & index number

43--1 196-3494-XX 1

-2 020-3043-XX 2

-3 020-2908-XX 1

-4 020-2910-XX 1

Series Probes optional accessories

Tektronix part number

Serial no. effective

Serial no. discont'd Qty Name & description

P6900 FLYING LEADSET

ADAPTER KIT; BAG OF 20 KLIPCHIP ADAPTER (40 TOTAL)

P6900 RETENTION ASSEMBLY KIT, QTY 2

P6900 RETENTION ASSEMBLY KIT, QTY 50

Figure 43: Optional accessories

P6900 Series Logic Analyzer Probes Instruction Manual 67

Replaceable parts

68 P6900 Series Logic Analyzer Probes Instruction M anual

Index

Symbols and Numbers

3D CAD ﬁle, 31

adapters

deﬁnition of, viii

alternate retention assembly, 14,

30 dimensio

analog signals

probing, 26

attaching probe labels, 1

ns, 30

calibration

probe, 55

el assignment, 37

chann

See also channel mapping channel assignment tables, 37 channel mapping

P6960, 37 P6960HS, 37

62, 40

P69 P6964, 42 P6980, 44, 46 P6982, 48, 50

cleaning

compression footprints, 13

nspection and, 55

i cLGA, vi cLGA interface clip

handling, 15

replacing, 56 clocking

source synchronous, 22 clocks, 21 commonly used terms, vi compression footprint, vi, 13 connecting

probes to logic analyzer, 10

probes to target system, 11

designinganinterface, 21

electrical c mechanical

differential input amplitude

deﬁnition, vii

dimensions

alternat

footprint, 30, 31 probe, 27 probe footprint, 35 retention posts, 29

docume

ntation

related, v

onsiderations, 33

considerations, 3 2

e retention

assembly, 30

electrical considerations

P6900 Series Probes load

model, 33

transmission lines, 33

ctrical speciﬁcations, 53

ele environmental speciﬁcations, 54

ﬁle a ttachments, 31 ﬂying lead set, vii

footprint

dimensions, 30, 31

functional check, viii, 55

High Density Differential Probe,

P6980, 7

High Density Differential Probe,

P6982, 8 High Density Probe, P6960, 2 High Density Probe, P6960HS, 3 High Density Probe, P6962, 4 High Density Probe, P6964, 6 high resolution timing modes, 25

inspection and cleaning, 55 installing r interface

etention posts, 11

design, 21

keepout area, viii, 29, 30

load model

P6900 Series Probes, 33

logic an

alyzer

connecting probes, 10

maintenance, 55

functional check, 55 inspection and cleaning, 55 probe calibration, 55

ckaging instructions, 57

repa service strategy, 56

mechanical considerations

physical attachment

requirements for P6900 Series Probes, 33

chanical speciﬁcations, 53

me merged module, 22 module, viii

ordering parts, 59

P6960

channel mapping, 37 pinout, 37

P6960HS

channel mapping, 37 pinout, 37

P6900 Series Logic Analyzer Probes Instruction Manual 69

Index

P6962

channel mapping, 40 pinout, 39

P6964

channel mapping, 42 pinout, 41

P6980

channel mapping, 44, 46 pinout, 44

P6982

channel mapping, 48, 50 pinout, 48

parts

ordering information, 59 using the replaceable parts

list, 60 PCB (printed c ircuit board), viii probe

sions, 27

dimen troubleshooting DUT

connections, 17 probe heads

handling the interface

clips, 15

probes

adapter, deﬁnition of, viii calibration, 55 cleaning the compression

footprints, 13

connecting probes to the logic

analyzer, 1

connecting probes to the target

system, 11 deﬁnition of, viii footprint dimensions, 35 head, deﬁnition of, viii labels, 1 P6960 High Density Probe, 2 P6960HS High Density

Probe, 3 P6962 High Density Probe, 4 P6964 High Density Probe, 6 P6980

P6982 High Density

product description, 1 returning, 57 sto

probing analog signals, 26

High Density

Differential Probe, 7

Differential Probe, 8

ring, 20, 57

qualiﬁers, 21

range recognition, 26 related documentation, v repackaging instructions, 57 replacement parts, 59, 60 replacing the cLGA interface

clip, 5 6

requirements

physical attachment for the

P6900 Series Probes, 33

retention post

using the correct retention

retention posts, 11

dimensions, 29 installing, 11

returning p

wires

post wires, 11

robes, 57

service strategy, 56 signal connections, 21 signal ﬁxturing, 21 signal routing, 32 SMT KlipChip, viii speciﬁc

storing probes, 20, 57

ations electrical, 53 environmental, 54 mechanical, 53

target system

ecting probes, 11

conn

terms

commonly used, vi

timing modes

high resolution, 25

transmission lines, 33

oubleshooting

probe DUT connections, 1 7

using the correct retention post

wires, 11

via-in-pad, 36 vias, 36

70 P6900 Series Logic Analyzer Probes Instruction M anual

Tektronix P6960,P6962,P6964,P6980,P6982,P6960HCD,P6960HS User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual