Tektronix TLA7SA16, P67SA08 Performance Verification

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TLA7SA08 & TLA7SA16 Series

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Product Speciﬁcations & Performance Veriﬁcation

Technical Reference Manual

This document applies to TLA System Software V5.7 or higher.

www.tektronix.com

P077040202*

077-0402-02

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Table of Contents

Preface .............................................................................................................. iii

Related Documentation ...................................................................................... iii

Speciﬁcations and Characteristics ............... .................................. ............................... 1

Atmospheri

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations .............................. 3

P67SA01SD Probe Speciﬁcations ............................................................................... 12

P67SAxx Midbus Probe Speciﬁcations ......................................................................... 13

P67SAxxS Slot Interposer Speciﬁcations....................................................................... 14

P67SA16G2 Midbus Probe Speciﬁcations.......................... .................................. .......... 16

P6716G3

Performance Veriﬁcation Procedures............................................................................ 19

Functional Check Procedures ............ ................................ .................................. ...... 20

Functional Veriﬁcation ....... .................................. ................................ .............. 20

c Characteristics........................................... ................................ ....... 1

Midbus Probe Speciﬁcations ......................................................................... 17

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation i

Table of Contents

List of Tables

Table 1: Atmospheric characteristics............................................................................. 1

Table 2: Dat

Table 3: Width and depth .......................................................................................... 3

Table 4: Clocking................................................................................................... 3

Table 5: SerDes ..................................................................................................... 3

Table 6: Lane processing .......................................................................................... 4

Table 7: Link processing...................................... .................................. ................... 5

Table 8: E

Table 9: Filtering . . .... . ..... . ..... . .... . ..... . ..... . ... . . ..... . ..... . ..... ..... . ..... . ..... . .... . . .... . ..... . ..... . 7

Table 10: Trigger state machine ................. ................................ ................................. 8

Table 11: Trigger machine actions................................................................................ 8

Table 12: Module input/trigger/backplane delay relationships . . ..... . ..... . ..... . ..... . ..... . ..... . ..... . .... 9

Table 13: Storage control ......................................................................................... 10

Table

Table 15: Conﬁguration memory ................................................................................ 10

Table 16: Mechanical ............................................................................................. 11

Table 17: Electrical speciﬁcation for P67SA01SD probe..................................................... 12

Table 18: Cable speciﬁcations for P67SA01SD probe.. ................................ ...................... 12

Table 19: Atmospheric characteristics for P67SA01SD probe ............................................... 12

ble 20: Electrical speciﬁcation for P67SAxx midbus probe ............................................... 13

Table 21: Atmospheric characteristics for P67SAxx midbus probe ......................................... 13

Table 22: Mechanical characteristics for P67SAxx midbus probe........................................... 13

Table 23: Electrical speciﬁcation for P67SAxxS slot interposer ............................................. 14

Table 24: Cable speciﬁcations for P67SAxxS slot interposer ........................ ........................ 14

Table 25: Mechanical characteristics for P67SAxxS slot interposer......................................... 15

Table 26: Atmospheric characteristics for P67SAxxS slot interposer ....................................... 15

Table 27: Electrical speciﬁcation for P67SA16G2 midbus probe............................ ................ 16

Table 28: Atmospheric characteristics for P67S16AG2 midbus probe................ ...................... 16

Table 29: Electrical speciﬁcation for P6716G3 midbus probe ............................................... 17

Table 30: Atmospheric characteristics for P67S16AG3 midbus probe................ ...................... 17

a input for differential probes....................................................................... 3

vent recognizer resources. ................................ ................................ ............. 6

14: Data placement................................... .................................. .................... 10

ii TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation

Preface

Related documentation

Item Purpose

TLA Quick Start User Manuals

Online Help

Installation Reference Sheets High-level installation information

Installation Manuals

XYZs of Logic Analyzers

Declassiﬁcation and Securities instructions Data security concerns speciﬁc to sanitizing

Application notes

Product Speciﬁcations & Performance Veriﬁcation Procedures

TPI.NET Documentation

Field upgrade kits

Optional Service Manuals Self-service documentation for modules and

High-level operational overview

In-depth operation and UI help

Detailed ﬁrst-time installation information

Logic analyzer basics

or removing memory devices from Tektronix products

Collection of logic analyzer application speciﬁc notes

TLA Product speciﬁcations and performance veriﬁcation procedures

Detailed information for controlling the logic analyzer using .NET

Upgrade information for your logic analyzer

mainframes

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation iii

Preface

iv TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation

Speciﬁcations and Characteristics

All speciﬁcations in this document are guaranteed unless noted Ty pic al.Typical characteristics describe typical or average performance and provide useful reference in

formation.

Speciﬁcations that are marked with the indirectly

The performance limits in this speciﬁcation are valid with these conditions:

The instrument must be in an environment with temperature, altitude, humidity, and vibration within the operating limits described in these speciﬁca

The instrument must have had a warm-up period of at least 30 minutes.

For modules, the performance limits in this speciﬁcation are valid with these conditions:

The logic protocol analyzer modules must be installed in a Logic Analyzer Mainframe.

The module must have been calibrated/adjusted at an ambient temperature between +20 °C and +30 °C.

Atmospheric Characteristics

The following table lists the Atmospheric characteristics of the Tektronix logic

tocol analyzers.

pro

symbol are checked directly (or

) at your nearest Tektronix location.

tions.

Table 1: Atmospheric characteristics

Characteristic Description

Temperature

Relative Hum idity

Operating (no media in CD or DV D drive of the mainframe)

0 °C to +40 °C, 15 °C/hr maximum gradient, noncondensing, derated 1°C per 300 meters (~1000 ft) above 1500 meters (~5000 ft) altitude

Nonoperating (no media)

-20 °C to +60 °C, 15 °C/hr maximum gradient, without disk media installed in disk drives

Operating (no media)

5% to 95% relative humidity (%RH), up to +30 °C

5% to 75% relative humidity above +30 °C up to +40 °C, noncondensing and as limited by a Maximum Wet-bulb Temperature of +29.4 °C

Nonoperating (no media)

5% to 95% relative humidity (%RH) up to +30 °C, 75% RH up to 60 °C, noncondensing, and as limited by a Maximum Wet-Bulb Temperature of +40 °C (derates relative humidity to 20% RH at +60 °C)

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 1

Speciﬁcations and Characteristics

Table 1: Atmospheric characteristics (cont.)

Characteristic Description

Altitude

Operating

Up to 3,000 meters (~10,000 ft), derated 1 °C per 300 meters (~1000 ft) above 1500 meters (~5000 ft) altitude

Nonoperating

Up to 12,000 meters (~40,000 ft)

2 TLA7SA08 & TLA7SA16 Series P roduct Speciﬁcations & P erformance Veriﬁcation

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations

TLA7SA08 & TLA

7SA16 Logic Protocol Analyzer Modules

Speciﬁcations

Table 2: Data input for differential probes

Characteri

Data rate

Number of FTS packets required to resynchronize following the L0s exit

(Typical

Table 3: Width and depth

Characteristic Description

Acquisition memory depth

stic

)

TLA7SA08 8 differential inputs, x4 linkNumber of inputs

TLA7SA16 16 differential inputs, x8 link

TLA7SA08 160 mega samples per differential input (4 GB physical memory total)

TLA7SA16 160 mega samples per differential input (8 GB physical memory total)

Descriptio

2.5 Gbps and

8.0 Gbps (modulated from -10% and +5%)

Gen1: 20 ns EIDLE minimum ÷ 4 FTS

Gen2: 20 ns EIDLE minimum ÷ 1 EIEO S + 6 FTS

Gen3: 20 n

5.0 Gbps (modulated from -10% to +10%)

s EIDLE minimum ÷ 1 EIEOS + 4 FTS

Table 4: Clockin g

Characteristic Description

External reference clock

Minimum peak-to-peak differential input voltage

pical)

(Ty

solute differential input voltage limit (Typical)

ock frequency (Typical)

requency tolerance (Typical)

150 mV

2.5 V

100 MHz

MHz through 110 M Hz when acquiring frequency margined data

±300 ppm

Table 5: SerDes

Characteristic D escription

Clock encoding standard Supports 8b/10b encoded serial data

Supports 128b/130b encoded serial data

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 3

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations

Table6: Lanepr

ocessing

Characteristic Description

Time required

dynamically change

200 ns minimum

Detials:

the data rate (Typical)

Maximum time to change to Gen 1 rate: 2 TS1

Maximum time to change to Gen 2 rate: 1 EIEOS + 3 TS1

Maximum time to change to Gen 3 rate: 1 EIEOS + 6 TS1

Polarity in

Descrambling polynomial used

Autoset lane number

version

Available o

Gen1/Gen2

Gen3

Each lane only autoset polarity at Gen 1 and Gen 2 rates.

The SUT must provide T S1 training sequences for the Autoset to work.

Changes

are not applied automatically. The software polls the lane number registers and then prompts

the user to use Autoset when changes are detected.

Autoset

lane polarity

Each lan

e has a training sequence recognizer that stores the last known lane polarity.

The SUT must provide T S1 training sequences for the Autoset to work.

Changes are not applied automatically. The software polls the lane number registers and then prompts

r to use Autoset when changes are detected.

the u se

Auto-track l ane rate

When th

e auto-track feature is enabled, data is acquired at the current data rate.

Training sequences must be acquired for the module to change rates. EIOS packets must be acquired to initiate the speed change. The signaling levels (speciﬁed above) must be met.

Force lane rate

Lane data groups

When forced, data is acquired at the speciﬁed rate of 2.5 Gbps, 5.0 Gbps, or 8.0 Gbps.

Reports the 8b/10b symbol information acquired from each lane or internal module status symbols

data is available.

if no

following information for Gen 1 and Gen2 is available when 8b/10b symbols are acquired:

The

EIDLE time

n all inputs

16+X5+X4+X3+X1

23+X21+X16+X8+X5+X2

has a training sequence recognizer that stores the last known lane number assignment. Can

parity error indicator

Dis

ning disparity error indicator

Run

code/D-code indicator

K-

bit code value

ll 10b value if an 8b/10b code error is encountered

Gen 3: Reports the 8b symbol information acquired from each lane and 2 bit Sync Character bits, or internal module status symbols if no symbol data is available

4 TLA7SA08 & TLA7SA16 Series P roduct Speciﬁcations & P erformance Veriﬁcation

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations

Table 7: Link pr

Characteristic Description

Cross-point switch

Lane alignme

Lane alignment exit

ignment exit recovery

Lane al

m skew between lanes of a link

Maximu

upport

Link s

Auto-track link width

ocessing

nt entrance

Any-to-any ch

If the link is not currently in the aligned state, the hardware will automatically attempt lane-to-lane alignment (deskew) on any of the following c

Skip ordere

Electrical

Entry/exi

Start data

k is currently in the aligned state, the hardware will abandon the

If the lin current alignment (deskew) settings on any of the following conditions:

Electrical idle ordered set

Misaligned COM symbol across the active lanes

Data rate mismatch occurs on the lanes within the link

Any lane wakes up from electrical idle

32 symb

12 symbol times

This de alignment module can deskew

TLA7SA08 One unidirectional x8, x4, x2, or

TLA7

Lin enabled.

Real-time resources that depend on link width (such as packet re

ol times

ﬁnes the maximum skew between lanes of a link that the lane

SA16

k-width changes are automatically tracked; this feature is always

cognizers) remain unusable through any change in link width.

annel mapping

onditions:

dset

idle exit ordered set

t of a TS2 training sequence

stream ordered set (Gen 3 only)

x1 link

directional x4, x2, or x1 link

One bi

nidirectional x16, x8, x4, x2,

One u or x1 link

One bidirectional x8, x4, x2, or x1

lin

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 5

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations

Table 8: Event r

Characteristic Description

DLLP packet re

TLP packet r

Symbol sequence recognizers

Link even

Link eve

t recognizers

nt:

ecognizer resources

cognizers

ecognizers

4 per link dire

Each recognizer supports full 32-bit m ask and match on the DLLP packet excluding the CRC and framing bytes.

Automatical or !Aligned.

4 per link di

Each recognizer supports full 32-bit mask and match for the ﬁrst 4 dwords of the TLP packet excluding the framing and sequence number.

Automatica or !Aligned.

4 shared be

Each recognizer supports full mask and match on each symbol in a sequence up to 16 symbols deep. Any position in the sequence can be marked continue if the current symbol does not satisfy the mask and match logic.

4 per link

Each recognizer is a unique logical OR of the selected link events

ty error

Dispari

10b Code error Asserts when an 8b/10b table lookup error is detected on any of the

rical i dle

Elect

DLLP frame error Asserts when an SDP start symbol is detected in a non-modulo-4 lane

TLP frame error Asserts when an STP start symbol is detected in a non-modulo-4 lane

DLLP CRC error Asserts when the calculated CRC does not match the CRC value in the

Logical idle error

Asserts when an 8b/10b disparity error is detected on any of the selected lanes. Each lane of the link can be individually included or excluded

select excluded

Asserts when electrical idle is detected on any of the selected lanes. Each lane of the link can be individually included or excluded

numb

Automatically disqualiﬁed when the link status is Rates_Vary, Aligning, or !Aligned

num

Automatically disqualiﬁed when the link status is Rates_Vary, Aligning, or !Aligned

Asserts when packet and ordered set trafﬁc is not active and a non-zero

ata symbol is detected in any of the active lanes in the link

Automatically disqualiﬁed when the link status is Rates_Vary, Aligning, or !Aligned

direction

ed lanes. Each lane of the link can be individually included or

ber

cket payload

ction

ly disqualiﬁed when the link status is Rates_Vary, Aligning,

rection

lly disqualiﬁed when the link status is Rates_Vary, Aligning,

tween link directions

with a NOT in which case the recognition process will only

6 TLA7SA08 & TLA7SA16 Series P roduct Speciﬁcations & P erformance Veriﬁcation

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations

Table 8: Event recognizer resources (cont.)

Characteristic Description

END Bad Packet

Gen 3 TLP FCRC Error Asserts when the calculated FCRC does not match the FCRC value in

Data rate change Programmed to assert when the link data rate changes:

Link width change

Asserts when an End Bad Symbol (Gen 1, Gen 2) or End Bad Token (Gen 3) occurs

Automatically disqualiﬁed when the link status is Rates_Vary, Aligning, or !Aligned

theGen3TLPtoken

Automatically disqualiﬁed when the link status is Rates_Vary, Aligning, or !Aligning

To Gen1 (2.5 Gbps)

To Gen2 (5.0 Gbps)

To Gen3 (8.0 Gbps)

To any rate different than the last known rate

Automatically disqualiﬁed when the link status is Rates_Vary, Aligning, or !Aligned

Can be programmed to assert when the link width changes:

Downtrain (to any width less than the last known width)

Uptrain (to any width more than the last known width)

x1, x2, x4, x8, or x16

Not x1, Not x2, Not x4, Not x8, or Not x16

To any width different than the last known width

Automatically disqualiﬁed when the link status is Rates_Vary, Aligning, or !Aligned

Table 9: Filtering

Characteristic Description

Bidirectional ﬁltering control Each direction of a link has independent ﬁlter control settings

Idle ﬁltering Logical idle and electrical idle conditions can be ﬁltered from storage.

Ordered set ﬁltering The following ordered sets can be selected for ﬁltering from storage:

S1, TS2, S K P, EIOS, FTS, EIEOS

SDS (Gen3 only)

DLLP packet ﬁltering The following DLLP packet types can be selected for ﬁltering from storage:

Ack, Nack, PM, FC1, FC2, UpdateFC, Vendor Speciﬁc

TLP packet ﬁltering The following TLP packet types can be selected for ﬁltering from s torage:

MRd, MRdLk, MWr, IORd, IOWr, CfgRd0, CfgWr0, CfgRd1, CfgWr1, Msg, MsgD, Cpl, CplD, CplLk, CplDLk, FetchAdd, Swap, CAS, LPrfx, EPrfx

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 7

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations

Table 10: Trigg

er state ma chine

Characteristic Description

Sequencer states

Sequencer rate

The trigger s

tate machine evaluates its logic and can advance states at

the symbol rate time. The symbol rate can be Gen 1, Gen 2, or Gen 3.

Event recog

nizer inputs per state

10 total, ei

ght programmable event recognizer inputs and two dedicated

event occurrence counter results.

Event occur

rence counters

Two 31-bit e

vent occurrence counters per state.

Each counter can be independently programmed to monitor any event recognizer output. The counter actions are automatic. They automatically increment

at the rate of the selected event recognizer output. And they

automatically reset when their host state is exited.

Global counter-timers There are four 48-bit signed global counter/timers that are actionable at

the rate of the sequencer.

Maximum c

ount value = 2

Maximum time value = (2

–1

– 1) × 3.7 ns = ~146 hours

Counter-timers have a 19 cycle ( 71.25 ns) latency before the result of any

-timer action can be tested by the trigger machine event logic.

counter

Backplane trigger

The back

plane trigger signal can be recognized as the trigger for the

acquisition.

Arm Hold-off The execution of the trigger state machine can be held off by using the

Arm input. The Arm input can be controlled by any other module in the

m. If Arm is not explicitly assigned, then the module will automatically

syste arm itself immediately at the beginning of each acquisition.

lane signal inputs

Backp

ger position

Trig

Up to four backplane signals can be used as events.

rigger position is programmable to any data sample.

The t

Table 11: Trigger machine actions

Characteristic Description

Trigger Triggers the acquisition memory.

Increment or decrement global counter

Counters can be incremented or decremented. These actions occur at the sequencer rate.

Reset global counter

Start or stop global timer

Counters can be reset.

Timers can be started or stopped. When stopped they hold their present value.

Reset global timer

Timers can be reset. When reset, it continues in the state it was in before the reset action – either running or stopped.

Reset and start or stop global timer Timer resources can be simultaneously reset and started or reset and

stopped in a single action.

Set or clear backplane signal Any of the four signals can be driven on the backplane to be used by

another module. All four backplane signals can be used.

If ARM is used then Signal-4 is not available.

8 TLA7SA08 & TLA7SA16 Series P roduct Speciﬁcations & P erformance Veriﬁcation

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations

Table 11: Trigger machine actions (cont.)

Characteristic Description

Trigger Out A Trigger Out signal can be driven to the backplane to trigger other

modules.

Goto state Jump to any state from any state.

Start or stop storage Turns storage on or off. Once turned off, no samples will be stored until

another start storage action is encountered.

The data sample containing the condition that stops storage is stored. This ensures that a partial packet is not truncated.

Table 12: Module input/trigger/backplane delay relationships

Charact

Real-t

Exter

Exte

Prob

Pro

Int

Internal TLA7SAxx to module trigger delay (Typical)

Internal TLA7SAxx to module arm delay (Typical)

Internal module to TLA7SAxx signal delay (Typical)

eristic

ime signal uncertainty (Typical)

nal trigger in to probe tip (Typical)

rnal signal in to probe tip (Typical)

e tip to external trigger out (Typical)

be tip to external signal out (Typical)

ernal TLA7SAxx to module signal delay (Typical)

A7SAxx to TLA7SAxx

LA7SAxx to TLA7Axx

LA7SAxx to TLA7Bxx

TLA7SAxx to TLA7Sxx

TLA7SAxx to TLA7SAxx

TLA7SAxx to TLA7Axx

TLA7SAxx to TLA7Bxx

TLA7SAxx to TLA7Sxx

TLA7SAxx to TLA7SAxx

TLA7SAxx to TLA7Axx

TLA7SAxx to TLA7Bxx

TLA7SAxx to TLA7Sxx

TLA7Axx to TLA7SAxx

TLA7Bxx to TLA7SAxx

TLA7Sxx to TLA7SAxx

tion

Descrip

te Offset ±15 ns

Data Ra

Gen1 = 98 ns

Gen2 = 4 ns

0ns

Gen3 =

690 ns + real-time signal uncertainty

715 ns + real-time signal uncertainty

920 ns + real-time signal uncertainty

900 ns + real-time signal uncertainty

144 ns + real-time signal uncertainty

114 ns + real-time signal uncertainty

-319 ns + real-time signal uncertainty

-107 ns + real-time signal uncertainty

127 ns + real-time signal uncertainty

112 ns + real-time signal uncertainty

-336 ns + real-time signal uncertainty

-153 ns + real-time signal uncertainty

136 ns + real-time signal uncertainty

104 ns + real-time signal uncertainty

-320 ns + real-time signal uncertainty

-47 ns + real-time signal uncertainty

154 ns + real-time signal uncertainty

562 ns + real-time signal uncertainty

374 ns + real-time signal uncertainty

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 9

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations

Table 12: Module input/trigger/backplane delay relationships (cont.)

Characteristic Description

Internal module to TLA7SAxx trigger delay (Typical)

TLA7Axx to TLA7SAxx

TLA7Bxx to TLA7SAxx

TLA7Sxx to TLA7SAxx

Internal module to TLA7SAxx arm delay (Typical)

TLA7Axx to TLA7SAxx

TLA7Bxx to TLA7SAxx

TLA7SAxx to TLA7SAxx

TLA7Sxx to TLA7SAxx

136 ns + real-time signal uncertainty

545 ns + real-time signal uncertainty

385 ns + real-time signal uncertainty

130 ns + real-time signal uncertainty

544 ns + real-time signal uncertainty

136 ns + real-time signal uncertainty

363 ns + real-time signal uncertainty

Table 13: Storage control

Characteristic Description

Initial storage state The initial storage state can be set to store all or s tore none at the

beginning of each acquisition.

start/stop storage trigger machine actions can b e used to change the

The storage state during the acquisition.

Table 14: Data placement

Characteristic Description

System time zero placement error (Typical)

Timestamp accuracy (Typical)

Data correlation error (Typical) Timestamp accuracy + System time zero placement error

Timestamp counter

Resolution 936 ps

Duration

2.4.18 Conﬁguration Memory Characteristics

±3.75 ns + 10 MHz backplane skew

±5 ns

292 hours (12 days)

Table 15: Conﬁguration memory

Characteristic Description

Nonvolatile memory retention time (Typical) NVRAM 10 years minimum data retention rate. The length of time that

FPGA images and other information stored in FLASH memory is retained in the absence of power to the instrument.

10 TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation

TLA7SA08 & TLA7SA16 Logic Protocol Analyzer Modules Speciﬁcations

Table 16: Mecha

Characteristic Description

Material

Weight

Overall dimensions

nical

TLA7SA08

TLA7SA16

Height

Width

Length

Chassis parts are constructed of aluminum alloy. The front panel is constructed of plastic laminated to steel front panel. Circuit boards are constructed

6lbs(2.72k

7 lbs (3.18 kg)

10.32 in (262 mm)

2.39 in (61 mm)

14.7 in (37

of glass laminate.

3 mm)

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 11

P67SA01SD Probe Speciﬁcations

P67SA01SD Pro

Table 17: Ele

Characteristic Description

General

Number of inputs 1 differential input

Input

Input impe

Minimum peak-to-peak differential input amplitude

Maximum

Input Co

ctrical speciﬁcation for P67SA01SD probe

dance (Typical)

nondestructive input signal to probe

mmon mode range

be Speciﬁcations

AC coupled 174  resistor in series with 1 f and terminating with 50 

268 V

p-p diff

±6.3 V

Table 18: Cable speciﬁcations for P67SA01SD probe

Characteristic Description

Physical length

6ft(1.8m)

Table 19: Atmospheric characteristics for P67SA01SD probe

Characteristic Description

Temperature

Humidity

Altitude

Operating

0 °C to +50 °C, with 15 °C/hour maximum gradient, noncondensing,

ated 1 °C per 300 meters (~1000 ft) above 1500 meters (~5000 ft)

der altitude

noperating

0 °C to +71 °C, with 15 °C/hour maximum gradient

-4

perating

% to 95% relative humidity (%RH) up to +30 °C

5% to 75% RH up to +50 °C

Nonoperating

5% to 95% RH up to +30 °C

5% to 60% RH up to +71 °C

Operating

Up to 3,000 meters (~10,000 ft), derate maximum operating temperature by 1 °C per 300 meters (~1000 ft) above 1500 meters (~5000 ft) altitude

Nonoperating

Up to 12000 meters (~40,000 ft)

12 TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation

P67SAxx Midbus Probe Speciﬁcations

P67SAxx Midbu

Table 20: Ele

Characteristic Description

General

Input

Input imp

Minimum peak-to-peak differential input amplitude

Maximum

Input common mode range ±6.3 V

ctrical speciﬁcation for P67SAxx midbus probe

edance (Typical)

nondestructive input signal to probe

s Probe Speciﬁcations

P67SA08 16 differential pairsNumber of inputs

P67SA16 16 differential pairs

AC couple 450  resistor in series with 1 f and terminating with 50 

268 mV

±6.3 V

p-p diff

Table 21: Atmospheric characteristics for P67SAxx midbus probe

Characteristic D escription

Temperature

Humidity

Altitude

Operating

0 °C to +50 °C, with 15 °C/hour maximum gradient, non-condensing, derated 1 °C per 1000 feet above 5000 feet altitude

Nonoperating

-40 °C to +71 °C, with 15 °C/hour maximum gradient

Operating

5% to 95% relative humidity (%RH) up to +30 °C

5% to 75% RH up to +50 °C

Nonoperating

5% to 95% RH up to +30 °C

5% to 60% RH up to +71 °C

Operating

Up to 3,000 meters (~10,000 ft), derate maximum operating temperature by 1 °C per 300 meters (~1000 ft) above 1500 meters (~5000 ft) altitude

Nonoperating

Up to 12000 meters (~40,000 ft)

Table 22: Mechanical characteristics for P67SAxx midbus probe

Characteristic Description

Weight

P67SA08 1 lb 0 oz (0.45 kg)

P67SA16 1 lb 14 oz (0.85 kg)

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 13

P67SAxxS Slot Interposer Speciﬁcations

P67SAxxS Slot

Table 23: Ele

ctrical speciﬁcation for P67SAxxS slot interposer

Interposer Speciﬁcations

Characteristic Description

General

Number of Inputs

P67SA16S 32 (16 upstream + 16 downstream) differential pairs

P67SA08S 16 (8 upstream + 8 downstream) differential pairs

P67SA04S 8 (4 upstream + 4 downstream) differential pairs

P67SA01S 2 (1 upstream + 2 downstream) differential pairs

Probe ga

800 mV

p-p diff

minimum

Gain is deﬁned as the differential peak-to-peak out put voltage divided by the differential peak-to-peak voltage at the probe tip.

l vary from channel to channel. Some channels may have gains up

Gain wil to approximately 3 dB at 800 mV

p-p diff

Output amplitude (Typical)

m output voltage

Minimu

800 mv

Maximum output voltage 1400 mv

Maximum output voltage 1600 mv

, with 800 mv

p-p diff

, with 800 mv

p-p diff

, with 1200 mv

p-p diff

input

Channel delay and skew – Through path (Typical)

±100 ps

Delay

P67SA08S, P67SA04S,

650 ps

P67SA01S

P67SA16S

890 ps ±100 ps

Input

Input impedance (Typical) 42.5 , single ended, 85  differential

Minimum peak-to-peak differential input amplitude

268

p-p diff

(Typical)

Maximum nondestructive input signal to probe 1.8 V

nput common mode range

p-p diff

Table 24: Cable speciﬁcations for P67SAxxS slot interposer

Characteristic Description

Physical length

6ft(1.8m)

14 TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation

P67SAxxS Slot Interposer Speciﬁcations

Table 25: Mecha

Characteristic Description

Overall dimensions Refer to the Probe Dimension section in the Tektronix Logic Protocol

Weight

nical characteristics for P67SAxxS slot interposer

Analyzer Solutions for PCI Express 3.0 Instruction Manual (Tektronix part number, 077-

P67SA16S 3 lb 12 oz (1.

P67SA08S 1 lb 15 oz ( 0.

P67SA04S 1 lb 2 oz (0.

P67SA01S 0 lb 10 oz ( 0

0400-xx)

7kg)

88 kg)

51 kg)

.28 kg)

Table 26: Atmospheric characteristics for P67SAxxS slot interposer

Characteristic Description

Temperature

Humidity

Altitude

Operating

0 °C to +50 °C, with 15 °C/hour maximum gradient, noncondensing, derated 1 °C per 300 meters (~1000 ft) above 1500 meters (~5000 ft) altitude

Nonoperating

-40 °C to +71 °C, with 15 °C/hour maximum gradient

Operating

5% to 95% relative humidity (%RH) up to +30 °C

5% to 75% RH up to +50 °C

Nonoperating

5% to 95% RH at up to +30 °C

5% to 60% RH at up to +71 °C

Operating

Up to 3,000 meters (10,000 ft), derate maximum operating temperature by 1 °C per 300 meters (~1000 ft) above 1500 meters (~5000 ft) altitude

Nonoperating

Up to 12000 meters (~40,000 ft)

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 15

P67SA16G2 Midbus Probe Speciﬁcations

P67SA16G2 Mid

Table 27: Ele

Characteristic Description

General

Number of inputs 16 differential pairs

Input

Input impe

Minimum peak-to-peak differential input amplitude

Maximum

Input common mode range ±6.3 V

Weight

ctrical speciﬁcation for P67SA16G2 midbus probe

dance (Typical)

nondestructive input signal to probe

bus Probe Speciﬁcations

AC coupled 450  resistor in series with 1 f and terminating with 50 

268 mV

p-p diff

±6.3 V

1lb15oz(0.88kg)

Table 28: Atmospheric characteristics for P67S16AG2 midbus probe

Characteristic Description

Temperature

Humidity

Altitude

Operating

0 °C to +50 °C, with 15 °C/hour maximum gradient, non-condensing, derated 1 °C per 1000 feet above 5000 feet altitude

Nonoperating

-40 °C to +71 °C, with 15 °C/hour maximum gradient

Operating

5% to 95% relative humidity (%RH) up to +30 °C

5% to 75% RH up to +50 °C

Nonoperating

5% to 95% RH up to +30 °C

5% to 60% RH up to +71 °C

Operating

Up to 3,000 meters (~10,000 ft), derate m aximum operating temperature by 1 °C per 300 meters (~1000 ft) above 1500 meters (~5000 ft) altitude

Nonoperating

Up to 12000 meters (~40,000 ft)

16 TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation

P6716G3 Midbus Probe Speciﬁcations

P6716G3 Midbu

Table 29: Ele

Characteristic Description

General

Number of inputs 16 differential pairs

Input

Input impe

Minimum peak-to-peak differential input amplitude

Maximum

Input common mode range ±7.5 V

ctrical speciﬁcation for P6716G3 midbus probe

dance (Typical)

nondestructive input signal to probe

s Probe Speciﬁcations

AC coupled 450  resistor in series with 1 f and terminating with 50 

120 mV

p-p diff

±7.5 V

Table 30: Atmospheric characteristics for P67S16AG3 midbus probe

Characteristic D escription

Temperature

Humidity

Altitude

Operating

0 °C to +50 °C, with 15 °C/hour maximum gradient, non-condensing, derated 1 °C per 1000 feet above 5000 feet altitude

Nonoperating

-40 °C to +71 °C, with 15 °C/hour maximum gradient

Operating

5% to 95% relative humidity (%RH) up to +30 °C

5% to 75% RH up to +50 °C

Nonoperating

5% to 95% RH up to +30 °C

5% to 60% RH up to +71 °C

Operating

Up to 3,000 meters (~10,000 ft), derate maximum operating temperature by 1 °C per 300 meters (~1000 ft) above 1500 meters (~5000 ft) altitude

Nonoperating

Up to 12000 meters (~40,000 ft)

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 17

P6716G3 Midbus Probe Speciﬁcations

18 TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation

Performance Veriﬁcation Procedures

There are no customer self-service performance veriﬁcation procedures for the TLA7SA08 or TLAS7SA16 Logic Protocol Analyzer modules. To verify the performance to your local Tektronix ofﬁce. However, you can perform a functional check. (See page 20, Functional Veriﬁcation.)

of your logic protocol analyzer module, you must return the module

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 19

Functional Check Procedures

Functional Ch

eck Procedures

Functional Veriﬁcation

Power-On and Extended

Diagnosti

Functional Extended diagnostics, and acquiring a signal from the SUT.

Do the following steps to run the power-on and extended diagnostics:

NOTE. Run

save any of the acquired data, do so before running the extended diagnostics.

You will need a mainframe with a logic protocol analyzer module installed in the mainframe.

NOTE. If you control your logic analyzer from a remote location, make sure

that you select Run Power-on Diagnostics in the TLA Connection dialog box. Other

veriﬁcation procedures consist of running the Power-on diagnostics,

ning the extended diagnostics will invalidate any acquired data. To

wise the instrument will bypass the power-on diagnostics.

Perform the following tests to complete the functional veriﬁcation procedure:

1. If you have not already done so, power on the instrument.

The instrument runs the power-on diagnostics each time that you power-on the instrument. If any failures occur, the diagnostic window will appear.

2. Go to the System menu and select Calibration and Diagnostics.

3. Scroll through the list of tests and verify that all power-on diagnostics pass.

NOTE. Allow the instrument to warm up for 30 minutes before continuing with the

Extended diagnostics.

4. Click the Extended Diagnostics tab.

5. Select the top-most selection for your module in the list of tests. For example,

if your logic protocol analyzer module is installed in Slot 3 of your mainframe, select Slot 3:TLA7SA08 - SA.

6. Select the type of test that you want to run (One Time, Continuous, or Until Fail).

7. Click Run to start the tests.

20 TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation

Functional Check Procedures

All tests that d status depending on the outcome of the tests.

8. After the test instrument passes all tests.

NOTE. Installing a module in the mainframe provides a means of verifying

connectivity and communication between the module and the mainframe. If the instrument fails any test, try using a different module and repeat the tests to isolate the problem to the mainframe or to the module.

isplayed an "Unknown" status will change to a Pass or Fail

s have completed, scroll through the list and verify that the

TLA7SA08 & TLA7SA16 Series Product Speciﬁcations & Performance Veriﬁcation 21

Tektronix TLA7SA16, P67SA08 Performance Verification

Specifications and Main Features

Frequently Asked Questions

User Manual