Tektronix Logic Analyzers
TLA7PG2 Pattern Generator Module
Breakthrough Solutions for Real-time Digital Systems Analysis
Features & Benefits
64 Channel Modules with Up to
2 Mb Vector Depth
Up to 268 MHz Clock Rate
Supports TTL/CMOS, ECL,
PECL/LVPECL, LVDS, LVCMOS
Standard Logic Levels
Variable Probe for Supporting
Variable Voltage Levels and Delay
of Two Channels for Functional
Verification
Pattern Sequencing Control of
Vector Output Allows Flexible
Definition of Complex Events
Works with All TLA700 Series
Logic Analyzer Mainframes
Applications
Digital Hardware Verification
and Debug
Digital Hardware Simulation
and Debug
Hardware and software engineers need
the ability to generate digital stimuli to
simulate infrequently encountered test
conditions in hardware design and
software program testing. A pattern
generator enables you to perform
functional verification, debugging and
stress testing for system hardware
design. This multi-channel, programmable
pattern generator module with sequential
control stimulates a prototype with data
from a simulator for extended analysis.
The pattern generator is ideal for designing
systems where surrounding boards, ICs
or buses that normally provide digital
signals to the device under test are
missing. With the pattern generator, you
can place a circuit in a desired state,
operate it at full speed or single-step it
through a series of states.
The TLA7PG2 features 64 channels and
supports up to a 268 MHz clock rate for
data output. The TLA7PG2 is made
compatible with numerous voltage levels
and technologies through the use of
external pattern generator probes.
The TLA7000 Series logic analyzers
capture waveform data in a form that
can be read by SynaptiCAD
WaveFormer Pro, VeriLogger Pro and
TestBencher Pro software tools.
SynaptiCAD’s tools can convert the
logic analyzer waveform data into stim-
ulus vectors for VHDL, Verilog, SPICE,
ABEL and pattern generators, including
the TLA7PG2. This functionality gives
engineers the ability to leverage the
work done during the design phase of
a product, simplifying the development
of a hardware test environment that
provides complete test coverage and
excellent debug capability.
Tektronix Logic Analyzers
TLA7PG2 Pattern Generator Module
Easily Create TLA7PG2 Stimulus Files – The TLA7PG2 Pattern Generator stimulus can be created
from a mixture of VHDL and Verilog test benches, simulation waveforms, real world data acquired by
a logic analyzer and waveforms created within SynaptiCAD’s timing diagram editing environment.
Characteristics
General
Data Width –
64 Channel full channel mode.
32 Channel half channel mode.
Module “Merging” – Up to five modules can be
“merged” to make up to a 320 channel module.
Merged modules exhibit the same depth as the
lesser of the 5 individual modules.
Number of Mainframe Slots Required – 2.
Data Rate – Internal Clock:
0.5 Hz to 134 MHz full channel mode.
1.0 Hz to 268 MHz half channel mode.
External Clock:
DC to 134 MHz full channel mode.
DC to 268 MHz half channel mode.
External Clock Input –
Polarity: positive or negative.
Threshold: –2.56 V to +2.54 V, nominal; programmable in 20 mV increments.
Sensitivity: <500 mV
Impedance: 1 kΩ terminated to ground.
Data Depth –
256 Kb full channel/512 Kb half channel.
1 Mb full channel/2 Mb half channel (optional).
.
p-p
Pattern Sequencing
Characteristics
Blocks – Separate sections of pattern program
that are output in a user definable order by the
Sequencer. Block pattern depth can be from 40
sequences (full channel mode) or 80 sequences
(half channel mode) up to the entire depth of the
TLA7PG2. A maximum of 4,000 Blocks may
be defined.
Sequencer – A 4,000 line memory that allows the
user to pick the output order of individual Blocks.
Each line in the sequencer allows the definition of a
Block to be output, a Repeat Count for that Block, A
Wait For event condition for the Block, the Signal
state for that Block (asserted or unasserted), and a
Jump If event Condition, with a sequence line to
jump to if the condition is satisfied.
Sub-sequences – Up to 256 contiguous lines of
the Sequencer memory may be defined as a Subsequence. A Sub-sequence can then be treated like
a block. (Example: 15 Sequences of Blocks are
defined as Sub-sequence A1. Now any line in the
Sequencer can output A1. Five calls to Subsequence A1 will be flattened out to 75 sequences
at run time.)
Jump If – Jumps to the specified sequence if
a user defined event is true. The user defined event
is a boolean combination of the eight external
event input.
Wait For – Pattern output is paused until the user
defined Event is true. One Wait For may be defined
for every Block.
Assert Signal – One of the four inter-module
signals is selected to be controlled from the pattern
generator program. Signals may be asserted and
unasserted allowing true interaction with the logic
analyzer modules and with other pattern generator
modules. Signal action (assert or unassert) may be
defined for every Block.
Repeat Count – The sequence is repeated from 1
to 65,536 times. Infinite may also be selected. One
Repeat Count may be defined for every block. Note
that a repeat value of 10,000 takes one sequence
line in memory, not 10,000.
Step – While in Step mode, the TLA7PG2, the user
can manually satisfy (i.e., click an icon) Wait For and
Jump conditional events. This allows the user to
debug the logic flow of the program’s sequencing.
Initialization Block – The unconditional Jump
command allows the user to implement an
equivalent function.
Logic Analyzer/Pattern Generator Connectivity to
Simulation Environments – The TLA600 and
TLA700 Series logic analyzers capture waveform
data in a form that can be read by SynaptiCAD
WaveFormer Pro, VeriLogger Pro, and TestBencher
Pro software tools. SynaptiCAD’s tools can convert
the logic analyzer waveform data into stimulus
vectors for VHDL, Verilog, SPICE, ABEL, and pattern
generators including the TLA7PG2.
SynaptiCAD’s WaveFormer Pro product offers a
timing diagram editing environment that enables
stimulus to be created using a combination of
graphically drawn signals, timing parameters that
constrain edges, clock signals and temporal and
Boolean equations for describing complex, quasirepetitive signal behavior.Advanced operations on
signals such as time scaling and shifting, and block
copy and pasting of signal behavior over an interval
of time are also supported.
Logic Analyzers • www.tektronix.com/logic_analyzers
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P6470 TTL/CMOS Probe
Number of Data Outputs –
16 in Full Channel Mode.
8 in Half Channel Mode.
Number of Clock Outputs – 1. (Only one of Clock
Output and Strobe Output can be enabled.)
Number of Strobe Outputs – 1. (Only one of Clock
Output and Strobe Output can be enabled.)
Clock Output Polarity – Positive.
Strobe Type – RZ only.
Strobe Delay – Zero or Trailing Edge.
Output Type –
HD74LVC541A for Data Output.
HD74LVC244A for Clock/Strobe Output.
Rise/Fall Time (20% to 80%) – Timing values
measured using 75 Ω termination (internal to
probe), 1 MΩ + <1 pF load and VOH set to 5.0 V
Clock/Strobe Output –
Rise: 640 ps typical.
Fall: 1.1 ns typical.
Data Output –
Rise: 680 ps typical.
Fall: 2.9 ns typical.
Rise/Fall Time (20% to 80%) – Timing values
measured using 75 Ω termination (internal to
probe), 510 Ω + 51 pF load and V
set to 5.0 V.
OH
Clock/Strobe Output –
Rise: 6.5 ns typical.
Fall: 6.3 ns typical.
Data Output –
Rise: 5.2 ns typical.
Fall: 4.5 ns typical.
Series Terminator Resistor – 75 Ω standard; 43,
100 and 150 Ω optional.
Output Voltage (nominal, load: 1 MΩ)– V
.
OH
2.0 V to 5.5 V, tri-statable, programmable in
25 mV increments.
Data Output Skew –
<570 ps typical between all data output pins of all
modules in the mainframe after inter-module skew
is adjusted manually.
<440 ps typical between all data output pins of
single probe.
Data Output to Strobe Output Delay – 1.7 ns
typical when strobe delay set to zero.
Data Output to Clock Output Delay – 2.4 ns typical.
External Clock Input to Clock Output Delay –
Full channel mode: 61 ns typical.
Half channel mode: 61 ns typical.
Number of External Event Inputs – 1.
Number of External Inhibit Inputs – 1.
P6470. P6471.
External Inhibit Input to Output Enable Delay –
34 ns typical for Data Output.
External Inhibit Input to Output Disable Delay –
86 ns typical for Data Output.
Probe D Data Output to Output Enable Delay –
(for Internal Inhibit) 7 ns typical for Data Output.
Probe D Data Output to Output Disable Delay –
(for Internal Inhibit) 8 ns typical for Data Output.
External Event Input to Clock Output Setup (for
inhibit) (event-filter: off) –
Full channel mode: 1.5 clocks + 240 ns typical.
Half channel mode: 2 clocks + 240 ns typical.
External Event Input and Inhibit Input –
Input Type: 74LVC14A.
Minimum Pulse Width: 200 ns.
P6471 ECL Probe
Number of Data Outputs –
16 in Full Channel Mode.
8 in Half Channel Mode.
Number of Clock Outputs – 1. (Only one of Clock
Output and Strobe Output can be enabled.)
Number of Strobe Outputs – 1. (Only one of Clock
Output and Strobe Output can be enabled.)
Clock Output Polarity – Positive.
Strobe Type – RZ only.
Strobe Delay – Zero or Trailing Edge.
Output Type –
100E151 for data output.
100EL16 for strobe output.
100EL04 for clock output.
All outputs are unterminated.
Rise/Fall Time (20% to 80%) – Timing values
measured using 51 Ω to –2.0 V.
Clock Output –
Rise: 320 ps typical.
Fall: 330 ps typical.
Tektronix Logic Analyzers
TLA7PG2 Pattern Generator Module
Data Output –
Rise: 1200 ps typical.
Fall: 710 ps typical.
Strobe Output –
Rise: 290 ps typical.
Fall: 270 ps typical.
Data Output Skew –
<255 ps typical between all data output pins of all
modules in the mainframe after inter-module skew
is adjusted manually.
<210 ps typical between all data output pins of
single probe.
Data Output to Strobe Output Delay – 2.94 ns
typical when strobe delay set to zero.
Data Output to Clock Output Delay – 780 ps typical.
External Clock Input to Clock Output Delay –
50 ns typical.
Number of External Event Inputs – 2.
External Event Input –
Input Level: ECL. Terminated with 75 KΩ, –2V.
Input Type: 10H116.
Minimum Pulse Width: 150 ns.
P6472 PECL/LVPECL Probe
Number of Data Outputs – 8 in full channel mode
or half channel mode.
Number of Clock Outputs – 1. (Only one of clock
output and strobe output can be enabled.)
Number of Strobe Outputs – 1. (Only one of clock
output and strobe output can be enabled.)
Number of External Event Inputs – 2.
Number of External Inhibit Inputs – 0.
Clock Output Polarity – Positive.
Strobe Type – RZ only.
Strobe Delay – Zero or Trailing Edge.
Output Type –
100EP90 for data output.
Logic Analyzers • www.tektronix.com/logic_analyzers
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