xx
P6450
Logic Analyzer Probe
ZZZ
with D-Max™ Probing Technology
Instruction Manual
There are no current European directives that apply to this
product. This product provides cable and test lead connections
to a test object of electronic measuring and test equipment.
Warning
The servicing instructions are for use by qualified personnel
only. To avoid personal injury, do not perform any servicing
unless you are qualified to do so. Refer to all safety summaries
prior to performing service.
www.tektronix.com
P071247801*
*
071-2478-01
Copyright © Tektronix. All rights reserved. Licensed software products are owned by Tektronix or its subsidiaries
or suppliers, and are protected by national copyright laws and international treaty provisions.
Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication
supersedes that in all previously published material. Specifications and price change privileges reserved.
TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.
D-Max is a registered trademark of Tektronix, Inc. MagniVu is a trademark of Tektronix, Inc.
cLGA is a registered trademark of Amphenol Intercon Systems, Inc.
Velcro is a registered trademark of Velcro Industries B.V.
Contacting Tektronix
Tektro ni
14150 SW Karl Braun Drive
P.O . B ox 5 0 0
Beaverton, OR 97077
USA
For pro
x, Inc.
duct information, sales, service, and technical support:
In North America, call 1-800-833-9200.
World wi de, vis i t www.tektronix.com to find contacts in your area.
Warranty
Tektronix warrants that this product will be free from defects in materials and workmanship for a p eriod of one (1)
year from the date of shipment. If any such product proves defective during this warranty p eriod, Tektronix, at its
option, either will repair the defective product without charge for parts and labor, or will provide a replacement
in exchange for the defective product. Parts, modules and replacement products used by Tektronix for warranty
work may be n
the property of Tektronix.
ew or reconditioned to like new performance. All replaced parts, modules and products become
In order to o
the warranty period and make suitable arrangements for the performance of service. Customer shall be responsible
for packaging and shipping the defective product to the service center designated by Tektronix, with shipping
charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a location w ithin
the country in which the Tektronix service center is located. Customer shall be responsible for paying all shipping
charges, duties, taxes, and any other charges for products returned to any other locations.
This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate
maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a) to repair damage
result
b) to repair damage resulting from improper u se or connection to incompatible equipment; c) to repair any damage
or malfunction caused by the use of non-Tektronix supplies; or d) to service a product that has been modified or
integrated with other products when the effect of such modification or integration increases the time or difficulty
of servicing the product.
THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THE PRODUCT IN LIEU OF ANY
OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY
IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
TRONIX' RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE
TEK
AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY.
TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL,
OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS
ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
[W2 – 15AUG04]
btain service under this warranty, Customer must notify Tektronix of the defect before the expiration of
ing from attempts by personnel other than Tektronix representatives to install, repair or service the product;
Table of Contents
General safety summary ............ ................................ ................................ .............. iv
Service safety summary........................................................................................... vi
Compliance Information......................................................................................... vii
Environmen
Preface ........... ................................ ................................ .................................. ix
Related Documentation ...................................................................................... ix
Commonly Used Terms ....................................................................................... x
Operating Basics ............ ................................ ................................ ....................... 1
Product Description ........................................................................................... 1
Attachi
Connecting the Probes to the Logic Analyzer ........................ ................................ ..... 5
Connecting the Probes to the Target System ............................................................... 6
Dressing the Probe Cables ........ ................................ ................................ .......... 11
Storing the Probe Head....................................................................................... 12
Reference .......................................................................................................... 13
gning an Interface Between the Probes and a Target System..................... .................. 13
Desi
Board Design ..... ................................ .................................. .......................... 16
Probe Footprint Dimensions................................................................................. 20
Other Design Considerations ............................................................................... 21
Probe Pinout Defi nition and Channel Assignment . ... . ... ... . ... .... ... . .. . ... . ... ... . ... ... . ... ... . ... . 23
Specifications ...................... ................................ ................................ ................ 25
chanical and Electrical Specifications .................. .................................. .............. 25
Me
Maintenance........................................................................................................ 27
Probe Calibration ............... .................................. ................................ ............ 27
Functional Check ............................................................................................. 27
Inspection and Cleaning.................................... .................................. ................ 27
Service Strategy................... ................................ ................................ ............ 27
Legacy Probe and Attachment Support .................................................................... 28
Repackaging Instructions ...................... ................................ .............................. 29
Replaceable Parts ....................... ................................ .................................. ........ 31
Parts Ordering Information ... ................................ ................................ .............. 31
Using the Replaceable Parts List ..... .................................. ................................ .... 31
Index
tal Considerations ...................... .................................. ..................... vii
ng Probe Labels ....................................................................................... 2
P6450 High-Density Logic Analyzer Probe Instruction Manual i
Table of Contents
List of Figure
Figure i: Flying lead set........................... .................................. ............................... x
Figure ii: P
Figure 1: P6450 High-Density probewith D-Max probing technology....................................... 1
Figure 2: Attaching labels to the P6450 probe ............... ................................ ................... 4
Figure 3: Connecting the logic analyzer probe......................................... ......................... 5
Figure 4: Installing the probe retention a ssembly.. ... . ... ... . ... ... . ... . .. . ... . ... ... . ... ... . ... .... ... . ... ... . 7
Figure 5: Proper handling of the interface clip.................................................................. 8
Figure 6:
Figure 7: Proper dressing of the probe cables.... ................................ .............................. 11
Figure 8: Protecting the probe head ......... .................................. ................................ .. 12
Figure 9: P6450 probe dimensions ........ .................................. ................................ .... 16
Figure 10: Alternate retention assembly dimensions ...................... ................................ .... 17
Figure 11: Keepout area ........ ................................ .................................. ................ 17
Figur
Figure 13: End-to-end layout ........................ .................................. .......................... 18
Figure 14: Signal routing on the target system................................................................. 19
Figure 15: High-Density probe load model......................................... ............................ 20
Figure 16: Probe footprint dimensions on the PCB.......................................... .................. 21
Figure 17: Optional Via-in-Pad placement recommendation..................................... ............ 22
gure 18: P6450 single-ended PCB footprint pinout detail.................................................. 23
Fi
Figure 19: Replacing the cLGA clip ................ .................................. .......................... 28
Figure 20: P6450 High-Density probe accessories .. ................................ .......................... 33
Figure 21: Optional accessories...................... .................................. .......................... 34
robe example.......................................................................................... xi
Connecting the probes to the target system ..................... ................................ ..... 9
e 12: Side-by-side layout................................................................................... 18
s
ii P6450 High-Density Logic Analyzer Probe Instruction Manual
List of Tables
Table i: Product documentation.................................................................................. ix
Table 1: Pro
Table 2: Logic analyzer clock and qualifier availability . . ... . ... ... . ... .... ... . ... ... . ... . ... ... . ... . ... ... . . 13
Table 3: 2X Demultiplexing source-to-destination channel assignments .. ... . ... .... ... . ... ... . ... ... . ... . 14
Table 4: Channel assignment for a P6450 single-ended logic analyzer probe.................... .......... 23
Table 5: M echanical and electrical specifications........................ ................................ ...... 25
Table 6: Environmental specifications .. .................................. ................................ ...... 25
Table 7: P
Table 8: Manufacturers cross index ....... ................................ ................................ ...... 32
Table 9: P6450 replaceable parts list ............................................................................ 32
Table 10: P6450 Probe optional accessories.................................................................... 33
be section and label combinations.................................................................. 2
arts list column descriptions...................................... .................................. .. 31
Table of Contents
P6450 High-Density Logic Analyzer Probe Instruction Manual iii
General safety summary
General safet
To avoid fire or personal
injury
ysummary
Review the fo
this product or any products connected to it.
To avoid pot
Only qualified personnel should perform service procedures.
While using this product, you may need to access other parts of a larger system.
Read the safety sections of the other component manuals for warnings and
cautions r
Connect and disconnect properly.Connect the probe output to the measurement
instrument before connecting the probe to the circuit under test. Connect the
probe reference lead to the circuit under test before connecting the probe input.
Disconnect the probe input and the probe reference lead from the circuit under test
before
Ground the product.This product is indirectly grounded through the grounding
condu
conductor must be connected to earth ground. Before making connections to
the input or output terminals of the product, e nsure that the product is properly
grounded.
disconnecting the probe from the measurement instrument.
ctor of the mainframe power cord. To avoid electric shock, the grounding
llowing safety precautions to avoid injury and prevent damage to
ential hazards, use this product only as specified.
elated to operating the system.
Observe all terminal ratings. To avoid fire or shock hazard, observe all ratings
and markings on the product. Consult the product manual for further ratings
information before making connections to the product.
The inputs are not rated for connection to mains or Category II, III, or IV circuits.
Do not apply a potential to any terminal, including the common terminal, that
exceeds the maximum rating of that terminal.
Power disconnect.The power cord disconnects the product from the power source.
Donotblockthepowercord;itmustremain accessible to the user at all times.
Do not operate without covers. Do not operate this product with covers or panels
removed.
Do not operate with suspected failures. If you suspect that there is damage to this
product, have it inspected by qualified service personnel.
Avoid exposed circuitry. Do not touch exposed connections and components when
power is present.
Use proper fuse.Use only the fuse type and rating specified for this product.
iv P6450 High-Density Logic Analyzer Probe Instruction Manual
General safety summary
Terms in this manual
Symbols and terms on the
product
Do not operate i
Do not operate in an explosive atmosphere.
Keep product surfaces clean and dry.
Provide prop
on installing the product so it has proper ventilation.
These terms may appear in this manual:
WAR N ING.
in injury or loss of life.
CAUTION
damage to this product or other property.
These t
erms may appear on the product:
DANGER indica t es an injury hazard immediately accessible as you read
the ma
n wet/damp conditions.
er ventilation.Refer to the manual's installation instructions for details
Warning statements identify conditions or practices that could result
. Caution statements identify conditions or practices that could result in
rking.
WARNING indicates an injury hazard not immediately accessible as you
the marking.
read
CAUTION indicates a hazard to property including the product.
The following symbol(s) may appear on the product:
P6450 High-Density Logic Analyzer Probe Instruction Manual v
Service safety summary
Service safet
ysummary
Only qualifie
safety summary and the General safety summary before performing any service
procedures.
Do not service alone. Do not perform internal service or adjustments of this
product unless another person capable of rendering first aid and resuscitation is
present.
Disconnect power. To avoid electric shock, switch off the instrument power, then
disconnect the power cord from the mains power.
Use care when servicing with power on. Dangerous voltages or currents may exist
in this p
test leads before removing protective panels, soldering, or replacing components.
To avoi
d personnel should pe rform service procedures. Read this Service
roduct. Disconnect power, remove battery (if applicable), and disconnect
d electric shock, do not touch exposed connections.
vi P6450 High-Density Logic Analyzer Probe Instruction Manual
Compliance Information
This section lists the EMC (electromagnetic compliance), safety, and
environmental standards with which the instrument complies.
Environmental Considerations
This section provides information about the environmental impact of the product.
Product En
riction of Hazardous
Rest
Substances
d-of-Life
Handling
Observe the following guidelines when recycling an instrument or component:
Equipment recycling. Production of this equipment required the extraction and
use of nat
harmful to the environment or human health if improperly handled at the product’s
end of life. To avoid release of such substances into the environment and to
reduce the use of natural resources, we encourage you to recycle this product in
an appropriate system that will ensure that most of the materials are reused or
recycled appropriately.
This product is classified as Monitoring and Control equipment, and is outside the
scope of the 2002/95/EC RoHS Directive.
ural resources. The equipment may contain substances that could be
This symbol indicates that this product complies with the applicable European
Union requirements according to Directives 2002/96/EC and 2006/66/EC
on waste electrical and electronic equipment (WEEE) and batteries. For
information about recycling options, check the Support/Service section of the
Tektronix Web site (www.tektronix.com).
P6450 High-Density Logic Analyzer Probe Instruction Manual vii
Compliance Information
viii P6450 High-Density Logic Analyzer Probe Instruction Manual
Preface
Related Documentation
This document provides information on using and s ervicing the P6450 logic
analyzer probe.
The following table lists related documentation that is available for your
instrumen
t. The documentation is available on the TLA Documentation CD and
on the Tektronix Web site (www.Tektronix.com/manuals).
For docum
entation not specified in the table, contact your local Tektronix
representative.
Table i: Product documentation
Item Purpose Location
vel operational overview
TLA Quick Start User Manual
Online Help
Installation Quick Reference
Cards
Installation Manuals
of Logic Analyzers
XYZs
Product Specifications TLA product specification
TPI.NET Documentation
Field upgrade kits
High-le
In depth operation and UI help
High-level installation information
Detailed first-time installation
rmation
info
Introduction to logic analyzer basics
documents
Detailed information for controlling
the logic analyzer using .NET
Upgrade information for your logic
analyzer product
Optional Service Manuals Self-service documentation for
modules and mainframes
P6450 High-Density Logic Analyzer Probe Instruction Manual ix
Preface
Commonly Used
Terms
cLGA
Compression Footprint
D-Max probing technology
Flying Lead Set
Refer to the following list of commonly used terms throughout the manual.
An acronym for compression Land Grid Array, a connector that provides an
electrical connection between a PCB and the probe input circuitry.
A connectorless, solderless contact between your PCB and the P6450 probes.
Connection is obtained by applying pressure between your PCB and the probe
through a cLGA c-spring.
The name that describes the technology used in the P6450 high-density logic
analyzer probe.
A lead set designed to attach to a P6450 probe to provide general-purpose probing
capability. (See Figure i.)
Figure i: Flying lead set
Functional Check
Procedure
Keepout Area
Module
x P6450 High-Density Logic Analyzer Probe Instruction Manual
Functional check procedures verify the basic functionality of the probes by
confirming that the probes recognize signal activity at the probe tips.
An area on a printed circuit board in which component, trace, and/or via placement
may be restricted.
The unit that plugs into a mainframe that provides instrument capabilities such
as logic analysis.
Preface
Module End
PCB
Probe
The end of the pr
An acronym for Printed Circuit Board; also known as Etched Circuit Board (ECB).
The device that connects a module with a target system. (See Figure ii.)
obe that plugs into the module unit.
Probe
Head
SUT
Figure ii: Probe example
The end of the probe that connects to the target system or probe adapter.
An acronym for System Under Test; alsoreferredtoastargetsystem.
P6450 High-Density Logic Analyzer Probe Instruction Manual xi
Preface
xii P6450 High-Density Logic Analyzer Probe Instruction Manual
Operating Basics
Product Description
This section provides a brief description of the Tektronix P6450 High-Density
Logic Analyzer Probe, information on attaching color-coded probe labels, and
probe and ada
system.
The P6450 probe is a 34-channel, high-density connectorless probe with D-Max
probing technology (See Figure 1.). The probe consists of one probe head that has
34 channels (32 data and 2 clock/qual).
pter connection instructions from the logic analyzer to the target
Figure 1: P6450 High-Density probewith D-Max probing technology
The following list details the capabilities and qualities of the P6450 probe:
Single-ended data inputs
cLGA contact eliminates need for built-in connector
Footprint supports direct signal pass-through
Supports PCB thickness of 1.27 mm to 6.35 mm (0.050 in to 0.250 in)
Consists of one independent probe head of 34 channels (32 data and 2
clock/quals), and two 34-channel module end connectors.
Narrow 34-channel probe head makes for easier placement and layout
2X mode, (for example, 1:2 demultiplexing) uses one-half of the probe head
Color-coded keyed attachment
P6450 High-Density Logic Analyzer Probe Instruction Manual 1
Operating Basics
Attaching Probe Labels
-3.5 V to +6.5 V i
nput operating range
500 mV minimum single-ended signal amplitude
Minimal loading of 0.7 pF at 20 kΩ to ground
Operation in normal or inverted polarity is acceptable (clock only)
When you purchase the P6450 logic analyzer probe, you must apply the
color-coded labels as described in this section. The labels help you identify the
probe connections at the logic analyzer end and at the target system end.
The following table lists the probe section and label color combinations. (See
Table 1.) Refer to the table and to the following figure when you attach the probe
labels.
(See Figure 2 on page 4.)
Table 1: Probe section and label combinations
Probe
section Channels
A3-A2
D3-D2
C3-C2 CK3,
E3-E2
CK0,
A3:7-0,
A2:7-0
QUAL0,
D3:7-0,
D2:7-0
C3:7-0,
C2:7-0
QUAL3,
E3:7-0,
E2:7-0
Label
color
Brown A1-A0
Blue D1-D0
White
Green
Probe
section Channels
C1-C0 QUAL1,
E1-E0
CK1,
A1:7-0,
A0:7-0
CK2,
D1:7-0,
D0:7-0
C1:7-0,
C0:7-0
QUAL2,
E1:7-0,
E0:7-0
Label
color
Orange
Yellow
Gray
Violet
P6450 Labels
Use the following instructions to attach probe labels to your Tektronix P6450
Logic Analyzer Probe.
NOTE. Always use flat-nosed tweezers to remove the labels from the sheet of
labels. Never peel labels with your fingers. The labels are made of soft vinyl and
can stretch and distort easily. To avoid stretching the label, always grasp it from
the top right corner while removing it from the sheet of labels.
The adhesive on the vinyl labels is extremely strong. Carefully align each label to
the intended outline on the module end and probe head before attaching it to the
probe. Once labels are placed on the probe, they become very difficult to remove.
2 P6450 High-Density Logic Analyzer Probe Instruction Manual
Operating Basics
You will be atta
head. Use the following steps to attach the probe labels:
1. Identify the m
2. From the sheet of labels, locate the color-coded label for the logic analyzer
end of the pr
3. Attach the matching colored labels to the probe head on the other end of the
probe cable
ching labels to the logic analyzer end and both sides of the probe
odule end of the probe cable. (See Figure 2 on page 4.)
obe cable.
. (See Figure 2 on page 4.)
P6450 High-Density Logic Analyzer Probe Instruction Manual 3
Operating Basics
Figure 2: Attaching labels to the P6450 probe
4 P6450 High-Density Logic Analyzer Probe Instruction Manual
Operating Basics
Connecting th
e Probes to the Logic Analyzer
Connect the logic analyzer probe and the optional retaining brackets as shown.
(See Figure 3.) The retaining brackets and hardware ship with the logic analyzer.
Figure 3: Connecting the logic analyzer probe
NOTE. The probe can be connected to the logic analyzer when it is powered on.
P6450 High-Density Logic Analyzer Probe Instruction Manual 5
Operating Basics
Connecting th
e Probes to the Target System
Cleaning the Compression
Footprints
Using the Probe Retention
Assembly
You can connect the P6450 probe to the target system without turning off the
power to the target system. The target system must have the probe retention
assembly ins
The following procedure is recommended to obtain best performance.
CAUTION. T
cleaning the compression footprint.
Prior to c
the board should be properly cleaned, according to the following steps:
1. Use a lin
grade isopropyl alcohol, and gently wipe the footprint surface.
2. Remove
The probe retention assembly provides a housing around the connector footprint
to help stabilize the probe. To install the probe retention assembly on the circuit
d, do the following:
boar
talled. Installation procedures are described on the following pages.
o avoid electrical damage, always power off your target system before
onnecting the probe to the target system, the compression footprints on
t-free, clean-room cloth lightly moistened with electronic/reagent
any remaining lint using a nitrogen air gun or clean, oil-free dry air.
1. Locate the correct footprint. If you intend to use multiple probes, your PCB
ultiple footprints. Be careful to select the correct one.
has m
2. Clean the compression footprint as described above .
3. Align the retention assembly over the footprint so that the keying pin on the
retention assembly lines up with the keying pin hole on the footprint. (See
gure4onpage7.)
Fi
4. Insert the retention assembly into the holes in the footprint on the PCB.
OTE. The following two steps are important to ensure that the retention assembly
N
is correctly mounted and that the probe makes proper contact with the PCB.
5. Hold the retention assembly so that it is firmly flush with the surface of
the footprint, and the four anchoring posts extend through the circuit board
to the opposite side.
6. Using a pair of needle-nose pliers, grasp one of the posts. Using the circuit
board hole as a fulcrum, bend the post outward so that it is flush with the PCB
6 P6450 High-Density Logic Analyzer Probe Instruction Manual
Operating Basics
surface, ancho
same manner. (See Figure 4 on page 7.)
7. Solder the anc
Figure 4: Installing the probe retention assembly
ring the assembly to the PCB. Bend the other three posts in the
horing posts to the PCB. (See Figure 4 on page 7.)
P6450 High-Density Logic Analyzer Probe Instruction Manual 7
Operating Basics
Handling the cLGA
Interface C lip (Probe
Head)
The cLGA interf
Keep the following points in mind when you handle the clip:
Always handle
avoid the contacts in the center. Do not touch the contacts with your fingers,
tools, wipes, or any other devices. (See Figure 5.)
ace clip in the probe head should always be handled with care.
the cLGA interface clip by the outer edges, and be careful to
Figure 5: Proper handling of the interface clip
Do not expose the connector to liquids or dry chemicals.
If the board pad array needs to be cleaned, only use isopropyl alcohol and
lint-free cloth as described above.
Immediately following cleaning, or immediately prior to placement of
connector to circuit board, blow off the board pad array and connector contact
array with clean, oil-free dry air or nitrogen to remove loose debris. First start
e blowing process by aiming away from the array areas, and then sweep
th
across the pad and contact arrays in a repeated motion to remove loose debris.
ace the connector onto the board pad array using the bosses or locator pins
Pl
for alignment. Use care to p revent incidental contact with other surfaces or
edges in the connector contact array area prior to board placement.
Always store the probe head in the protective cover when not in use. (See
Figure 8 on page 12.)
8 P6450 High-Density Logic Analyzer Probe Instruction Manual
Operating Basics
Connect the Probe
Connect the pro
1. Align the silver screw on the probe to the silver side of the retention assembly.
bes using the following steps. (See Figure 6.)
bleshooting Probe
Trou
Connections to the SUT
Figure 6: C onnecting the probes to the target system
2. Start both screws in the retention assembly, and tighten them evenly to ensure
that the probe approaches and ma t es squarely to the PCB. If access is limited,
use the adjustment tool that came with your probe. The probe is completely
ened to the PCB when the screws stop in the assembly.
fast
3. Verify that all of the channels are functional.
The most obvious symptom of a problem with the probe installation is seeing
incorrect data in the logic analyzer acquisition. However, the nature of the
incorrect data has a very consistent characteristic; the data from multiple channels
to a logic low and stay there. Intermittent bad data, or a single dead channel
go
are not failures typically associated with probe installation problems.
lightly move the probe head to either side, or press down on the probe head
1.S
while making new acquisitions. If good data is now being acquired, then the
probe mounting is m ost likely the cause.
2. If good data is not acquired, then remove the probe and check the retention
assembly for too much play. If there is significant play, then the probe
mounting is most likely the cause.
P6450 High-Density Logic Analyzer Probe Instruction Manual 9
Operating Basics
3. If the retentio
the bottom of the assembly and the circuit board surface, then move the probe
with bad data from one logic analyzer probe location to another.
4. If the problem follows the probe, then the probe is the problem. Visually
inspect the cLGA interface clip on the probe for any damage or missing
c-spring metal contacts.
If there is damage to the interface clip, or if any c-spring metal contacts are
missing, replace the cLGA interface clip. (See page 27, Replacing the cLGA
Clip.)
5. If the problem doesn't follow the probe, it is either the logic analyzer or the
probe connection at its previous location. Move the probe back to the original
location to be certain it was not a connection problem at the logic analyzer end.
6. Place another probe in the retention assembly of the original probe. If the new
probe acquires data, then the old probe is probably at fault.
n assembly has minimal play and you cannot see a gap between
10 P6450 High-Density Logic Analyzer Probe Instruction Manual
Operating Basics
Dressing the P
robe Cables
Use the Velcro cable managers to combine the cables together or to help relieve
strain on the probe connections.
Hang the probe cables so that you relieve the tension on the probes at the retention
posts. (See Figure 7.)
Figure 7: Proper dressing of the probe cables
P6450 High-Density Logic Analyzer Probe Instruction Manual 11
Operating Basics
Storing the Pr
obe Head
To protect the interface clip, it is important to properly store the probe head when
the probe is not in use. (See Figure 8.)
Gently slide the probe cover over the probe end and store the probe.
Figure 8: Protecting the probe head
12 P6450 High-Density Logic Analyzer Probe Instruction Manual
Reference
This section provides reference information for the P6450 High-Density Probe
with D-Max probing technology.
Designing an Interface Between the Probes and a Target System
Once you have determined which probe is required, use the following information
to design t
he appropriate connector into your target system board.
Signal Fixturing
This section contains information to consider for signal fixturing.
Considerations
Clocks an
channels. Inputs designated as clocks can cause the logic analyzer to store data.
Qualifiers Clocks Every logic analyzer has some special purpose input channels.
Inputs designated as clocks can cause the logic analyzer to store data. Qualifier
channels can be logically ANDed and ORed with clocks to further define when
the logic analyzer should latch data from the system under test. Routing the
approp
can acquire data correctly. Unused clocks can be used as qualifier signals.
Depen
a different set of clock and qualifier channels. The following table shows the
clock and qualifier channels available for each module.
Table 2: Logic analyzer clock and qualifier availability
TLA
Module
TLA5201B
TLA5202B
TLA5203B
TLA5204B
Clock Inputs Qualifier Inputs
CLK:0 CLK:1 CLK:2 CLK:3 QUAL:0 QUAL:1 QUAL:2 QUAL:3
××
××××
ЧЧЧЧЧЧ
ЧЧЧЧЧЧЧЧ
dQualifiers. Every logic analyzer has some special purpose input
riate signals from your design to these inputs ensures that the logic analyzer
ding on the channel width, each TLA5000B Series logic analyzer will have
All clock and qualifier channels are stored. The logic analyzer always stores the
logic state of these channels every time it latches data.
Since clock and qualifier channels are stored in the logic analyzer memory, there
is no need to double probe these signals for timing analysis. When switching
from state to timing analysis, all of the clock and qualifier signals will be visible.
This allows you to route signals not needed for clocking to the unused clock
and qualifier channels.
P6450 High-Density Logic Analyzer Probe Instruction Manual 13
Reference
It is a good prac
tice to take advantage of the unused clock and qualifier channels
to increase your options for when you will latch data. Routing several clocks and
strobes in your design to the logic analyzer clock inputs will provide you with a
greater flexibility in the logic analyzer Setup menu.
As an example, look at a microprocessor with a master clock, data strobe, and an
address strobe. Routing all three of these signals to logic analyzer clock inputs
will enable you to latch data on the processor master clock, only when data is
strobed, or only w hen address is strobed. Some forethought in signal routing can
greatly ex
pand the ways in which you can latch and analyze data.
A microprocessor also provides a good example of signals that can be useful
as qualifi
ers. There are often signals that indicate d ata reads versus data writes
(R/W), signals that show when alternate bus masters have control of the processor
buses (DMA), and signals that show when various memory devices are being
used (ChipSel). All of these signals are good candidates for assignment to
qualifier channels.
By logically ANDing the clock with one of these qualifiers you can program the
logic analyzer to store only data reads or data writes. Using the DMA signal as a
qualifier provides a means of filtering out alternate bus master cycles. Chip selects
mit data latching to specific memory banks, I/O ports, or peripheral devices.
can li
Demultiplexing Multiplexed Buses. TLA5000B Series logic analyzers support 2X
demultiplexing. Each signal on a dual multiplexed bus can be demultiplexed into
its own logic analyzer channel. See the following table to d etermine the correct
channel groups to use.
ble 3: 2X Demultiplexing source-to-destination channel assignments
Ta
stination channels receiving target system test data
Source
connecting
annel
ch
groups TLA5204B TLA5203B TLA5202B TLA5201B
3:7-0
A
2:7-0
A
A1:7-0 D1:7-0 D1:7-0 D1:7-0
A0:7-0 D0:7-0 D0:7-0 D0:7-0
C3:7-0 C1:7-0 C1:7-0
C2:7-0 C0:7-0 C0:7-0
E3:7-0 E1:7-0
E2:7-0 E0:7-0
CLK:0 QUAL:1 QUAL:1
CLK:1 QUAL:0 QUAL:0
CLK:2 QUAL:3
CLK:3 QUAL:2
De
D
D
3:7-0
2:7-0
D
D
3:7-0
2:7-0
C3:7-0 C3:7-0
C2:7-0 C2:7-0
14 P6450 High-Density Logic Analyzer Probe Instruction Manual
Reference
When demultipl
the multiplexed bus. Data from the source channels are routed to the destination
channels internal to the logic analyzer. The table 3 shows the mapping of source
channels to destination channels. (See Table 3 on page 14.)
Demultiplexing affects only the main memory for the destination channels. This
means that the MagniVu memory is filled with data from whatever is connected to
the demultiplexing destination channel probe inputs. This provides an opportunity
to acquire high resolution MagniVu data on a few extra channels. Connecting the
demultipl
activity in the MagniVu memory but not the main memory.
High Resolution Timing. The high resolution timing mode provides double the
normal 500 MHz sample rate on one-half of the channels. B y trading half of
the analyzer's channels, the remaining channels can be sampled at a 1 GHz rate
with dou
By taking care to assign critical signals to the demultiplexing source channels, you
can obt
affects only the main memory you will still have the MagniVu data available for
all of the signals that are disconnected from the main memory when you switch
to the high resolution timing modes.
Range recognition . When using range recognizers, the probe groups and probe
chan
most-significant probe group to the least-significant probe group based on the
following order:
ble the memory depth.
ain extra timing resolution where it is most needed. Since demultiplexing
nels must be in hardware order. Probe groups must be used from the
exing data there is no need to connect the destination channels to
exing destination channels to other signals will allow viewing of their
C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3
CK2 CK1 CK0
Probe channels must be from the most-significant channel to the least-significant
channel based on the following order:
76543210
The above examples assumes a 136-channel logic analyzer. The missing channels
in logic analyzers with fewer than 136 channels are ignored.
P6450 High-Density Logic Analyzer Probe Instruction Manual 15
Reference
Board Design
This section provides information that helps you design your PCB mechanically
and electrically for u se with the P6450 probe.
Probe Dimensions
The following figure shows the dimensions for the P6450 probe. (See Figure 9.)
Figure 9: P6450 probe dimensions
16 P6450 High-Density Logic Analyzer Probe Instruction Manual
Reference
Probe Retention Assembly
Dimensions and K eepout
The probe reten
to help stabilize the probe.
All dimension
Figure 10.)
CAUTION. To avoid solder creep, bend the assembly wires out after you insert the
wires in the board, and then solder the wires.
Figure 10: Alternate retention assembly dimensions
The following figure shows the keep out area required for the alternate retention
assembly. (See Figure 11.)
tion assembly provides a housing around the connector footprint
s are per standard IPC tolerance, which is ±0.004 in. (See
Figure 11: Keepout area
TE. Tektronix has provided a 3D CAD solid model file (named
NO
dmax_socket_assembly.stp) for the plastic retention assembly. It also includes
footprint information for your circuit board. The file is attached to this PDF file.
To access the attached file, open the PDF fileandclickonthepaperclipiconon
theleftsideofthedocumentviewer.
P6450 High-Density Logic Analyzer Probe Instruction Manual 17
Reference
Side-by-side and
End-to-end Layout
Dimensions
The following fi
(See Figure 12.)
Figure 12: Side-by-side layout
The following figure shows the dimensions for an end-to-end footprint layout.
(See Figure 13.)
gure shows the dimensions for side-by-side footprint layout.
Figure 13: End-to-end layout
18 P6450 High-Density Logic Analyzer Probe Instruction Manual
Reference
Signal Routing
The following fi
single-ended data configuration. (See Figure 14.)
Figure 14: Signal routing on the target system
gure shows examples of pass-through signal routing for a
Mechanical
Considerations
ctrical Considerations
Ele
This section provides information on compression footprint requirements and
physical attachment requirements.
The PCB holes, in general, do not have an impact upon the integrity of your
signals when the signals routed around the holes have the corresponding return
current plane immediately below the signal trace for the entire signal path from
driver to receiver.
NOTE. For optimum signal integrity, there should be a continuous, uninterrupted
ground return plane along the entire signal path.
This section provides information on transmission lines and load models for
the P6450 probe.
The low-frequency model is typically adequate for rise and fall times of 1 ns
or slower in a typical 25 Ω source impedance environment (50 W runs with a
pass-through connection). For source impedance outside this range, and/or rise
nd fall times faster than 1 ns, use the high-frequency model to determine if a
a
significant difference is obtained in the modeling result.
The compression land pattern pad is not part of the load model. Make sure that
you include the compression land pad in the modeling.
P6450 High-Density Logic Analyzer Probe Instruction Manual 19
Reference
Transmission L
ensure that stubs, which are greater than 1/4 length of the signal rise time, are
modeled as transmission lines.
P6450 Probe Load Model. The following electrical model includes a
low-frequency model of the High-Density Single-Ended Probe. (See Figure 15.)
Figure 15: High-Density probe load model
Probe Footprint Dimensions
Use the probe footprint dimensions to lay out your circuit board pads and holes
for attaching the retention posts. (See Figure 16 on page 21.) If you are using the
alternate retention assembly, all dimensions remain the same as shown below,
except the overall length and width. (See Figure 10 on page 17.) Pad finishes that
are su
ines. Due to the high performance nature of the interconnect,
pported include immersion gold, immersion silver, and hot air solder level.
All dimensions are per standard IPC tolerance, which is ±0.004 in.
. Tektronix recommends using immersion gold surface finish for best
NOTE
performance.
tronix also recommends that the probe attachment holes float or remain
Tek
unconnected to a ground plane. This prevents overheating the ground plane
and promotes quicker soldering of the retention posts to your PCB. The probe
retention posts are designed to allow you to solder the retention posts from either
side of your PCB.
20 P6450 High-Density Logic Analyzer Probe Instruction Manual
Reference
Figure 16: Probe footprint dimensions on the PCB
NOTE. You must maintain a solder mask web between the pads when traces are
routed between pads on the same layer. The solder mask must not encroach onto
the pads within the pad dimensions. (See Figure 11 on page 17.)
Other Design Considerations
Via-in-pad
Traditional layout techniques require vias to be located next to a pad and a signal
ed to the pad, causing a stub and more PCB board area to be used for the
rout
connection. Many new digital designs require you to minimize the electrical
effects of the logic analyzer probing that you design into the circuit board.
Using via-in-pad to route signals to the pads on the circuit board allows you to
minimize the stub length of the signals on your board, thus providing the smallest
intrusion to your signals. It also enables you to minimize the board area that
is used for the probe footprint and maintain the best electrical performance of
your design.
P6450 High-Density Logic Analyzer Probe Instruction Manual 21
Reference
The following fi
Figure 17.). Detail A describes the recommended position of the via with respect
to the pad.
All dimensions are per standard IPC tolerance, which is ±0.004 in.
gure shows a footprint example where two pads use vias. (See
e 17: Optional Via-in-Pad placement recommendation
Figur
22 P6450 High-Density Logic Analyzer Probe Instruction Manual
Reference
Probe Pinout D
efinition and Channel Assignm ent
This section contains probe pinout definitions and channel assignment tables for
the P6450 probe.
P6450 Single-ended
Probewith D-Max probing
technology
The following figure shows the pad assignments, pad numbers, and signal names
for the PCB footprint of the P6450 single-ended logic analyzer probe. (See
Figure 18.) The P6450 probe has 32 data channels, one clock, and one qualifier
for each footprint.
Figure 18: P6450 single-ended PCB footprint pinout detail
The following table lists the channel mapping to a logic analyzer module for a
P6450 single-ended logic analyzer probe. (See Table 4.)
Table 4: Channel assignment for a P6450 single-ended logic analyzer probe
Number of channels 136 136 or 102 136 or 102 136 or 102 68 68 or 34
Pin Signal Probe4 Probe 3 Probe 2 Probe 1 Probe 2 Probe 1
A1 D0 E2:0 A2:0 A0:0
A2 D1 E2:1 A2:1 A0:1
A3
A4 D4 E2:4 A2:4 A0:4
A5 D5 E2:5 A2:5 A0:5
A6
A7
A8
A9
A10 D10 E3:2 A3:2 A1:2
A11 D11 E3:3 A3:3 A1:3
A12
A13 D14 E3:6 A3:6 A1:6
A14 D15 E3:7 A3:7 A1:7
A15
A16 D18 E1:5 D3:5 D1:5
A17 D19 E1:4 D3:4 D1:4
A18
A19 D22 E1:1 D3:1 D1:1
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
CK1 Q3 CK0 CK1 CK3 CK1 CK3
NC NC NC NC NC NC NC
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
C2:0
C2:1
C2:4
C2:5
C3:2
C3:3
C3:6
C3:7
C1:5
C1:4
C1:1
A0:0
A0:1
A0:4
A0:5
A1:2
A1:3
A1:6
A1:7
D1:5 A3:5
D1:4 A3:4
D1:1 A3:1
C2:0
C2:1
C2:4
C2:5
C3:2
C3:3
C3:6
C3:7
P6450 High-Density Logic Analyzer Probe Instruction Manual 23
Reference
Table 4: Channel assignment for a P6450 single-ended logic analyzer probe (cont.)
Number of channels 136 136 or 102 136 or 102 136 or 102 68 68 or 34
Pin Signal Probe4 Probe 3 Probe 2 Probe 1 Probe 2 Probe 1
A20 D23 E1:0 D3:0 D1:0
A21
A22 D24 E0:7 D2:7 D0:7
A23 D25 E0:6 D2:6 D0:6
A24
A25 D28 E0:3 D2:3 D0:3
A26 D29 E0:2 D2:2 D0:2
A27
B1
B2 D2 E2:2 A2:2 A0:2
B3 D3 E2:3 A2:3 A0:3
B4
B5 D6 E2:6 A2:6 A0:6
B6 D7 E2:7 A2:7 A0:7
B7
B8 D8 E3:0 A3:0 A1:0
B9 D9 E3:1 A3:1 A1:1
B10
B11 D12 E3:4 A3:4 A1:4
B12 D13 E3:5 A3:5 A1:5
B13
B14 D16 E1:7 D3:7 D1:7
B15 D17 E1:6 D3:6 D1:6
B16
B17 D20 E1:3 D3:3 D1:3
B18 D21 E1:2 D3:2 D1:2
B19
B20
B21
B22
B23 D26 E0:5 D2:5 D0:5
B24 D27 E0:4 D2:4 D0:4
B25
B26 D30 E0:1 D2:1 D0:1
B27 D31 E0:0 D2:0 D0:0
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
NC NC NC NC NC NC NC
CK2Q2Q0CK2Q1CK2CK0
GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
C1:0
C0:7
C0:6
C0:3
C0:2
C2:2
C2:3
C2:6
C2:7
C3:0
C3:1
C3:4
C3:5
C1:7
C1:6
C1:3
C1:2
C0:5
C0:4
C0:1
C0:0
D1:0 A3:0
D0:7 A2:7
D0:6 A2:6
D0:3 A2:3
D0:2 A2:2
A0:2
A0:3
A0:6
A0:7
A1:0
A1:1
A1:4
A1:5
D1:7 A3:7
D1:6 A3:6
D1:3 A3:3
D1:2 A3:2
D0:5 A2:5
D0:4 A2:4
D0:1 A2:1
D0:0 A2:0
C2:2
C2:3
C2:6
C2:7
C3:0
C3:1
C3:4
C3:5
24 P6450 High-Density Logic Analyzer Probe Instruction Manual
Specifications
Mechanical and Electrical Specifications
The mechanical and electrical specifications for the P6450 probe are listed below.
(See Table 5.) The electrical specifications apply when the probe is connected
between a compatible logic analyzer and a target system.
Refer to the Tektronix TLA5000B Logic Analyzer Product Specifications &
Performance Verification document (available on the Tektronix Logic Analyzer
Family Product Documentation CD or downloadable from the Tektronix Web
site) for a complete list of specifications, including overall system specifications.
Table 5: Mechanical and electrical specifications
Characteristic P6450
Threshold accuracy ±100 mV
Input resistance
Input capacitance 0.7 pF
Minimum digital signal swing 500 mV p-p
Maximum nondestructive input signal to
probe
Delay from probe tip to module input
connector
Probe length
Operating range
20 kΩ ±1%
±15 V
7.33 ns
1.8 m (6 ft)
+6.5Vto-3.5V
The following table lists environmental specifications for the probe. (See Table 6.)
The probe is designed to meet Tektronix standard 062-2847-00 class 5.
Table 6: Environmental s
Characteristic P69xx
Temperature
Operating
Non-operating
Humidity
Altitude Operating
Non-operating
Electrostatic immunity 6 kV
pecifications
0 °C to +50 °C (0 °F to +122 °F)
-51 °C to +71 °C (-60 °F to +160 °F)
10 °C to 30 °C (+50 °F to +86 °F) 95%
relative humidity
30 °C to 40 °C (+86 °F to +104 °F) 75%
relative humidity
40 °C to 50 °C (+104 °F t
relative humidity
9843 ft (3,000 m)
40,000 ft (12,192 m)
o +122 °F) 45%
P6450 High-Density Logic Analyzer Probe Instruction Manual 25
Specifications
26 P6450 High-Density Logic Analyzer Probe Instruction Manual
Maintenance
The P6450 High-Density Logic Analyzer Probe does not require scheduled or
periodic maintenance. Refer to the Functional Check section below to verify
the basic functionality of the probes.
Probe Calib
ration
To confirm that the probes meet or exceed the performance requirements for
published specifications with a compatible logic analyzer module, you must return
the probes
Functional Check
Connect t
in the LA Setup window.
Inspection and Cleaning
CAUTION. To prevent damage during the probe connection process, do not touch
the exposed edge of the interface clip. Do not drag the contacts against a hard
edge o
To maintain a reliable electrical contact, keep the probes free of dirt, dust, and
cont
the c-spring contacts. For more extensive cleaning, use only a damp cloth. Never
use abrasive cleaners or organic solvents.
to your local Tektronix service center.
he logic analyzer probes to a signal source and check for signal activity
r corner.
aminants. Remove dirt and dust with a soft brush. Avoid brushing or rubbing
Service Strategy
The P6450 probe uses replaceable c-spring cLGA c lips. See page 30 for the
replacement procedure. If a probe failure other than the cLGA clip occurs, return
the entire probe to your Tektronix service center for repair.
Replacing the cLGA Clip
P6450 High-Density Logic Analyzer Probe Instruction Manual 27
For replacement part number information, refer to the Replaceable Parts list. (See
Table 9 on page 32.) To replace the clip, do the following:
Maintenance
1. Gently pull one
the entire clip. (See Figure 19.)
2. Align the new c
3. Test the probe to confirm that all channels are functional.
Figure 19: Replacing the cLGA clip
side of the clip away from the probe head and then remove
lip with the probe head and gently snap it into place.
Legacy Probe and Attachment Support
Nexus Technology, a Tektronix Partner, sells accessories that allow you to use
450 probe with legacy attachment connectors.
the P6
Please contact Nexus Technology directly for more information.
Contact Information:
Nexus Technology
Phone: 877-595-8116
Fax: 877-595-8118
28 P6450 High-Density Logic Analyzer Probe Instruction Manual
Repackaging Instructions
Use the original packaging, if possible, to return or store the probes. If the
original packaging is not available, use a corrugated cardboard shipping carton.
Add cushioning material to prevent the probes from moving inside the shipping
container.
Enclose the following information when shipping the probe to a Tektronix Service
Center:
Maintenance
Owner's address
Name and phone number of a contact person
Type of probe
Reason for return
Full des
cription of the service required
P6450 High-Density Logic Analyzer Probe Instruction Manual 29
Maintenance
30 P6450 High-Density Logic Analyzer Probe Instruction Manual
Replaceable Parts
This chapter contains a list of the replaceable components for the P6450 probe.
Use this list to identify and order replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning
change in part number.
Part number
Instrument type or model number
Instrument serial number
Instrument modification number, if applicable
any
Using the Replaceable Parts List
Replaceable Parts
Table 7: Parts list column descriptions
Column Column name Description
1
2 Tektronix part
3 and 4
5
6
Figure & index
number
number
Serial number Column three indicates the serial number at which the part was first effective. Column four
Qty This indicates the quantity of parts used.
Name &
description
TheP6450 probe contains only the cLGA clip as a replaceable part. If probe failure
occurs, return the entire probe to your Tektronix service representative for repair.
Refer to the following list for replaceable items:
Items in this section reference figure and index numbers to the exploded view illustrations
that follow.
Use this part number when ordering replacement parts from Tektronix.
indicates the serial number at which the part was discontinued. No entries indicates the
part is good for all serial numbers.
An item name is separated from the description by a colon (:). Because of space limitations,
an item name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook
H6-1 for further item name identification.
P6450 High-Density Logic Analyzer Probe Instruction Manual 31
Replaceable Parts
Table 7: Parts list column descriptions (cont.)
Column Column name Description
7
8
Mfr. code This indicates the code of the actual manufacturer of the part.
Mfr. part
This indicates the actual manufacturer's or vendor's part number.
number
Abbreviations
Mfr. Code to Manufacturer
Cross Index
Abbreviations conform to American National Standard ANSI Y1.1-1972.
The table titled Manufacturers Cross Index shows codes, names, and addresses of
manufacturers or vendors of components listed in the parts list.
Table 8: Manufacturers cross index
Mfr. cod
80009
e
Manufac
TEKTRO
turer
NIX INC
Address City, st
14150 S
W KARL BRAUN DR PO BOX 500
Table 9: P6450 replaceable parts list
e
Figur
& index
r
numbe
20-1 010-
-2 020-2622-00 2
-3 200-4893-00 1
-4 020-2908-00 1
onix
Tek tr
part
r
numbe
0775-10
020-2539-00 1
6-0300-00
34
3-1890-00
00
071-2478-XX 1
335-1990-00 1
Seria
no.
effec
l
tive
Seria
no.
disco
l
nt’d
Qty Name &
P6450 STANDARD ACCESSORIES
1
1
1
P6450 PROBE (INCLUDES SHEET OF LABELS)
COMP
SAFETY CONTROLLED
ER,PROTECTIVE; BLACK VINYL (PLASTISOL)
COV
WITH STATIC-DISSIPATIVE ADDITIVE
MARY P69XX RETENTION KIT, QTY 2 CONNECTORS
PPI
KIT, RETENTION; P6450
STRAP,VELCRO;ONE WRAP,BLACK,0.500W X
8.00L,QTY 2 BAGGED & LABELED
TOOL,HAND; USED TO TIGHTEN PROBE HEAD TO DUT
ANUAL, TECH; INSTRUCTION, P6450 HIGH DENSITY
M
LOGICANALYZERPROBE
6450 PROBE, SHEET OF LABELS
P
ate, zip code
BEAVER
description
ONENT KIT, CLGA INTERFACE CLIP; 1 EA,
TON, OR 97077-0001
Mfr.
Mfr.
code
9
8000
80009 020-2622-00
80009 200-4893-00
80009 020-2908-00
80009 020-2539-00
009
80
009
80
80009 071-2478-XX
80009 335-1990-00
part
numbe
0775-10
010-
6-0300-00
34
3-1890-00
00
r
32 P6450 High-Density Logic Analyzer Probe Instruction Manual
Replaceable Parts
Figure 20: P6450 High-Density probe accessories
Table 10: P6450 Probe optional accessories
Figure
&index
number
21-1 196-3494-00 1
-2
-3 020-2
-4 020-2910-00 1
-5
nix
Tek tro
part
number
SMG50
908-00
020-2539-00 1
Serial
no.
effect
ive
Serial
no.
discon
t’d
Qty Name & d
2
1
escription
FLYING LEADSET
ADAPTER KIT; BAG OF 20 KLIPCHIP ADAPTER (40
TOTAL)
P69xx ALTERNATE RETENTION ASSEMBLY KIT, QTY 2
ALTERNATE RETENTION ASSEMBLY KIT, QTY 50
P69xx
KIT, RETENTION; P6960/P6980
Mfr.
Mfr.
code
80009 196-3494-00
80009
80009 020-2
80009 020-2910-00
80009 020-2539-00
part
number
SMG50
908-00
P6450 High-Density Logic Analyzer Probe Instruction Manual 33
Replaceable Parts
Figure 21: Optional accessories
34 P6450 High-Density Logic Analyzer Probe Instruction Manual
Index
Symbols and Numbers
3D CAD file, 17
C
Calibration
probe, 27
Cleaning
inspection and, 27
cLGA Inte
Connecting
rface Clip
replacing, 27
probes to logic analyzer, 5
probes to target system, 6
E
Electrical specifications, 25
F
ttachments, 17
file a
Functional check, 27
I
Inspection and cleaning, 27
L
Labels
attaching to the probe, 2
Logic analyzer
onnecting probes, 5
c
M
Maintenance, 27
functional c
inspection and cleaning, 27
probe calibration, 27
repackaging instructions, 29
service strategy, 27
Mechanical specifications, 25
heck, 27
O
Ordering
parts information, 31
P
Parts
ordering information, 31
using the replaceable parts
list, 31
Probes
ration, 27
calib
connecting probes to the logic
analyzer, 5
connecting probes to the target
system, 6
P6450 High Density Probe, 1
duct description, 1
pro
returning, 29
storing, 29
R
Repackaging instructions, 29
Replacing the cLGA interface
clip, 27
Returning probes, 29
S
Safety Summary, iv
Service st
Specifications
Storing probes, 29
rategy, 27
electrical, 25
mechanical, 25
T
Target system
connec
ting probes, 6
P6450 High-Density Logic Analyzer Probe Instruction Manual 35
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