Tektronix MIPI D-PHY, MIPI M-MPHY Reference manual
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Technical Reference
MIPI® D-PHY* Measurements & Setup Library
Methods of Implementation (MOI) for Verification, Debug,
Characterization, Compliance and Interoperability Test
DPOJET
077-0428-01
Opt. D-PH
Y
www.tektronix.com
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Copyright:
No part(s) of this document may be disclosed, reproduced or used for any purposes other than as needed to
support the use of the products of MIPI® Alliance members.
Licensed software products are owned by Tektronix or its suppliers and are protected by United
States copyright laws and international treaty provisions. Tektronix products are covered by U.S. and foreign
patents, issued and pending. Information in this publication supersedes that in all previously published
material. Specifications and price change privileges reserved.
TEKTRONIX, TEK and RT-Eye are registered trademarks of Tektronix, Inc.
Contacting Tektronix
Tektronix, Inc.
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Beaverton, OR 97077 USA
For product information, sales, service, and technical support:
• In North America, call 1-800-833-9200.
• Worldwide, visit www.tektronix.com to find contacts in your area.
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Contents
INTRODUCTION ..................................................................................................................................................... 5
ELECTRICAL CHARACTERISTICS .............................................................................................................................. 6
GROUP 1: Data Lane LP TX ELECTRICALS ........................................................................................................... 7
Test 1.1.1 – Data Lane LP-TX Thevenin Output High Level Voltage (VOH).................................................... 7
Test 1.1.2 – Data Lane LP-TX Thevenin Output Low Level Voltage (VOL) ..................................................... 9
Test 1.1.3 – Data Lane LP-TX 15%-85% Rise Time (TRLP) ............................................................................ 10
Test 1.1.4 – Data Lane LP-TX 15%-85% Fall Time (TFLP) ............................................................................. 12
Test 1.1.5 – Data Lane LP-TX Slew Rate vs. CLOAD (δV/δtSR) .................................................................... 13
GROUP 2: Clock Lane LP TX ELECTRICALS ........................................................................................................ 17
GROUP 3: HS TX ELECTRICAL TESTS ................................................................................................................. 18
TEST 1.3.1 – DATA LANE HS ENTRY: DATA LANE TLPX VALUE ..................................................................... 18
Test 1.3.2 – Data Lane HS Entry: THS-PREPARE Value ............................................................................... 20
Test 1.3.3 – Data Lane HS Entry: THS-PREPARE + THS-ZERO Value............................................................. 22
Test 1.3.4 – Data Lane HS TX Differential Voltage (VOD) ............................................................................ 25
Test 1.3.5 – Data Lane HS TX Differential Voltage Mismatch (∆VOD) ......................................................... 29
Test 1.3.6 – Data Lane HS TX Single-Ended Output High Voltage (VOHHS) ................................................ 30
Test 1.3.7 – Data Lane HS TX Static Common-Mode Voltage (VCMTX) ...................................................... 35
Test 1.3.8 – Data Lane HS TX VCMTX Mismatch (∆VCMTX(1,0)) ................................................................ 39
Test 1.3.9 – Data Lane HS TX Common-Level Variations Between 50-450 MHz (VCMTX(LF)) .................... 41
Test 1.3.10 – Data Lane HS TX Common-Level Variations Above 450 MHz (VCMTX(HF)) ......................... 44
Test 1.3.11 – Data Lane HS TX 20%-80% Rise Time (tR) .............................................................................. 47
Test 1.3.12 – Data Lane HS TX 20%-80% Fall Time (tF) ............................................................................... 49
Test 1.3.13 – Data Lane HS Exit: THS-TRAIL Value ....................................................................................... 50
Test 1.3.14 – Data Lane LP TX: 30%-85% Post-EoT Rise Time (TREOT) ....................................................... 53
GROUP 4: Clock Lane HS TX ELECTRICAL TESTS ............................................................................................... 55
GROUP 5: HS-TX CLOCK-TO-DATA LANE TIMING REQUIREMENTS ................................................................ 56
Test 1.5.1 – HS Entry: TCLK-PRE Value ........................................................................................................ 56
Test 1.5.2 – HS Exit: TCLK-POST Value ......................................................................................................... 57
Test 1.5.3 – HS Clock Rising Edge Alignment to First Payload Bit ............................................................... 60
Test 1.5.4 – Data-to-Clock Skew (TSKEW(TX)) ............................................................................................. 62
GROUP 6: LP-TX INIT, ULPS, AND BTA REQUIREMENTS .................................................................................. 65
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Test 1.6.3 – ULPS Exit: Transmitted TWAKEUP Interval .............................................................................. 65
Test 1.6.4 – BTA: TX-Side TTA-GO Interval Value ........................................................................................ 67
Appendix A – Resource Requirements ................................................................................................................ 73
Appendix B – DUT Connection ............................................................................................................................ 74
Appendix C – Deskew Procedure ........................................................................................................................ 76
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INTRODUCTION
The tests contained in this document are organized in order to simplify the identification of
information related to a test, and to facilitate in the actual testing process. There is no implied order for
execution of these tests in this document.
The test definitions themselves are intended to provide a high-level description of the
motivation, resources, procedures, and methodologies specific to each test.
Copyright:
No part(s) of this document may be disclosed, reproduced or used for any purpose other than as needed to
support the use of the products of MIPI ® Alliance members
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ELECTRICAL CHARACTERISTICS
Overview:
This selection of tests verifies various Electrical Characteristic requirements of D-PHY* products
defined in Section 8 of the D-PHY* Specification, version 0.9.
Group 1 tests (1.1.x) verify the Data Lane Low-Power TX electrical requirements defined in Section
8.1.2 of the D-PHY Standard.
Group 2 tests (1.2.x) verify the Clock Lane Low-Power TX electrical requirements defined in Section
8.1.2 of the D-PHY Standard.
Group 3 tests (1.3.x) verify the Data Lane High Speed TX electrical requirements defined in Section
8.1.2 of the D-PHY Standard.
Group 4 tests (1.4.x) verify the Clock Lane High Speed TX electrical requirements defined in Section
8.1.2 of the D-PHY Standard.
Group 5 tests (1.5.x) verify the Clock to Data Lane Timing Requirements Specifications.
Group 6 tests (1.6.x) verify several miscellaneous LP-TX timing and behavioral requirements pertaining
to initialization (INIT), Ultra-Low Power State (ULPS) and Bus Turnaround (BTA).
Tektronix, Inc.
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GROUP 1: Data Lane LP TX ELECTRICALS
Overview:
This group of tests verifies the Data Lane Low-Power TX electrical requirements defined in Section
8.1.2 of the D-PHY* Standard.
All the Measurements in group 2 are similar to the measurements in group 1, except that this uses the
clock lanes instead of the data lanes. So connect the Differential clock lane (Vcp, Vcn) to the scope
channels (Ch3 , Ch4) respectively.
Status:
The preliminary draft descriptions for the tests defined in this group are considered complete, and the
tests are pending implementation (during which time additional revisions/modifications are likely to
occur).
Test 1.1.1 – Data Lane LP-TX Thevenin Output High Level Voltage (VOH)
Purpose: To verify that the Thevenin Output High Level Voltage (VOH) of the DUT’s Data Lane LP transmitter is
within the conformance limits.
References:
[1] D-PHY* Standard, Section 8.1.2, Line 1382
[2] Ibid, Section 8.1.2, Table 18
[3] UNH* D-PHY* Conformance Test Suite, ver0.08, Test 1.1.1
Resource Requirements: Real-time DSO, D-PHY* test signal generator.
Last Modification: October 16, 2009
Discussion [3]:
The D-PHY Specification states, “VOH is the Thevenin output, high-level voltage in the high-level state,
when the pad pin is not loaded.” [1].
In this test, the DUT’s Data Lane VOH values will be measured using a high-speed, real-time DSO while
the DUT is driving an LP signaling sequence into an open termination. (Note that this test may be performed
while the DUT is sourcing a fixed LP-11 state, but is typically intended to be performed in conjunction with the
other tests in this group on a single captured LP Escape Mode sequence waveform, in which case the
measurement is performed on the output- high bits only.) For the measurement, VOH is measured as the
mode of all waveform samples that are greater than
50% of the absolute peak-to-peak VDP and VDN signal amplitudes. (Note that this measurement is performed
separately on both the VDP and VDN waveforms, and for each DUT Data Lane.)
The value of VOH for both the VDP and VDN signals for each Data Lane shall be between 1.1 V and 1.3
V in order to be considered conformant [2].
Test Setup: See Appendices A and B.
Test Procedure:
1. Connect the DUT to the Test System (See Appendix A).
2. Create a condition that causes the DUT to source a continuous LP-11 state.
3. Recall setup file “D-PHY_Test_1_1_1_Voh.set”. Press Single button to reach the desired part of
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the signal.
4. Note the value of Mean RMS as VOH.
• Place cursors in the LP-11 part of the signal.
• Go to Measure→ Amplitude→ RMS.
• Ensure that the correct source is chosen and cursor gating is applied.
5. Repeat for Channel 2 (DN) and note the result
.
Observable Results:
• Verify that VOH for the VDP waveform is between 1.1 and 1.3 Volts for each Data Lane.
• Verify that VOH for the VDN waveform is between 1.1 and 1.3 Volts for each Data Lane.
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Test 1.1.2 – Data Lane LP-TX Thevenin Output Low Level Voltage (VOL)
Purpose: To verify that the Thevenin Output Low Level Voltage (VOL) of the DUT’s Data Lane LP transmitter is
within the conformance limits.
References:
[1] D-PHY* Standard, Section 8.1.2, Line 1381
[2] Ibid, Section 8.1.2, Table 18
[3] UNH* D-PHY* Conformance Test Suite, ver0.08, Test 1.1.2
Resource Requirements: Real-time DSO, D-PHY* test signal generator.
Last Modification: October 16, 2009
Discussion [3]:
The D-PHY Specification states, “VOL is the Thevenin output, low-level voltage in the LP transmit
mode. This is the voltage at an unloaded pad pin in the low-level state.” [1].
In this test, the DUT’s Data Lane VOL values will be measured using a high-speed, real-time DSO while
the DUT is driving an LP signaling sequence into an open termination. (Note that this test is intended to be
performed in conjunction with the other tests in this group on a single captured LP Escape Mode sequence
waveform, in which case the measurement is performed on the output-low bits only.) For the purpose of this
measurement, VOL is measured as the mode of all waveform samples that are less than 50% of the absolute
peak-to-peak VDP and VDN signal amplitudes. (Note that this measurement is performed separately on both
the VDP and VDN waveforms, and for each DUT Data Lane.)
The value of VOL for both the VDP and VDN signals for each Data Lane shall be between –50 mV and +50 mV
in order to be considered conformant [2].
Test Setup: See Appendix A and B.
Test Procedure:
1. Connect the DUT to the Test System (See Appendix B).
2. Create a condition that causes the DUT to source a continuous LP-00 state.
3. Load the setup file named D-PHY_Test_1_1_2_Vol.set. (Timebase settings changed to
accommodate more edges)
4. Press single to go to the desired part of the signal
4. Make sure cursors are set to cover only the portion of the waveform where both Dp and Dn
are simultaneously low. Read the Channel1 and Channel2 RMS voltage measurement from the
display.
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Observable Results:
• Verify that VOL for the VDP waveform is between -50 and +50 mV for each Data Lane.
• Verify that VOL for the VDN waveform is between -50 and +50 mV for each Data Lane.
Test 1.1.3 – Data Lane LP-TX 15%-85% Rise Time (TRLP)
Purpose: To verify that the 15%-85% Rise Time (TRLP) of the DUT’s Data Lane LP transmitter is within the
conformance limits.
References:
[1] D-PHY* Specification, Section 8.1.2, Line 1395
[2] Ibid, Section 8.1.2, Table 19
[3] UNH* D-PHY* Conformance Test Suite, ver0.08, Test 1.1.3
Resource Requirements: Real-time DSO, D-PHY* test signal generator.
Last Modification: October 16, 2009
Discussion [3]:
The D-PHY Specification states, “The times TRLP and TFLP are the 15%-85% rise and fall times,
respectively, of the output signal voltage, when the LP transmitter is driving a capacitive load CLOAD. The 15%-
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85 % levels are relative to the fully settled VOH and VOL voltages.” [1].
In this test, the two single-ended VDP and VDN signals from the DUT’s Data Lane LP transmitter will be
captured using two channels of a real-time DSO. Using the measured VOH and VOL LP-TX Thevenin Output
Voltage Levels as references, the 15%-85% Rise Time (TRLP) will be measured independently for each rising
edge of the VDP and VDN waveforms. The mean value across all observed rising edges will be computed to
produce the final TRLP result, and the maximum and minimum observed values will be reported as informative
results.
The value of TRLP for VDP and VDN shall be less than 25ns in order to be considered conformant [2].
Test Setup: See Appendix A and B.
Test Procedure:
1. Connect the DUT to the Test System (See Appendix B).
2. Recall setup “D-PHY_Test_1_1_3_tRLP.set”.
3. Press single to go to the desired part of the signal.
4. Measure TRLP from the Rise time values.
Observable Results:
• Verify that TRLP is less than 25 ns for the VDP waveform for all CLOAD cases for each Data Lane.
• Verify that TRLP is less than 25 ns for the VDN waveform for all CLOAD cases for each Data Lane.
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Test 1.1.4 – Data Lane LP-TX 15%-85% Fall Time (TFLP)
Purpose: To verify that the 15%-85% Fall Time (TFLP) of the DUT’s Data Lane LP transmitter is within the
conformance limits.
References:
[1] D-PHY* Specification, Section 8.1.2, Line 1395
[2] Ibid, Section 8.1.2, Table 19
[3] UNH* D-PHY* Conformance Test Suite, ver0.08, Test 1.1.4
Resource Requirements: Real-time DSO, D-PHY* test signal generator.
Last Modification: October 16, 2009
Discussion [3]:
The D-PHY Specification states, “The times TRLP and TFLP are the 15%-85% rise and fall times,
respectively, of the output signal voltage, when the LP transmitter is driving a capacitive load CLOAD. The 15%
to
85% levels are relative to the fully settled VOH and VOL voltages.” [1].
In this test, the two single-ended VDP and VDN signals from the DUT’s Data Lane LP transmitter will be
captured using two channels of a real-time DSO. Using the measured VOH and VOL LP-TX Thevenin Output
Voltage Levels as references, the 15% to 85% Fall Time (TFLP) will be measured independently for each falling
edge of the VDP and VDN waveforms. The mean value across all observed falling edges will be computed to
produce the final TFLP result, and the maximum and minimum observed values is reported as informative
results.
The value of TFLP for VDP and VDN shall be less than 25 ns in order to be considered conformant [2].
Test Setup: See Appendix A and B.
Test Procedure:
1. Connect the DUT to the Test System (See Appendix B).
2. Recall setup “D-PHY_Test_1_1_4_tFLP.set”.
3. Press single to go to the desired part of the signal.
4. Measure TFLP from the Fall time values.
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Observable Results:
• Verify that TFLP is less than 25 ns for the VDP waveform for all CLOAD cases for each Data Lane.
• Verify that TFLP is less than 25 ns for the VDN waveform for all CLOAD cases for each Data Lane.
Test 1.1.5 – Data Lane LP-TX Slew Rate vs. CLOAD (δV/δtSR)
Purpose: To verify that the Slew Rate (δV/δtSR) of the DUT’s Data Lane LP transmitter is within the
conformance limit, for different capacitive loading conditions.
References:
[1] D-PHY* Specification, Section 8.1.2, Line 1397
[2] Ibid, Section 8.1.2, Table 19 [3] Ibid, Section 8.1.2, Figure 45
[4] UNH* D-PHY* Conformance Test Suite, ver0.08, Test 1.1.5
Resource Requirements: Real-time DSO, D-PHY* test signal generator.
Last Modification: October 16, 2009
Discussion [4]:
The D-PHY Specification states, “The slew rate δV/δtSR is the derivative of the LP transmitter output
signal voltage over time. The slew rate specification shall be met for the 15% - 85% range while driving a
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capacitive load, CLOAD.” [1]. A Figure is provided in the specification that shows a graphical representation of
the Slew Rate conformance range, is reproduced below.
Figure: Slew Rate vs. CLOAD Mask
The specific values are defined in [2] as:
• δV/δtSR into CLOAD = 0pF shall be between 30 and 500 mV/ns.
• δV/δtSR into CLOAD = 5pF shall be between 30 and 200 mV/ns.
• δV/δtSR into CLOAD = 20pF shall be between 30 and 150 mV/ns.
• δV/δtSR into CLOAD = 70pF shall be between 30 and 100 mV/ns.
The specification also states that the maximum Slew Rate requirement is to be measured when the
output voltage is between 15% and below 85% of the “fully settled LP signal levels” and is measured as an
average across any 50 mV segment of the output signal transition.
Also note that the minimum Slew Rate requirement is applicable over the vertical region between 400
and
930 mV across any 50 mV segment of the output signal transition. [2]. (This is different from the applicable
range for the maximum Slew Rate specification.)
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In this test, the two single-ended VDP and VDN signals from the DUT’s Data Lane LP transmitter is
captured using two channels of a real-time DSO. The Slew Rate is measured independently for each edge of the
VDP and VDN signals. Maximum and minimum Slew Rate values is computed and reported for each rising and
falling edge, across the applicable vertical ranges using a 50 mV vertical window. The measurement is repeated
for all CLOAD cases, and for all Data Lanes.
Test Setup: See Appendix A and B.
Test Procedure:
1. Connect the DUT to the Test System (See Appendix B).
2. Configure the load termination for CLOAD = 0pF.
3. Create a condition that causes the DUT to source an LP Escape Mode sequence on Data Lane 0.
4. From the oscilloscope main menu, select Analyze > Jitter and Eye Analysis > Select.
5. Recall setup file D-PHY_Test_1_1_5_SlewrFLP.set.
6. Press Single button on the oscilloscope panel to reach the desired part of the signal.
7. Apply cursors to the specific part of the signal with rising and falling edges.
8. Press Single on DPOJET to make the measurement.
Repeat the previous steps for CLOAD values of 5 pF, 20 pF, and 70 pF.
10. Repeat the previous steps for Data Lanes 1, 2, and 3 (if the DUT implements multiple Data
Lanes).
9.
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Observable Results:
• Verify that the maximum δV/δtSR into a CLOAD of 0 pF is less than 500 mV/ns, for each Data Lane.
• Verify that the maximum δV/δtSR into a CLOAD of 5 pF is less than 200 mV/ns, for each Data Lane.
• Verify that the maximum δV/δtSR into a CLOAD of 20 pF is less than 150 mV/ns, for each Data Lane.
• Verify that the maximum δV/δtSR into a CLOAD of 70 pF is less than 100 mV/ns, for each Data Lane.
• For all load cases, verify that the minimum δV/δtSR is greater than 30 mV/ns, for each Data Lane.
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Test Name
Setup File
Test 1.2.1 – Clock Lane LP-TX Thevenin Output High Level Voltage(VOH)
D-PHY_Test_1_2_1_Voh.set
Test 1.2.2 – Clock Lane LP-TX Thevenin Output Low Level Voltage (VOL)
D-PHY_Test_1_2_2_Vol.set.
Test 1.2.3 – Clock Lane LP-TX 15%-85% Rise Time (TRLP)
D-PHY_Test_1_2_3_tRLP.set”.
Test 1.2.4 – Clock Lane LP-TX 15%-85% Fall Time (TFLP)
D-PHY_Test_1_2_4_tFLP.set”.
Test 1.2.5 – Clock Lane LP-TX Slew Rate vs. CLOAD (δV/δtSR)
D-PHY_Test_1_2_5_SlewrFLP.set
Tektronix, Inc.
GROUP 2: CLOCK LANE LP TX ELECTRICALS
All the Measurements in this group are similar to the measurements in Group 1, except that this uses the clock
lanes instead of the data lanes. So connect the Differential clock lane (Vcp, Vcn) to the scope channels (Ch3 ,
Ch4) respectively.
The Table below gives the setups used for these group2 measurements
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GROUP 3: HS TX ELECTRICAL TESTS
Overview:
This group of tests verifies the High Speed TX electrical requirements of the data lane as defined in the
D-PHY* Standard.
TEST 1.3.1 – DATA LANE HS ENTRY: DATA LANE TLPX VALUE
Purpose: To verify that the HS AC Common-Mode Signal Level Variations above 450 MHz (VCMTX(HF)) of the
DUT transmitter are below the maximum allowable limit.
References:
[1] D-PHY* Specification, Section 5.2, Line 746
[2] Ibid, Section 5.9, Table 14
[3] UNH* D-PHY* Conformance Test Suite, ver0.08, Test 1.3.1
Resource Requirements: Real-time DSO, D-PHY* test signal generator.
Last Modification: October 16, 2009
Discussion[3]:
The D-PHY Low-Power (LP) mode of operation is comprised of state transitions occurring at some
implementation-
specific rate less than 20M transitions/sec. Note that these state transitions may have different meanings
depending on the context (Control, Escape, or LPDT mode), and do not equate to ‘bits’ on the wire. The D-PHY
Specification specifies that, “All LP state periods shall be at least TLPX in duration.” [1], and defines the
minimum value of TLPX to be 50 ns [2].
In this test, the focus is specifically the duration of the last LP-01 state that occurs immediately before
an HS burst sequence. The state will be measured starting at the time where the VDP falling edge crosses
below the maximum low-level LP threshold, VIL,MAX (550 mV), and ending at the time where the VDN falling
edge crosses below the same VIL,MAX threshold. A picture of the TLPX interval is shown in the figure below.
Test Setup: See Appendix A and B.
Test Procedure:
1. Recall setting file “D-PHY_Test_1_3_1_tLPX.set” using the main menu: File/Recall…/Setup
2. Press the Multiview Zoom button and then press Single on the oscilloscope.
3. Verify if the zoom is correctly located as per the diagram shown above.
4. Note the minimum value of Delay between Ch1 and Ch2 at the bottom of the screen.
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5. The value should be greater than 50 ns to meet the required specification.
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Observable Results:
• Verify that TLPX value is greater than 50 ns.
Tektronix, Inc.
Test 1.3.2 – Data Lane HS Entry: THS-PREPARE Value
Purpose: To verify that the duration of the final LP-00 state immediately before HS transmission (THS-
PREPARE) is within the conformance limits.
References:
[1] D-PHY* Specification, Section 5.14.2, Line 1027
[2] Ibid, Section 5.9, Table 14
[3] UNH* D-PHY* Conformance Test Suite, ver0.08, Test 1.3.2
Resource Requirements: Real-time DSO, D-PHY* test signal generator.
Last Modification: October 16, 2009
Discussion [3]:
As part of the process for switching the Data Lane into HS mode, the D-PHY Specification provides a
specification for the minimum time interval that a device must transmit the final LP-00 state before enabling
HS mode (which occurs at the start of the THS-ZERO interval). This interval is defined as THS-PREPARE, and is
shown in the figure below.
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Figure: THS-PREPARE Interval
In this test, the DUT will be configured to source an HS burst sequence, starting and ending with LP-11
states. The THS-PREPARE interval begins at the time where the Data Lane VDN signal crosses below VIL,MAX
(550 mV), and ends at the beginning of the extended THS-ZERO HS differential state, at the point where the
VOD differential voltage crosses above the minimum valid HS-RX differential threshold level (+/-70 mV). The
measured duration of THS-PREPARE should be between (40 ns + 4*UI) and (85 ns + 6*UI) (where UI is the
nominal HS Unit Interval for the DUT) in order to be considered conformant.
Test Setup: See Appendix A and B.
Test Procedure:
1. Recall setting file “D-PHY_Test_1_3_2_tHSprep.set”, using the main menu: File/Recall…/Setup
2. Ensure the cursors are marked at the location as per the diagram above.
3. Note the value of ∆t as THS-PREPARE
4. Calculate the limits (40 ns + 4*UI) and (85 ns + 6*UI). Confirm that as THS-PREPARE is between
these limits.
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Observable Results:
• Verify that THS-PREPARE is within the limits of (40 ns + 4*UI) and (85 ns + 6*UI).
Test 1.3.3 – Data Lane HS Entry: THS-PREPARE + THS-ZERO Value
Purpose: To verify that the combined time of THS-PREPARE plus the time the DUT Data Lane transmitter drives
the HS-0 differential state prior to transmitting the HS Sync sequence (THS-ZERO) is greater than the
minimum required duration.
References:
[1] D-PHY* Standard, Section 5.14.2, Line 1028
[2] Ibid, Section 5.9, Table 14
[3] UNH* D-PHY* Conformance Test Suite, ver0.08, Test 1.3.3
Resource Requirements: Real-time DSO, D-PHY* test signal generator.
Last Modification: October 16, 2009
Discussion [3]:
As part of the process for switching the Data Lane into HS mode, the D-PHY Specification provides a
specification for the minimum duration that a device must drive the extended Data HS-0 differential state
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prior to starting HS differential data transmission. This interval is defined as THS-ZERO, and is shown in the
figure below.
Figure: THS-ZERO Interval
In this test, the DUT will be configured to source an HS burst sequence, starting and ending with LP-11
states. The (THS-PREPARE + THS-ZERO) interval begins at the time where the Data Lane VDN signal crosses
below VIL,MAX (550 mV), and ends at the end of the extended THS-ZERO HS-0 differential state, at the point
corresponding to the start of the first bit of the HS Sync sequence. (Note this point is not at the first HS-1
transition, but rather three HS Unit Intervals prior, as the Sync sequence starts with 0001. Thus there is no
visible delineation between the extended HS-0 and the first HS-0 of the Sync sequence.) The measured
duration of (THS-PREPARE + THS-ZERO) should be greater than (145 ns + 10*UI) ns (where UI is the nominal HS
Unit Interval for the DUT) in order to be considered conformant.
Test Setup: See Appendix A and B.
Test Procedure:
1. Connect the DUT to the Test System (See Appendix A)
2. Recall setup file “D-PHY_Test_1_3_3_tHSp_tHs0.set”. Press Single button to capture the
desired part of the signal.
3. (Note: If you do not see the zoomed portion of the signal, press the Multiview Zoom button.)
4. Ensure that the cursors are placed as per the diagram above. Include both THS-PREPARE + THS-
ZERO
when taking measurement. Note the ∆t value as the total THS-PREPARE + THS-ZERO.
5. Repeat for each data lane.
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