Tektronix Logic Analyzer Solutions for PCI Express 3.0 Primary User

xx

Tektronix Logic Protocol Analyzer Solutions

ZZZ

for PCI Express 3.0

Instruction Manual

TektronixLogic Protocol Analyzer Solutions for PCI Express 3.0

TLA7012/16 Mainframes
TLA Application Software V5.8+
TMS160PCIE3 Software
TLA7SAxx Logic Protocol Analyzer Modules
P67SAxxx Serial Analyzer Probes

www.tektronix.com

P077040003*

*

077-0400-03

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supersedes that in all previously published material. Specifications and price change privileges reserved.

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

DPOJET is a registered trademark of Tektronix, Inc.

PCI Express is a registered trademark of PCI-SIG®.

G3PO is a trademark of Corning Gilbert Inc.

October 25

, 2011

Contacting Tektronix

Tektronix, Inc.
14150 SW
P.O . B o x 5 00
Beaverton, OR 97077
USA

For product information, sales, service, and technical support:

In Nor
World w i de, visit www.tektronix.com to find contacts in your area.

Karl Braun Drive

th America, call 1-800-833-9200.

Warranty

Tektronix warrants that this product will be free from defects in materials and workmanship for a period of one (1)
year from the date of shipment. If any such product proves defective during this warranty period, Tektronix, at its
option, either will repair the defective product without charge for parts and labor, or will provide a replacement
in exchange for the defective product. Parts, modules and replacement products used by Tektronix for warranty
work may be n
the property of Tektronix.

ew or reconditioned to like new performance. All replaced parts, modules and products become

In order to o
the warranty period and make suitable a rrangements for the performance of service. Customer shall be responsible
for packaging and shipping the defective product to the service center designated by Tektronix, with shipping
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This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate
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result
b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any damage
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THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THE PRODUCT IN LIEU OF ANY
OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY
IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

TRONIX' RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE

TEK
AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY.
TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL,
OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS
ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

[W2 – 15AUG04]

btain service under this warranty, Customer must notify Tektronix of the defect before the expiration of

ing from attempts by personnel other than Tektronix representatives to install, repair or service the product;

Warranty

Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on
the media will be free from defects in materials and workmanship for a period of three (3) months from the date of
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Tektronix does not warrant that the functions contained in this software product will meet Customer's requirements
or that the operation of the programs will be uninterrupted or error-free.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration
of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and
workmanship within a reasonable time thereafter, Customer may terminate the license for this software product
and return this software product and any associated materials for credit or refund.

THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THE PRODUCT IN LIEU OF ANY
OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY
IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
TEKTRO
PAYMENT IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH
OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL, O R CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX
OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

[W9b – 15AUG04]

this software product is provided “as is” without warranty of any kind, either express or implied.

NIX' RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER'S

Ta ble of Contents

General Safety Summary ......................................................................................... xi

Service Safety Summary.................. ................................ .................................. ..... xiii

Compliance Information ......................................................................................... xiv

EMC Compliance......... ................................ .................................. ................. xiv

Safety Compliance........................................................................................... xiv

Environmental Considerations ................ ................................ ............................. xvi

Preface ............................................................................................................ xvii

Related Documentation .................................................................................... xvii

Product Description ....... .................................. ................................ ....................... 1

TLA7SA16 x8 Logic Protocol Analyzer Module .................................. ................... 1

TLA7SA08 x4 Logic Protocol Analyzer Module .................................. ................... 1

Midbus Probes...... .................................. ................................ ..................... 2

Slot Interposer Probes ............................... ................................ ..................... 2

Solder-Down Probe ............................ ................................ ........................... 3

Logic Protocol Analyzer Module Controls and Connectors ............... ............................... 4

Front Panel................................ ................................ ................................ . 4

LED Indicators ............................................................................................ 7

Logic Protocol Analyzer and Logic Analyzer Compatibility .... . . . . . . . . . . . . .................... . . . . . . . . . 9

Options and Accessories.......................................................................................... 10

Install Common Hardware........................................................................................ 15

Connecting the Instrument to the SUT ............................ .................................. ............ 16

Clock Cable ................................................................................................... 18

Connecting a Clock Cable .............. ................................ ................................ 18

Connecting a Clock Jumper Cable..................................................................... 18

Connecting a Probe to the Logic Protocol Analyzer Module.............. .............................. 19

Connect the Midbus Probe................................................................................... 19

Handling the Probe Head ....................... .................................. ...................... 20

Connect the Probe........................................................................................ 21

Arranging the Midbus Probe Cables. ................................ ................................ .. 22

Connect the Slot Interposer Probe .......................................................................... 23

Handling the Probe Head ....................... .................................. ...................... 23

Connect the Probe........................................................................................ 23

Connecting a Probe to a x16 Link.......................... ................................ ............ 25

Optional Lane Adapters Installation Overview..................................... .................. 27

Installing the Slot SUT Card Support Bracket . . . . . . . . .................. . . . . . . . . . . ............... . . . . . 28

Connect the Solder Down Probe ............................................................................ 30

Connect to the Logic Protocol Analyzer Module..................................................... 30

P75TLRST Solder Tip........... ................................ .................................. ...... 31

Applying and Removing Power............................................................................. 34

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual i

Table of Contents

Install the TMS

Set Up the Logic Protocol Analyzer Module ............................. ................................ ...... 37

Setup Window ................. ................................ .................................. .................. 38

Open the Setup Window ..................................................................................... 39

Monitoring Signal Activity .... ................................ .................................. ............ 41

Auto Configuration . ................................ ................................ .......................... 42

Link Rate Controls....................................................................................... 43

SUT Reference Clock ........... ................................ ................................ ........ 44

Descramble and Deskew ........ ................................ .................................. ...... 45

Defining a Data Filter.. . . . . . . . . . . . . . . ...................... . . . . . . . . . . . . . . ................... . .. . . . . . . . . . . 45

Maximum Idle Time Detector .......................................................................... 45

Assigning Lanes.. ................................ .................................. ...................... 45

Multimodule Configurations................................................................................. 47

Probe Calibration .................................................................................................. 48

Calibrate the Probes .................. ................................ ................................ ........ 49

Calibration Results Table Overview ............................. ................................ ...... 50

Probe Recalibration Information ... .................................. ................................ .. 51

Trigger Window ........................... ................................ .................................. ...... 52

Open the Trigger Window ............................. ................................ ...................... 52

Add States, Clauses, Events, and Actions to the Trigger Window .. .................................. .. 53

Delete States, Clauses, Events, and Actions from the Trigger Window .. .............................. 54

Trigger Events........................... ................................ ................................ ...... 54

Create a TLP Event ...................................................................................... 55

Create a DLLP Event.................................................................................... 56

Create a Link Event.............................. ................................ ........................ 57

Create a Sequence Event ................ .................................. .............................. 58

Event Counter, Global Counter, and Timer Overview ................. .............................. 59

Create a Signal-In Event ................................................................................ 60

Trigger Actions ............................................................................................... 60

Acquiring and Viewing Data ..................................................................................... 61

Transaction Window .... ................................ .................................. ........................ 62

Transaction View ....................... .................................. ................................ .... 62

Status Area ............................ ................................ ................................ ........ 63

Packet View ................................................................................................... 63

Examining Transactions...................................... .................................. .............. 64

Physical Layer View.......................................................................................... 64

Using the Transaction Window with the Listing Window ............................................... 65

Bird’s Eye View ................... ................................ ................................ ................ 66

Viewfinder ................................................................................................ 66

Location Bar........ ................................ ................................ ...................... 67

Flow Control Visualization Overview...................................................................... 68

160PCIe3 Support Software ................................................................... 35

ii Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Table of Contents

Configure the Fl

Flow Control Statistics .................................................................................. 69

Summary Profile Window ........................ ................................ ................................ 70

Summary Statistics Tab Notebook Information ............................. .............................. 71

Element Table Information .................................................................................. 72

Create a Custom Element .................. ................................ ................................ .. 74

Listing Window.......... .................................. ................................ ........................ 75

Add Two Sides of a Link to a Single Listing Window . ................................ .................. 76

Change the Data Display in the Listing or Waveform Windows .................... .................... 76

Bus-Specific Fields ... ................................ ................................ ........................ 77

10-Bit Mode Acquisition.. . . . . . . . . . . . . . ................... . . . . . . . . . . . . . . . .................... . . . . . . . . . . . . .... 78

Change from Binary Listing Symbol Tables to 10-Bit Mode.... .................................. ...... 78

Disassembler Special Messages.................................... .................................. ............ 79

Vendor Defined Message (VDM) Support...................................................................... 81

Probe Dimensions ................................................................................................. 83

Midbus Probe Cable Dimensions .. ................................ ................................ .... 83

P67SA08 Midbus Probe Head Dimensions ........................................................... 84

P67SA08G2 Midbus Probe Head Dimensions ....................................................... 85

P67SA16 Midbus Probe Head Dimensions ........................................................... 86

P67SA16G2 Midbus Probe Head Dimensions ....................................................... 87

Slot Interposer Probe Cable Dimensions .............................................................. 88

P67SA16 Slot Interposer Probe Dimensions...................................... .................... 88

P67SA08S, P67SA04S, and P67SA01S Slot Interposer Probe Dimensions ........ . . . . . . . . . . .... 89

Circuit Board Design........ .................................. ................................ .................... 94

Mechanical Design ........................................................................................... 94

Footprint Dimensions and Keep-Out Area ................................ ............................ 94

Routing Considerations for the Midbus Probe Footprint .......................................... 101

Midbus Probe CAD Symbols for PCB Layout .......................................................... 103

P67SA01SD Probe Solder Tips ........................................................................... 104

TriMode Resistor Solder Tip ......................................................................... 105

Tip Topology ........................................................................................... 105

Soldering the Tips.................. ................................ ................................ .... 106

Reference Clock Cable Three-Pin Connector ............................. .............................. 109

Electrical Design............................................................................................ 111

Measuring Signal Eye ................................................................................. 111

P67SAxx Midbus Probe Circuit Impact ............................................................. 112

P67SA16G2 x8 or P67SA08G2 x4 Midbus Probe Circuit Impact ............... ................ 113

P67SAxx Slot Interposer Probe Circuit Impact..................................... ................ 114

P67SA01SD Solder-Down Probe Circuit Impact .............................. .................... 115

Reference Clock Signal .................................................................................... 117

Recognize the Reference Clock Signal by Connecting to the SUT with a Clock Cable ....... 117

ow Control Visualization......................................... .................... 69

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual iii

Table of Contents

Recognize the C

Midbus Footprint Pin and Probe Input Assignments .................... ................................ .... 119

General Guidelines for Lane Mapping ................................................................... 120

x8 PCI Express Midbus Pin Assignments............... ................................ ............ 121

x4 PCI Express Midbus Pin Assignments............... ................................ ............ 124

P67SA16G2 x8 Midbus Probe Pin Assignments ................................................... 127

P67SA08G2 x4 Midbus Probe Pin Assignments ................................................... 128

Diagnostics ............. .................................. ................................ ........................ 129

Power-On Diagnostics ....................... ................................ .............................. 129

Extended Diagnostics ...................................................................................... 129

Troubleshooting.................................................................................................. 130

General Troubleshooting............. .................................. ................................ .... 130

Probe Troubleshooting ..................... ................................ ................................ 131

Using the P67UHDSMA Probe .......... .................................. .......................... 131

Care and Maintenance .................... .................................. ................................ .... 136

Exterior Inspection ..................... ................................ ................................ .... 136

Inspection and Cleaning...................................... .................................. ............ 137

Module Exterior Cleaning Procedure................................................................ 137

Probe Retention Mechanism Cleaning Procedure.................................................. 137

Probe Cleaning Procedure ............................ ................................ ................ 137

Cleaning the Probe Head.......... ................................ .................................. .. 138

Storing the Probe............................................ ................................ ................ 138

Repackaging Instructions .............................. .................................. .................. 138

Appendix A: TLA Application Software ............. .................................. ...................... 139

Updating the Logic Protocol Analyzer Module Firmware ............................................. 139

Appendix B: File Attachments ....................... .................................. ........................ 141

Probe Electrical Simulation Models.. .................................. ................................ .. 141

Midbus Probe CAD Symbols for PCB Layout .......................................................... 142

Midbus Probe 3D CAD Models........................................................................... 143

Slot Interposer Probe 3D CAD Models .................................................................. 144

DSP Filter Files for Probe Troubleshooting ......... . . . . . . . . . . . . .................... . . . . . . . . . . . . ........ 144

Appendix C: Installing the Midbus Retention M echanism . .............................. .. .. . . . . . . . . . . . . . . 145

Cleaning the Footprint ................... ................................ .................................. 145

Installing the Midbus Retention Mechanism . . . . . ................... . . . . . . . . . . .................... . . . . . . 145

Installing the Retention Mechanism for the P67SA08 or P67SA16 Midbus Probes . . . . . . . .... 146

Appendix D: System Design Review Checklist.............................................................. 151

General Considerations ............................ .................................. ...................... 151

Midbus Probe Configuration .............................................................................. 151

Mechanical Considerations.......... ................................ .................................. .... 151

Electrical Considerations ...................... ................................ ............................ 153

lock Signal Embedded in the Data Stream....................................... 118

iv Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Table of Contents

Appendix E: Rea

Appendix F: Adding Probes to the P67SA01SD Probe Connector ........................................ 159

Appendix G: Solder-Down Probe Bullets..................................................................... 161

Removing the Bullets ...................... ................................ ................................ 161

Inspecting the Bullets and Connectors ................................................................... 163

Installing the Bullets..... . . . . . . . . . . . . . .................... . . . . . . . . . . . . .................. . . . . . . . . . . . . ........ 163

Glossary

Index

rranging Wires in the Probe Connector ................... ................................ 155

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual v

Table of Contents

List of Figure

Figure 1: P67SA16 x8 midbus probe............ .................................. ............................... 2

Figure 2: P67SA08S x8 Slot interposer probe ......... ................................ ......................... 3

Figure 3: P67SA01SD Solder-Down probe ..................................................................... 4

Figure 4: TLA7SA08 logic protocol analyzer front panel ....... ................................ ............. 5

Figure 5: TLA7SA16 logic protocol analyzer front panel ....... ................................ ............. 6

Figure 6: Installing a module. . . .................... . . . . . . . . . . . . .................... . . . . . . . . . . . . .................. 15

Figure 7: Installation overview .................................................................................. 16

Figure 8: Clock cable and clock jumper

Figure 9: Connecting a probe to the retention mechanism.......................... .......................... 21

Figure 10: Arranging the midbus probe cables................................................................. 22

Figure 11: Connecting a slot interposer probe ....................... .................................. ........ 24

Figure 12: Installing an optional slot probe adapter . . . . . . . .................... . . . . . . . . . . . . .................... 27

Figure 13: Slot SUT card s upport bracket configurations..................................................... 29

Figure 14: Installing the P67SA01SD probe . . . . . . . ................ . . . . . . . . . . . . .................. . . . . . . . . . . .... 31

Figure 15: Connecting the P75TLRST tip to the probe head................................................. 32

Figure 16: Connecting wires to the circuit...................................... ................................ 33

Figure 17: Connecting the tip to the circuit....................................... .............................. 34

Figure 18: Default Setup window ............................................................................... 40

Figure 19: Changes identified in the Setup window ........................... ................................ 42

Figure 20: Setup window with changes from auto configuration ............................................ 43

Figure 21: Changes from the default channel-lane connections...... ................................ ........ 46

Figure 22: Calibration Dashboard, initial setup .................... . . . . . . . . . . . . .................... . . . . . . . . . . . . 48

Figure 23: Calibration Dashboard, calibrated system ..................... .................................. .. 48

Figure 24: Default Trigger window ............................................................................. 52

Figure 25: Specifying a TLP event .............................................................................. 55

Figure 26: Defining a TLP ....................................................................................... 55

Figure 27: Specify

Figure 28: Defining a DLLP ..................................................................................... 56

Figure 29: Specifying a Link event.................................. .................................. .......... 57

Figure 30: Defining a Link event ...... ................................ .................................. ........ 57

Figure 31: Specifying a symbol sequence ...................................................................... 58

Figure 32: Defining a symbol sequence................................. .................................. ...... 58

Figure 33: Event counter ......................................................................................... 59

Figure 34: Specifying a global counter ......................................................................... 59

Figure 35: Specifying a timer ............ ................................ ................................ ........ 59

Figure 36: Transaction window.................................................................................. 62

Figure 37: Side-by-side Transaction window and Listing window .......................................... 65

Figure 38: BEV with Viewfinder and Location Bar ........................................................... 67

s

cable ................... ................................ .............. 18

ing a DLLP event............................................................................ 56

vi Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Table of Contents

Figure 39: BEV C

Figure 40: Opening the Summary Profile window ............................................................ 70

Figure 41: Summary Profile window............................................................................ 71

Figure 42: Summary Profile window (Summary Statistics Tab Notebook)................................. 72

Figure 43: Define Packet window for a Custom element in the Summary Profile window ............... 74

Figure 44: Data displayed in the Listing window.............................................................. 75

Figure 45: P67SA08, P67SA08G2, P67SA16, and P67SA16G2 cable length dimensions ....... . . . . . . . . 83

Figure 46: P67SA08 midbus probe head dimensions ..... .................................. .................. 84

Figure 47: P67SA08G2 midbus probe head dimensions...................................................... 85

Figure 48: P67SA16 midbus probe head dimensions ..... .................................. .................. 86

Figure 49: P67SA16G2 midbus probe head dimensions...................................................... 87

Figure 50: P67SA16S, P67SA08S, P67SA04S and P67SA01S Slot Interposer probe cable lengths .. . . 88

Figure 51: P67SA16S Slot Interposer Probe dimensions ..................................................... 89

Figure 52: P67SA08S, P67SA04S, and P67SA01S Slot Interposer probe dimensions.................... 90

Figure 53: PCI Express Compliance Load Board (CLB1).............. ................................ ...... 91

Figure 54: P75TLRST Solder Tip dimensions ..... .................................. .......................... 91

Figure 55: TriMode Resistor Solder Tip dimensions.......................................................... 92

Figure 56: Connecting the P67SA01SD Solder-Down probe ............ .................................. .. 93

Figure 57: x8 midbus footprint dimensions and keep-out area (front side of circuit board) . . ............ 95

Figure 58: x8 midbus footprint dimension and keep-out area (back side of circuit board) .............. . 96

Figure 59: Footprint pad details for x8 and x4 midbus probes ............................................... 96

Figure 60: x4 midbus footprint dimensions and keep-out area (front side of circuit board) . . ............ 97

Figure 61: x4 midbus footprint dimension and keep-out area (back side of circuit board) .............. . 98

Figure 62: P67SA16G2 x8 Midbus footprint dimensions and keep-out area............................... 99

Figure 63: P67SA08G2 x4 Midbus footprint dimensions and keep-out area............................. 100

Figure 64: Recommended trace routing on the primary surface layer................. .................... 102

Figure 65: P67SA08 x4 midbus probe CAD symbol........................................................ 103

Figure 66: P67SA16 x8 midbus probe CAD symbol........................................................ 103

Figure 67: P75TLRST TriMode Long Reach Solder Tip. ................................ .................. 104

Figure 68: TriMode Resistor Solder Tip ...................................................................... 105

Figure 69: Typical wire length from probe tip to circuit .................................................... 106

Figure 70: P75TLRST solder tip with 0.010 inch of tip wire .............. ................................ 107

Figure 71: P75TLRST solder tip with 0.050 inch of tip wire .............. ................................ 107

Figure 72: P75TLRST solder tip with 0.100 inch of tip wire .............. ................................ 108

Figure 73: P75TLRST solder tip with 0.200 inch of tip wire .............. ................................ 108

Figure 74: Reference clock cable connector dimensions ................................................... 110

Figure 75: Signal eye measurements (time versus voltage) ................................................ 111

Figure 76: Probe impact of the P67SAxx midbus probe ........................ ............................ 112

Figure 77: S-parameter data of retention mechanism only ................................................. 113

Figure 78: S-parameter data of retention mechanism plus P67SA16G2 x8 or P67SA08G2 x4 Midbus

probe ......................................................................................................... 114

onfiguration panel with Flow Control selected ........................................... 69

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual vii

Table of Contents

Figure 79: Prob

Figure 80: S-parameter data of P67SA01SD Solder-Down probe ......................................... 116

Figure 81: Slot interposer probe with a reference clock cable connected ............................. .... 117

Figure 82: P67SA16 x8 midbus probe footprint pin assignments ................. ........................ 119

Figure 83: P67SA08 x4 midbus probe footprint pin assignments ................. ........................ 119

Figure 84: x8 midbus footprint connections for an upstream or downstream configuration ............ 121

Figure 85: x

Figure 86: x8 midbus footprint connections for an upstream and downstream configuration .......... 123

Figure 87: x4 midbus footprint connections for an upstream or downstream configuration ............ 124

Figure 88: x4 midbus footprint connections for an upstream and downstream configuration .......... 125

Figure 89: x4 midbus footprint connections for an upstream and downstream configuration. ......... 126

Figure 90: P67SA16G2 Midbus probe footprint pin assignments ......................................... 127

Figure 9

Figure 92: P67SA08 x4 midbus probe footprint pin assignments ................. ........................ 128

Figure 93: P67SA08G2 x4 midbus footprint connections to module connectors .. ...................... 128

Figure 94: P67UHDSMA probe connected to the inputs of a Tektronix oscilloscope (example 1) . . . . 133

Figure 95: P67UHDSMA probe connected to the inputs of a Tektronix oscilloscope (example 2) . . . . 134

Figure 96: x8 footprint.......................................................................................... 145

Figu

Figure 98: Connecting the P67SA08 midbus probe to the retention mechanism on the circuit board . 148

Figure 99: Installing the retention mechanism ............ . . . . . . . . . . . . . .................... . . . . . . . . . . . . ...... 149

Figure 100: Soldering the anchoring posts to the circuit board (PCB) .. ................................ .. 150

Figure 101: Opening the probe connector .................................................................... 156

Figure 102: Removing the probe sleeve ...................................................................... 156

Fi

Figure 104: Removing individual wires ...... ................................ ................................ 157

Figure 105: Inserting additional probe wires ............................... ................................ .. 159

Figure 106: Replaceable bullets and tool ..................................................................... 161

Figure 107: Removing the bullet contacts .................................................................... 162

Figure 108: Inspect the bullet contacts........................................................................ 163

Figure 109: Installing the bullet contacts . ...................... . . . . . . . . . . . . . . ........................ . . . . . . . . 164

1: P67SA16G2 x8 Midbus footprint connections to module connectors........................ 127

re 97: Connecting the P67SA16 midbus probe to the retention mechanism on the circuit board . 147

gure 103: Probe labels.... ................................ ................................ .................... 157

e impact of the P67SAxxS slot probe................. ................................ ...... 115

8 midbus footprint connections in an upstream and downstream configuration ........... 122

viii Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

List of Tables

Table 1: Front panel indicators and connectors ................................................................. 7

Table 2: Status LEDs............................................................................................... 8

Table 3: TLA7SAxx logic protocol analyzer module standard accessories......................... ........ 10

Table 4: P67SA16 and P67SA08 Midbus probes standard accessories ....... .............................. 10

Table 5: P67SA16 and P67SA08 Midbus probes optional accessories...................................... 10

Table 6: P67SAxxS slot probes standard accessories ......................................................... 11

Table 7: P67SAxxS slot probes optional accessories................ .................................. ........ 11

Table 8: P67SA01SD Solder-Down probe

Table 9: P67SA01SD Solder-Down probe optional accessories ............................................. 12

Table 10: P67SA16G2 x8 Midbus probe standard accessories............................................... 12

Table 11: P67SA08G2 x4 Midbus probe standard accessories............................................... 12

Table 12: P67SA16G2 and P67SA08G2 Midbus probes optional accessories ............................. 13

Table 13: TLA7SAxx logic protocol analyzer module and P67SAxxx probes service options . . ........ 13

Table 14: P67UHDSMA standard accessories ................................................................. 13

Table 15: TLA Modules and midbus probes per link.......................................................... 17

Table 16: TLA Modules and slot interposer probes per link ......................... ........................ 17

Table 17: TLA Modules and solder down probes per link.................................................... 17

Table 18: Status indicators in the Setup window............................................................... 41

Table 19: Channel-lane connector colors ... ................................ ................................ .... 46

Table 20: Trigger events .......................................................................................... 54

Table 21: Trigger event recognizer resources .................. .................................. .............. 54

Table 22: Trigger actions ......................................................................................... 60

Table 23: Special characters in the Listing window ... ................................ ........................ 75

Table 24: Logic protocol analyzer disassembly display options ............................................. 77

Table 25: Training sequence messages.......................... ................................ ................ 79

Table 26: Packet framing messages ............................................................................. 79

Table 27: DLLP mess

Table 28: TLP header messages ..... ................................ .................................. .......... 79

Table 29: CRC checking messages ........................ ................................ ...................... 80

Table 30: General acquisition m essages . . . . . . ...................... . . . . . . . . . . . . ...................... . . . . . . . . . . 80

Table 31: Recommended circuit board design criteria ........................................................ 94

Table 32: Trace characterisitics . . . . .................... . . . . . . . . . . . . .................... . . . . . . . . . . . . ............ 101

Table 33: Reference clock cable three-pin connector pin assignments................................ .... 110

Table 34: Reference clock electrical requirements .......................... ................................ 118

Table 35: Failure symptoms and possible causes ............................................................ 130

Table 36: Internal inspection checklist........................................................................ 136

Table 37: Probes and related electrical simulation models ......................... ........................ 141

Table 38: Midbus probe CAD symbols for PCB layout................................... .................. 142

Table of Contents

standard accessories......................... .................... 11

ages............ .................................. ................................ .......... 79

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual ix

Table of Contents

Table 39: Midbu

Table 40: Slot interposer probe 3D CAD models.. ................................ .......................... 144

Table 41: Probes and related DSP filter files ....................... ................................ .......... 144

Table 42: P67SA16 x8 Midbus probe retention assembly kit .................. ............................ 147

Table 43: P67SA08 x4 Midbus probe retention assembly kit .................. ............................ 148

Table 44: P67SA16G2 x8 Midbus probe retention assembly kit........................................... 150

Table 45: P6

Table 46: Midbus probe configuration .......................... .................................. ............ 151

Table 47: Midbus probe..................................... ................................ .................... 151

Table 48: Slot interposer probe ................................................................................ 152

Table 49: Reference clock connector.......................................................................... 152

Table 50: Midbus probe..................................... ................................ .................... 153

Tabl e 51

Table 52: Reference clock connector.......................................................................... 154

: Slot interposer probe ...... .................................. ................................ ........ 154

s probe 3D CAD models.. ................................ ................................ .. 143

7SA08G2 x4 Midbus probe retention assembly kit........................................... 150

x Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

General Safety Summary

General Safet

To Avoid Fire or Personal

Injury

ySummary

Review the fo
this product or any products connected to it.

To avoid pot

Only qualified personnel should p erform service procedures.

While using this product, you may need to access other parts of a larger system.
Read the safety s ections of the other component manuals for warnings and
cautions r

Use proper power cord. Use only the power cord specified for this product and
certified for the country of use.

Use proper voltage setting. Before applying power, ensure that the line selector
is in the proper position for the source being used.

Connect and disconnect properly. Do not connect or disconnect probes or test
leads while they are connected to a voltage source.

Ground the product. This product is grounded through the grounding conductor
of the power cord. To avoid electric shock, the grounding conductor must be
connected to earth ground. Before making connections to the input or output
terminals of the product, ensure that the product is properly grounded.

llowing safety precautions to avoid injury and prevent damage to

ential hazards, use this product only as specified.

elated to operating the system.

Observe all terminal ratings. To avoid fi re or shock hazard, observe all ratings
and markings on the product. Consult the product manual for further ratings
information before making connections to the product.

The inputs are not rated for connection to mains or Category II, III, or IV circuits.

Connect the probe reference lead to earth ground only.

Do not apply a potential to any terminal, including the common terminal, that
exceeds the maximum rating of that terminal.

Power disconnect. The power cord disconnects the product from the power source.
Do not block the power cord; it must remain accessible to the user at all times.

Do not operate without covers. Do not operate this product with covers or panels
removed.

Do not operate with suspected failures. If you suspect that there is damage to this
product, have it inspected by qualified service personnel.

Avoid exposed circuitry. Do not touch exposed connections and components when
power is pre sent.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual xi

General Safety Summary

TermsinThisManual

Symbols and Terms on the

Product

Do not operate i

Do not operate in an explosive atmosphere.

Keep product surfaces clean and dry.

Provide prop

on installing the product so it has proper ventilation.

These terms may appear in this manual:

WARNING.

in injury or loss of life.

CAUTION

damage to this product or other property.

These t

erms may appear on the product:

DANGER indicates an injury hazard immediately accessible as you read
the ma

n wet/damp conditions.

er ventilation. Refer to the manual's installation instructions for details

Warning statements identify conditions or practices that could result

. Caution statements identify conditions or practices that could result in

rking.

WARNING indicates an injury hazard not immediately accessible as you

the marking.

read

CAUTION indicates a hazard to property including the product.

The following symbol(s) may appear on the product:

xii Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Service Safety S ummary

Service Safet

y Summary

Only qualifie
Safety Summary and the General Safety Summary before performing any service
procedures.

Do Not Service Alone. Do not perform internal service or adjustments of this
product unless another person capable of rendering first aid and resuscitation is
present.

Disconnect Power. To avoid electric shock, switch off the instrument power, then
disconnect the power cord from the mains power.

UseCareWhenServicingWithPowerOn. Dangerousvoltagesorcurrentsmay
exist in
disconnect test leads before removing protective panels, soldering, or replacing
components.

To avoid electric shock, do not touch exposed connections.

d personnel should perform service procedures. Read this Service

this product. Disconnect power, remove battery (if applicable), and

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual xiii

Compliance Information

Compliance In

EMC C om pliance

EMC Compliance

Australia / New Zealand

Declaration of

Conformity – EMC

formation

This section
environmental standards with which the instrument complies.

Meets the intent of Directive 2004/108/EC for Electromagnetic Compatibility
when it is used with the product(s) stated in the specifications table. Refer to the
EMC specification published for the stated products. May not meet the intent of
the directive if used with other products.

European contact.

Tektronix UK, Ltd.
Western Peninsula
Western Road
Bracknell, RG12 1RF
United Kingdom

Complies with the EMC provision of the Radiocommunications Act per the
following standard, in accordance with ACMA:

CISPR 11:2003. Radiated and Conducted Emissions, Group 1, Class A, in
accordance with EN 61326-1:2006.

lists the EMC (electromagnetic compliance), safety, and

Safety Compliance

Equipment Type

Safety Class

Pollution Degree

Description

Test and measuring equipment.

Class 1 – grounded product.

A measure of the contaminants that could occur in the environment around
and within a product. Typically the internal environment inside a product is
considered to be the same as the external. Products should be used only in the
environment for which they are rated.

Pollution Degree 1. No pollution or only dry, nonconductive pollution occurs.
Products in this category are generally encapsulated, hermetically sealed, or
located in clean rooms.

Pollution Degree 2. Normally only dry, nonconductive pollution occurs.
Occasionally a temporary conductivity that is caused by condensation must
be expected. This location is a typical office/home environment. Temporary
condensation occurs only when the product is out of service.

xiv Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Compliance Information

Pollution Degree

Installation (Overvoltage)

Category Descriptions

Pollution Degr
that becomes conductive due to condensation. These are sheltered locations
where neither temperature nor humidity is controlled. The area is protected
from direct sunshine, rain, or direct wind.

Pollution Degree 4. Pollution that generates persistent conductivity through
conductive dust, rain, or snow. Typical outdoor locations.

Pollution Degree 2 (as defined in IEC 61010-1). Note: Rated for indoor use only.

Terminals on this product may have different installation (overvoltage) category
designations. The installation categories are:

Measurement Category IV. For measurements performed at the source of
low-voltage installation.

Measurement Category III. For measurements performed in the building
installation.

Measurement Category II. For measurements performed on circuits directly
connected to the low-voltage installation.

Measurement Category I. For measurements performed on circuits not
directly connected to MAINS.

ee 3. Conductive pollution, or dry, nonconductive pollution

Overvoltage Category

Overvoltage Category I (as defined in IEC 61010-1)

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual xv

Compliance Information

Environmenta

l Considerations

Product End-of-Life

Handling

Restriction of Hazardous

Substances

This section provides information about the environmental impact of the product.

Observe the following guidelines when recycling an instrument or component:

Equipment recycling. Production of this equipment required the extraction and
use of natural resources. The equipment may contain substances that could be
harmful to
end of life. In order to avoid release of such substances into the environment and
to reduce the use of natural resources, we encourage you to recycle this product
in an appropriate system that will ensure that most of the materials are reused or
recycled appropriately.

This product has been classified as Monitoring and Control equipment, and is
outside the scope of the 2002/95/EC RoHS Directive.

the environment or human health if improperly handled at the product’s

This sym
Union requirements according to Directives 2002/96/EC and 2006/66/EC
on waste electrical and electronic equipment (WEEE) and batteries. For
informa
Tektronix Web site (www.tektronix.com).

bol indicates that this product complies with the applicable European

tion about recycling options, check the Support/Service section of the

xvi Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Preface

Preface

Related Documentation

This manual d

escribes how to install and use a TLA7SA16 or TLA7SA08 Logic

Protocol Analyzer, probes, and software with your PCI Express 3 system.

The following table lists related documentation, available f rom the Tektronix
Web site (www.tektonix.com/manuals).

The TLA7SA08 & TLA7SA16 PCIe3 Product Specifications and Performance
Ver i fication Technical Reference Manual (Tektronix part number
077-0402-xx) lists the product specifications and high-level functional check
procedures for your TLA7SA16 or TLA7SA08 Logic Protocol Analyzer
Module and probes.

d documentation

Relate

Item Purpos

TLA Qui

Onlin

Inst

Installation Manuals

XYZ

Dec

Application notes

P
Verification Procedures

T

Field upgrade kits

Optional Service Manuals Self-service documentation for modules and

ck Start User Manuals

eHelp

allation Reference Sheets

s of Logic Analyzers

lassification and Se curities instructions

roduct Specifications & Performance

PI.NET Documentation

e

High-level operational overview

In-depth operation and UI help

-level installation information

High

iled first-time installation information

Deta

Logic analyzer basics

a security concerns specific to sanitizing

Dat
or removing memory devices from Tektronix
products

Collection of logic analyzer application

ecific notes

sp

LA Product specifications and performance

T
verification procedures

Detailed information for controlling the logic
analyzer using .NET

Upgrade information for your logic analyzer

mainframes

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual xvii

Preface

xviii Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Product Description

Tektronix provides two different logic protocol analyzer modules and probes. The
logic protocol analyzer modules have acquisition rates of 8.0 GT/s, 5.0 GT/s, and

2.5 GT/s to acquire PCIe3, PCIe2, and PCIe1 data. They provide packet-level
triggering, sequence triggering, and error triggering. The modules acquire up to
160 million
the modules are the number of inputs.

8b/10b symbols or bytes-per-lane. The main difference between

TLA7SA16 x8 Logic

Protocol A

nalyzer Module

TLA7SA08 x4 Logic

Protocol Analyzer Module

The TLA7SA16 Logic Protocol Analyzer Module has 16 differential inputs and
supports x

The TLA7SA08 Logic Protocol Analyzer Module has 8 differential inputs and
supports x1, x2, and x4 links.

1, x2, x4, and x8 links.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 1

Product Description

Midbus Probes

A midbus probe c
board. To install the retention mechanism to either a PCI Express Gen3, Gen2,
or Gen 1 footprint on your circuit board, refer to the instructions in Appendix C.
(See page 145, Installing the Midbus Retention Mechanism.) Tektronix offers
the following midbus probes:

P67SA16 x8 Midbus probe

P67SA08 x4 Midbus probe

P67SA16G2 x8 Midbus probe

P67SA08G2

onnects to a retention mechanism installed on your circuit

x4 Midbus probe

ure 1: P67SA16 x8 midbus probe

Fig

Slot Interposer Probes

2 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

A slot interposer probe connects to a PCI Express slot on your SUT. Tektronix

fers the following slot interposer probes:

of

P67SA16S PCI Express x16 slot interposer probe

P67SA08S PCI Express x8 slot interposer probe

P67SA04S PCI Express x4 slot interposer probe

P67SA01S PCI Express x1 slot interposer probe

Product Description

Solder-Down Probe

Figure 2

The P67SA01SD probe connects to your SUT through the differential solder-down
tip (P7
each signal connector to the logic protocol module. (See page 159, Adding Probes
to the P67SA01SD Probe Connector.)

: P67SA08S x8 Slot interposer probe

5TLRST). Up to four probes (one differential pair each) can be installed in

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 3

Product Description

Figure 3: P67SA01SD Solder-Down probe

Logic Protocol Analyzer Module Controls and Connectors

section briefly describes the logic protocol analyzer controls and connectors.

This

Front Panel

The front panel provides indicators for checking the status of the logic protocol
analyzer. It includes probe connectors, two probe power connectors, and four

nectors for a reference clock. The TLA7SA08 has two probe connectors.

con
(See Figure 4.) The TLA7SA16 has four probe connectors. (See Figure 5.) A
description of the indicators and connectors is provided. The functions of the
indicators and connectors are the same for both modules except where noted.
(See Table 1 on page 7.)

4 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Product Description

Figure 4: TLA7SA08 logic protocol analyzer front panel

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 5

Product Description

Figure 5: TLA7SA16 logic protocol analyzer front panel

6 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Product Description

Table 1: Front p

Item
number Indicator or connector Description

1 READY indicat

2

3 ARM'D indic

4

5

6

7

8LEDind

9 Probe connectors

anel indicators and connectors

or

ACCESSED in

TRIG'D indicator The TRIG’D indicator lights when the logic protocol analyzer module triggers and stays on

Reference Clock Output
connecto

Reference Clock Input
connectors

Probe Power connectors The probe power connectors provide power to the probes.

dicator

ator

rs

icators

The READY indicator lights continuously after the logic protocol analyzer module
successfully completes the power-on process. If the indicator fails to light within five
seconds of po

The ACCESSE
analyzer module.

The ARM’D in
an acquisition.

until the module finishes acquiring data.

The Reference Clock Output SMA connectors (labeled + and – ) provide a means of
passing t
external module.

Two SMA connectors (labeled + and – ) provide differential clock input connections from
the SUT or from another module.

Three groups of LED indicators provide different information. (See page 7, LED
Indicators.)

Four connectors for the TLA7SA16 module (two for the TLA7SA08 module) provide the
probe
for the TLA7SA16 module (A or B for the TLA7SA08 module). The letters correspond to
the graphic display in the Setup window.

he differential clock signal from the Reference Clock Input connectors to another

connections for the module. Each connector is labeled with a letter A, B, C, or D

wer-on, an internal module failure may be present.

D indicator lights anytime the controller accesses the logic protocol

dicator lights when the logic protocol analyzer module is armed during

LED Indicators

The TLA7SA16 x8 modules have 32 front panel LEDs that provide information
on the status of the SUT. The TLA7SA08 x4 modules have 15 LEDs.

Link Rate LEDs. ThetopsetofLEDsaretheLink Rate LEDs. They monitor the
current rate of the SUT and indicate the most-recent rate detected by the module.
The TLA7SA16 x8 module has two columns of LEDs; the TLA7SA08 x4 module
has one.

The top LEDs (Row 1) show that the SUT is operating at 2.5 GT/s.

The center LEDs (Row 2) show that the SUT is operating at 5.0 GT/s.

The bottom LEDs (Row 3) show that the SUT is operating at 8.0 GT/s.

TheLEDshelpidentifyproblemsonthelink. The link might not be operating at
the highest-reported rate detected by the module on at least one direction of the
link. The rate of each link is determined from Lane 0; there is no indication if
other lanes are running at different rates. For the x8 modules, the two columns
indicate the rate in each direction – the system tracks the current rate indicated
by the direction of each link.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 7

Product Description

Status LEDs. Th

e Status LEDs provide an indication that the system is operating
as expected after the first turn-on. If the top two LEDs are turned on, the system is
working as expected.

Table 2: Status LEDs

Row / LED Description

TLA7SA16 and TLA7SA08

Top r ow

Diagnostics passed

Reference Clock found

Second row

Link Locked Down

Link Locked Up

TLA7SA16 only

Third, fourth, and fifth rows

Acquisition progress These LEDs progressively light in a downward

The left LED is on when the module has passed
the diagnostics. If the LED is off, check the Module
diagnostics to determine which diagnostics have
failed. If the Power On diagnostics fail, the Power On
Diagnostics dialog box appears on the screen. If it
does not, select Calibratio n and Diagnostics from
the System menu to display the dialog box.

The right LED turns on when the module has locked
onto a reference clock. The clock can be internal or
external. This LED should always be on unless an
external reference clock is selected and is not present.

This LED monitors the Serdes status of all lanes of the
Down link. The LED is on when all lanes are symbol
locked or in the EIDLE state. If the link is in the EIDLE
state, the LED blinks at a s teady rate.

This LED monitors the Serdes status of all lanes of
the Up link. The LED is on when all lanes are symbol
locked or in the EIDLE state. If the link is in the EIDLE
state, the LED blinks at a s teady rate.

direction after an acquisition has started (the RUN
button was pressed or clicked). The fifth row indicates
that the link is aligned (deskewed).

Activity LEDs. The lower set of LEDs show the current Serdes status of each lane.
The LEDs track the status of the Dn/Up settings in the Setup window. An LED is
on when the corresponding lane is symbol locked. The LEDs a re on when the
lane is in the EIDLE state (and the EIDLE timeout counter has not expired). The
lanes are logically numbered to indicate their position in the link.

8 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Product Description

Ifthereisapro
A blinking LED indicates an invalid condition, such as the lane not achieving
a symbol lock. For another example, if a problem occurs that causes the link
to downgrade to a x4 link, LEDs 4 through 7 will turn off. Refer to the Setup
window to determine which physical lane is associated with the logical lane.

NOTE. The Up and Dn indications on the front panel do not apply when all lanes

are capturi

blem, you can quickly see which logical lane has the problem.

ng a single unidirectional link.

Logic Protocol Analyzer and Logic Analyzer Compatibility

Install the TLA7SA08 & TLA7SA16 Logic Protocol Analyzer modules in either a
TLA7012 portable mainframe logic analyzer, or a TLA7016 benchtop mainframe
logic analyzer. The logic analyzer must have TLA Software V5.8 or higher
installed, and the latest version of the TMS160PCIe3 Tektronix PCI Express
Support

Software.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 9

Options and A ccessories

Options and Ac

cessories

The followin
Analyzer Modules and TLA7SA16 Logic Protocol Analyzer Modules.

Table 3: TLA

Accessory

Reference clock cable, SMA-to-3 pin header

Cable assembly, reference clock jumper

The following tables list the accessories for the P67SA16 and P67SA08 Midbus
probes. F
refer to the information in Appendix C. (See page 145, Installing the Midbus
Retention Mechanism.)

Table 4: P67SA16 and P67SA08 Midbus probes standard accessories

Accessory

Probe case 016-1994-xx

x8 Bolster assembly kit (includes1/16-inch hex wrench)

x8 Retention mechanism 131-8616-xx

x4 Bolster assembly kit (includes1/16-inch hex wrench)

x4 Retention mechanism 131-8617-xx

Probe head jack screw adjustment tool 003-1890-xx

Probe cable straps (two straps)

g table lists the accessories for the TLA7SA08 Logic Protocol

7SAxx logic protocol analyzer module standard accessories

Tektr onix
part number

672-6285-x

174-5392-

or descriptions of the bolster assembly kits and retention mechanisms

Tektr onix
part number

020-3056-xx

020-3057-xx

346-0300-xx

x

xx

Table 5: P67SA16 and P67SA08 Midbus probes optional accessories

Tektr onix

cessory

Ac

8 Retention assembly kit, P67SA16

x

Consisting of the x8 retention mechanism (Tektronix part number,
131-8616-xx) and the bolster assembly kit (Tektronix part number,

20-3056-xx)

0

x4 Retention assembly kit, P67SA08

Consisting of the x4 retention mechanism (Tektronix part number,
131-8617-xx) and the bolster assembly kit (Tektronix part number,
020-3057-xx)

rt number

pa

020-4016-xx

020-4008-xx

10 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Options and Accessories

The following t

ables list the accessories for the P67SAxxS slot probes.

Table 6: P67SAxxS slot probes standard accessories

Tektronix

Accessory

Probe case, P67SA16S

Probe case, P67SA08S, P67SA04S, P67SA01S

Probe cable straps (two straps)

Tall support bracket, P67SA16S

Short support bracket, P67SA08S, P67SA04S

part number

016-2002-xx

016-1994-xx

346-0300-xx

407-5559-xx

407-5560-xx

Table 7: P67SAxxS slot probes optional accessories

Tektronix

Accesso

PCI Expr

PCI Exp

PCI Exp

ry

ess x16 to x8 adapter, P67SA16S

ress x16 to x4 adapter, P67SA16S, P67SA08S

ress x16 to x1 adapter, P67SA16S, P67SA08S, P67SA04S

part num

013-0392-xx

013-0391-xx

013-0375-xx

ber

The following tables list the accessories for the P67SA01SD Solder-Down probe.

Table 8: P67SA01SD Solder-Down probe standard accessories

Tektronix

Accessory

Probe case 016-2009-xx

Solder kit, ROHS-compliant (two spools w ire, one spool solder)

G3PO bullet removal tool

Bullet contacts (QTY 4)

Solder tip P75TLRST

Probe cable straps (package of 2 straps)

part number

-2754-xx

020

-1896-xx

003

3-0359-xx

01

16-1953-xx

0

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 11

Options and A ccessories

Table 9: P67SA0

Accessory

Probe power adapter (one required to power up to eight P67SA01SD
probes)

Solder tip tape (strip of 10)

Solder kit, ROHS-compliant (two spools wire, one spool solder)

Probe cable straps (package of 2 straps)

G3PO bullet removal tool

Bullet contacts (QTY 4)

Probe power adapter 878-0509-xx

Solder tip P75TLRST

Trimode

Resist

resistor solder tip, with resistor leads

or conversion kit to add resistor leads to P75TLRST trimode solder tip

1SD Solder-Down probe optional accessories

Tektr onix
part number

P67SA01SD
Option 1P

066-8237-xx

020-2754-xx

016-1953-xx

003-1896-xx

013-0359-xx

020-293

020-2937-xx

6-xx

The following tables list the accessories for the P67SA16G2 x8 Midbus probe
and the P67SA08G2 x4 Midbus probe.

Table 10: P67SA16G2 x8 Midbus probe standard accessories

Tektr onix

Accessory

Probe case 016-1994-xx

Retention assemblies , full-width (50 contacts), long wires with integrated
CLGA contacts (two sets)

Jewel case (used to hold retention mechanism)

Probe head jack screw adjustment tool 003-1890-xx

Probe cable straps (four straps)

part number

131-7941-xx

006-8173-xx

346-0300-xx

able 11: P67SA08G2 x4 Midbus probe standard accessories

T

ektronix

T

Accessory

robe case

P

Retention assemblies, half-width (26 contacts), long wires with integrated
CLGA contacts (two sets)

Jewel case (used to hold retention mechanism)

Probe head jack screw adjustment tool 003-1890-xx

Probe cable straps (four straps)

part number

16-1994-xx

0

131-7951-xx

006-8173-xx

346-0300-xx

12 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Options and Accessories

Table 12: P67SA

Accessory

x8 Retention assembly kit, P67SA16G2

Consisting of the full-width (50 contacts) retention assemblies
(Tektronix p
part number, 006-8173-xx)

x4 Retention assembly kit, P67SA08G2

Consisting of the half-width (26 contacts) retention assemblies
(Tektronix
part number, 006-8173-xx)

16G2 and P67SA08G2 Midbus probes optional accessories

art number, 131-7941-xx) and the jewel case (Tektronix

part number, 131-7951-xx) and the jewel case (Tektronix

Tektronix
part number

020-2784-xx

020-2785-x

x

The following table lists the service options for the modules and probes.

Table 13: TLA7SAxx logic protocol analyzer module and P67SAxxx probes service
options

Option

Service Offerings

Repair warranty extended to cover three years (including warranty)

Repair warranty extended to cover five years (including warranty)

Calibration services extended to cover three years C3

Calibration services extended to cover five years C5

number

R3

R5

ollowing table lists the accessories for the P67UHDSMA four-differential

The f
inputs, x2, UHD-to-SMA probe leadset for use with the P67xx and P67SAxx
series probes.

Table 14: P67UHDSMA standard accessories

Tektronix

Accessory

50 Ω SMA terminator (QTY 8)

SMA connector, female-to-female (QTY 8)

part number

015-1022-xx

015-1012-xx

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 13

Options and A ccessories

14 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Install Common Hardware

This manual is written assuming that your logic analyzer mainframe is already
installed properly. However, a high-level module installation overview is
provided. If

TLA7000 Series Logic Analyzers Installation Manual.

CAUTION. To avoid damaging the mainframe, do not install or remove any

modules while the mainframe is powered on. Always power off the instrument
before installing or removing modules.

Cover any empty module slots with a blank cover (Tektronix part number,
333-4206-xx).

Install the modules in the mainframe. (See Figure 6.) Use a screwdriver to tighten
the retaining screws to 2.5 in-lbs after seating the modules in place.

you need additional help installing your mainframe, refer to the

Figure 6: Installing a module

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 15

Connecting the Instrument to the SUT

Connecting th

e Instrument to the SUT

The probes co
following illustration shows possible connections to your SUT. Choose the
probing scheme that works for your application.

nnect your logic protocol analyzer module to the SUT. The

Figure 7: Installation overview

16 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Connecting the Instrument to the SUT

The following t

ables list the number of probes needed per module to connect to a
link. Refer to the previous illustration for an overview of the connections to the
logic analyzer and SUT. (See Figure 7 on page 16.)

Additional probe connection information is provided later in this document; refer
to those sections for additional information.

Table 15: TLA Modules and midbus probes per link

Link TLA M od ules Probes

x16

x8

x4, x2, or
x1

Table 16

Link TLA Modu

x16

x8

x4, or x2

x1

2 TLA7SA16 2 P67SA16

1 TLA7SA16 1 P67SA16

1 TLA7SA16 or 1 TLA7SA08 1 P67SA16 or P67SA08

: TLA Modules and slot interposer probes per link

les

2 TLA7SA

1 TLA7S

1 TLA7

1 TLA7

16

A16

SA16 or 1 TLA7SA08

SA16 or 1 TLA7SA08

Probes

1 P67SA1

1 P67SA

A04S

1 P67S

A01S

1 P67S

6S

08S

Table 17: TLA Modules and solder down probes per link

Link TLA M od ules Probes

x16

x8

x4

x1

2TLA7SA16 32 P67SA01SD

1 TLA7SA16 16 P67SA01SD

1 TLA7SA16 or 1 TLA7SA08 8 P67SA01SD

1 TLA7SA16 or 1 TLA7SA08 2 P67SA01SD

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 17

Connecting the Instrument to the SUT

Clock Cable

Two clock connection cables are included with your logic protocol analyzer
module. One is for connecting the reference clock input of the module to the
SUT or slot in
module to another.

terposer probe, and the other is a jumper cable for connecting one

Connecting a Cloc k Cable

Connecting a Clock

Jumper Cable

Figure 8

Connect a clock cable by following these steps:

1. Connect one end of the cable to the Ref Clock input connectors (+ and –) on

2. Connect the other end of the correct cable to the SUT three-pin connector or

1. Connect one end of the cable to the Ref Clock input connectors (+ and –) on

2. Connect the other end of the cable to the Ref Clock output connectors

NOTE. Clock Reference Source must be set to SUT if either clock cable is used.

(See page 44, SUT Reference Clock.)

: Clock cable and clock jumper cable

the logic protocol analyzer module; screw the SMA connectors down until

re snug.

they a

lot interposer probe three-pin connector.

the s

the logic protocol analyzer module; screw the SMA connectors down until

yaresnug.

the

and–)onanothermodule.

(+

18 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Connecting the Instrument to the SUT

Connecting a P

robe to the Logic Protocol Analyzer Module

Follow these steps to connect a probe to the logic protocol analyzer:

1. Note the label on the module-end of the probe connector and connect the

probe to the appropriate connector on the logic protocol analyzer (for example
connect the probe with the A connector label to the A connector on the logic
protocol an

NOTE. If you have a multi-module system, make sure that you connect the probe

power connectors to the same module as the respective data probe connectors.
Connecting the probe power connectors to the wrong module will prevent the
probes from being calibrated correctly and the probes will not acquire the correct
data. Pay attention to the probe power connector labels when connecting the
probes t

2. Note the labels on the probe power connectors and connect the power

3. Tighten the connector screws using the adjustment tool included with your

o the modules.

connectors to the same module as the data probe connectors.

probe.

alyzer).

Connect the Midbus Probe

The P67SA08 and P67SA16 Midbus probes are designed for use with the
TLA
PCIe2, and PCIe1 data from PCIe3 footprints. The P67SA16G2 x8 Midbus and
the P67SA08G2 x4 Midbus probes are designed to connect the TLA7SA08 and
TLA7SA16 Logic Protocol Analyzer modules to signals using PCIe2 footprints.
The general probe connection procedures are the same for all the midbus probes;
however the P67SA16G2 x8 Midbus and the P67SA08G2 x4 Midbus probes

equire a different type of retention mechanism.

r

Connect the midbus probe from the logic protocol analyzer to a retention
mechanism on your circuit board. Instructions for installing a retention
mechanism are provided in Appendix B. (See page 145, Installing the Midbus
Retention Mechanism.)

7SA08 and TLA7SA16 Logic Protocol Analyzer modules to capture PCIe3,

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 19

Connecting the Instrument to the SUT

Handling the Probe Head

Handle the prob

Handle the probe head by the outer casing. Do not touch the contacts in the
center with fin

Do not expose the connector to liquids or dry chemicals.

NOTE. Be car

connected to a powered module. The probe head may become warm to the touch;
the probe is operating normally.

When connecting the probe, be careful not to touch the probe head contacts to
any other surfaces or components on your circuit board.

CAUTION. Static discharge can damage the probe head. Always wear a grounded

antistatic wrist strap whenever handling the probe head. Also verify that anything
to which the probe head is connected does not carry a static charge.

e head with care. Keep the following points in mind:

gers, tools, wipes, or any other devices.

eful when handling the probe head while the midbus probe is

20 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Connecting the Instrument to the SUT

Connect the Probe

Follow these st
your circuit board:

1. Locate the cor

your PCB has multiple retention mechanisms. Be careful to select the correct
one.

2. Align the probe h ead with the retention mechanism. Both are keyed so that

the probe can only be inserted one way.

3. Press the probe head into the retention mechanism.

eps to connect a midbus probe to the retention mechanism on

rect retention m echanism. If you intend to use multiple probes,

Figure 9: Connecting a probe to the retention mechanism

4. Startbothmountingscrewsintheposts, and tighten them evenly to ensure

that the probe approaches and mates squarely to the PCB. Use the adjustment
tool included with your probe. Proper installation torque is 1 in-lb.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 21

Connecting the Instrument to the SUT

Arranging the Midbus

Probe Cables

Hang the probe c
and tension on the retention mechanism is minimized. Route the cables as straight
as possible, maximizing the bend radius, and making sure that a 90 degree bend
does not occur within three inches o f the circuit board surface. (See Figure 10.)

ables so that the probe head is perpendicular to the circuit board,

Figure 10: Arranging the midbus probe cables

22 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Connecting the Instrument to the SUT

Connect the Sl

ot Interposer Probe

Handling the Probe Head

Connect the slot interposer probe to a PCI Express slot on your SUT.

Handle the probe head with care. Keep the following points in mind:

Handle the probe head by the outer casing. Do not touch the contacts with
fingers, tools, wipes, or any other devices.

Do not expose the connector to liquids or dry chemicals.

When conne
any other surfaces or components on your circuit board.

CAUTION. Static discharge can damage the probe head. Always wear a grounded

antistatic wrist strap whenever handling the probe head. Also verify that anything
to which the probe head is connected does not carry a static charge.

NOTE. If your system requires a slot probe adapter, install the adapter before

you install the slot interposer probe. (See page 27, Optional Lane Adapters
Installation Overview.)

cting the probe, be careful not to touch the probe head contacts to

ect the Probe

Conn

Connect a slot interposer probe to a PCI Express slot on your SUT by following
these steps:

CAUTION. Connecting the slot probe head to a powered SUT can damage the slot

be. D o not hot-plug the slot interposer probe head into a powered SUT. Always

pro
power off the SUT before installing the slot probe head into the SUT.

isconnect the power supply to your SUT. Disconnect the PC power supply if

1.D

your SUT is connected to one.

NOTE. To provide additional mechanical support for the PCI Express c ard w hen it

connected to the slot probe, install the slot probe bracket. (See page 28, Installing
the Slot SUT Card Support Bracket.)

2. Locate the correct PCI Express slot.

3. Remove the PCI Express card that is in the PCI Express slot of the SUT.

4. Align the probe head with the slot.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 23

Connecting the Instrument to the SUT

5. Press the probe

NOTE. Remove the slot probe bracket if it interferes with the add-in PCI Express

card.

6. Position the mounting bracket and attach the screws.

7. Press your PCI Express card device into the probe.

head into the slot.

Figure 11: Connecting a slot interposer probe

NOTE. When the slot interposer is installed, connect the power connector to the

ule. The module must be powered on whenever the SUT is powered on for the

mod
PCI Express signals to reach the PCI Express card connected to the probe.

TE. Unlike the bottom edge connector on the slot interposer probe, you can

NO

hot plug your PCI Express card (if hot plugging is supported) into the top edge
connector of the slot interposer probe without powering down the SUT.

24 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Connecting the Instrument to the SUT

Connecting a Probe to a

x16 Link

To ca pture sign
slot interposer probe. Connect the probe by following these steps:

NOTE. To provide additional mechanical support for the PCI Express c ard w hen it

connected to the slot probe, install the slot probe bracket. (See page 28, Installing
the Slot SUT Card Support Bracket.)

CAUTION. Connecting the slot probe head to a powered SUT can damage the slot

probe. Do n
power off the SUT before installing the slot probe head into the SUT.

1. Disconne

power supply, disconnect the power supply.

2. Locate t

3. Remove the PCI Express card that is in the PCI Express slot of the SUT.

4. Align the probe head with the slot.

5. Press the probe head into the slot.

als from a x16 link you need to connect two modules to a single

ot hot-plug the slot interposer probe head into a powered SUT. Always

ct the power supply to your SUT. If your SUT is connected to a PC

he correct PCI Express slot.

NOTE. Remove the slot probe bracket if it interferes with the add-in PCI Express

card.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 25

Connecting the Instrument to the SUT

6. Position the mounting bracket and attach the screws.

7. Press your PCI Express card device into the probe.

8. Conne

NOTE. The slot probes have two power connectors. Connect the power connectors

to the same module as the respective data connectors. Pay attention to labels on
the probe power connectors when connecting them to the module. The modules
must be powered on whenever the SUT is powered on for the PCI Express signals

each the PCI Express card connected to the probe.

to r

NOTE. Unlike the bottom edge connector on the slot interposer probe, you can

hot plug your PCI Express card (if hot plugging is supported) into the top edge

onnector of the slot interposer probe without powering down the SUT.

c

ct the probe to the two modules and connect the probe power connector

to both modules.

26 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Connecting the Instrument to the SUT

Optional Lane Adapters

Installation Overview

Tektronix prov
x16 sockets on the SUT. The following adapters are a vailable:

PCI Express x1

PCI Express x16 to x4 adapters for use with the P67SA16S and P67SA08S
slot probes

PCI Express x16 to x1 adapters for use with the P67SA16S, P67SA08S, and
P67SA04S slot probes

The part numbers for the adapters are listed with the P67SAxxS optional
accessories. (See Table 7 on page 11.)

The adapters have minimal impact on system performance, typically increasing
the measured jitter by less than 6 ps on the probe and SUT. Added jitter depends on
a number
match of the source and distance of the source from the add-in card.

The fol
probe. (See Figure 12.)

lowing illustrations shows how to install a x16-to-x8 adapter with a slot

ides a series of optional lane adapters for systems that do not have

6 to x8 adapters for use with the P67SA16S slot probes

of factors in the system configuration, including the output impedance

Figure 12: Installing an optional slot probe adapter

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 27

Connecting the Instrument to the SUT

Installing the Slot SUT

Card Support Bracket

Use the slot SUT
for your PCI Express card when connecting to the slot probe. The following
orientations are available; use the orientation that meets your needs. (See
Figure 13 on page 29.) The illustration shows the support bracket connected to a
x16 slot probe; connections to the x8, x4, and x1 probes are similar.

NOTE. The Slot SUT card support brackets cannot be used when your system

includes th
by the adapters.

Install t
(Option A).

Install
in an adjacent card s lot (Option B).

Install
(Option C).

Use eit
to the slot probe.

e optional slot probe adapters, due to the additional height added

the support bracket parallel with the existing PCI Express bracket

the support bracket perpendicular to the existing PCI Express bracket

her the supplied screws or existing screws to connect the support bracket

card support bracket to provide additional mechanical support

he support bracket parallel with the existing PCI Express bracket

28 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Connecting the Instrument to the SUT

Figure 13: Slot SUT card support bracket configurations

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 29

Connecting the Instrument to the SUT

Connect the So

Connect to th

lder Down Probe

e Logic

Protocol Analyzer Module

The probe connects to the module and to the probe tip, and the probe tip is
soldered to the circuit. Install the probe by following these steps.

1. Plug the signal connector into the module and tighten the hold-down screws.

2. Plug the probe power adapter into the module and tighten the hold-down

screws.

NOTE. The probe power adapter can be ordered as an option for the solder-down

probe (P67SA01SD Option IP). (See Table 9 on page 12.)

3. Plug the power connector into any one of the receptacles on the Power
Adapter.

4. Plug the solder tip into the solder-down probe.

30 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Connecting the Instrument to the SUT

Figure 14: Installing the P67SA01SD probe

P75TLRST Solder Tip

Install the probe tip by following these steps:

NOTE. This tip is very small and must be handled carefully. The following

procedures describe the proper techniques for using the tip.

Connect to the Probe Head. The probe body and tip cable ends are keyed to
ensure correct installation.

1. Orient the probe body with the + and – inputs on top.

2. Align the tip cable lead with the red band to the + input.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 31

Connecting the Instrument to the SUT

Figure 15: Connecting the P75TLRST tip to the probe head

3. Hold the cable connector by hand and push the cable into the probe body
until you feel a click. The cable housing is fully seated when it is flush with
theedgeo

4. To remove the tip, pull the cable tab straight out from the probe body.

f the probe body.

CAUTION

the probe. To avoid this, pull only on the cable tab when removing the tip.

Connec

in this manual for reference. (See Figure 54 on page 91.) Design the tip footprint
into your circuit board layout for easier test connections.

To connect the probe tip to your circuit, use the wire and solder that are provided
in the wire replacement kit. The kit includes:

1. Identify a location where the tip can be placed, soldered, and attached to

2. Lay the wires against a circuit board pad, trace, or other conductive feature.

3. Solder the wires to your circuit.

. Pulling the cables when removing the probe tip can damage the tip or

t to the Circuit. The dimensions of the solder tip connections are provided

0.004 in (0.1016 mm) wire

08 in (0.2032 mm) wire

0.0

SAC305 solder (RoHS compliant)

your circuit. When working with long wires (~1 inch), keep the finished wire

ngths of the signal and ground connections as short as possible.

le

If vias or through-holes are very close, thread the wires through them.)

(

32 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Connecting the Instrument to the SUT

Figure 16

4. Attach t

5. Clean out the tip vias with a solder-wick material if you are reusing the tip.

6. Press the tip to the circuit board and quickly solder the wires to the tip. Keep

7. Clip off the excess wire from all of the solder joints.

8. Push the end of the tip into the probe head until it seats in the probe head.

: Connecting wires to the circuit

ip tape to the bottom of the tip.

Thread

all fin

the wires through the tip.

ished wire lengths as short as possible.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 33

Connecting the Instrument to the SUT

Figure 17: Connecting the tip to the circuit

9. Secure the probe to the circuit board with tape or with the hook-and-loop
strips and dots that are included with the probe.

Applying and Removing Power

After you have connected all probes to the SUT, you are ready to apply power to
the SUT and the logic protocol analyzer.

NOTE. When using slot interposer probes power on the logic protocol analyzer

ore applying power to the SUT.

bef

NOTE. Unlike the bottom edge connector on the slot interposer probe, you can

t plug your PCI Express card (if hot plugging is supported) into the top edge

ho
connector of the slot interposer probe without powering down the SUT.

34 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Install the TMS160PCIe3 Support Software

Install the TM

S160PCIe3 Support Software

Use the follo

Before you use the logic protocol analyzer, verify that your mainframe has the
most curren
The TLA Application software must be installed on all mainframes and PCs that
will use the logic protocol analyzer modules, including any PCs that will remotely
control the logic protocol analyzer. (See page 139, TLA Application Software.)

The following CDs are needed to install the software:

TMS160PCIe3 Support Software CD, Tektronix part number 063-4263-xx

TMS160x
number 063-4326-xx

1. Insert t

This CD contains the TMS160PCIe3 Support Software and the TLA
Applic

2. Start Windows Explorer, navigate to the media drive, and execute the file

TLA_V

a. Click Ye s to start the software installation and follow the on-screen

wing procedure to install the TMS160PCIe3 support software.

t TLA Application software and the TMS160PCIe3 Support Software.

xxx TLA Add-On Data Windows Software CD, Tektronix part

he TMS160PCIe3 Support Software CD in the media drive.

ation Software.

58_Setup.exe to install the TLA Application software.

ructions.

inst

b. Select Ye s t o A ll if you are asked for permission to overwrite any

d-only files.

rea

3. Execute the file TMS160PCIE3_Setup.exe to install the TMS160PCIe3
ftware.

so

a. Click Ye s to start the software installation and follow the on-screen

nstructions.

i

b. Select Ye s t o A ll if you are asked for permission to overwrite any

ead-only files.

r

4. Remove the TMS160PCIe3 Support Software CD from the media drive.

5. Insert the TMS160xxxx TLA Add-On Data Windows Software CD in the

media drive.

6. Using Windows Explorer, navigate to the media drive and execute the file

TMS160_Add_On_DataWindows_Setup.exe.

This step installs additional software required for the TMS160PCIe3
application.

7. Follow the on-screen instructions to install the software.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 35

Install the TMS160PCIe3 Support Software

8. Remove the CD wh

9. Start the TLA and connect to the mainframe.

If a message appears instructing you to update the firmware, refer the firmware
upgrade instructions in Appendix A. (See page 139, Updating the Logic Protocol

Analyzer Mo

dule Firmware.)

en the installation is complete.

36 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Set Up the Logic Protocol Analyzer Module

NOTE. Refer to the information earlier in this document for installing common

hardware, co
SUT and to the logic protocol analyzer.

nnecting the instrument to the SUT, and connecting probes to the

Thelogicpr
on characteristics of the link. For the auto configuration to function properly, the
logic protocol analyzer must sense Gen 1 or Gen 2 training sets. To ensure that the
logic protocol analyzer senses the training sequences, perform the following steps.

1. Start the TLA application and wait for the Setup window to appear.

2. Start or restart the SUT so that the logic protocol analyzer can sense the

training sequences on the bus.

NOTE. If this is a first-time setup, the Setup window will display status messages

and indications in the Calibration dashboard that probe calibration is required.
Calibrate the probes before continuing this procedure. (See page 49, Calibrate
the Pr

3. Use the Setup window to view signal activity. Adjust the link characteristics

as needed to conform to your specific SUT behavior (such as, polarity, width,
and r

4. If this is the first-time setup, use the default trigger settings in the Trigger

win

5. Click Run to acquire and validate initial data in the Transaction and Listing

di

otocol analyzer can automatica lly configure the Setup window based

obes.)

ate).

dow to acquire some data to see if the instrument behaves as expected.

splay windows.

NOTE. The Transaction and Listing windows appear automatically to display

data from the SUT to help you validate that the system is set up correctly.

6. Use the Summary Profile window together with the Transaction and Listing

windows to analyze high-level transaction information linked to lowest-level
physical layer symbols across the entire acquisition.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 37

Setup Window

Setup Window

The Setup win
or default the system. If your system includes more than one logic protocol
analyzer module, the system displays the Setup window for the module in the
lowest-numbered slot. By default, he Setup window automatically configures the
logic protocol analyzer based on the characteristics of the link.

NOTE. After starting the TLA application, start or restart the SUT so that the

logic prot

The Setup window provides easy access to a variety of configuration options to
do the fo

Acquire bidirectional data

Calibrate probes attached to the module and to the SUT

Specify the link width and transfer rate

Use a clock embedded in the data stream or use an external clock connected
to the front panel

Establish storage conditions such as hardware filtering, link scrambling and
deskewing, specifying the storage length, and specifying the trigger position

dow is the default window when you start the TLA application

ocol analyzer senses the Gen 1 or Gen 2 training sequences.

llowing:

Establish which modules are associated to links

38 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Setup Window

Open the Setup

Window

The Setup window is the default window when you start the TLA application. If
the Setup window does not display, open the window using one of the following
methods:

ClicktheSetupIconintheTLAExplorer.

By default the first logic protocol analyzer is identified as SA 1.

Click the Setup button in the System Navigation toolbar.

If your system has more than one module, select the appropriate module from
the Setup button.

Click the Setup button on the Logic Protocol Analyzer icon in the System
window.

Click Next Setup in the Window menu or press the F10 key.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 39

Setup Window

The default Set
status indicators near the center of the window will vary depending on the signal
activity at the probe tip.

up window is shown below. (See Figure 18.) The color of the

Figure 18: Default Setup window

40 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Setup Window

Monitoring Si

gnal Activity

After you have connected the probes and installed the software and firmware,
monitor the signal activity on each of the lanes to make sure that your system
is operating
representation of the logic protocol analyzer module shows a status indicator for
each lane. Use the status indicators to determine if the SUT produces the signals
that the module can recognize. The logic protocol analyzer constantly monitors
the status of each l ane, even when data is not being acquired. The status of each
lane is mirrored by the front-panel LEDs.

A description of each status indicator is listed below.

Table 18: Status indicators in the Setup window

Indicator Description

correctly and that the probes are connected properly. A graphic

No signal (gray). A signal has not been assigned to a lane.
(See page 45, Assigning Lanes.)

Signal missing. The signal is assigned to a lane, but it is not
recognized. This symbol appears when a lane is inactive.

Signal (yellow). A signal is detected, but not locked. The data
is not recognized.

Data signal (green). A signal is detected and recognized as
data.

Clock signal. A clock signal is detected via the clock cable
connected to the SUT or slot interposer probe. The colors
and patterns of the clock signal indicator function similar to
those of the other status indicators. This indicator is gray if
the SUT Reference Clock selection is set to Not Used. (See
page 44, SUT R eference Clock.)

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 41

Setup Window

Auto Configura

tion

The logic protocol analyzer automatically configures the link direction, maximum
link width, link rate, and other settings that the system senses through the setup
and the SUT. T
reduces the time required to make an initial acquisition. All of the controls that
the system tracks use a “Track” prefix, such as Track Direction, Track Training,
or Track Rate. The system tracks the configuration settings until you manually
make a change in the setup.

When you manually change any of the configuration settings, the system displays a
list of the changed settings at the top of the window. For example in the following
illustration, the left side shows the system operating in the auto-configuration
mode. Th
in which the Link Direction, Width, and Lanes are not being automatically
configured. (See Figure 19.)

Figure 19: Changes identified in the Setup window

his allows the module and software to track the state of the link and

e right side of the illustration shows a manually-configured system,

In addition to providing indications of which link characteristics are manually
tracked, the system also provides indications in the Setup window where it sensed
discrepancies between the manual settings and the automatically-detected settings.
For example, in the following illustration, the Link Direction has been set to only
acquire downstream data. (See Figure 20 on page 43.) Next to its setting, the

stem provides the indication that it has detected traffic in both directions.

sy

42 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Setup Window

Link Rate Controls

Figure 20: Setup window with changes from auto configuration

Any change from the auto configuration activates the Auto Configure button. To
return the system to the auto-configured state, click the Auto Configure button or
manually change the controls to their auto-configured states.

By default, when the TLA application starts, or when you reset the Auto
Configuration (by clicking the Auto Configure button), the Link Rate selection
is set to Track Rate. The actual detected rate is displayed adjacent to the Link
Rate drop-down list. The detected rate may show rates in both the up and down

ection.

dir

If you select a specific link rate, the system displays the detected values. If

e detected values differ from the selected link rate, the detected values are

th
highlighted.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 43

Setup Window

SUT Reference Clock

If the Link Rate
for one or both of the link directions. This is an error condition and the detected
link rate values are highlighted.

NOTE. If the Link Rate is set to Track Rate and the link trains down from 8.0 GT/s

to a slower rate, the logic protocol module returns to the last known rate. For
example, a rate change from 5.0 GT/s to 8.0 GT/s and back to 5.0 GT/s operates
correctly.

2.5 GT/s will fail.

NOTE. The

capture of Compliance State when using the 8.0 GT/s rate.

In Auto C
recovering the clock signal embedded in the data. The SUT Reference clock is set
to Not Used. A stable reference signal is generated by the logic protocol analyzer
and synchronizes with the embedded clock signal. A clock cable connection is
not required, since the logic protocol analyzer recognizes the embedded signal
from the probe.

To use an external clock signal, Tektronix recommends connecting a clock cable
to make sure that data is accurately synchronized with the clock signal. Select an
appr
is connected correctly. (See page 18, Connecting a Clock Cable.)

onfiguration, the logic protocol analyzer can recognize a clock signal by

oximate frequency for your application. Make sure the reference clock cable

is set to Track Rate, the system can report back a mixed value

However, a change from 5.0 GT/s to 8.0 GTS/s and then down to

TLA7SA08 & TLA7SA16 Logic Protocol Analyzers do not support the

44 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Setup Window

Descramble and Deske w

Defining a Data Filter

Maximum Idle Time

Detector

In the Auto Confi
setting of the link. To change the scrambling, select one of the other entries; the
instrument senses the change and highlights the changed area. The following
guidelines provide information when you should select items in the Link Data
Storage area:

Select Descramble to store data in a descrambled format.

Select Store as 10b Data to store data in 10b format.

Select Store as 8b Data to store data in the more conventional 8b d ata format.

Select Deskew Lanes to view time-aligned lane data in the listing window.

The Setup window provides a means of filtering data to focus on the data you are

interested in. Select a predefined data filter from the list, or click
Filter button) and select what you want to filter from the data stream. Click OK
when done.

When the logic protocol analyzer is auto configured and an electrical idle occur
longer than the specified timeout, the instrument switches the acquisition rate
to 2.5 GT/s.

guration m ode, the logic protocol analyzer tracks the scrambling

(Define

s

Assigning Lanes

Some applications return to an electrical idle after a preset time period. The
circuits should have returned from an L1 state within that time-out period.
However, some tests might require a longer time-out setting. You may want to
limit the idle time by checking the Limit Idle Time check box and by specifying a
set time.

In the center of the Setup window, the graphic representation of the logic protocol
analyzer module shows the channel-lane connectors (lines drawn between
numbered lanes and channels d epending on the number of lanes in use). A line
connects each signal to a lane so that data will be recorded and displayed properly
in the data windows. Unless all connected indicators are green, the logic protocol
analyzer will not be able to identify packet structures correctly.

When you first open the Setup window, or default the module, the channels and
lanes are already connected to support the default settings for the attached probes.
The instrument is auto configured and automatically tracks the status of the
lanes (as indicated by the Track Lanes drop-down box). As soon as the system
senses any training sequences, it updates the lines (if necessary) to match the
mapping reported by the probe. The lines in the Setup window appear as gray
lines (system assigned).

To manually change the channel-lane indicators, click and drag the lines so that
the signals are connected to the lanes as your design dictates. The Track Lanes
check box changes its state depending on connections (mixed connections or all
manual connections).

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 45

Setup Window

If you decide to

manually configure the module, the color of the lines appear in
a different color to indicate the change. The following table shows the different
color possibilities.

Table 19: Channel-lane connector colors

Channel-lane connector Description

System assigned channel-lane connectors

Manually assigned lines channel-lane connectors

In the following illustration, the connections are limited to the downstream
direction. (See Figure 21 on page 46.) In this example the lines from Dn 2, Dn 3,
Dn 4, and Dn 5 are system assigned, indicated by the gray lines. The lines from
Dn 0, Dn 1, Dn 6, and Dn 7 are were manually drawn as indicated by the darker
colored l

ines.

ure 21: Changes from the default channel-lane connections

Fig

46 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Setup Window

Multimodule C

onfigurations

If your system has two logic protocol analyzer modules, each set up as
unidirectional modules, the system automatically establishes them as a
bidirection
modules and all are set up as unidirectional modules, additional controls
appear in the Setup window to allow you manually assign the pairs of modules
comprising the bidirectional link. Select the module from the drop-down list. For
convenience, click Setup to open the Setup window associated with the selected
module.

al pair. If your system contains more than two logic protocol analyzer

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 47

Probe Calibration

Probe Calibra

tion

When working
should be calibrated to the logic protocol analyzer and to the SUT. The Setup
window includes a Calibration Dashboard on the right side of window to quickly
show the status of the probe calibration.

For systems operating with PCI Express 3 rates, a partially filled-in dashboard or
a dashboard with highlighted information indicates that calibration is required. A
common example showing when calibration is required is during an initial setup.

NOTE. Systems operating with PCI Express 1 or PCI Express 2 rates will not

require calibration.

The following illustration shows an example of the dashboard for a PCI
Express 3 system with an initial setup. Note the missing information in the
dashboard.

with high-speed serial analysis, probes attached to the instrument

Figure 22: Calibration Dashboard, initial setup

When the dashboard displays the calibration information without any highlighting,
the probes are calibrated. (See Figure 23 on page 48.)

Figure 23: Calibration Dashboard, calibrated system

48 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Probe Calibration

When the system
previous setup, the dashboard uses highlighting to show that calibration is needed.

Reasons for ca

The initial use of the system. Calibration is needed because the dashboard
contains mi

The instrument detects a rate different than the most recent calibration value.
Therateinf

The instrument detects a width or series of widths wider than the most
recent cal
calibration, the information is highlighted in the dashboard..

Improvin
highlighted BER indicates that either the calibration was stopped before
reaching the desired target BER, of that the system could not achieve the
desired BER. The initial calibration might be good enough to start; but further
debugging may require a better error rate.

Adding a new probe (one or two entries in the dashboard). The Probe ID
information is highlighted when the instrument detects a different probe ID
than the ID than the most recent calibration value.

Returning to an existing setup with a new SUT. Relocating the instrument and
probes from one location to a nother will require confirming that the module

robes are calibrated to the new SUT.

and p

detects information in the dashboard that is different from the

librating or recalibrating the probes include the following:

ssing information.

ormation is highlighted in the dashboard.

ibration value. If the current lane mapping differs from the prior

g the calibration to achieve a lower bit error rate (BER). A

Calibrate the Probes

en the instrument senses any changes from the most recent values used for

Wh
calibration, the dashboard highlights the changed elements.

rform the following steps to calibrate the probes:

Pe

1. Click Calibration Details at the bottom of the dashboard to view and access
he calibration options.

t

A drawer opens showing the status of the current probe calibration. A status
message at the top of the drawer provides an estimate of the time required to
calibrate the probes. Other information includes the Gain setting of each probe
and a list of the calibration results for each lane.

The Calibrate button is labeled Calibrate whenever a calibration is required.
The label changes to Recalibrate after a successful calibration.

2. Click Calibrate to begin the probe calibration. The probe calibration may

take several minutes to comple t e.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 49

Probe Calibration

Calibration Results Table

Overview

During the cali
progress of the calibration. When the calibration is complete, the results are
updated in the Calibration Results table.

3. If necessary, click Cancel to terminate the calibration.

If the syste
displays Stop. S topping the calibration will not remove any of the calibration
that has b een successfully completed. Clicking Cancel returns the calibration
process to the same state as w hen the calibration started.

The Calibration Results table provides a summary of the probe calibration status.
The probe calibration process includes the following stages:

The initial determination stage

One or mo

The system displays a progress bar at the top of the Probe Calibration Results

howing the progress of the calibration.

table s

The Calibration Results Table displays a row for each lane associated with a probe

el. For example, a x4 system will only display four lanes in each direction;

chann
the remaining rows will be blank. The table includes the following columns:

bration process, status messages and a progress bar shows the

m has completed part of the calibration process, the button label

re refinement stages

ction check boxes. These check boxes allow you to calibrate or recalibrate

Sele
individual lanes. This is helpful to achieve a better error rate for specific lanes.

e label. The Lane label defines the lane number and the direction (Up or

Lan
Down).

alization value. This value will most likely vary from lane to lane to

Equ
achieve the lowest possible error rate.

t Error Rate (~BER). The table lists the B ER value achieved during the

Bi
calibration. A value of ? indicates that a BER has not yet been calculated.
During the calibration, the BER value displays as --. The dashes are replaced
by an actual value when the calibration has been completed. If the BER is
not sufficient, it might be possible to recalibrate the lane to achieve a better
value. Select the lanes to be calibrated and confirm that the Target BER has
been set to the desired value. Click Calibrate to adjust the EQ only for the
selected lanes.

50 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Probe Calibration

Probe Recalibration

Information

Under certain s
to the lane mapping.

Reasons for re

The module has been defaulted. The system might be able to restore the lane
mapping ass
cannot be restored, calibration is required.

A saved syst
from the current probe or module lane mapping, calibration might be required.
The system offers a choice of waiting to see if the system can update the lane
mapping (based on the observed training set) or overwriting the current lane
mapping with the lane mapping saved with the calibration. In the latter case,
the system displays a Map Lanes button in the Calibration Status area. Click

Map Lane

Lane mapping has changed. When the lane mapping changes to use a new
probe c
remapped to probe channels that had already been calibrated, recalibration
will not be required.) If the SUT has changed its lane mapping since the
logic protocol analyzer was c alibrated, such that new probe channels are
needed, recalibration is required. The system senses the c hange and displays a
message that recalibration is required.

ituations, you might have to recalibrate the probes due to changes

calibrating probes are listed below:

ociated with the defaulted module. However, if the lane mapping

em has been loaded. If the saved system configuration is different

s to use the lanes saved with the calibration.

hannel, the system will need to be recalibrated. (If the lanes are

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 51

Trigger Window

Trigger Window

After defining parameters in the Setup window, define a trigger that tells the logic
protocol analyzer when to begin recording data. The logic protocol analyzer
provides pow
specify trigger conditions on any field within a packet.

Open the Trigger Window

NOTE. The instrument has a separate Trigger window for each installed module.

Make sure that you select the Trigger window that applies to your module.

Open the Trigger window by doing one of the following:

erful triggering capabilities including predefined trigger templates to

Click the Trigger icon in the TLA Explorer.

By default the first logic protocol analyzer is identified as SA 1.

Select the Logic Protocol Analyzer from the Trigger button in the TLA toolbar.

he Trigger button on the Logic Protocol Analyzer icon in the System

Click t
window.

Trig ger: SA 1 in the Window menu.

Click

Click Define Trigger in the Setup window.

The default Trigger window is shown below. (See Figure 24.)

Figure 24: Default Trigger window

52 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Trigger Window

Quick Tips

Click to collapse the current trigger state to provide more room on the
screen.

Click to expand the current trigger state.

Look for the or to expand or collapse information in the current Clause.
They are indicators that there may be more or less information to display
on screen.

Click one of the three icons at the top of the Trigger window to open the
default trigger window

The Store and Trigger Position controls are identical to those in the Setup
window.

, load a trigger , or save a trigger .

Add States, Clauses, Events, and Actions to the Trigger Window

A trigger definition is a logical expression consisting of events and actions within
clauses
and one clause (Clause 1). A trigger definition can have up to eight trigger states
with eight trigger clauses per state. To work with states, clauses, events, and
actions, do the following:

, within states. The default Trigger window starts with one s tate (State 1).

1. Begin editing the clause by selecting Events (IF) and Actions (THEN).

2. To add additional events or actions to the clause, click Add Event or Add

Action.

3. Multiple events can be joined by a logical AND or an OR. Click AND to

change it to an OR. Actions can only be joined by an AND.

4. To add another clause or state, click Add Clause or Add State.

5. Add

states, clauses, events, and actions by right-clicking and selecting from

the context menu.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 53

Trigger Window

Delete States

, Clauses, Events, and Actions from the Trigger Window

Trigger Events

Delete states, clauses, events, and actions by clicking the appropriate button in the
Trigger window, selecting from the Edit menu, or by right-clicking and selecting
from the cont

Trigger ev

ext menu.

ents are listed in the following table.

Table 20: Trigger events

Event Description

Anything Recognizes any data.

TLP

DLLP

Sequence Recognizes a specific ordered set or symbol sequence.

Link Event

Timer

Counter Recognizes a specified counter value.

Signal In Recognizes a signal from another module.

Recognizes the presence or absence of a specificTLP.
Choose the TLP from a list, or define a TLP.

Recognizes the presence or absence of a specific DLLP.
Choose the DLLP from a list, or define a DLLP.

Choose the Sequence from a list, or define a Sequence.

Recognizes link events and link errors. Choose the Link
Event from a list, or define a Link Event and specify which
lanes to monitor.

Recognizes a specified timer value.

The following table provides additional information about the event recognizer
resources. You may need to be aware of these when setting up the Trigger window.

ble 21: Trigger event recognizer resources

Ta

ent recognizer

Ev

DLLP packet recognizers 4 per link direction

TLP packet recognizers 4 per link direction

Symbol sequence recognizers

Link event recognizers 4 per link direction

scription

De

shared between link directions

4

54 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Trigger Window

Create a TLP Event

1. Select TLP from

Figure 25: Specifying a TLP event

2. Click the ellipsis to defineamoredetailedTLP.

Figure 2

6: Defining a TLP

the list and specify your TLP.

3. Enter a

will be created. To change the radix, right-click and select from the list. Edit
the TLP definition and click Close when you are finished. The new TLP
will now appear in the list.

meaningful name for the TLP or select one from the list and a copy

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 55

Trigger Window

Create a DLLP Event

1. Select DLLP fro

Figure 27: Specifying a DLLP event

2. Click the ellipsis to defineamoredetailedDLLP.

Figure 28: Defining a DLLP

m the list and specify your DLLP.

3. Enter a meaningful name for the DLLP or select one from the list and a copy
e created. To change the radix, right-click and select from the list. Edit

will b
the DLLP definition and click Close when you are done. The new DLLP
will now appear in the list.

56 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Trigger Window

Create a Link Event

1. Select Link Eve

Figure 29: Specifying a Link event

2. Click the ellipsis to define a more detailed Link event.

nt from the list and specify your Link event.

Figure 30: Defining a Link event

3. Enter a meaningful name for the Link event or select one from the list and a
copy will be created. Edit the Link event definition and click Close when you

done. The new event will now appear in the list.

are

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 57

Trigger Window

Create a Sequence Event

1. Select Sequenc

Figure 31: Specifying a symbol sequence

2. Click the ellipsis to define a more detailed symbol sequence.

e from the list and specify your symbol sequence or ordered set.

Figure 32: Defining a symbol sequence

3. Enter a meaningful name for the symbol sequence or select one from the list
and a copy will be created. Define a symbol sequence with a maximum of
16 symbols per lane. Click the K to change it to a D or an X. An X indicates

t the trigger will recognize either a K or a D control bit. To change the

tha
radix, right-click and select from the list, or just click the radix text. Edit the
symbol sequence definition and click Close when you are done. The new
symbol sequence will now appear in the list.

58 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Trigger Window

Event Counter, Global

Counter, and Timer

Overview

Four types of ev
increment every time the event occurs (or does not occur). These counters are
called event counters and are associated with the following events:

TLP

DLLP

Sequence

Link Event

Figure 33: Event counter

There are two event counters in every state. Event counters are limited to
counting only the event they are associated with. To create a counter that can b e
incremented, decremented, and reset by a ny clause in any state, select Counter
from the event list. This type of counter is called a global counter.

There are four counter/timers that may be used as either Global Counters, or
Global Timers. A counter/timer can not be used as both a Global Counter and a
Global Timer in the same trigger program. Each individual counter timers are
independently enabled to be a Global Counter or a Global Timer.

ents have counters associated with them. The counter will

Figure 34: Specifying a global counter

Global counters are usually combined with another clause or state that increments,
decrements, or resets the counter with an action. See Actions.

Timers are also global, meaning that they can be started, stopped and reset by any
clause in any state. Select Timer from the event list and specify your timer.

Figure 35: Specifying a timer

Timers are usually combined with another clause or state that starts, stops, or
resets the timer with an action. (See page 60, Trigger Actions.) A maximum of
four global counters or timers are available.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 59

Trigger Window

Create a Signal-In Event

Select Signal I

n from the event list and specify a signal number.

There are four global signals that can be used for triggering by any module
installed in t

he logic analyzer mainframe.

Trigger Actions

When an even
taken. Click Add Action to join multiple actions with a logical AND.

Trigger Ac

Table 22: Trigger actions

Action Description Interactions

Trigger Triggers the current module and causes

acquisition memory postfill to begin.

Trigger All Modules

Wait for System Trigger Used for a module that does not trigger

Go To Causes a change to a different trigger

Counter actions

Timer actions

Set and Clear Signal Sets or clears one of the four internal

Arm Module

Start and Stop Storing Begins or ends storing of samples.

Do Nothing

Also known as a System trigger. This
signal is also available at the System
Trigger Out connector.

itself or any other module, but waits to be
triggered by another module.

state.

Increments, decrements, or resets
counters.

Starts, stops, or resets timers. Counter 1, 2, 3, and 4 actions conflict with

system signals.

Sends an Arm signal to another module.
The other module begins running its
trigger program.

Used as a placeholder when defining a
complicated trigger program.

t (IF) in a clause becomes TRUE, the associated action (THEN) is

tions are listed in the following table.

When Trigger is used in the trigger
program, Trigger All Modules cannot be
used.

When Trigger All Modules is used in the
trigger program, Trigger cannot be used.

Capable of receiving the following three
(mutually exclusive) trigger actions:
Trigger, Trigger all Modules, or Wait for
System Trigger.

Use only one in clause definition.

Counter 1, 2, 3, and 4 actions conflict with
Timer 1, 2, 3, and 4 actions respectively.
The actions also conflict with their
respective events.

Timer 1, 2, 3, and 4 actions respectively.
The actions also conflict with their
respective events.

Use only one in a trigger program.
Mutually exclusive with Arm Module
action.

Can only arm one module in a trigger
program, but actions can be taken
throughout the trigger program.

Does not override other actions specified
in a clause.

60 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Acquiring and Viewing Data

The TMS160PCIE3 PCI Express Support software provides predefined setups
for the data windows. When you first acquire data, the logic protocol analyzer
displays the
window information, all modules with the supported software loaded are identified
as participating links.

Use the Transaction window to locate transactions of interest and to help
understand the detailed sequence of the transactions. After locating a
transaction of interest, use the Transaction window to further examine the
packet sequence, timing, and internal content to confirm any suspected
problems.

Use the Bird’s Eye View (BEV) with the Transaction window for a high-level
view of the overall acquisition. Configure the BEV to display a visualization
for flow c
credit overflows.

Transaction w indow and the Listing window. Based on the Setup

ontrol credits and then use the Packet view to identify possible

Acquiring and Viewing Data

Use the
protocol elements within a region and across the entire acquisition.

Use th
symbol data (ordered sets, DLLPs, and TLPs). Each column represents a lane
of PCI Express data with a disassembled view of the packet data. This allows
you to quickly view symbol data as it flows across the link.

Use the Waveform window to display rows of symbol data. Each row
represents a lane of PCI Express data. Use iView to correlated data from an
external Tektronix oscilloscope in the same waveform window.

Use the New Data Window wizard to select and set up other data windows as
needed for your application.

NOTE. If your logic protocol analyzer is configured to acquire multiple protocols,

r if the system does not detect any protocols in the setup, the Components

o
and Links dialog box appears on the screen when you attempt to create a new
Transaction window. Fill out the necessary fields in the dialog box to associate
the links captured by the logic protocol analyzer to the Transaction window.

Summary Profile window to view a summary statistical analysis of

e Listing window to display columns of disassembled PCI Express

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 61

Transaction Window

Transaction Window

The Transaction window provides a display o f packet information, colored
by packet type, to view transactions and overall packet flow, interspersed with
physical lay
flows within your system.

The Transaction window has elements similar to other data windows such as the
toolbar to search data, apply filters, and manage other aspects of the display. The
following illustration shows some of the key elements in the Transaction window.

er activity (such as ordered sets) to gain an understanding of traffic

e 36: Transaction window

Figur

Transaction View

Quick Tip

Links are represented as relationships between the end point columns.

ck a transaction to show the link relationship by displaying a Feynman

Cli
diagram. (See page 64, Examining Transactions.)

Use the mouse with rollover messages to show the amount of time required

or the transaction or to identify errors in the transaction.

f

62 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Status Area

Transaction Window

The status area separates the Transaction and Packet views in the Transaction
window. It provides additional information about the status of the Transaction
window inclu

Status messages and error messages as they occur

A progress bar showing the status of searches and filtering taking longer than
two seconds

A statistics panel showing the statistics from the BEV Viewfinder.

Access to the Summary Profile window through the Display Summary button.
(See page 71, Summary Statistics Tab Notebook Information.)

ding the following items:

Packet V

iew

Quick Tips

The Packet view shows the primary source of information in the Transaction
window. All acquired packets are interleaved in the timestamp followed by the
source
amounts of time.

The co
packet. To add or remove columns, right-click the mouse and select Add/Remove
Columns from the context menu; add or delete columns from the Field Chooser
menu.

Each major row in the Packet view represents a packet. Click the + sign to expand
the fields to see more packet information. Minor rows in the Packet view show
low-level information such as ordered sets and error conditions. A special type
of row is associated with Training Sets. Neither a packet, nor a single phy-layer
in

Coloring provides a way to differentiate packets, such as Memory Reads, Memory
W
symbolic ordered sets, and errors.

(transmitter) ID. Packets come in different sizes and transmit in varying

lumns in the Packet view show information from the fields available to the

dication, Training Set rows show information about the current state of the link.

rites, ACK, NACK, message types and special events (ordered sets with data,

Position the mouse over special events to display rollover messages with
additional information about the event.

Position the mouse over Training Set fields to display rollover messages with
additional information about the field value.

Reduce the packet rows to a few pixels high to only display the color bands
without the detailed text labels by continuing to select Smaller Text from the
right-click menu. This provides an easy way view more data in the window.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 63

Transaction Window

Examining Transactions

Click a transaction to see the packets that make up the transaction. Other
packets involved in the transaction are added to the appropriate columns and are
highlighted. Click the transaction a second time to remove the highlighting.

All packets related by the transaction are highlighted and have arrows drawn
from them to their ultimate delivery time; all other packets are attenuated with
grayed-out text. Ends of the arrows indicate when a packet has fully arrived;
position t

NOTE. Because packets do not flow across links instantly, abnormally long or

short transmission times can indicate the source of a problem. Use the timestamp
to indicate when the packet left the sending component.

If the target row does not display (is filtered out) the arrow is drawn to the top
of the nearest visible and appropriate timestamp row. The arrowhead is rendered
with a colored border with a white fill. The last line for the last packet to complete
is shown by a square-end cap; it indicates there are no more packets in the current
trans

he mouse on the arrow to show amount of time between packets.

action.

Physical Layer View

A vertical line indicates how long the component was involved with the

saction after it received the first packet.

tran

Packet view shows Physical layer information in addition to the packet

The
information. Use the Packet view to look for errors and gaps due to hardware
filtering or to identify other problems in the Physical layer. The interleaving
of the physical information with the packet information can help in identifying
elements of interest.

Special events are identified as information events, ordered sets, or error messages.
These events may be displayed as horizontal lines starting in the left side of the
Packet view. Each line has a different appearance; use the rollover messages with
the mouse to provide more information about the special events.

64 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Using the Transaction Window with the Listing Window

Use the Transaction window and Listing window together to trace problems
from the Transaction window by locking cursor 1 to the same data in the Listing
window. By default, the system positions the windows side-by-side to view
activity in both windows at the same time.

Transaction Window

Figure 37: Side-by-side Transaction window and Listing window

Find a link rate change because of new sets of training information (moving from
TS1 to TS2). Look for the relative lane data in the Listing window to identify the

change. Then look for additional information in the Listing window to see the

rate
lane data to identify what is going on.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 65

Bird’s Eye View

Bird’s Eye View

The Bird’s Eye View (BEV) displays Flow Control across the entire acquisition.
When you identify an area of interest, such as a possible buffer overflow, use
the BEV to nav
Transaction window. (See Figure 38.)

igate to the data and view the details of the transactions in the

Viewfinder

Updating in
on the amount of data that needs to be updated.

Use the BEV
visualization. (See page 69, Configure the Flow Control Visualization.)

Use the Viewfinder to move to areas of interest within the BEV. The system
updates
the Status area of the Transaction window. The displayed statistics depend on the
visualizations displayed in the BEV.

NOTE. Changing the position or the size of the Viewfinder in the Transaction

window changes the position and size of the Viewfinder in the Summary Profile
window.

formation in the BEV might take a few moments or longer, depending

Configuration panel to configure the properties of the Flow Control

statistics about the data within the Viewfinder region and displays them in

66 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Bird’s Eye View

Location Bar

Figure 38: BEV with Viewfinder and Location Bar

The Location bar represents the current location of the first packet in the Packet
view. Change the position of the Location bar in the BEV using one of the
following methods:

Drag the Location bar to a new location within the BEV. The Packet and
Transaction views are updated with new data for that position.

Click on any location within the BEV. The Packet and Transaction view
positions are updated to show the first element associated with the Location
bar position.

Scroll the data in the Packet or Transaction views. The Location bar moves to
the new location in the BEV.

The Location Bar and the Viewfinder operate independently– moving the
Location Bar does not impact the position of the Viewfinder. To move both the
Location Bar and the Viewfinder simultaneously, use the Alt key with the mouse
as described in the on-screen rollover messages.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 67

Bird’s Eye View

Flow Control V

isualization Overview

The Flow Control v isualization displays a graphical representation of Flow
Control Credits. The BEV displays up to six Flow Control g raphs where each is a
vertical lin

Use the BEV Configuration panel to define the credit values to display with each
line. For a g
union of elements as specified in the configuration panel. F or example, if you
specified all data values in the up direction, the line would identify the absolute
maximum value of all data values within the time slice. The line represents the
following ranges of values:

When
that location and see the resultant data in the Packet and Transaction views.

e showing the Flow Control activity.

iven time slice, the line displays the absolute maximum value for the

Okay. The Okay range is any range of values below the Critical threshold
value.

Critical. The Critical range is arbitrarily set by the application to be 80%
of the Overflow threshold.

Overflow. The Overflow range is determined by the threshold value that you
set in the BEV Configuration panel. Setting the Overflow threshold adjusts
the sensitivity of the visualization to errors. Setting the threshold to a low

will render errors more frequently. Setting the thresholds to a value

value
greater than 100% decreases the potential for showing errors.

younoticeanareaofinterestinthevisualization, move the L ocation bar to

Quick Tip

Move the mouse over one of the Overflow ranges in the BEV to display a

llover message that provides information for the highest three overflow

ro
values.

68 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Bird’s Eye View

Configure the Flow Control

Visualization

1. Click the Config
BEV Configuration panel. The panel shows the options for the Flow Control
visualization. (See Figure 39.)

Figure 39: BEV Configuration panel with Flow Control selected

2. Select the links to display by clicking the check box under the Links to
Display area; clear the check box for any links that you do not want to display.

NOTE. Any unidirectional links are disabled and cannot be displayed in the BEV.

ure BEV tab at the top-right side of the BEV to open the

Flow Control Statistics

Each differential in the BEV is represented by a Column button in the BEV
Configuration panel. Rearrange the Column buttons by clicking and dragging
the column to the desired position.

3. Determine the differentials to display in the BEV by clicking the check box at
the top of the column.

4. Click a Column button to open a drawer showing the virtual channels and
credits to display in the BEV.

Tabs within each column allow you to select the virtual channels to display.

5. Select a Virtual Channel tab and then select the individual credits to display
by clicking the check boxes in the panel.

The label on the Column button summarizes the credits for that column.

ove the Viewfinder to any data of interest. The Statistics panel in the Status area

M
of the Transaction window shows the minimum values for the differential within
the bounds of the Viewfinder. Values are hyperlinks; click a hyperlink to go to the
first instance of that value in the Transaction window.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 69

Summary Profile Window

Summary Profil

eWindow

Use the Summa
protocol elements within a region and across the entire acquisition. The window
provides real-time statistics without the need to take a separate acquisition to
view the overall health of your system. Summary information includes statistical
analysis of the trace elements such as:

TLPs

DLLPs

Ordered sets

Errors

Custom

A Summary Profile window is associated with one or more Transaction widows
for any one protocol. To view the Summary Profile window, click the Display

Summar

ry Profile window to view a summary statistical analysis of

y button on the status bar of the Transaction window.

Figure 40: Opening the Summary Profile window

70 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Summary Profile Window

The following i
window.

Figure 41: Summary Profile window

llustration shows the major components of the Summary Profile

Summary Statistics Tab Notebook Information

The Sum
statistics. The tabs identify the individual links or copies of the links with an
associated Transaction window instance. Each tab contains a list of protocol
elements and a list of the totals of elements in the Viewfinder regions in the
overall acquisition.

The summary band at the top of each tab provides a brief summary of the statistics
for the selected link including the average transaction latency, the total bytes
transmitted, and the total bandwidth utilization.

mary Statistics Tab Notebook contains a collection of the summary

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 71

Summary Profile Window

Figure

Element Table Information

The Element table contains the following items:

42: Summary Profile window (Summary Statistics Tab Notebook)

ocol Element. This column lists the hierarchy of the elements in the

Prot
protocol. Click the arrow to display any sub-elements and the details for those
elements. The column may contain filtered items (in italics) that represent
items not displayed in the Transaction window bec ause of post-processing
filtering. Click elements with hyperlinks to scroll the associated Transaction
window to the first instance of the element.

The In Viewfinder columns list the totals of each element within the
Viewfinder regions. Click an item a Viewfinder column to scroll to the

rst occurrence of the corresponding item in the Transaction window. (See

fi

Figure 42.)

72 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Summary Profile Window

The In Total col
acquisition. Click an item in the column to scroll to the first occurrence of
the corresponding item in the Transaction window.

The Overview column contains a summary of each element in the acquisition
including the following items:

Viewfinder. The Viewfinder specifies an area within the sparklines that

looks interesting. This is the same area displayed by the Viewfinder in
the BEV in the Transaction window. Changing the Viewfinder updates
the statistics under In Viewfinder columns. Click the updated hyperlink
to go to the first instance (in the Transaction window) on an element in
the Viewfi

NOTE. Changing the position or the size of the Viewfinder in the Summary

Profile window changes the position and size of the Viewfinder in the BEV.

Sparklines, a summary of the entire trace data for each element broken

into segments (approximately 40 discrete sections over the entire trace).
The horizontal (X) dimension is each segment; the vertical (Y) dimension
depends on the maximum value of the element and which root element the
sparklineispartof.

umn lists the grand totals of each element in the entire

nder region.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 73

Summary Profile Window

Create a Custo

mElement

Use the Custom element to establish user-defined protocol elements for which
the Summary Profile window will provide appropriate statistics. The Custom
element does
of values for the fields of a packet that may or may not correspond to an existing
packet definition.

1. Click the button n ext to the Custom element to open the Define Packet

2. Select one of the default packet types from the Name list. (See Figure 43.)

not create a new packet type, but provides a means to specify a set

window.

e43:Define Packet window for a Custom element in the Summary Profile

Figur
window

3. Enter a name for the packet and then change the values of the fields for
your needs.

4. Save the Custom element by clicking Save. The new element is added to the
Protocol Element list.

Guidelines for using Custom elements are listed below:

LPs start with an SDP and complete with an End or EDB with mod4 lane

DL
starts and a maximum of two SDP per symbol times.

LPs start with SDP and finish with an End or EDB with mod4 lane starts and

T
a maximum of one STP per symbol time.

The maximum packet sizes are defined by Max_Payload_Size.

74 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Listing Window

Listing Window

Use the Listing window with the Transaction window and Summary Profile
window to display disassembled data in a list format; packets appear in searchable
columns.

Figure 44: Data displayed in the Listing window

The Listing window displays special characters and strings to indicate significant

s. (See Table 23.) The columns that display in the Listing window depend

event
on the Acquire settings in the Setup window.

Table 23: Special characters in the Listing window

Character or string Description

>

--

Insufficient room on the screen to show all available data

Invalid data or group, including read data

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 75

Listing Window

Add Two Sides o

f a Link to a Single L isting Window

If you are using two logic protocol analyzer modules and one is connected to the
upstream side of a link and the other module is connected to the downstream side,
display both
the following steps:

1. Select New D
Window wizard.

2. Click List

3. Press the Ctrl key on your keyboard and select the two modules from the

Data from

Both modules should be selected in the wizard.

4. Click Next >.

5. Enter a name for the new Listing window and then click Finish.

The wizard will close and display the data from both modules in the new
listing window.

6. If necessary, edit the window by adding or moving columns to display the
data that you are interested in.

sides of the link in a single listing window. To do this, complete

ata Window from the Window menu to start the New Data

ing and then Click OK.

list.

Change the Data Display in the Listing or Waveform Windows

The logic protocol analyzer provides different ways for viewing data in Listing
and Waveform windows. Change the display settings in the properties pages of
either display window:

ick the Properties icon

1. Cl
pages for the respective display.

ick the Disassembly tab to select the Disassembly property page.

2. Cl

3. Change the display items as needed.

The following table lists some of the display settings that you can change in the
Listing window.

in either display window to open the property

76 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual

Listing Window

Table 24: Logic

Disassembly p
page selections Settings Description

Show

Highlight

mble Across Gaps

Disasse

protocol analyzer disassembly display options

roperty

All (default)

Non-Idle Sam

TLP/DLLPs O

TLPs Only Only samples containing

TLP Headers Only Only samples containing

None (de

Yes or No

ples

nly

fault)

(default)

All required d
disassembled and shown
including logical idle
samples

Logical idle samples are
hidden

Only sample
TLPs and DLLPs are shown

TLPs are shown

TLP heade

Nothing is highlighted

General
setting. (not recommended
for PCI Express data)

ata i s

s containing

rs are shown

listing window

Any errors in link traffic detected by the disassembler are displayed regardless of
the display option that you selected.

Bus-SpecificFields

Disassemble and Display

Extended Link Details

Calculate CRC

In the Controls area of the Disassembly property page, select any of the following
controls to change the way data is displayed.

When working with bidirectional data with a single module, the data window can
only disassemble and display either upstream or downstream data. Select the data
thatyouwanttoviewintheListingwindow.

Set the Extended Link Details mode to ON or OFF to show or hide extended
packet information in the Listing window. If you set it to OFF, the Link_Details
column displays general packet information on a single line. If you set it to ON,
the Link_Details column displays extended packet information on multiple lines.
All packet fields are decoded and displayed in the Link_Details column. TLP
payload data is displayed double word aligned along with the lower word address
starting with the address acquired in the TLP header.

The disassembler calculates the CRCs for all packets when Calculate CRS is set to
ON. If the calculated value differs from the value acquired from the link, an error
message is displayed in the Link_Details column. The default setting is OFF.

Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual 77

Listing Window

By default, the
is a TLP, or with the sample containing the SDP if it is a DLLP. By setting this
property to ON, the packet field values are displayed on the same line as the
TLP_fmttype and DLLP_type group values.

field values are aligned with the sample containing the STP if it

10-Bit Mode Acquisition

When the logic protocol analyzer is configuredtoacquirethelinkin10-bitmode,
the Listing window displays the symbol encoding in the individual lane columns.
No further link analysis is performed.

Change from Binary Listing Symbol Tables to 10-Bit Mode

To change the radix of a binary listing symbol table to radix in 10-bit mode
acquisi

1. Select a column and right-click.

2. Select one of the symbol files from the list, or click Other andthennavigate

tion, perform the following steps:

to the location of the symbol file.

78 Tektronix Logic Protocol Analyzer Solutions for PCI Express 3.0 Instruction Manual