Tektronix KPXI Ultra-High Speed DIO Card User's Manual Primary User

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KPXI Ultra-High Speed DIO Card

User’s Manual

KPXI-DIO80-900-01 Rev. A / January 2007

A GREATER MEASURE OF CONFIDENCE

ECA 42912

WARRANTY

Keithley Instruments, Inc. warrants this product to be free from defects in material and workmanship for a period of
1 year from date of shipment.

Keithley Instruments, Inc. warrants the following items for 90 days from the date of shipment: probes, cables,
rechargeable batteries, diskettes, and documentation.

During the warranty period, we will, at our option, either repair or replace any product that proves to be defective.

To exercise this warranty, write or call your local Keithley Instruments representative, or contact
Keithley Instruments headquarters in Cleveland, Ohio. You will be given prompt assistance and return instructions.
Send the product, transportation prepaid, to the indicated service facility. Repairs will be made and the product
returned, transportation prepaid. Repaired or replaced products are warranted for the balance of the original
warranty period, or at least 90 days.

LIMITATION OF WARRANTY

This warranty does not apply to defects resulting from product modification without Keithley Instruments’ express
written consent, or misuse of any product or part. This warranty also does not apply to fuses, software,
non-rechargeable batteries, damage from battery leakage, or problems arising from normal wear or failure to follow
instructions.

THIS WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING ANY
IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR USE. THE REMEDIES
PROVIDED HEREIN ARE BUYER’S SOLE AND EXCLUSIVE REMEDIES.

NEITHER KEITHLEY INSTRUMENTS, INC. NOR ANY OF ITS EMPLOYEES SHALL BE LIABLE FOR ANY
DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF
ITS INSTRUMENTS AND SOFTWARE EVEN IF KEITHLEY INSTRUMENTS, INC., HAS BEEN ADVISED IN
ADVANCE OF THE POSSIBILITY OF SUCH DAMAGES. SUCH EXCLUDED DAMAGES SHALL INCLUDE, BUT
ARE NOT LIMITED TO: COSTS OF REMOVAL AND INSTALLATION, LOSSES SUSTAINED AS THE RESULT
OF INJURY TO ANY PERSON, OR DAMAGE TO PROPERTY.

A G R E A T E R M E A S U R E O F C O N F I D E N C E

Keithley Instruments, Inc.

Corporate Headquarters • 28775 Aurora Road • Cleveland, Ohio 44139

440-248-0400 • Fax: [phone] • 1-888-KEITHLEY (534-8453) • www.keithley.com

12/06

KPXI

Ultra-High Speed DIO Card

User’s Manual

©2007, Keithley Instruments, Inc.

Document Number:

All rights reserved.

Cleveland, Ohio, U.S.A.

KPXI-DIO80-900-01 Rev. A / January 2007

Manual Print History KPXI Ultra-High Speed DIO Card User’s Manual

Manual Print History

The print history shown below lists the printing dates of all Revisions and Addenda created for this
manual. The Revision Level letter increases alphabetically as the manual undergoes subsequent
updates. Addenda, which are released between Revisions, contain important change information that
the user should incorporate immediately into the manual. Addenda are numbered sequentially. When a
new Revision is created, all Addenda associated with the previous Revision of the manual are
incorporated into the new Revision of the manual. Each new Revision includes a revised copy of this
print history page.

Revision A (Document Number KPXI-DIO80-900-01) ........................................January 2007

All Keithley Instruments product names are trademarks or registered trademarks of Keithley Instruments, Inc.
Other brand names are trademarks or registered trademarks of their respective holders.

KPXI-DIO80-900-01 Rev. A / January 2007

The following safety precautions should be observed before using this product and any associated instrumentation. Although
some instruments and accessories would normally be used with non-hazardous voltages, there are situations where hazardous
conditions may be present.

This product is intended for use by qualified personnel who recognize shock hazards and are familiar with the safety precautions
required to avoid possible injury. Read and follow all installation, operation, and maintenance information carefully before using
the product. Refer to the manual for complete product specifications.

If the product is used in a manner not specified, the protection provided by the product may be impaired.

The types of product users are:

Responsible body is the individual or group responsible for the use and maintenance of equipment, for ensuring that the
equipment is operated within its specifications and operating limits, and for ensuring that operators are adequately trained.

Operators use the product for its intended function. They must be trained in electrical safety procedures and proper use of the
instrument. They must be protected from electric shock and contact with hazardous live circuits.

Maintenance personnel perform routine procedures on the product to keep it operating properly, for example, setting the line
voltage or replacing consumable materials. Maintenance procedures are described in the manual. The procedures explicitly state
if the operator may perform them. Otherwise, they should be performed only by service personnel.

Safety Precautions

Service personnel are trained to work on live circuits, and perform safe installations and repairs of products. Only properly

trained service personnel may perform installation and service procedures.

Keithley Instruments products are designed for use with electrical signals that are rated Measurement Category I and
Measurement Category II, as described in the International Electrotechnical Commission (IEC) Standard IEC 60664. Most
measurement, control, and data I/O signals are Measurement Category I and must not be directly connected to mains voltage or
to voltage sources with high transient over-voltages. Measurement Category II connections require protection for high transient
over-voltages often associated with local AC mains connections. Assume all measurement, control, and data I/O connections are
for connection to Category I sources unless otherwise marked or described in the Manual.

Exercise extreme caution when a shock hazard is present. Lethal voltage may be present on cable connector jacks or test
fixtures. The American National Standards Institute (ANSI) states that a shock hazard exists when voltage levels greater than
30V RMS, 42.4V peak, or 60VDC are present. A good safety practice is to expect that hazardous voltage is present in any
unknown circuit before measuring.

Operators of this product must be protected from electric shock at all times. The responsible body must ensure that operators
are prevented access and/or insulated from every connection point. In some cases, connections must be exposed to potential
human contact. Product operators in these circumstances must be trained to protect themselves from the risk of electric shock.
If the circuit is capable of operating at or above 1000 volts, no conductive part of the circuit may be exposed.

Do not connect switching cards directly to unlimited power circuits. They are intended to be used with impedance limited sources.
NEVER connect switching cards directly to AC mains. When connecting sources to switching cards, install protective devices to
limit fault current and voltage to the card.

Before operating an instrument, make sure the line cord is connected to a properly grounded power receptacle. Inspect the
connecting cables, test leads, and jumpers for possible wear, cracks, or breaks before each use.

12/06

When installing equipment where access to the main power cord is restricted, such as rack mounting, a separate main input
power disconnect device must be provided, in close proximity to the equipment and within easy reach of the operator.

For maximum safety, do not touch the product, test cables, or any other instruments while power is applied to the circuit under
test. ALWAYS remove power from the entire test system and discharge any capacitors before: connecting or disconnecting
cables or jumpers, installing or removing switching cards, or making internal changes, such as installing or removing jumpers.

Do not touch any object that could provide a current path to the common side of the circuit under test or power line (earth) ground.
Always make measurements with dry hands while standing on a dry, insulated surface capable of withstanding the voltage being
measured.

The instrument and accessories must be used in accordance with its specifications and operating instructions or the safety of the
equipment may be impaired.

Do not exceed the maximum signal levels of the instruments and accessories, as defined in the specifications and operating
information, and as shown on the instrument or test fixture panels, or switching card.

When fuses are used in a product, replace with same type and rating for continued protection against fire hazard.

Chassis connections must only be used as shield connections for measuring circuits, NOT as safety earth ground connections.

If you are using a test fixture, keep the lid closed while power is applied to the device under test. Safe operation requires the use
of a lid interlock.

If a screw is present, connect it to safety earth ground using the wire recommended in the user documentation.

!

The symbol on an instrument indicates that the user should refer to the operating instructions located in the manual.

The symbol on an instrument shows that it can source or measure 1000 volts or more, including the combined effect of
normal and common mode voltages. Use standard safety precautions to avoid personal contact with these voltages.

The symbol on an instrument shows that the surface may be hot. Avoid personal contact to prevent burns.

The symbol indicates a connection terminal to the equipment frame.

The WARNING heading in a manual explains dangers that might result in personal injury or death. Always read the associated
information very carefully before performing the indicated procedure.

The CAUTION heading in a manual explains hazards that could damage the instrument. Such damage may invalidate the
warranty.

Instrumentation and accessories shall not be connected to humans.

Before performing any maintenance, disconnect the line cord and all test cables.

To maintain protection from electric shock and fire, replacement components in mains circuits, including the power transformer,
test leads, and input jacks, must be purchased from Keithley Instruments. Standard fuses, with applicable national safety
approvals, may be used if the rating and type are the same. Other components that are not safety related may be purchased
from other suppliers as long as they are equivalent to the original component. (Note that selected parts should be purchased only
through Keithley Instruments to maintain accuracy and functionality of the product.) If you are unsure about the applicability of a
replacement component, call a Keithley Instruments office for information.

To clean an instrument, use a damp cloth or mild, water based cleaner. Clean the exterior of the instrument only. Do not apply
cleaner directly to the instrument or allow liquids to enter or spill on the instrument. Products that consist of a circuit board with
no case or chassis (e.g., data acquisition board for installation into a computer) should never require cleaning if handled
according to instructions. If the board becomes contaminated and operation is affected, the board should be returned to the
factory for proper cleaning/servicing.

Table of Contents

Section Topic Page

1 Introduction............................................................................................. 1-1

Introduction ................................................................................................. 1-2

Safety symbols and terms .......................................................................... 1-2

Applications ................................................................................................ 1-2

Features...................................................................................................... 1-3

Specifications.............................................................................................. 1-3

General Specifications ......................................................................... 1-3

Supporting software.................................................................................... 1-3

Programming library............................................................................. 1-4

KDAQ-LVIEW LabVIEW® driver .......................................................... 1-4

Unpacking and inspection........................................................................... 1-4

Inspection for damage.......................................................................... 1-4

Shipment contents ............................................................................... 1-4

Instruction manual................................................................................ 1-4

Repacking for shipment........................................................................ 1-5

2 Installation............................................................................................... 2-1

Introduction ................................................................................................. 2-2

Handling precautions .................................................................................. 2-2

PCI configuration ........................................................................................ 2-2

Plug-and-play ....................................................................................... 2-2

Configuration........................................................................................ 2-2

Troubleshooting.................................................................................... 2-2

Installation................................................................................................... 2-3

Layout .................................................................................................. 2-6

Terminal blocks .................................................................................... 2-6

3 Connection and Operation .................................................................. 3-1

Connector Pin Assignment ......................................................................... 3-2

Wiring and Termination ........................................................................ 3-3

Operation.................................................................................................... 3-4

Configuration........................................................................................ 3-4

Block diagram ...................................................................................... 3-5

Digital I/O data flow .............................................................................. 3-6

Input FIFO and output FIFO................................................................. 3-6

Bus-mastering DMA ............................................................................. 3-7

Scatter/gather DMA.............................................................................. 3-8

Clocking mode ..................................................................................... 3-8

Starting mode ....................................................................................... 3-9

Active terminator ................................................................................ 3-10

Digital input operation mode............................................................... 3-10

Digital output operation mode ............................................................ 3-15

Auxiliary DIO ...................................................................................... 3-18

8254 Programmable Interval Timer .......................................................... 3-19

Intel® (NEC®) 8254 ........................................................................... 3-19

Control byte........................................................................................ 3-19

Mode definition................................................................................... 3-20

Table of Contents KPXI Ultra-High Speed DIO Card User’s Manual

Section Topic Page

4 Registers .................................................................................................. 4-1

Introduction to registers............................................................................... 4-2

I/O port base address ........................................................................... 4-2

DI_CSR: DI Control and Status Register ............................................. 4-3

DO_CSR: DO Control and Status Register .......................................... 4-5

Auxiliary Digital I/O Register ................................................................. 4-6

INT_CSR: Interrupt Control and Status Register ................................. 4-7

DI_FIFO: DI FIFO direct access port ................................................... 4-7

DO_FIFO: DO external data FIFO direct access port .......................... 4-8

FIFO_CR: FIFO almost empty/full register .......................................... 4-8

POL_CNTRL: Control Signal Polarity Control Register ....................... 4-9

PLX® PCI-9080 DMA Control Registers ............................................ 4-10

Appendix Topic Page

A KDIO-DRVR User’s Guide ................................................................... A-1

Introduction to KDIO-DRVR ....................................................................... A-2

About the KDIO-DRVR software.......................................................... A-2

KDIO-DRVR hardware support............................................................ A-2

KDIO-DRVR language support............................................................ A-2

KDIO-DRVR overview ................................................................................ A-3

General configuration function group .................................................. A-3

Actual sampling rate function group .................................................... A-4

Analog output function group............................................................... A-4

Digital input function group .................................................................. A-4

Digital output function group ................................................................ A-6

Timer/counter function group............................................................... A-7

DIO function group .............................................................................. A-8

Creating a KDIO-DRVR application ........................................................... A-9

Contiguous memory allocation in driver for continuous operation....... A-9

Fundamentals of building Windows XP/2000 Application.......................... A-9

Microsoft® Visual Basic (Version 6.0) .................................................. A-9

Using Microsoft Visual Basic.NET ...................................................... A-11

Microsoft Visual C/C++....................................................................... A-11

KDIO-DRVR application hints ................................................................... A-11

Digital input programming hints ......................................................... A-12

Digital output programming hints....................................................... A-17

DAQ event message programming hints........................................... A-21

Interrupt event message programming hints ..................................... A-22

Continuous data transfer in KDIO-DRVR ................................................. A-23

Continuous data transfer mechanism................................................ A-23

Double-buffered / multiple-buffered DI operation............................... A-23

KDIO-DRVR utilities for Win32................................................................. A-25

KDIO-DRVR configuration utility (configdrv)...................................... A-25

KDIO-DRVR data file converter utility (KIDAQCvt)............................ A-26

B KDIO-DRVR Function Reference....................................................... B-1

Function description................................................................................... B-2

Data types............................................................................................ B-2

Function reference............................................................................... B-2

Status Codes............................................................................................ B-38

Data file format......................................................................................... B-40

Header............................................................................................... B-40

ChannelRange................................................................................... B-41

Data Block ......................................................................................... B-42

Function Support...................................................................................... B-43

ii KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Table of Contents

Appendix Topic Page

C KIDAQ®-LabVIEW Compatible Interface Guide............................. C-1

Introduction to KIDAQ®-LabVIEW ............................................................. C-2

Overview.............................................................................................. C-2

Using KIDAQ LabVIEW VIs in LabVIEW............................................. C-2

KIDAQ LabVIEW Programming........................................................... C-3

Device Driver Handling .............................................................................. C-4

Windows XP/2000 Device Driver......................................................... C-4

Driver Utility ......................................................................................... C-4

KIDAQ Utilities ........................................................................................... C-4

KIDAQ Registry/Configuration utility.................................................... C-4

KIDAQ Devices Explorer ..................................................................... C-4

KIDAQ LabVIEW VIs Overview.................................................................. C-5

Analog Input VIs .................................................................................. C-6

Analog Output VIs................................................................................ C-6

Digital I/O VIs....................................................................................... C-7

Timer/Counter VIs................................................................................ C-7

Calibration and Configuration VIs ........................................................ C-8

Error Handler VI................................................................................... C-8

Distribution of Applications......................................................................... C-8

Windows XP/2000 ............................................................................... C-8

D KIDAQ®-LabVIEW Compatible Function Reference..................... D-1

Introduction ................................................................................................ D-2

Hardware support....................................................................................... D-2

KPXI-DIO series: ................................................................................. D-2

KPXI-DAQ series: ................................................................................ D-2

Digitizer series: .................................................................................... D-2

Analog input VIs......................................................................................... D-3

Easy analog input VIs.......................................................................... D-3

Intermediate analog input VIs.............................................................. D-7

Analog output VIs..................................................................................... D-21

Easy analog output VIs...................................................................... D-21

Intermediate analog output VIs.......................................................... D-24

Advanced analog output VIs.............................................................. D-32

Digital I/O VIs ........................................................................................... D-33

Easy Digital I/O VIs............................................................................ D-33

Intermediate Digital I/O VIs................................................................ D-37

Advanced Digital I/O VIs.................................................................... D-45

Counter VIs .............................................................................................. D-46

Easy Counter VIs .............................................................................. D-46

Intermediate Counter VIs .................................................................. D-50

Advanced Counter VIs ...................................................................... D-63

Calibration and Configuration VIs ............................................................ D-67

Calibration VIs .................................................................................. D-67

Other Calibration and Configuration VIs............................................ D-68

Service VIs ............................................................................................... D-70

Error Codes ............................................................................................. D-71

AI Range Codes ...................................................................................... D-73

AI Data Format ....................................................................................... D-76

Service Form

KPXI-DIO80-900-01 Rev. A / January 2007 iii

Table of Contents KPXI Ultra-High Speed DIO Card User’s Manual

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iv KPXI-DIO80-900-01 Rev. A / January 2007

List of Figures

Section Figure Title Page

2 Figure 2-1 Typical PXI module installation...................................................... 2-4

Figure 2-2 Device manager (successful installation) ...................................... 2-5

Figure 2-3 KPXI-DIO-32-80M Layout Diagram ............................................... 2-6

3 Figure 3-1 CN1 pin assignment ...................................................................... 3-3

Figure 3-2 Block diagram................................................................................ 3-5

Figure 3-3 Data flow of digital input................................................................. 3-6

Figure 3-4 Data flow of digital output .............................................................. 3-6

Figure 3-5 Maximum data throughput............................................................. 3-7

Figure 3-6 Scatter/gather DMA for digital output............................................. 3-8

Figure 3-7 Timer configuration ........................................................................ 3-9

Figure 3-8 FIFO operation flow (A) .............................................................. 3-10

Figure 3-9 FIFO operation flow (B) ............................................................... 3-11

Figure 3-10 External clock mode operation flow............................................. 3-12

Figure 3-11 DI-REQ as input data strobe (when rising edge active) .............. 3-12

Figure 3-12 DI-REQ as input data strobe (when falling edge active).............. 3-12

Figure 3-13 Digital input DMA operation flow ................................................. 3-13

Figure 3-14 DI-REQ and DI-ACK handshaking............................................... 3-13

Figure 3-15 Data queued in FIFO ................................................................... 3-14

Figure 3-16 Digital Output DMA in Internal Clock Mode ................................. 3-15

Figure 3-17 DO-REQ as output data strobe.................................................... 3-15

Figure 3-18 Digital output DMA in handshaking mode.................................... 3-16

Figure 3-19 DO-REQ and DO-ACK Handshaking .......................................... 3-16

Figure 3-20 Burst handshaking mode............................................................. 3-17

Figure 3-21 Burst handshaking mode operation flow...................................... 3-17

Figure 3-22 Pattern generator function operation ........................................... 3-18

Appendix Figure Title Page

A Figure A-1 Open Project dialog box .............................................................. A-10

Figure A-2 Basic KDIO-DRVR building blocks .............................................. A-12

Figure A-3 One-shot digital input programming............................................. A-13

Figure A-4 Synchronous continuous digital input programming.................... A-14

Figure A-5 Non-multiple-buffered asynchronous continuous digital input ..... A-15

Figure A-6 Multiple-buffered asynchronous continuous digital input ............. A-16

Figure A-7 Synchronous continuous digital output programming.................. A-18

Figure A-8 Asynchronous continuous digital output programming ................ A-18

Figure A-9 Pattern generation digital output programming ........................... A-19

Figure A-10 Multiple-buffered asynchronous continuous digital output ........... A-20

Figure A-11 Double/multiple buffer mode principle ......................................... A-24

Figure A-12 Driver configuration window......................................................... A-25

Figure A-13 DAQ File Conversion Utility ......................................................... A-26

Figure A-14 Loading source binary data file.................................................... A-27

List of Figures KPXI Ultra-High Speed DIO Card User’s Manual

Appendix Figure Title Page

B Figure B-1 TOGGLE_OUTPUT mode timing .................................................. B-4

Figure B-2 PROG_ONE_SHOT mode timing ................................................. B-4

Figure B-3 RATE_GENERATOR mode timing ................................................ B-5

Figure B-4 SQ_WAVE_RATE_GENERATOR mode timing ............................ B-5

Figure B-5 SOFT_TRIG mode timing ............................................................. B-5

Figure B-6 HARD_TRIG mode timing............................................................. B-5

Figure B-7 DAQ File Conversion Utility......................................................... B-42

C Figure C-1 Function Browser Options............................................................. C-2

Figure C-2 Functions palette........................................................................... C-3

Figure C-3 Keithley PXI Devices Explorer ...................................................... C-5

D Figure D-1 Analog input palette ...................................................................... D-3

Figure D-2 Analog output palette .................................................................. D-21

Figure D-3 Digital I/O palette......................................................................... D-33

vi KPXI-DIO80-900-01 Rev. A / January 2007

List of Tables

Section Table Title Page

1 Table 1-1 General Specifications................................................................... 1-3

3 Table 3-1 Connector pin assignment legend ................................................. 3-2

Table 3-2 32-bit I/O data path ........................................................................ 3-4

Table 3-3 Control Byte ................................................................................. 3-19

Table 3-4 Control Byte: (Base + 7, Base + 11) ............................................ 3-19

Table 3-5 SC1 and SC1 - Select Counter (Bit 7 and Bit 6) .......................... 3-19

Table 3-6 RL1 and RL0 - Select Read/Load operation (Bit 5 and Bit 4)...... 3-20

Table 3-7 M2, M1 and M0 - Select Operating Mode (Bit 3, Bit 2, and Bit 1) 3-20

Table 3-8 BCD - Select Binary/BCD Counting (Bit 0) .................................. 3-20

4 Table 4-1 Registers format ............................................................................ 4-2

Table 4-3 DI control and status register data format...................................... 4-3

Table 4-2 I/O port base address .................................................................... 4-3

Table 4-4 DO Control and status register data format................................... 4-5

Table 4-5 Auxiliary digital I/O register data format ......................................... 4-6

Table 4-6 Interrupt control and status register data format............................ 4-7

Table 4-7 DI FIFO direct access port data format.......................................... 4-7

Table 4-8 DO external data FIFO direct access port data format.................. 4-8

Table 4-9 FIFO almost empty/full register data format .................................. 4-9

Table 4-10 Control signal polarity control register data format ........................ 4-9

Appendix Table Title Page

B Table B-1 Suggested data types.................................................................... B-2

Table B-2 Channel_Pn data format.............................................................. B-16

Table B-3 Status codes returned by KDIO-DRVR........................................ B-38

Table B-4 Data file header ........................................................................... B-40

Table B-5 Data structure of ChannelRange unit .......................................... B-41

Table B-6 KDIO-DRVR model function ........................................................ B-43

D Table D-1 KI AI acquire waveform.................................................................. D-3

Table D-2 KI AI acquire waveforms ................................................................ D-4

Table D-3 KI AI sample channel..................................................................... D-6

Table D-4 KI AI sample channels ................................................................... D-6

Table D-5 KI AI clear ...................................................................................... D-7

Table D-6 KI AI config .................................................................................... D-9

Table D-7 2-byte binary array....................................................................... D-12

Table D-8 Scaled and Binary Arrays ............................................................ D-14

Table D-9 Scaled Array ................................................................................ D-16

Table D-10 KI AI single scan .......................................................................... D-17

Table D-11 KI AI start ..................................................................................... D-19

Table D-12 KI AO generate waveform ........................................................... D-22

Table D-13 KI AO generate waveforms.......................................................... D-22

Table D-14 KI AO update channel.................................................................. D-23

List of Tables KPXI Ultra-High Speed DIO Card User’s Manual

Appendix Table Title Page

D Table D-15 KI AO update channels ............................................................... D-24

Table D-16 KI AO clear.................................................................................. D-25

Table D-17 KI AO Config ............................................................................... D-25

Table D-18 KI AO start................................................................................... D-27

Table D-19 KI AO wait ................................................................................... D-28

Table D-20 KI AO write binary array.............................................................. D-29

Table D-21 KI AO write binary array scaled array ......................................... D-30

Table D-22 KI AO Trigger and Gate Config ................................................... D-32

Table D-23 KI Read from Digital Line ............................................................ D-34

Table D-24 KI Read from Digital Port ............................................................ D-34

Table D-25 KI Write to Digital Line................................................................. D-35

Table D-26 KI Write to Digital Port................................................................. D-36

Table D-27 KI DIO Clear................................................................................ D-37

Table D-28 KI DIO Config .............................................................................. D-38

Table D-29 KI DIO Read................................................................................ D-40

Table D-30 KI DIO Start................................................................................. D-42

Table D-31 KI DIO Write ................................................................................ D-43

Table D-32 KI DIO Port Config ...................................................................... D-45

Table D-33 KI Count Events or Time ............................................................. D-46

Table D-34 KI Generate Delayed Pulse......................................................... D-47

Table D-35 KI Generate Pulse-Train.............................................................. D-48

Table D-36 KI Measure Pulse-Width or Period.............................................. D-49

Table D-37 KI Continuous Pulse Generator Config ....................................... D-50

Table D-38 KI Counter Divider Config ........................................................... D-52

Table D-39 KI Counter Read ......................................................................... D-53

Table D-40 KI Counter Start........................................................................... D-54

Table D-41 KI Counter Stop........................................................................... D-55

Table D-42 KI Delayed Pulse Generator Config ............................................ D-56

Table D-43 KI Down Counter or Divider Config............................................. D-58

Table D-44 KI Event or Time Counter Config ................................................ D-59

Table D-45 KI Pulse-Width or Period Measurement Config .......................... D-61

Table D-46 KI UpDown Counter Config......................................................... D-62

Table D-47 KI ICTR Control........................................................................... D-63

Table D-48 KI KPXI-DAQ series devices and Digitizer Series Calibrate ...... D-67

Table D-49 KI Route Signal .......................................................................... D-68

Table D-50 KI SSI Control ............................................................................ D-69

Table D-51 KI Error Handler ......................................................................... D-70

Table D-52 Error Codes: KIDAQ LabVIEW VIs ............................................. D-71

Table D-53 Analog Input Range .................................................................... D-73

Table D-54 Valid analog input ranges (specified by module)......................... D-75

Table D-55 Analog Input data format (by Model)........................................... D-76

viii KPXI-DIO80-900-01 Rev. A / January 2007

In this section:

Top ic Pag e

Introduction ....................................................................................... 1-2

Safety symbols and terms ............................................................... 1-2

Applications ...................................................................................... 1-2

Features ............................................................................................. 1-3

Specifications.................................................................................... 1-3

Supporting software ......................................................................... 1-3

Section 1

Introduction

General Specifications.................................................................. 1-3

Programming library ..................................................................... 1-4

KDAQ-LVIEW LabVIEW® driver................................................... 1-4

Unpacking and inspection ............................................................... 1-4

Inspection for damage .................................................................. 1-4

Shipment contents........................................................................ 1-4

Instruction manual ........................................................................ 1-4

Repacking for shipment................................................................ 1-5

Section 1: Introduction KPXI Ultra-High Speed DIO Card User’s Manual

Introduction

The KPXI-DIO-32-80M module is an ultra-high speed digital I/O module, which consists of 32
digital input or output channels. High performance designs and the state-of-the-art technology
make this module ideal for high speed digital input and output applications.

The module performs high-speed data transfers using bus mastering DMA and scatter/gather via
32-bit PCI bus architecture. The maximum data transfer rates can be up to 80MB per second. It is
very suitable for interface between high speed peripherals and your computer system.

The module is configured as two ports, PORTA and PORTB, each port controls 16 digital I/O lines.
The I/O can configure as either input or output, and 8-bit or 16-bit. Depending on the connected
device, users can configure it to meet many high speed digital I/O requirements.

There are 4 different digital I/O operation modes supported:

1. Internal Clock: the digital input and output operations are paced by internal clock and

transferred by bus mastering DMA.

2. External Clock: the digital input operation is paced by external strobe signal ( DIREQ )

and transferred by bus mastering DMA.

3. Handshaking: through REQ signal and ACK signal, the digital I/O data can have

simple handshaking data transfer.

4. Pattern Generation: You can output a digital pattern repeatedly at a predetermined

rate. The transfer rate is controlled by internal timer.

Safety symbols and terms

The following symbols and terms may be found on the KPXI-Isolated DIO series module or used in
this manual.

The symbol indicates that the user should refer to the operating instructions located in the

!

manual.

The symbol shows that high voltage may be present on the terminal(s). Use standard safety
precautions to avoid personal contact with these voltages.

The symbol on an instrument shows that the surface may be hot. Avoid personal contact to
prevent burns.

The WARNING heading used in this manual explains dangers that might result in personal injury
or death. Always read the associated information very carefully before performing the indicated
procedure.

The CAUTION heading used in this manual explains hazards that could damage the unit. Such
damage may invalidate the warranty.

Applications

• Interface to high-speed peripherals

• High-speed data transfers from other computers

• Automated test equipment (ATE)

• Electronic and logic testing

• Interface to external high-speed A/D and D/A converter

• Digital pattern generator

• Waveform and pulse generation

• Parallel digital communication

1-2 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 1: Introduction

Features

The Model KPXI-DIO-32-80M Ultra-High Speed DIO module provides the following advanced
features:

• 32 digital input/output channels

• Extra 4-bit TTL digital input and output channels

• Transfer up to 80M Bytes per second

• SCSI active terminator for high speed and long distance data transfer

• 32-bit PCI bus

• Plug-and-play

• Scatter/gather DMA

• On-board internal clock generator

• Internal timer/external clock controls input sampling rate

• Internal timer control digital output rate

• ACK and REQ for handshaking

• TRIG signal controls start of data acquisition/pattern generation

• On-board 64KB FIFO

• 100-pin SCSI style connector

Specifications

Refer to the product data sheet for updated KPXI Ultra-High Speed 32-Channel DIO PXI module
specifications. Check the Keithley Instruments website at www.keithley.com for the latest updates
to the specifications. See below for

General Specifications

Table 1-1

General Specifications

Dimensions

Operating
temperature

Storage temperature

Humidity

Power Consumption

Connector

General Specifications.

179mm (L) x 102mm (H)

0°C to 60ºC (Operating)

-20ºC to 80ºC

5% to 90% non-condensing

+5V @ 830mA max. with on-board terminator off
+5V @ 1A max. with on-board terminator on

100-pin male SCSI-II style cable connector

Supporting software

Keithley Instruments provides versatile software drivers and packages for users’ different
approaches to building a system.

All software options are included in the Keithley Instruments CD.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 1-3

Section 1: Introduction KPXI Ultra-High Speed DIO Card User’s Manual

Programming library

A function library (KDIO-DRVR) is provided for customers who are writing their own programs.
KDIO-DRVR includes device drivers and DLL’s for Windows XP
binary compatible across Windows XP/2000. Therefore, all applications developed with
KDIO-DRVR are compatible across Windows XP/2000. The developing environment can be VB,
VC++, BC5, or any Windows programming language that allows calls to a DLL. Documentation
includes a User's Guide (refer to
Reference (refer to Appendix B: KDIO-DRVR Function Reference).

KDAQ-LVIEW LabVIEW® driver

KDAQ-LVIEW contains the VI’s which are used to interface with National Instruments’ Lab-VIEW1
software package. The KDAQ-LVIEW supports Windows XP/2000. The LabVIEW driver is shipped
free with the board. Documentation includes an Interface Guide (refer to

LabVIEW Compatible Interface Guide), and an interface Function Reference (refer to Appendix D:
KIDAQ®-LabVIEW Compatible Function Reference).

The above software drivers are shipped with the board.

Unpacking and inspection

Inspection for damage

CAUTION Your Model KPXI-DIO-32-80 module contains electro-static sensitive

components that can be easily be damaged by static electricity.

®

and Windows 2000®. DLL’s are

Appendix A: KDIO-DRVR User’s Guide) and a Function

Appendix C: KIDAQ®-

Therefore, handle the module on a grounded anti-static mat. The operator
should be wearing an anti-static wristband, grounded at the same point as the
anti-static mat.

The Model KPXI-DIO-32-80 Ultra-High Speed DIO module was carefully inspected electrically and
mechanically before shipment.

Inspect the module carton for obvious damages. Shipping and handling may damage the module.
Make sure there are no shipping and handling damages on the module’s carton before continuing.

After opening the carton, extract the module and place it only on a grounded anti-static surface
with component side up. Save the original packing carton for possible future shipment.

Again, inspect the module for damages. Report any damage to the shipping agent immediately.

Shipment contents

The following items are included with every Model KPXI-DIO-32-80 Ultra-High Speed DIO module
order:

• Model KPXI-DIO-32-80 Ultra-High Speed DIO module

• CD containing required software and manuals

Instruction manual

A CD-ROM containing this User’s Manual and required software is included with each
Model KPXI-DIO-32-80 Ultra-High Speed DIO module order. If a hardcopy of the User’s Manual is

1. National Instruments™, NI, and LabVIEW are trademarks of the National Instruments Corporation.

1-4 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 1: Introduction

required, you can order the Manual Package (Keithley Instruments Part Number:
KPXI-DIO80-900-01). The Manual Package includes an instruction manual and any pertinent
addenda.

Always check the Keithley Instruments’ website at www.keithley.com for the latest revision of the
manual. The latest manual can be downloaded (in PDF format) from the website.

Repacking for shipment

Should it become necessary to return the Model KPXI Ultra-High Speed DIO series module for
repair, carefully pack the unit in its original packing carton or the equivalent, and follow these
instructions:

• Call Keithley Instruments’ repair department at 1-888-KEITHLEY (1-888-534-8453) for a
Return Material Authorization (RMA) number.

• Let the repair department know the warranty status of the Model KPXI Ultra-High Speed
DIO series module.

• Write ATTENTION REPAIR DEPARTMENT and the RMA number on the shipping label.

• Complete and include the Service Form located at the back of this manual.

CAUTION The boards must be protected from static discharge and physical shock.

Never remove any of the socketed parts except at a static-free workstation.
Use the anti-static bag shipped with the product to handle the board. Wear a
grounded wrist strap when servicing.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 1-5

Section 1: Introduction KPXI Ultra-High Speed DIO Card User’s Manual

This page left blank intentionally.

1-6 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

In this section:

Top ic Pag e

Introduction ........................................................................................... 2-2

Handling precautions ........................................................................... 2-2

PCI configuration .................................................................................. 2-2

Installation ............................................................................................. 2-3

Section 2

Installation

Plug-and-play ................................................................................... 2-2

Configuration .................................................................................... 2-2

Troubleshooting................................................................................ 2-2

Layout............................................................................................... 2-6

Terminal blocks................................................................................. 2-6

Section 2: Installation KPXI Ultra-High Speed DIO Card User’s Manual

Introduction

This section contains information about handling and installing Keithley Instruments’ KIDAQ®
KPXI series modules:

• Handling precautions

• PCI configuration

• Installation

Handling precautions

CAUTION Use care when handling the KPXI series modules. The modules contain

electro-static sensitive components that can be easily damaged by static
electricity.

When handling, make sure to observe the following guidelines:

• Only handle the module on a grounded anti-static mat.

• Wear an an anti-static wristband that is grounded at the same point as the anti-static mat.

PCI configuration

Plug-and-play

The Interrupt and I/O port address are the variables associated with automatic configuration, the
resource allocation is managed by the system BIOS. Upon system power-on, the internal
configuration registers on the board interact with the BIOS. As a plug-and-play component, the
board requests an interrupt number via its PCI controller. The system BIOS responds with an
interrupt assignment based on the board information and system parameters. These system
parameters are determined by the installed drivers and the hardware load recognized by the
system. If this is the first time a KIDAQ
system, a hardware driver needs to be installed. Refer to

Configuration

Configuration is done on a board-by-board basis for all PXI boards on your system. Configuration
is controlled by the system and software. There is no jumper setting required (or available) for
base address, DMA, and interrupt IRQ.

The configuration is not static, but is subject to change with every boot of the system as new
boards are added or removed.

Troubleshooting

If your system doesn't boot or if you experience erratic operation with your PXI board in place, it's
likely caused by an interrupt conflict (perhaps the BIOS Setup is incorrectly configured). In
general, the solution, is to consult the BIOS documentation that comes with your system.

®

KPXI series module will be installed on your Windows®

Installation for detailed information.

NOTE For best module performance, install the module in a PXI slot that provides bus-

mastering capability.

2-2 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 2: Installation

Installation

Step 1. Install driver software

Windows® will find the new module automatically. If this is the first time a KPXI series digital I/O
module has been installed, a hardware driver needs to be installed. Use the following installation
procedure as a guide.

NOTE Keithley Instruments controllers are pre-loaded with the necessary drivers.

For Windows XP/2000:

1. Insert the CD shipped with the module. The CD should auto load. From the base menu
install the KDIO-DRVR. This is the hardware driver that recognizes the KPXI series
modules. If the CD does not auto load run, then under x:\KDIO-DRVR\DISK1\, you will find
SETUP.EXE (x is the drive letter of your CDROM). This will run the CD menu. On the CD
menu, click the driver for your model to install.

2. When you complete driver installation, turn off the system.

Step 2. Inspect the module

Keeping the “Handling precautions” information in mind, inspect the module for damage. With the
module placed on a firm flat surface, press down on all socketed IC's to make sure that they are
properly seated.

If the module does not pass the inspection, do not proceed with the installation.

CAUTION Do not apply power to the module if it has been damaged.

The module is now ready for installation.

Step 3. Install the module

Remove power from the system and install the KPXI card in an available slot.

The PXI connectors are rigid and require careful handling when inserted and removed. Improper
handling of modules can easily damage the backplane.

To insert the module into a PXI chassis, use the following procedure as a guide:

1. Turn off the system.

2. Align the module's edge with the card guide in the PXI chassis.

3. Slide the module into the chassis until resistance is felt from the PXI connector.

4. Push the ejector upwards and fully insert the module into the chassis. Once inserted, a
"click" can be heard from the ejector latch.

5. Tighten the screw on the front panel.

6. Turn on the system.

To remove a module from a PXI chassis, use the following procedure as a guide:

1. Turn off the system.

2. Loosen the screw on the front panel.

3. Push the ejector downwards and carefully remove the module from the chassis.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 2-3

Section 2: Installation KPXI Ultra-High Speed DIO Card User’s Manual

Figure 2-1

Typical PXI module installation

Typical PXI
chassis

Card guide

Front panel
screw

Modules edge

Ejector latch

Step 4. Verify installation

When the system is turned on for the first time with a new module present (or a module in a new
slot), Windows Add New Hardware Wizard attempts to locate the correct driver. If it cannot find
the correct driver, even after you have loaded the driver above in Step 1, then force the Add New
Hardware Wizard to look in Windows system32 directory. The driver files should be in this
location. If they are not, shutdown the system, remove the module, and restart the installation
process.

When the Add New Hardware Wizard finishes, the window will verify whether or not installation
was successful. To confirm if the module is installed correctly at a later time, use Windows Device
Manager. In the Device Manager under KIDAQ Boards, look for a device name matching the
model number of the newly installed board (see
installation is complete. If the board appears with a exclamation point or warning in Device
Manager, the installation was unsuccessful. If unsuccessful, use Device Manager to update the

2-4 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

Figure 2-2 for an example). If it is found,

KPXI Ultra-High Speed DIO Card User’s Manual Section 2: Installation

driver or un-install the module, power down the system, remove the module, and attempt
installation again from Step 1.

Figure 2-2

Device manager (successful installation)

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 2-5

Section 2: Installation KPXI Ultra-High Speed DIO Card User’s Manual

Layout

Figure 2-3

KPXI-DIO-32-80M Layout Diagram

Terminal blocks

The KPXI-DIO-32-80M can be connected with two daughter boards: KPXI-DIO-TB or
KPXI-32-DIO-TB. The functionality and connections are specified as follows:

Connect with KPXI-DIO-TB

The KPXI-DIO-TB is a direct connection for the add-on module that is equipped with a SCSI-100
connector. User can connect this terminal block with a 100-pin SCSI type cable (KPXI-DIO-CAB)
to the KPXI-DIO-32-80M. It is suitable for the applications of 32-bit digital input or 32-bit digital
output. The Model KPXI-32-DIO-TB can be used as well. Two of these terminal blocks combined
with a KPXI-DIO-CAB2 cable breaks up the pins into two separate 50 pin blocks allowing easier
access.

2-6 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

In this section:

Top ic Pag e

Connector Pin Assignment .................................................................. 3-2

Operation ............................................................................................... 3-4

Section 3

Connection and Operation

Wiring and Termination ..................................................................... 3-3

Configuration .................................................................................... 3-4

Block diagram................................................................................... 3-5

Digital I/O data flow........................................................................... 3-6

Input FIFO and output FIFO ............................................................. 3-6

Bus-mastering DMA ......................................................................... 3-7

Scatter/gather DMA .......................................................................... 3-8

Clocking mode.................................................................................. 3-8

Starting mode ................................................................................... 3-9

Active terminator............................................................................. 3-10

Digital input operation mode........................................................... 3-10

Digital output operation mode......................................................... 3-15

Auxiliary DIO................................................................................... 3-18

8254 Programmable Interval Timer ................................................... 3-19

Intel® (NEC®) 8254........................................................................ 3-19

Control byte .................................................................................... 3-19

Mode definition ............................................................................... 3-20

Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

Connector Pin Assignment

KPXI-DIO-32-80M comes equipped with one 100-pin SCSI type connector (CN1) located on the
face plate. The pin assignment of CN1 is illustrated in

Table 3-1

Connector pin assignment legend

Pins Signal Name Signal Type Signal Direction Description

1…50 GND GND Ground – these lines are the ground reference for

51..66 PB15…PB0 DATA I/O PortB bidirectional data lines-PB15 is the MSB,

67 DOACK CONTROL I Digital output Acknowledge lines – In

68 DOREQ CONTROL O Request line – In handshaking mode, DOREQ

69 DOTRIG CONTROL I DO TRIG- can be used to control the start of data

70…73 AUXDO3…0 DATA O AUX DO 3…0 – can be used as extra output data

85..100 PA1 5…PA0 DATA I/O PortA bidirectional data lines-PA15 is the MSB,

82 DIACK CONTROL O Digital output Acknowledge lines – In

83 DIREQ CONTROL I Request line – In handshaking mode, DIREQ

84 DITRIG CONTROL I DI TRIG – can be used to control the start of data

78…81 AUXDI3…0 DATA I AUX DI 3…0 – can be used as extra input data or

74…77 TERMPWR POWER TERMPWR -- 4.7V active terminator power

Table 3-1 and Figure 3-1.

all other signals

and PB0 is the LSB.

handshaking mode, DOACK carries handshaking
status information from the peripheral.

carries handshaking control information to
peripheral.

output in all DO modes and to control the stop of
pattern generation in pattern generation mode.

or can be used as extra control signals.

and PA0 is the LSB.

handshaking mode, DIACK carries handshaking
status information to the peripheral.

carries handshaking control information from
peripheral. In external clock mode, DIREQ carries
the external clock input.

acquisition in all DI modes.

can be used as extra control signals.

output

3-2 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

PA0

Figure 3-1

CN1 pin assignment

DI_TRG
DI_REQ
DI_ACK

TERMPWR
TERMPWR
TERMPWR
TERMPWR

DO_TRG
DO_REQ

DO_ACK

PA1

PA2

PA3
PA4

PA5

PA6
PA7

PA8

PA9

PA10

PA11

PA12
PA13
PA14
PA15

AUXI0
AUXI1
AUXI2
AUXI3

AUXO0
AUXO1
AUXO2
AUXO3

PB0

PB1

PB2
PB3

PB4

PB5
PB6
PB7

PB8

PB9

PB10

PB11

PB12
PB13

PB14

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

GND

50

GND

49

GND

48

GND

47

GND

46

GND

45

GND

44

GND

43

GND

42

GND

41

GND

40

GND

39

GND

38

GND

37

GND

36

GND

35

GND

34

GND

33

GND

32

GND

31

GND

30

GND

29

GND

28

GND

27

GND

26

GND

25

GND

24

GND

23

GND

22

GND

21

GND

20

GND

19

GND

18

GND

17

GND

16

GND

15

GND

14

GND

13

GND

12

GND

11

GND

10

GND

9

GND

8

GND

7

GND

6

GND

5

GND

4

GND

3

GND

2

GND

1

Wiring and Termination

Transmission line effects and environment noise, particularly on clock and control lines, can lead
to incorrect data transfers if you do not take care when running signal wires to and from the
devices.

Take the following precautions to ensure a uniform transformation line and minimize noise pickup:

1. Use twisted-pair wires to connect digital I/O signals to the device. Twist each digital I/O sig­nal with a GND line.

2. Place a shield around the wires connecting digital I/O signal to device.

3. Route signals to the devices carefully. Keep cabling away from noise sources, such as
video monitor.

For KPXI-DIO-32-80M, it is important to terminate your cable properly to reduce or eliminate signal
reflections in the cable. This module supports active terminator on board. You can enable or
disable the terminator by software selection. This is a good way to include termination on the
signal transmission.

Additional recommendations apply for all signal connections to your KPXI-DIO-32-80M, and are
listed as follows:

1. Separate KPXI-DIO-32-80M device signal lines from high-current or high-voltage line.
These lines are capable of inducing currents in or voltages on the KPXI-DIO-32-80M if they
run in parallel paths at a close distance. To reduce the magnetic coupling between lines,

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 3-3

Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

separate them by a reasonable distance if they run in parallel, or run the lines at right angles
to each other.

2. Do not run signal lines through conduits that also contain power lines.

3. Protect signal lines from magnetic fields.

Operation

This section provides the detailed operation information for the KPXI-DIO-32-80M, including I/O
configuration, block diagram, input/output FIFO, bus-mastering DMA, scatter/gather, clocking
mode, starting mode, termination, I/O transfer mode, and auxiliary digital I/O.

Configuration

The 32-bit I/O data path for the KPXI-DIO-32-80M can be configured as 8-bit, 16-bit, or 32-bit. The
possible configuration modes are listed as follows.

Table 3-2

32-bit I/O data path

Mode Channel Description

DI32 PORTA (DI0…DI15)

PORTB (DI16..DI31)

DO32 PORTA

(DO16…DO31)
PORTB

(DO0…DO15)
DI16DO16
(default mode)

DI16DO8 PORTA (DI0…DI15)

DI8DO16 PORTA (DI0…DI7)

DI8DO8 PORTA (DI0…DI7)

PORTA (DI0…DI15)

PORTB

(DO0…DO15)

PORTB (DO0…DO7)

PORTB

(DO0…DO15)

PORTB (DO0…DO7)

Both PORTA and PORTB
are configured as input
channel

Both PORTA and PORTB
are configured as output
channel

PORTA is 16-CH input
PORTB is 16-CH output

PORTA is 16-CH input
PORTB is 8-CH output

PORTA is 8-CH input
PORTB is 16-CH output

PORTA is 8-CH input
PORTB is 8-CH output

3-4 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

NOTE PORTA is default as Input channel; PORTB is default as output channel.

In DI32 mode, the PORTB has to be configured as the extension of PORTA, that is,
PORTB is the input port (DI16…DI31). PORTB control signals are disabled.

In DO32 mode, the PORTA has to be configured as the extension of PORTB, that is,
PORTA is the output port (DO16…DO31). PORTA control signals are disabled.

DI0: input LSB, DI31: input MSB;
DO0:output LSB, DO31:output MSB.
LSB: Least Significant Bit, MSB: Most Significant Bit

Block diagram

Figure 3-2 shows the block diagram of the KPXI-DIO-32-80M. The block diagram includes the I/O

registers, two 16K FIFOs, auxiliary DIO, active terminators, and so on.

Figure 3-2

Block diagram

PORTA: 16 Digital I/O Port can be set as terminated mode or non-terminated mode

PORTB: 16 Digital I/O Port can be set as terminated mode or non-terminated mode

FIFO: Two 16K words FIFO for digital I/O data buffer

AUX DO 3..0: Four auxiliary digital outputs

AUX DI 3..0: Four auxiliary digital inputs

DITRIG: Digital input trigger line

DIACK/DIREQ: Digital input handshaking signals

DOTRIG: Digital output trigger line

DOACK/DOREQ: Digital output handshaking signals

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 3-5

Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

Digital I/O data flow

When applying digital input functions, the data will be sampled into the input FIFO periodically and
then transfer to the system memory by the bus mastering DMA of the PCI Bridge (default
configuration).

Figure 3-3

Data flow of digital input

On the other hand, Figure 3-4 shows the data flow of 16-bit digital output operation. After the bus
mastering DMA of the PCI Bridge transfers the output data to the output FIFO, the KPXI-DIO-32­80M will output the data to the external devices in a pre-assigned period.

Figure 3-3 show the data flow of the 16-bit digital input operation.

Figure 3-4

Data flow of digital output

The width of local data bus on the KPXI-DIO-32-80M can be programmable to be 8-bit, 16-bit or
32-bit. The default data width is 16-bit. Port A is default to be input port, and Port B is default to be
output one. When 8-bit data width is applied, only the lower byte of the bus will be used. While we
program the data width to be 32-bit, the two ports will operate in the same manner.

Input FIFO and output FIFO

Because the data transfer rate between external devices and the KPXI-DIO-32-80M is
independent from that between KPXI-DIO-32-80M and the PXI bus, two 16K words FIFOs are
provided to be I/O buffers.

For digital input operation, data is sampled and transferred to the input FIFO. When the input FIFO
is non-empty, the PCI bridge will automatically transfer the data from the input FIFO to the system
memory in the background when the PXI bus is available.

When the data transfer rate from the external device to the input FIFO (DI pre-transfer rate) is
lower than that from input FIFO to system memory (DI post-transfer rate), the input FIFO is usually
empty. On the contrary, when DI pre-transfer rate is higher than DI post-transfer rate, the FIFO
becomes full and the overrun situation occurs if the data size is larger than the FIFO size, that is
16K samples. When DI overrun happens, the next input data will be lost until the input FIFO
becomes non-full once again. Users can check the overrun status by using the function
KDIO_DI_ContStatus. See
this function.

Appendix B: KDIO-DRVR Function Reference for more information on

3-6 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

For digital output operation, data is moved from system memory to the output FIFO by bus
mastering DMA, assume the data transfer rate is DO pre-transfer rate. Then, the data will be
transferred to the external devices periodically as we configured, assume the transfer rate is DO
post-transfer rate. When the DO pre-transfer rate is higher than the DO post-transfer rate, the
DMA transfer stops as the output FIFO becomes full. On the contrary, if DO pre-transfer rate is
lower than DO post-transfer rate. The underrun situation occurs as the output FIFO becomes
empty. The output data remains when underrun happens. User can check the underrun status by
using the function KDIO_DI_ContStatus. See
more information on this function.

NOTE The max data length should be 16K instead of 32K. Users can send repetitive pattern of

8-/16-/32-bit width with a length of 16K samples, because of the FIFO depth is as it is no
matter how wide the bus. Users should remember that the FIFO chip size is 32K bytes
with 16-bits width. Therefore, for each bit, the depth is 16K.

NOTE If you need more depth of data, the data have to be in the PC memory and chain the

pattern memory circularly, and then do chaining mode DMA which will generate the
desired pattern repetitively.

Appendix B: KDIO-DRVR Function Reference for

Bus-mastering DMA

Digital I/O data transfer between KPXI-DIO-32-80M and PC’s system memory is through bus
mastering DMA, which is controlled by PCI bridge chip PLX PCI-9080. The PCI bus master means
the device requires fast access to the bus or high data throughput in order to achieve good
performance.

However, users should note that when more than one bus masters request the bus ownership, all
masters will share the bandwidth of PCI bus and the performance of each master will unavoidably
drop. Therefore, in order to obtain the maximum data throughput of the KPXI-DIO-32-80M, it is
recommended to remove or disable the bus mastering function of other bus masters, such as
network, SCSI, modem adapters, and so on.

The maximum data throughput of the KPXI-DIO-32-80M is also limited by the data throughput of
the bridge chipset (North Bridge: NB) between PCI bus and system memory. The typical data
throughput of NB chipset is 120MB/second for input and 100MB/second for output. Please refer to
the

Figure 3-5. Check the chipset specifications on your main-board to determine

KPXI-DIO-32-80M‘s maximum data throughput. The 80MB/second data throughput of
KPXI-DIO-32-80M is guaranteed in the pervious system setup by using the internal
20MHz-sampling rate.

Figure 3-5

Maximum data throughput

From Figure 3-5, we can find that NB chipset is the bottleneck of the maximum data transfer rate
as only one bus master exists. When the transfer rate users required is smaller than the maximum
transfer rate, by using scatter/gather (refer to
maximum data size as they have on their system memory. However, if the data should be real-time
saved to the hard-disk rather than memory, the bottleneck would be the data transfer rate of the
hard-disk driver.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 3-7

Scatter/gather DMA), users can transfer the

Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

Scatter/gather DMA

The PCI Bridge also supports the function of scatter/gather bus mastering DMA, which helps the
users to transfer a large amount of data by linking the all memory blocks into a continuous linked
list.

In the multi-user or multi-tasking operating system, like Microsoft Windows®, it is difficult to
allocate a large continuous memory block to do the DMA transfer. Therefore, the PLX PCI-9080
provides the function of scatter/gather or chaining mode DMA to link the non-continuous memory
blocks into a linked list so that users can transfer a very large amount of data without limiting by
the fragment of small size memory. Users can configure the linked list for the input DMA channel
or the output DMA channel. The
descriptors. Each descriptor contains a PCI address, a local address, a transfer size, and the
pointer to the next descriptor. Users can allocate many small size memory blocks and chain their
associative DMA descriptors altogether by their application programs. The KPXI-DIO-32-80M’s
software driver provides the easy settings of the scatter/gather function, and some sample
programs are also provided within the Keithley Instruments CD. Users can refer to these sample
programs.

Figure 3-6

Scatter/gather DMA for digital output

Figure 3-6 shows the linked list that is constructed by three DMA

In non-chaining mode, the maximum DMA data transfer size is 2M double words (8M bytes).
However, by using chaining mode, scatter/gather, there is no limitation on DMA data transfer size.
Users can also link the descriptor nodes circularly to achieve a double-buffered mode DMA.

Clocking mode

The data input to or output from the FIFO is operated in a specific rate. The specific sampling rate
or the pacer rate can be programmable by software, by external clock, or by easy handshaking
protocol.

Four clocking modes are provided in the KPXI-DIO-32-80M to sample input data to the FIFO or
output date from FIFO to the external devices. They are:

1. Internal Clock: Three sources are available to activate both digital input and digital output.
They are 20MHz, 10MHz, and programmable timer 82C54. There are three counters in 82C54,
counter 0 is used to generate sampling clock for digital input, counter 1 is used timer pacer for
digital output, and counter 2 is used for interrupt function. The configuration is illustrated in

3-7.

3-8 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

Figure

KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

Figure 3-7

Timer configuration

2. External Clock: This mode is only applied for digital input. The digital inputs are handled by the
external clock strobe (DI-REQ). The DI-ACK signal reflects the almost full status of the input FIFO.
The DI-ACK is asserted when input FIFO is not almost full, which means the external device can
input data. If the input FIFO is almost full, the DI-ACK is de-asserted, then the external device
should pause data transfer and wait for the assertion of DI-ACK. If the external device follows the
rule, there would be no data lost due to FIFO overrun.

3. Handshaking: For the digital input, through DI-REQ input signal from external device and DI­ACK output signal to the external device, the digital input can have simple handshaking data
transfer.

For the digital output, through DO-REQ output signal to the external device and DO-ACK input
signal from external device, the digital output can have simple handshaking data transfer

4. Burst Handshaking: This mode is available for both digital output and digital input. If the digital
output DMA use internal clock and the burst handshaking mode is enable, the KPXI-DIO-32-80M
output data only when DO-ACK is asserted. That is, the external device can control the data input
from the KPXI-DIO-32-80M by asserting the DO-ACK pin when it is ready to receive data.

NOTE Because the internal clock is based on 10MHz clock, specific sampling or pacer rates

such as 9MHz cannot be generated by software. For digital input, users can use the
external clock source. However, for digital output, users should replace the default
40MHz oscillator because the current version of KPXI-DIO-32-80M does not support
external clock for digital output.

The frequency of external input clock cannot exceed 40MHz due to the local bus timing
requirement.

When users replace the default oscillator on board, the corresponding frequency would
be changed, for example, by replacement with 36Mhz oscillator, the internal clock selec­tion would be changed to 18MHz, 9MHz, and 9MHz base timer output.

Starting mode

Users can also control the starting mode of digital input and output by external signals (DITRIG
and DOTRIG) with the software programs. The trigger modes includes NoWait, WaitTRIG,
WaitFIFO, and WaitBoth.

1. NoWait: The data transfer is started immediately when a I/O transfer command is issued.

2. WaitTRIG: The data transfer will not start until external trigger signal (DI-TRIG for digital
input, DO-TRIG for digital output) is activated.

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Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

3. WaitFIFO: This starting mode is only available for digital output. The data transfer is started
until the output FIFO is almost empty. The threshold of FIFO almost empty is software
programmable.

4. WaitBoth: This starting mode is only available for digital output. The data transfer is started
until the output FIFO is almost empty and DO-TRIG signal is activated.

Active terminator

For KPXI-DIO-32-80M, it is important to terminate your cable properly to reduce or eliminate signal
reflections in the cable. The KPXI-DIO-32-80M supports active terminator on board; you can
enable or disable the terminator by software selection.

The active terminator is the same as the one used in SCSI 2. When the terminator is ON, it
presents a terminal 110-ohm impedance to the transmission line to match the line impedance.
When it is OFF, it just add a few pF capacitance to the line.

Digital input operation mode

Digital input DMA in internal clock mode

There are three sources to trigger digital input in the internal clock mode: 20MHz, 10MHz, and
programmable timer 82C54. There are three counters in 82C54, where the counter 0 is used for
sampling clock source for digital input. The operations sequence of digital input with internal clock
are listed as follows:

1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.

2. Enable or disable the active terminators.

3. Define the input sampling rate to be 20MHz, 10MHz, or the output of 82C54 counter 0.

4. Define the starting mode to be NoWait or WaitTRIG.

5. The digital input data are stored in the input FIFO after a DI command is issued and waiting
for DI-TRIG signal if in WaitTRIG mode.

6. The data in the input FIFO will be transferred into system memory directly and automatically
by bus mastering DMA.

The operation flow is shown below:

Figure 3-8

FIFO operation flow (A)

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KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

Figure 3-9

FIFO operation flow (B)

NOTE When the DMA function of digital input starts, the input data will be stored in the FIFO of

the KPXI-DIO-32-80M. The data then transfer to system memory if PCI bus is available. If
the speed of translation from external device to the FIFO on board is higher than that
from FIFO to system memory or the PCI bus is busy for a long time, the FIFO become full
and overrun situation occurs after the next data being written to the input FIFO. Users
should check the overrun status to see whether the overrun occurs or not. Some input
data will lost when the input FIFO is overrun.

The overrun occurs when the DMA idle time (from the end of DMA transfer N to the start
of DMA transfer N+1) is longer than the on-board FIFO buffer time. The FIFO size is 16K
sample, so it has 1.6 ms buffer time for 10MHz sampling rate if the FIFO is empty when
last DMA is complete. Users may try different DMA buffer size to see how the DMA buffer
size affects the overall performance. Generally, the larger DMA size the less overhead,
however, the process time required between DMAs also increases.

Digital input DMA in external clock mode

The digital input data transfer can be controlled by external strobe, which is from pin-83 DI-REQ of
CN1. The operation sequence is very similar to Internal Clock. The only difference is the clock
source comes from the outside peripheral devices. The operations sequence of digital input with
external clock are as follows:

1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.

2. Enable or disable the active terminators.

3. Define the input sampling rate as external clock. Connect the external clock to the input pin
DI-REQ.

4. Define the starting mode to be NoWait or WaitTRIG.

5. The digital input data are stored in the input FIFO after a DI command is issued and waiting
for DI-TRIG signal if in WaitTRIG mode..

6. The data saved in FIFO will transfer to system memory of your computer directly and
automatically by bus mastering DMA.

7. The DI-ACK signal indicates the status of the KPXI-DIO-32-80M’s input FIFO is in external
clock mode. When the digital input circuit of KPXI-DIO-32-80M is enabled and its FIFO is
not almost full, the DI-ACK signal will remain asserted. If the external device does not
transfer data according to the status of DI-ACK, the on-board FIFO could be full and data
could be lost.

The operation flow is show in Figure 3-10.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 3-11

Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

Figure 3-10

External clock mode operation flow

Figure 3-11 and Figure 3-12 are timing diagrams of the DI-REQ and the input data.

Figure 3-11

DI-REQ as input data strobe (when rising edge active)

Figure 3-12

DI-REQ as input data strobe (when falling edge active)

NOTE From the timing diagram of external clock mode, the maximum frequency can be up to

40MHz. However, users should note that when the sampling frequency of digital input is
higher than the PCI bus bandwidth (33Mhz) or the bandwidth of chipset (30Mhz typically)
from PCI bus to system memory, overruns may occur. Users should check the overrun
status when the DMA block size is larger than 16K samples. If overrun always happens,
users should reduce the DMA block size or slow down the sampling frequency. For
example, the DMA block size should be smaller than 64K when the external clock is
40Mhz in the DOS Operation.

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KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

Digital input DMA in handshaking mode

For digital input, through DI-REQ input signal and DI-ACK output signal, the digital input can have
simple handshaking data transfer. The operations sequence of digital input with handshaking are
listed:

1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.

2. Enable or disable the active terminators.

3. Define the input sampling rate as handshaking mode. Connect the handshaking signals of
the external device to input pin DI-REQ and output pin DI-ACK.

4. Define the starting mode to be NoWait or WaitTRIG.

5. After digital input data is ready on device side, the peripheral device should strobe data into
the KPXI-DIO-32-80M by asserting a DI-REQ signal.

6. The DI-REQ signal caused the KPXI-DIO-32-80M to latch digital input data and store it into
FIFO.

7. The KPXI-DIO-32-80M asserts a DI-ACK signal when it is ready for another input, the step
5 to step 7 will be repeated again.

8. The data saved in FIFO will transfer to system memory of your computer directly and
automatically by bus mastering DMA.

The operation flow is show as below:

Figure 3-13

Digital input DMA operation flow

The following figure shows the timing requirement of the handshaking mode digital input operation.

Figure 3-14

DI-REQ and DI-ACK handshaking

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Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

NOTE DI-REQ must be asserted until DI-ACK asserts, DI-ACK will be asserted until

DIREQ de-asserts.

Continuous digital input

If the digital input operation is still active after the completion of the previous DMA transfer and
does not clear the data in the input FIFO when the next DMA starts, the KPXI-DIO-32-80M can
achieve the continuous digital input function in a high-speed sampling rate. In this case, the input
FIFO buffers the input data and waits for the next DMA to move the queued data to the system
memory. To keep the overrun of the input FIFO from causing data to be lost on of the continuous
digital input, the latency time of the next DMA should be smaller than the time to overrun the input
FIFO. There are some rules of thumb should be mentioned here:

1. The lower the sampling frequency is, the longer the time to overrun the input FIFO is. That
means the fewer overrun situations will occur.

2. To reduce the latency time between two DMA transfers, please disable unnecessary PCI
bus mastering devices, and remove the unnecessary processes in your application
programs.

3. When high-speed sampling frequency is applied, the larger block size will improve the
efficiency of DMA transferring, and probability of overrun in the DMA process will be
reduced.

4. To truly maximize the speed of the high-speed continuous digital input, it is recommended to
execute your application programs in the non-multi task operation system to reduce the
latency time between two DMA transfers.

Figure 3-15

Data queued in FIFO

NOTE The latency time between two DMA transfers is different from the PCI bus latency time

mentioned in the previous section “Bus Mastering.” The former means the time difference
between two consecutive DMA processes started by the software. And the latter means
the time difference between two consecutive hardware DMA requests on the PCI bus
within a DMA process.

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KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

Digital output operation mode

Digital output DMA in internal clock mode

There are three sources to trigger digital output: 20MHz, 10MHz, and programmable timer 82C54.
There are three counters in 82C54, where the counter 1 is used timer pacer for digital output. The
operations sequence of digital output with internal clock are listed:

1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.

2. Enable or disable the active terminators.

3. Define the output timer pacer rate to be 20MHz, 10MHz, or the output 82C54 timer 1. The
timer pacer controls the output rate.

4. Define the starting mode to be NoWait, WaitTRIG, WaitFIFO, or WaitBoth

5. The output data saved in the system memory will be transferred to output FIFO directly and
automatically by bus mastering DMA.

6. The digital output data will be transferred to the external device after a DO command is
issued and DO-TRIG signal is activated.

The operation flow is shown in Figure 3-15:

Figure 3-16

Digital Output DMA in Internal Clock Mode

As the data output in the internal clock mode, the DO-REQ signal could be used as the output
strobe to indicate the output operation to the external device. The timing diagram of the DO-REQ
is shown as follows:

Figure 3-17

DO-REQ as output data strobe

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Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

Digital output DMA in handshaking mode

For digital output, through DO-REQ output signal and DO-ACK input signal, the digital output can
have simple handshaking data transfer.

The operations sequence of digital output in handshaking mode are listed:

1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.

2. Enable or disable the active terminators.

3. Define the output clock mode as handshaking mode. Connect the handshaking signals of
the external device to output pin DO-REQ and input pin DO-ACK.

4. Define the starting mode to be NoWait, WaitTRIG, WaitFIFO, or WaitBoth

5. Digital output data is moved from PC’s system memory to output FIFO by using bus
mastering DMA.

6. After output data is ready. A DO-REQ signal is generated and sent the output data to the
external device.

7. After a DO-ACK signal is received, the steps 6 and 7 will be repeated.

The operation flow is shown in Figure 3-18:

Figure 3-18

Digital output DMA in handshaking mode

The timing diagram of the DO-REQ and DO-ACK in the DO handshaking mode is shown in

Figure 3-19:

Figure 3-19

DO-REQ and DO-ACK Handshaking

NOTE DO-ACK must be de-asserted before DO-REQ asserts, DO-ACK can be asserted any

time after DO-REQ asserts, DOREQ will be reasserted after DO-ACK is asserted.

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KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

Digital output DMA in burst handshaking mode

The burst handshaking mode is a fast and reliable data transfer protocol. It has both advantage of
handshaking mode, which is reliable, and the advantage of internal clock mode, which is fast.
When using this mode, the sender has to check the availability of receiver indicated by the DO­ACK signal before it starts to send data. Once the DO-ACK is asserted, the receiver has to keep
the DO-ACK signal asserted until its input buffer becomes too small. When the DO-ACK is de­asserted, indicating the receiver’s buffer has not much space for new data, the sender is still
allowed to send up to 4 data sets to the receiver, and the receiver has to receive these data. The
following figure illustrates the operation of the burst handshaking mode:

Figure 3-20

Burst handshaking mode

The operations sequence of digital output in burst handshaking mode are listed:

1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.

2. Enable or disable the active terminators.

3. Define the output clock as burst handshaking mode and decide the timer pacer rate to be
20Mhz, 10Mhz, or the output of 82C54 timer 1.

4. Connect the handshaking signals of the external device to output pin DO-REQ and input pin
DO-ACK.

5. Define the starting mode to be NoWait, TrigWait, WaitFIFO, or WaitBoth

6. Digital output data is moved from PC’s system memory to output FIFO by using bus
mastering DMA.

7. After output data is ready. DO-REQ signals are generated and sent the output data to the
external device when the DO-ACK is asserted.

The operation flow is shown in Figure 3-21:

Figure 3-21

Burst handshaking mode operation flow

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Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

NOTE When the DMA function of digital output starts, the output data will transfer to the output

FIFO of KPXI-DIO-32-80M when PXI bus is available. If the speed of translation from the
FIFO on board to the external device is higher than that from system memory to the
output FIFO or the PCI bus is busy for a long time, the FIFO become empty and under­run situation occurs after the next data being read from the output FIFO. Users should
check the under-run status to see whether the under-run occurs or not. Some output data
will repeat when the output FIFO is under-run.

To avoid the under-run of output FIFO when digital output starts and PXI bus is still busy,
it is highly recommended to set the starting mode to be WaitFIFO. The higher the timer
pace rate is, the larger amount of almost empty threshold should be set to prevent the
under-run situation.

Pattern generator

The digital data is output to the peripheral device periodically based on the clock signals occurring
at a constant rate. The digital pattern are stored in the KPXI-DIO-32-80M’s on-board FIFO with the
length of pattern less than or equal to 16K samples.

The operations sequence of pattern generator are listed:

1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.

2. Enable or disable the active terminators.

3. Define the output timer pacer rate to be 20MHz, 10MHz, or the output 82C54 timer 1. The
timer pacer controls the output rate.

4. Set the output patterns into the output FIFO by direct FIFO access

5. Start the pattern generator function.

6. The pattern generator function will not stop until users stop the process

Figure 3-22

Pattern generator function operation

Auxiliary DIO

The KPXI-DIO-32-80M also includes four auxiliary digital inputs and four digital outputs, which can
be applied to achieve the simple I/O functions.

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KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

8254 Programmable Interval Timer

NOTE The material of this section is adopted from “Intel Microprocessor and Peripheral

Handbook Vol. II — Peripheral.”

Intel® (NEC®) 8254

The Intel (NEC) 8254 contains three independent, programmable, multi-mode 16 bit counter/
timers. The three independent 16 bit counters can be clocked at rates from DC to 5 MHz. Each
counter can be individually programmed with 6 different operating modes by appropriately
formatted control words. The most commonly uses for the 8254 in microprocessor based system
are:

• programmable baud rate generator

• event counter

• binary rate multiplier

• real-time clock

• digital one-shot

• motor control

For more information about the 8254, please refer to NEC Microprocessors and peripherals or the
Intel Microprocessor and Peripheral Handbook.

Control byte

The 8254 occupies eight I/O address locations in the I/O map as shown in Table 3-3:

Table 3-3

Control Byte

Base + 0 LSB OR MSB OF COUNTER 0
Base + 4 LSB OR MSB OF COUNTER 1
Base + 8 LSB OR MSB OF COUNTER 2
Base + C CONTROL BYTE for Chip 0

Before loading or reading any of these individual counters, the control byte (Base + C) must be
loaded first. The format of control byte is contained in the following tables (

Table 3-8):

Table 3-4

Control Byte: (Base + 7, Base + 11)

Bit 7 6 5 4 3 2 1 0

SC1 SC0 RL1 RL0 M2 M1 M0 BCD

Table 3-5

SC1 and SC1 - Select Counter (Bit 7 and Bit 6)

Table 3-4 through

SC1 SC0 COUNTER

0 0 0
0 1 1
1 0 2
1 1 ILLEGAL

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Section 3: Connection and Operation KPXI Ultra-High Speed DIO Card User’s Manual

Table 3-6

RL1 and RL0 - Select Read/Load operation (Bit 5 and Bit 4)

RL1 RL0 OPERATION

0 0 COUNTER LATCH
0 1 READ/LOAD LSB
1 0 READ/LOAD MSB
1 1 READ/LOAD LSB FIRST, THEN MSB

Table 3-7

M2, M1 and M0 - Select Operating Mode (Bit 3, Bit 2, and Bit 1)

M2 M1 M0 MODE

0 0 0 0
0 0 1 1
x 1 0 2
x 1 1 3
1 0 0 4
1 0 1 5

Table 3-8

BCD - Select Binary/BCD Counting (Bit 0)

0 BINARY COUNTER 16-BITS
1 BINARY CODED DECIMAL (BCD) COUNTER (4

DECADES)

NOTE 1. The count of the binary counter is from 0 up to 65,535.

2. The count of the BCD counter is from 0 up to 99,999.

Mode definition

In 8254, there are six different operating modes can be selected. They are:

Mode 0: Interrupt on terminal count

The output will be initially low after the mode set operation. After the count is loaded into the
selected count register, the output will remain low and the counter will count. When terminal count
is reached, the output will go high and remain high until the selected count register is reloaded with
the mode or a new count is loaded. The counter continues to decrement after terminal count has
been reached.

Rewriting a counter register during counting results in the following:

(1) Write 1st byte stops the current counting.

(2) Write 2nd byte starts the new count.

Mode 1: Programmable one-shot.

The output will go low on the count following the rising edge of the gate input. The output will go
high on the terminal count. If a new count value is loaded while the output is low it will not affect the

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KPXI Ultra-High Speed DIO Card User’s Manual Section 3: Connection and Operation

duration of the one-shot pulse until the succeeding trigger. The current count can be read at
anytime without affecting the one-shot pulse.

The one-shot is re-triggerable, hence the output will remain low for the full count after any rising
edge of the gate input.

Mode 2: Rate generator

Divided by N counter. The output will be low for one period of the input clock. The period from one
output pulse to the next equals the number of input counts in the count register. If the count
register is reloaded between output pulses the present period will not be affected, but the
subsequent period will reflect the new value.

The gate input when low, will force the output high. When the gate input goes high, the counter will
start form the initial count. Thus, the gate input can be used to synchronized by software.

When this mode is set, the output will remain high until after the count register is loaded. The
output then can also be synchronized by software.

Mode 3: Square wave rate generator

Similar to MODE 2 except that the output will remain high until one half the count has been
completed (or even numbers) and go low for the other half of the count. This is accomplished by
decrement the counter by two on the falling edge of each clock pulse. When the counter reaches
terminal count, the state of the output is changed and the counter is reloaded with the full count
and the whole process is repeated.

If the count is odd and the output is high, the first clock pulse (after the count is loaded)
decrements the count by 1. Subsequent clock pulses decrement the clock by 2 after time-out, the
output goes low and the full count is reloaded. The first clock pulse (following the reload)
decrements the counter by 3. Subsequent clock pulses decrement the count by 2 until time-out.
Then the whole process is repeated. In this way, if the count is odd, the output will be high for (N +

1)/2 counts and low for (N - 1)/2 counts.

In Modes 2 and 3, if a CLK source other then the system clock is used, GATE should be pulsed
immediately following Way Rate of a new count value.

Mode 4: Software triggered strobe

After the mode is set, the output will be high. When the count is loaded, the counter will begin
counting. On terminal count, the output will go low for one input clock period, then will go high
again.

If the count register is reloaded during counting, the new count will be loaded on the next CLK
pulse. The count will be inhibited while the GATE input is low.

Mode 5: Hardware triggered strobe

The counter will start counting after the rising edge of the trigger input and will go low for one clock
period when the terminal count is reached. The counter is re-triggerable. the output will not go low
until the full count after the rising edge of any trigger.

For the detailed description of the 8254, please refer to the Intel Micro-system Components
Handbook.

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3-22 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

In this section:

Top ic Pag e

Introduction to registers.................................................................. 4-2

Section 4

Registers

I/O port base address ....................................................................... 4-2

DI_CSR: DI Control and Status Register ......................................... 4-3

DO_CSR: DO Control and Status Register ...................................... 4-5

Auxiliary Digital I/O Register............................................................. 4-6

INT_CSR: Interrupt Control and Status Register ............................. 4-7

DI_FIFO: DI FIFO direct access port ............................................... 4-7

DO_FIFO: DO external data FIFO direct access port ...................... 4-8

FIFO_CR: FIFO almost empty/full register ...................................... 4-8

POL_CNTRL: Control Signal Polarity Control Register ................... 4-9

PLX® PCI-9080 DMA Control Registers ........................................ 4-10

Section 4: Registers KPXI Ultra-High Speed DIO Card User’s Manual

Introduction to registers

This section describes the format of the KPXI-DIO-32-80M registers.

This information is quite useful for the programmers who wish to handle the module by low-level
programming. In addition, users can realize how to use software driver to manipulate this module
after understanding the registers' structure of the KPXI-DIO-32-80M.

The KPXI-DIO-32-80M functions as a 32-bit PCI master device on the PXI bus. There are three
types of registers on the KPXI-DIO-32-80M: PCI Configuration Registers (PCR), Local
Configuration Registers (LCR) and KPXI-DIO-32-80M’s registers.

The PCR, which is compliant to the PCI-bus specifications, is initialized and controlled by the plug­and-play (PnP) PCI BIOS. Users can study the PCI BIOS specification to understand the
operation of the PCR.

The LCR is specified by the PCI bus controller PLX PCI-9080, which is provided by PLX
technology Inc. (www.plxtech.com) . It is not necessary for users to understand the details of the
LCR if you use the software library. The base address of the LCR is assigned by the PCI PnP
BIOS. The assigned address is located at offset 14h of PCR.

I/O port base address

The registers of the KPXI-DIO-32-80M are shown in Table 4-1. The base address of these
registers is also assigned by the PCI plug-and-play BIOS. The assigned base address is stored at
offset 18h of the PCR. Therefore, users can read the PCR to know the base address by using
BIOS function call. Note that the KPXI-DIO-32-80M registers are all 32 bits. Users should access
these registers by 32 bits I/O instructions.

Table 4-1

Registers format

Bit 7 6 5 4 3 2 1 0

Relay Output DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Output Readback RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

The KPXI-DIO-32-80M occupies 8 consecutive 32-bit I/O addresses in the I/O address space.

Table 4-2 shows the I/O Map of KPXI-DIO-32-80M.

4-2 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 4: Registers

Table 4-2

I/O port base address

Address Read Write

Base + 0 DI_CSR DI_CSR
Base + 4 DO_CSR DO_CSR
Base + 8 AUX_DIO AUX_DIO
Base + C INT_CSR INT_CSR
Base + 10 DI_FIFO DI_FIFO
Base + 14 DO_FIFO DO_FIFO
Base + 18 - FIFO_CR
Base + 1C POL_CTRL POL_CTRL
Base + 20 8254_COUNT0 8254_COUNT0
Base + 24 8254_COUNT1 8254_COUNT1
Base + 28 8254_COUNT2 8254_COUNT2
Base + 2C 8254_CONTROL 8254_CONTROL

Legend:
DI_CSR: Digital input control and status register
DO_SCR: Digital output control and status register
AUX_DIO: Auxiliary digital I/O port
INT_CSR: Interrupt control and status register
DI_FIFO: DI FIFO direct access port
DO_FIFO: DO FIFO direct access port
FIFO_CR: FIFO almost empty/full programming register
POL_CTRL: Polarity control register for the control signals

Note:

1. I/O port is 32-bit width

2. 8-bit or 16-bit I/O access is not allowed.

DI_CSR: DI Control and Status Register

Digital input control and status checking is done by this register.

Address: BASE + 00

Attribute: READ/WRITE

Data Format:

Table 4-3

DI control and status register data format

Bit # 3~0 DI_HND_SHK DI_CLK_SEL DI_32
Bit # 7~4 0 PA_TERM_OFF DI_WAIT_TRIG -- (1)
Bit # 11~8 DI_FIFO_FULL DI_OVER DI_FIFO_CLR DI_EN
Bit # 15~12 - - - DI-FIFO_EMPTY
Bit # 31~16 Don’t Care

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 4-3

Section 4: Registers KPXI Ultra-High Speed DIO Card User’s Manual

DI_32 (R/W)

0: Input port is not 32-bit wide (16-bit or 8-bit wide)

1: Input port is 32-bit wide, PORTB is configured as the extension of PORTA. PORTA is

input lines 0…15 and PORTB is input lines 16…31. All PORTB control signals are
disabled.

DI_CLK_SEL (R/W)

00: use timer0 output as input clock

01: use 20MHz clock as input clock

10: use 10MHz clock as input clock

11: use external clock (DI_REQ) as input clock

DI_HND_SHK (R/W)

0: No handshaking

1: REQ/ACK handshaking mode

DI_WAIT_TRIG (R/W)

0: start input sampling immediately

1: delay input sampling until DITRIG is active

PA_TERM_OFF (R/W)

0: PORTA terminator ON

1: PORTA terminator OFF

DI_EN (R/W)

0: Disable digital inputs

1: Enable digital inputs

DI_FIFO_CLR (R/W)

0: No effect

1: Clear digital input FIFO. If both PORTA and PORTB are configured as inputs, both FIFO

will be cleared. Always get 0 when read.

DI_OVER (R/W)

0: DI FIFO does not full during input sampling

1: DI FIFO full during input sampling, some input data was lost, write “1” to clear this bit

DI_FIFO_FULL (RO)

0: DI FIFO is not full

1: DI FIFO is full

4-4 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 4: Registers

DI_FIFO_EMPTY (RO)

0: DI FIFO is not empty

1: DI FIFO is empty

DO_CSR: DO Control and Status Register

Digital input control and status checking is done by this register.

Address: BASE + 04

Attribute: READ/WRITE

Table 4-4

DO Control and status register data format

Bit # 3~0 DO_WAIT_NAE DO_MODE DO_32
Bit # 7~4 PG_STOP_TRIG PB_TERM_OFF DO_WAIT_TRG PAT_ GEN
Bit # 11~8 DO_FIFO_FULL DO_UNDER DO_FIFO_CLR DO_EN
Bit # 15~12 - - BURST_HNDSH (2) DO_FIFO_EMPTY
Bit # 31~16 Don’t Care

DO_32 (R/W)

0: Output port is not 32-bit wide ( 16-bit or 8-bit wide)

1: Output port is 32-bit wide, PORTA is configured as the extension of PORTB. That

means PORTB is output lines (0…15), and PORTA is output lines (16…31). All PORTA
control signals are disabled.

DO_MODE (R/W)

00: use timer1 output as output clock

01: use 20MHz clock as output clock

10: use 10MHz clock as output clock

11: REQ/ACK handshaking mode

DO_WAIT_NAE (R/W)

0: do not wait output FIFO not almost empty flag

1: delay output data until FIFO is not almost empty

PAT_GEN(R/W)

0: pattern generation disable (FIFO data do not repeat during data output)

1: pattern generation enable (FIFO data repeat themselves during data output)

DO_WAIT_TRIG (R/W)

0: start output data immediately

1: delay output data until DOTRIG is activated

PB_TERM_OFF (R/W)

0: PORTB terminator ON

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 4-5

Section 4: Registers KPXI Ultra-High Speed DIO Card User’s Manual

1: PORTB terminator OFF

PG_STOP_TRIG (R/W)

0: no effect

1: Stop pattern generation when DOTRIG is de-asserted

DO_EN (R/W)

0: Disable digital outputs

1: Enabled digital outputs

DO_FIFO_CLR (R/W)

0: No effect

1: Clear digital output FIFO. If both PORTA and PORTB are configured as outputs, both

FIFO will be cleared. Always get 0 when read.

DI_UNDER (R/W)

0: DO FIFO does not empty during data output

1: DO FIFO is empty during data output, some output data may be output twice. Write 1 to

clear this bit

DO_FIFO_FULL (RO)

0: DO FIFO is not full

1: DO FIFO is full

DO_FIFO_EMPTY (RO)

0: DO FIFO is not empty

1: DO FIFO is empty

BURST_HNDSHK (R/W)

0: disable burst handshaking mode

1: enable burst handshake mode

Auxiliary Digital I/O Register

Auxiliary 4-bit digital inputs and 4-bit digital outputs

Address: BASE + 08

Attribute: READ/WRITE

Table 4-5

Auxiliary digital I/O register data format

Bit # 3~0 DO_AUX_3 DO_AUX_2 DO_AUX_1 DO_AUX_0
Bit # 7~4 DI_AUX_3 DI_AUX_2 DI_AUX_1 DI_AUX_0
Bit # 31~8 Don’t Care

This auxiliary digital I/O is controlled by program I/O only.

4-6 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 4: Registers

DO_AUX_3 ~ DO_AUX_0 (R/W)

4-bit auxiliary output port. Program I/O only.

DI_AUX_3 ~ DI_AUX_0 (R)

4-bit auxiliary input port. Program I/O only

INT_CSR: Interrupt Control and Status Register

The interrupt of KPXI-DIO-32-80M is controlled and status is checked through this register.

Address: BASE + 0x0C

Attribute: READ/WRITE

Table 4-6

Interrupt control and status register data format

Bit # 3~0 T2_INT AUXDIO_INT T2_EN AUXDIO_EN
Bit # 7~4 - - Reserved Reserved
Bit # 31~8 Don’t Care

AUXDIO_EN (R/W)

0: Disable AUXDI0 interrupt

1: Interrupt CPU on falling edge of AUXDI0

T2_EN (R/W)

0: Disable Timer 2 interrupt

1: Interrupt CPU on falling edge of Timer 2 output

AUXDI0_INT (R/W)

0: AUXDI does not generate interrupt

1: AUXDI interrupt occurred. Write “1” to clear

T2_INT (R/W)

0: Timer 2 does not generate interrupt

1: Timer 2 interrupt occurred. Write “1” to clear

DI_FIFO: DI FIFO direct access port

The digital input FIFO data can be accessed through this port directly.

Address: BASE + 0x10

Attribute: READ/WRITE

Table 4-7

DI FIFO direct access port data format

Bits 7 6 5 4 3 2 1 0

Bit # 7~0 DI_FIFO_8
Bit # 15~8 DI_FIFO_16
Bit # 31_16 DI_FIFO_32

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 4-7

Section 4: Registers KPXI Ultra-High Speed DIO Card User’s Manual

DI_FIFO_8

Bit 7 ~ Bit 0 of digital input FIFO

DI_FIFO_16

Bit 15 ~ Bit 8 of digital input FIFO if the digital input is configured as 16-bit wide or 32-bit wide

DI_FIFO_32

Bit 31 ~ Bit 16 of digital input FIFO if the digital input is configured as 32-bit wide

NOTE Although this port is R/W port, write operation should be avoided in normal operation. If

both PORT A and PORT B are configured as output ports, read/write to this port is
meaningless.

DO_FIFO: DO external data FIFO direct access port

The digital output FIFO data can be accessed through this port directly.

Address: BASE + 0x0C

Attribute: READ/WRITE

Table 4-8

DO external data FIFO direct access port data format

Bits 7 6 5 4 3 2 1 0

Bit # 7~0 DO_FIFO_8
Bit # 15~8 DO_FIFO_16
Bit # 31_16 DO_FIFO_32

DO_FIFO_8

Bit 7 ~ Bit 0 of digital output FIFO

DO_FIFO_16

Bit 15 ~ Bit 8 of digital output FIFO if the digital output is configured as 16-bit wide or 32-bit wide.

DO_FIFO_32

Bit 31 ~ Bit 16 of digital output FIFO of the digital output is configured as 32-bit wide

NOTE Although this port is R/W port, read operation should be avoided in normal operation. If

both PORTA and PORTB are configured as input ports, read/write to this port is
meaningless.

FIFO_CR: FIFO almost empty/full register

This register is used to control the FIFO programmable almost empty/full flag.

Address: BASE + 0x018

Attribute: WRITE Only

4-8 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Section 4: Registers

Table 4-9

FIFO almost empty/full register data format

Bits 7 6 5 4 3 2 1 0

Bit 15~0 PB_PAE_PAF
Bit 31_16 PA_PAE_PAF

PB_PAE_PAF (WO)

Programmable almost empty/full threshold of PORTB FIFO, 2

consecutive writes are required to program PORTB FIFO.

Programmable almost empty threshold first.

PA_PAE_PAF(WO)

Programmable almost empty/full threshold of PORTA FIFO, 2

consecutive writes are required to program PORTA FIFO.

Programmable almost empty threshold first.

POL_CNTRL: Control Signal Polarity Control Register

This register is used to control the control signals’ polarity. The control signals include DI_REQ,
DI_ACK, DI_TRG, DO_REQ, DO_ACK and DO_TRG.

Address: BASE + 0x1C

Attribute: READ/WRITE

Table 4-10

Control signal polarity control register data format

Bit # 3~0 DO_REG_NEG DI_TRG_NEG DI_ACK_NEG DI_REQ_NEG

Bit # 71~4 - - DO_TRG_NEG DO_ACK_NEG
Bit # 31~8 Don’t Care

DI_REQ_NEQ (R/W)

0: DI_REQ is rising edge active

1: DI_REQ is falling edge active

DI_ACK_NEQ (R/W)

0: DI_ACK is rising edge active

1: DI_ACK is falling edge active

DI_TRG_NEQ (R/W)

0: DI_TRG is rising edge active

1: DI_TRG is falling edge active

DO_REQ_NEQ (R/W)

0: DO_REQ is rising edge active

1: DO_REQ is falling edge active

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics 4-9

Section 4: Registers KPXI Ultra-High Speed DIO Card User’s Manual

DO_ACK_NEQ (R/W)

0: DO_ACK is rising edge active

1: DO_ACK is falling edge active

DO_TRG_NEQ (R/W)

0: DO_TRG is rising edge active

1: DO_TRG is falling edge active

PLX® PCI-9080 DMA Control Registers

Bus-mastering DMA as well as the control and status registers of PCI-bus interrupts are built into
the PLX PCI-9080 ASIC. Contact PLX
Control Registers.

®

Technology, Inc., for information on PLX® PCI-9080 DMA

4-10 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

In this appendix:

Top ic Page

Introduction to KDIO-DRVR ............................................................ A-2

About the KDIO-DRVR software.......................................................A-2

KDIO-DRVR hardware support.........................................................A-2

KDIO-DRVR language support......................................................... A-2

KDIO-DRVR overview ....................................................................... A-3

General configuration function group ...............................................A-3

Actual sampling rate function group .................................................A-4

Analog output function group............................................................ A-4

Digital input function group ...............................................................A-4

Digital output function group............................................................. A-6

Timer/counter function group............................................................ A-7

DIO function group ........................................................................... A-8

Appendix A

KDIO-DRVR User’s Guide

Creating a KDIO-DRVR application............................................... A-9

Contiguous memory allocation in driver for continuous operation .... A-9

Fundamentals of building Windows XP/2000 Application......A-9

Microsoft

Using Microsoft Visual Basic.NET .................................................. A-11

Microsoft Visual C/C++................................................................... A-11

®

Visual Basic (Version 6.0) ...............................................A-9

KDIO-DRVR application hints....................................................... A-11

Digital input programming hints ......................................................A-12

Digital output programming hints.................................................... A-17

DAQ event message programming hints........................................ A-21

Interrupt event message programming hints ..................................A-22

Continuous data transfer in KDIO-DRVR ..................................A-23

Continuous data transfer mechanism.............................................A-23

Double-buffered / multiple-buffered DI operation............................ A-23

KDIO-DRVR utilities for Win32 .....................................................A-25

KDIO-DRVR configuration utility (configdrv)................................... A-25

KDIO-DRVR data file converter utility (KIDAQCvt)......................... A-26

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Introduction to KDIO-DRVR

About the KDIO-DRVR software

KDIO-DRVR is a software development kit for Keithley Instruments PXI digital I/O modules. It
contains a high performance data acquisition driver for developing custom applications under
Windows XP or Windows 2000

The memory and data buffer management capabilities free developers from dealing with complex
low-level command issues. That is, KDIO-DRVR is constructed to provide a simple programming
interface in communication with the Keithley PXI digital I/O modules. The easy-to-use functions
provided by KDIO-DRVR allow a programmer to use the features of the module in a high level
way.

1

environments.

Using KDIO-DRVR also allows you to take advantage of the power and features of Microsoft
Win32s
extended memory. Also, using KDIO-DRVR under in the Microsoft Visual Basic
makes it easy to create custom user interfaces and graphics.

In addition to the software drivers, some sample programs are provided for your reference to
demonstrate use of the driver and decrease development time.

®

for your data acquisition applications, including running multiple applications and using

KDIO-DRVR hardware support

Keithley will periodically upgrade KDIO-DRVR for new Keithley PXI digital I/O modules. Please
refer to Release Notes for the modules that the current KDIO-DRVR actually supports. The
following modules are currently supported by the KDIO-DRVR driver:

• KPXI-DIO-16-16: 16-channel isolated digital I/O module

• KPXI-DIO-48: 48-bit digital I/O module

• KPXI-RDI-8-16: 8 relay output and 16 isolated input module

• KPXI-DIO-32-80M: 80 Mbytes/second Ultra-high speed 32 channels digital I/O module with
bus mastering DMA transfer supporting scatter gather technology

• KPXI-DIO-32-32: 32 isolated channels DI & 32 isolated channels DO module

• KPXI-DIO-64-0: 64 isolated channels DI module

• KPXI-DIO-0-64: 64 isolated channels DO module

KDIO-DRVR language support

®

environment

KDIO-DRVR is a DLL (Dynamic-Link Library) version for using under Windows XP/2000. It can
work with any Windows programming language that allows calls to a DLL, such as Microsoft
Visual C/Visual C++
above), etc.

1. Windows XP, Windows 2000, Microsoft Win32s, Visual C/Visual C++, and Visual Basic are trademarks of

Microsoft Corporation.

the

2. Borland is a trademark of the Borland Software Corporation.

A-2 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

®

(5.0 or above), Borland® C++ (5.0 or above)2, or Visual Basic® (4.0 or

®

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

KDIO-DRVR overview

NOTE Based on the configuration of an individual module, some of the function groups will not

apply to a particular module.

This section describes the classes of functions in KDIO-DRVR and briefly describes each function.

KDIO-DRVR functions are grouped to the following classes:

• General Configuration Function Group

• Actual Sampling Rate Function Group

• Analog Output Function Group

• Digital Input Function Group

– Digital Input Configuration functions
– One-Shot Digital Input functions
– Continuous Digital Input functions
– Asynchronous Digital Input Monitoring functions

• Digital Output Function Group

– Digital Output Configuration functions
– One-Shot Digital Output functions
– Continuous Digital Output functions
– Asynchronous Digital Output Monitoring functions

• Timer/Counter Function Group

• DIO Function Group

– Digital Input/Output Configuration function
– Dual-Interrupt System Setting function

General configuration function group

Use these functions to initialize and configure the data acquisition card.

KDIO_Register_Card

Initializes the hardware and software states of a KIDAQ PCI-bus data acquisition card.
Register_Card must be called before any other KDIO-DRVR library functions can be called for that
card.

KDIO_Release_Card

Tells KDIO-DRVR library that this registered card is not used currently and can be released. This
would make room for a new card to be registered.

KDIO_GetCardType

Gets the card type of the device with a specified card index.

KDIO_GetCardIndexFromID

Gets the card type and the sequence number of the device with a specified card id.

KDIO_GetBaseAddr

Gets the I/O base addresses of the device with a specified card index.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-3

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

KDIO_GetLCRAddr

Gets the LCR base address (defined by the PCI controller on board) of the device with a specified
card index.

Actual sampling rate function group

KDIO_GetActualRate

Returns the actual sampling rate the device will perform for the defined sampling rate value.

Analog output function group

One-shot analog output functions

KDIO_AO_WriteChannel

Writes a binary value to the specified analog output channel.

KDIO_AO_VWriteChannel

Accepts a voltage value, scales it to the proper binary value and writes a binary value to the
specified analog output channel.

KDIO_AO_VoltScale

Scales a voltage to a binary value.

Digital input function group

Digital input configuration functions

KDIO_DI_DIO32M80_Config

Informs KDIO-DRVR library of the trigger source and trigger properties selected for the digital input
operation of the KPXI-DIO-32-80M. You must call this function before calling the function to
perform continuous digital input operation of the KPXI-DIO-32-80M. This function is used only with
Model KPXI-DIO-32-80M.

KDIO_DI_InitialMemoryAllocated

Gets the actual size of digital input DMA memory that is available in the device driver.

One-Shot Digital Input Functions

KDIO_DI_ReadLine

Reads the digital logic state of the specified digital line in the specified port.

KDIO_DI_ReadPort

Reads digital data from the specified digital input port.

A-4 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

Continuous digital input functions

KDIO_DI_ContReadPort

Performs continuous digital input on the specified digital input port at a rate as close as possible to
the rate you specified.

KDIO_DI_ContReadPortToFile

Performs continuous digital input on the specified digital input port at a rate as close as possible to
the rate you specified and saves the acquired data in a disk file.

KDIO_DI_ContStatus

Checks the current status of the continuous digital input operation.

KDIO_DI_EventCallBack

Controls and notifies the user’s application when a specified DAQ event occurs. The notification is
performed through a user-specified callback function.

KDIO_DI_ContMultiBufferSetup

Set up the buffer for multi-buffered continuous digital input.

KDIO_DI_ContMultiBufferStart

Starts the multi-buffered continuous digital input on the specified digital input port at a rate as close
as possible to the rate you specified.

Asynchronous digital input monitoring functions

KDIO_DI_AsyncCheck

Checks the current status of the asynchronous digital input operation.

KDIO_DI_AsyncClear

Stops the asynchronous digital input operation.

KDIO_DI_AsyncDblBufferTransfer

Copies half of the data of circular buffer to user buffer. You can execute this function repeatedly to
return sequential half buffers of the data.

KDIO_DI_AsyncMultiBufferNextReady

Checks whether the next buffer of data in circular buffer is ready for transfer during an
asynchronous multi-buffered digital input operation.

KDIO_DI_AsyncDblBufferOverrun

Checks or clears overrun status of the double-buffered digital input operation.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-5

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Digital output function group

Digital output configuration functions

KDIO_DO_DIO32M80_Config

Informs KDIO-DRVR library of the trigger source and trigger properties selected for the digital
output operation of the KPXI-DIO-32-80M. You must call this function before calling the function to
perform continuous digital output operation of the KPXI-DIO-32-80M. This function is used only
with Model KPXI-DIO-32-80M.

KDIO_DO_InitialMemoryAllocated

Gets the actual size of digital output DMA memory that is available in the device driver.

One-Shot Digital Output Functions

KDIO_DO_WriteLine

Sets the specified digital output line in the specified digital output port to the specified state. This
function is only available for those cards that support digital output read-back functionality.

KDIO_DO_WritePort

Writes digital data to the specified digital output port.

KDIO_DO_ReadLine

Reads the specified digital output line in the specified digital output port.

KDIO_DO_ReadPort

Reads digital data from the specified digital output port.

Continuous digital output functions

KDIO_DO_ContWritePort

Performs continuous digital output on the specified digital output port at a rate as close as possible
to the rate you specified.

KDIO_DO_ContStatus

Checks the current status of the continuous digital output operation.

KDIO_DO_EventCallBack

Controls and notifies the user’s application when a specified DAQ event occurs. The notification is
performed through a user-specified callback function.

KDIO_DO_PGStart

Performs pattern generation operation.

KDIO_DO_PGStop

Stops pattern generation operation.

A-6 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

KDIO_DO_ContMultiBufferSetup

Set up the buffer for multi-buffered continuous digital output.

KDIO_DO_ContMultiBufferStart

Starts the multi-buffered continuous digital output on the specified digital output port at a rate as
close as possible to the rate you specified.

Asynchronous digital output monitoring functions

KDIO_DO_AsyncCheck

Checks the current status of the asynchronous digital output operation.

KDIO_DO_AsyncClear

Stops the asynchronous digital output operation.

KDIO_DO_AsyncMultiBufferNextReady

Checks whether the next buffer is ready for new data during an asynchronous multi-buffered digital
output operation.

Timer/counter function group

Timer/counter functions

KDIO_CTR_Setup

Configures the selected counter to operate in the specified mode.

KDIO_CTR_Read

Reads the current contents of the selected counter.

KDIO_CTR_Clear

Sets the output of the selected counter to the specified state.

KDIO_CTR_Update

Writes a new initial count to the selected counter.

KDIO_CTR_CT12_ClkSrc_Config

Sets the counter clock source.

KDIO_CTR_CT12_CK1_Config

Sets the source of CK1.

KDIO_CTR_CT12_Debounce_Config

Sets the debounce clock.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-7

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

DIO function group

Digital input/output configuration functions

KDIO_DIO_PortConfig

This function is only used by the Digital I/O cards whose I/O port can be set as input port or output
port. This function informs KDIO-DRVR library of the port direction selected for the digital input/
output operation. You must call this function before calling functions to perform digital input/output
operation.

Dual-interrupt system setting functions

KDIO_SetDualInterrupt

Controls two interrupt sources of Dual Interrupt system.

KDIO_INT_EventMessage

Controls and notifies the user’s application when an interrupt event occurs. The notification is
performed through a user-specified callback function or the Windows PostMessage API.

KDIO_INT1_EventMessage

Controls the interrupt sources of INT1 of Dual Interrupt system and notifies the user’s application
when an interrupt event occurs. The notification is performed through a user-specified callback
function or the Windows PostMessage API.

KDIO_INT2_EventMessage

Controls the interrupt sources of INT2 of Dual Interrupt system and notifies the user’s application
when an interrupt event occurs. The notification is performed through a user-specified callback
function or the Windows PostMessage API.

Local interrupt setting functions

KDIO_DIO32M80_SetInterrupt

Controls the interrupt sources (AUXDI and Timer2) of local Interrupt system of KPXI-DIO-32-80M.
This function is used only with Model KPXI-DIO-32-80M.

KDIO_AUXDI_EventMessage

Controls AUXDI Interrupt and notifies the user’s application when an interrupt event occurs. The
notification is performed through a user-specified callback function or the Windows PostMessage
API.

KDIO_T2_EventMessage

Controls Timer2 Interrupt and notifies the user’s application when an interrupt event occurs. The
notification is performed through a user-specified callback function or the Windows PostMessage
API.

A-8 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

Creating a KDIO-DRVR application

Contiguous memory allocation in driver for continuous operation

The continuous data transfer functions in KDIO-DRVR input or output blocks of data to or from a
Keithley Instruments PXI digital I/O device. To avoid the data transfer performance reduction
caused by memory fragmentation, KDIO-DRVR allocates physically contiguous buffers in device
driver when the system boots.

KDIO-DRVR provides a utility, configdrv to set/modify the sizes of contiguous memory allocated
in driver for continuous analog input, analog output, digital input, digital output. Device driver will
try to allocate these sizes of memory. The size of initially allocated memory is the maximum
memory size that continuous data transfer can be performed. Please refer to the section,

KDIO-DRVR configuration utility (configdrv), for the description of this utility.

KDIO-DRVR inputs or outputs blocks of data stored in the driver buffer to or from a Keithley PXI
device. For input operations, the specified count of data are transferred to the driver buffer and
KDIO-DRVR copies the data from the driver buffer (kernel level) to a user buffer (user level). For
output operations, KDIO-DRVR copies the data from a user buffer (driver level) to the driver buffer
(kernel level) and transfers outgoing data from the driver buffer to the Keithley PXI device.

However, if only polling I/O is performed, the initially allocated memory is not needed and you can
use the utility,

KDIO-DRVR configuration utility (configdrv) to set the buffer size to be 0.

Fundamentals of building Windows XP/2000 Application

The following paragraphs outline how to create Windows1 XP/2000 KDAQ-DRVR projects using
Microsoft Visual Basic® (Version 6.0), Microsoft Visual Basic.NET, and Microsoft Visual C/C++®.

Microsoft® Visual Basic (Version 6.0)

To create a Windows XP/2000® Keithley KDIO-DRVR application using the API and Microsoft
Visual Basic, follow these steps:

Step 1: Enter Visual Basic and open or create a project to use KDIO-DRVR

To create a new project, select New Project from the File menu.

To use an existing project:

1. Open the file by selecting Open Project from the File menu. The Open Project dialog box

appears (Figure A-1).

1. Windows XP, Windows 2000, Microsoft Visual Basic.NET, Microsoft Visual C/Visual C++, and Microsoft

Visual Basic

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-9

are trademarks of the Microsoft Corporation.

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Figure A-1

Open Project dialog box

2. Load the project by finding and double-clicking the project file name in the applicable
directory.

Step 2: Include function declarations and constants file (kdiodrvr.bas)

If it is not already included in the project, add the kdiodrvr.bas file as a module to your project. All
function declarations and constants are contained in this file. These function declarations and
constants are used to develop data acquisition applications.

Step 3: Design the application interface

Add elements, such as a command button, list box, or text box, etc., on the Visual Basic form used
to design the interface. These elements are standard controls from the Visual Basic Toolbox. To
place a needed control on the form:

1. Select the needed control from the Toolbox.

2. Draw the control on the form. Alternatively, to place the default-sized control on the form,
click the form. Use the Select Objects tool to reposition or resize controls.

Step 4: Set control properties

Set control properties from the properties list. To view the properties list, select the desired control
and do one of the following:

• Press F4

• Select the Properties command in the View menu

or

• Click the Properties button on the Toolbar.

Step 5: Write the event codes

The event codes define the action desired when an event occurs. To write the event codes:

1. Double-click the control or form needing event code (the code module will appear).

2. Add new code as needed. All functions that are declared in kdiodrvr.bas can be called to
perform data acquisition operations (refer to tables contained later in this manual).

A-10 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

Step 6: Run your application

To run the application, either:

• Press F5

•Select Start from the Run menu

or

• Click the Start icon on the Toolbar

Using Microsoft Visual Basic.NET

To create a data acquisition application using KDAQ-DRVR and Visual Basic.NET, use the
procedure for
KDIODRVR.VB (instead of the file named kdiodrvr.bas).

Microsoft® Visual Basic (Version 6.0) as an outline, but in step 2, use the file named

Microsoft Visual C/C++

To create a Windows XP/2000 KDAQ-DRVR library application using the KDAQ-DRVR function
library and Microsoft Visual C/C++, follow these steps:

Step 1: Enter Visual C/C++ and open or create a project that will use the
KDIO-DRVR

NOTE The project can be a new or existing one.

Step 2: Include function declarations and constants file (kdiodrvr.h)

Include kdiodrvr.h in the C/C++ source files that call KDIO-DRVR functions by adding the
following statement in the source file:

#include "kdiodrvr.h"

NOTE: KDIO-DRVR function declarations and constants are contained in kdiodrvr.h. Use the

functions and constants to develop data-acquisition applications.

Step 3: Build your application

1. Set suitable compile and link options.

2. Select Build from the Build menu (Visual C/C++ 4.0 and higher).

3. Remember to link the Keithley Command Compatible library: KDIO-DRVR.LIB

KDIO-DRVR application hints

This section provides the programming schemes showing the function flow of that KDIO-DRVR
performs analog I/O and digital I/O.

The figure below shows the basic building blocks of a KDIO-DRVR application. However, except
using KDIO_Register_Card at the beginning and KDIO_Release_Card at the end, depending on
the specific devices and applications you have, the KDIO-DRVR functions comprising each
building block vary.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-11

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Figure A-2

Basic KDIO-DRVR building blocks

The programming schemes for digital input/output are described individually in the following
sections.

Digital input programming hints

KDIO-DRVR provides two kinds of digital input operation ⎯ non-buffered single-point digital input
operation and buffered continuous digital input operation.

The non-buffered single-point DI uses software polling method to read data from the device.
The programming scheme for this kind of DI operation is described in

programming.

The buffered continuous DI uses DMA transfer method to transfer data from device to user’s
buffer. The maximum number of count in one transfer depends on the size of initially allocated
memory for digital input in the driver. We recommend the applications use the
KDIO_DI_InitialMemoryAllocated function to get the size of initially allocated memory before
performing continuous DI operation.

The buffered continuous analog input includes synchronous continuous DI, non-double-buffered
asynchronous continuous DI and double-buffered asynchronous continuous DI. They are
described in

asynchronous continuous digital input programming, and Multiple-buffered asynchronous
continuous digital input programming. About the special consideration and performance issues for

the buffered continuous digital input, refer to the section titled Continuous data transfer in KDIO-

DRVR for details.

Synchronous continuous digital input programming, Non-multiple-buffered

One-shot digital input

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KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

One-shot digital input programming

This section describes the function flow typical of non-buffered single-point digital input readings.
While performing one-shot DI operation, the devices whose I/O port can be set as input or out put
port need to include port configuration function at the beginning of your application.

NOTE The following example uses a KPXI-DIO-48. Other DIO modules are similar (exceptions

are noted).

Figure A-3

One-shot digital input programming

Example Code Fragment

card = KDIO_Register_Card(KPXI_DIO_48, card_number);
//port configured
KDIO_PortConfig(card ,Channel_P1A, INPUT_PORT);
KDIO_PortConfig(card, Channel_P1B, INPUT_PORT);
KDIO_PortConfig(card, Channel_P1CL, INPUT_PORT);
KDIO_PortConfig(card, Channel_P1CH, INPUT_PORT);
//DI operation
KDIO_DI_ReadPort(card, Channel_P1A, &inputA);
…
KDIO_Release_Card(card);

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-13

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Synchronous continuous digital input programming

This section describes the function flow typical of synchronous digital input operation. While
performing continuous DI operation, the DI configuration function has to be called at the beginning
of your application. In addition, for synchronous DI, the SyncMode argument in continuous DI
functions has to be set as SYNCH_OP.

NOTE The following example uses a KPXI-DIO-32-80M. Other DIO modules are similar with the

exception being that some modules do not require the _Config function call (specifically,
if the module’s ports are dedicated as inputs or outputs only).

Figure A-4

Synchronous continuous digital input programming

KDIO_DI_xxxx_Config

xxxx means the card type,

(

e.g.

KDIO_DI_DIO32M80_Config)

With SyncMode=SYNCH_OP

KDIO_DI_ContReadPort /
KDIO_DI_ContReadPortToFile

Example Code Fragment

card = KDIO_Register_Card(KPXI_DIO_32_80M, card_number);
…
KDIO_DI_DIO32M80_Config (card, 16, TRIG_CLK_10MHZ, DIO32M80_WAIT_NO,
DIO32M80_TERM_ON, 0, 1, 1);
KDIO_DI_ContReadPort(card, 0, pMem, data_size, (F64)sample_rate, SYNCH_OP)
…
KDIO_Release_Card(card);

Non-multiple-buffered asynchronous continuous digital input programming

This section describes the function flow typical of non-double-buffered asynchronous digital input
operation. While performing continuous DI operation, the DI configuration function has to be called
at the beginning of your application. In addition, for asynchronous DI operation, the SyncMode
argument in continuous DI functions has to be set as ASYNCH_OP.

A-14 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

NOTE The following example uses a KPXI-DIO-32-80M. Other DIO modules are similar with the

exception being that some modules do not require the _Config function call (specifically,
if the module’s ports are dedicated as inputs or outputs only).

Figure A-5

Non-multiple-buffered asynchronous continuous digital input

KDIO_DI_xxxx_Config

xxxx means the card type,

(

e.g.

KDIO_DI_DIO32M80_Config)

With SyncMode=ASYNCH_OP

KDIO_DI_ContReadPort /
KDIO_DI_ContReadPortToFile

KDIO_DI_AsyncCheck

No

Operation complete?

Yes

KDIO_DI_AsyncClear

Example Code Fragment

card = KDIO_Register_Card(KPXI_DIO_32_80M, card_number);
…
KDIO_DI_DIO32M80_Config(card, 16, TRIG_CLK_10MHZ, DIO32M80_WAIT_NO,
DIO32M80_TERM_ON, 0, 1, 1);
KDIO_DI_ContReadPort(card, 0, pMem, data_size, (F64)sample_rate, ASYNCH_OP)

do {
KDIO_DI_AsyncCheck(card, &bStopped, &count);
} while (!bStopped);
KDIO_DI_AsyncClear(card, &count);
…
KDIO_Release_Card(card);

Multiple-buffered asynchronous continuous digital input programming

This section describes the function flow typical of multi-buffered asynchronous digital input
operation. While performing continuous DI operation, the DI configuration function has to be called
at the beginning of your application. For asynchronous DI, the SyncMode argument in continuous
DI functions has to be set as ASYNCH_OP.

NOTE The following example uses a KPXI-DIO-32-80M. Other DIO modules are similar with the

exception being that some modules do not require the _Config function call (specifically,
if the module’s ports are dedicated as inputs or outputs only).

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-15

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Figure A-6

Multiple-buffered asynchronous continuous digital input

KDIO_DI_xxxx_Config

xxxx means the card type,

(

e.g. KDIO_DI_DIO32M80_Config

KDIO_DI_ContMultiBufferSetup

KDIO_DI_ContMultiBufferStart

KDIO_DI_AsyncMultiBufferNextReady

)

No

Next half buffer

ready?

Yes

Handling the ready data

No

Want to stop

the operation?

Yes

KDIO_DI_AsyncClear

Example Code Fragment

card = KDIO_Register_Card(KPXI_DIO_32_80M, card_number);
…
KDIO_DI_DIO32M80_Config(card, 16, TRIG_CLK_10MHZ, DIO32M80_WAIT_NO,
DIO32M80_TERM_ON, 0, 0, 0);

//setting the DMA buffers repeatedly

KDIO_DI_ContMultiBufferSetup (card, in_buf, data_size, &BufferId);
KDIO_DI_ContMultiBufferSetup (card, in_buf, data_size, &BufferId);
…
// start multi-buffered DI
KDIO_DI_ContMultiBufferStart (card, 0, 1);
do {

do {
KDIO_DI_AsyncMultiBufferNextReady(card, &HalfReady, &viewidx);
} while (!HalfReady);
//Handling the ready data
} while (!clear_op);
KDIO_DI_AsyncClear(card, &count);
…
KDIO_Release_Card(card);

A-16 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

Digital output programming hints

KDIO-DRVR provides three kinds of digital output operation ⎯ non-buffered single-point digital
output operation, buffered continuous digital output operation and pattern generation.

The non-buffered single-point DO uses software polling method to write data to the device. The
programming scheme for this kind of DO operation is described in

programming scheme.

The buffered continuous DO uses DMA transfer method to transfer data from user’s buffer to
device. The maximum number of count in one transfer depends on the size of initially allocated
memory for digital output in the driver. We recommend the applications use
KDIO_DO_InitialMemoryAllocated function to get the size of initially allocated memory before
start performing continuous DO operation.

The buffered continuous digital output includes synchronous continuous DO and asynchronous
continuous DO. They are described in

Synchronous continuous digital output programming and
Asynchronous continuous digital output programming individually. About the special consideration

and performance issues for the buffered continuous digital output, refer to the section titled

Continuous data transfer in KDIO-DRVR for details.

The Pattern Generation DO outputs digital data patterns repeatedly at a predetermined rate. The
programming scheme for this kind of DO operation is described in

programming.

One-shot digital output

Pattern generation digital output

One-shot digital output programming scheme

This section describes the function flow typical of non-buffered single-point digital output
operation. While performing one-shot DO operation, the cards whose I/O port can be set as input
or output port need to include port configuration function at the beginning of your application.

NOTE The following example uses a KPXI-DIO-48. Other DIO modules are similar with the

exception being that some modules do not require the _Config function call (specifically,
if the module’s ports are dedicated as inputs or outputs only).

Example Code Fragment

card = KDIO_Register_Card(KPXI_DIO_48, card_number);
//port configured
KDIO_PortConfig(card ,Channel_P1A, OUTPUT_PORT);
KDIO_PortConfig(card, Channel_P1B, OUTPUT_PORT);
KDIO_PortConfig(card, Channel_P1CL, OUTPUT_PORT);
KDIO_PortConfig(card, Channel_P1CH, OUTPUT_PORT);
//DO operation
KDIO_DO_WritePort(card, Channel_P1A, outA_value);
…
KDIO_Release_Card(card);

Synchronous continuous digital output programming

This section describes the function flow typical of synchronous digital output operation. While
performing continuous DO operation, the DO configuration function has to be called at the
beginning of your application. In addition, for synchronous DO operation, the SyncMode argument
in continuous DO functions for synchronous mode has to be set as SYNCH_OP.

NOTE The following example uses a KPXI-DIO-32-80M. Other DIO modules are similar with the

exception being that some modules do not require the _Config function call (specifically,
if the module’s ports are dedicated as inputs or outputs only).

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-17

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Figure A-7

Synchronous continuous digital output programming

KDIO_DO_xxxx_Config

xxxx means the card type,

(

e.g. DO_DIO32M80_Config

With SyncMode=SYNCH_OP

KDIO_DO_ContWritePort

)

Example Code Fragment

card = KDIO_Register_Card(KPXI_DIO_32_80M, card_number);
…
KDIO_DO_DIO32M80_Config (card, 16, TRIG_INT_PACER, DIO32M80_WAIT_NO,
DIO32M80_TERM_ON, 0, 0x40004000);
KDIO_DO_ContWritePort(card, 0, DoBuf, count, 1, (F64)sample_rate, SYNCH_OP);
…
KDIO_Release_Card(card);

Asynchronous continuous digital output programming

This section describes the function flow typical of asynchronous digital output operation. While
performing continuous DO operation, the DO configuration function has to be called at the
beginning of your application. In addition, for asynchronous DO operation, the SyncMode
argument in continuous DO functions for asynchronous mode has to be set as ASYNCH_OP.

NOTE The following example uses a KPXI-DIO-32-80M. Other DIO modules are similar with the

exception being that some modules do not require the _Config function call (specifically,
if the module’s ports are dedicated as inputs or outputs only).

Figure A-8

Asynchronous continuous digital output programming

KDIO_DO_xxxx_Config

xxxx means the card type,

(

e.g. KDIO_DO_DIO32M80_Config

KDIO_DO_ContWritePort

KDIO_DO_AsyncCheck

No

Operation complete?

With SyncMode=ASYNCH_OP

)

Yes

KDIO_DO_AsyncClear

A-18 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

Example Code Fragment

card = KDIO_Register_Card(KPXI_DIO_32_80M, card_number);
…
KDIO_DO_DIO32M80_Config (card, 16, TRIG_INT_PACER, DIO32M80_WAIT_NO,
DIO32M80_TERM_ON, 0, 0x40004000);
KDIO_DO_ContWritePort(card, 0, DoBuf, count, 1, (F64)sample_rate, ASYNCH_OP);

do {
KDIO_DO_AsyncCheck(card, &bStopped, &count);
} while (!bStopped);

KDIO_DO_AsyncClear(card, &count);
…
KDIO_Release_Card(card);

Pattern generation digital output programming

This section describes the function flow typical of pattern generation for digital output. While
performing pattern generation of DO, the DO configuration function has to be called at the
beginning of your application.

NOTE The following example uses a KPXI-DIO-32-80M. Other DIO modules are similar with the

exception being that some modules do not require the _Config function call (specifically,
if the module’s ports are dedicated as inputs or outputs only).

Figure A-9

Pattern generation digital output programming

Example Code Fragment

card=KDIO_Register_Card(KPXI_DIO_32_80M, card_number);
…
KDIO_DO_DIO32M80_Config (card, 16, TRIG_INT_PACER, DIO32M80_WAIT_NO,
DIO32M80_TERM_ON, 0, 0x40004000);
//start pattern generation
KDIO_DO_PGStart (card, out_buf, 10000, 5000000);
…
//stop pattern generation
KDIO_DO_PGStop (card);
KDIO_Release_Card(card);

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-19

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Multiple-buffered asynchronous continuous digital output programming

This section describes the function flow typical of multi-buffered asynchronous digital output
operation. While performing continuous DO operation, the DO configuration function has to be
called at the beginning of your application. For asynchronous DO, the SyncMode argument in
continuous DO functions has to be set as ASYNCH_OP.

NOTE The following example uses a KPXI-DIO-32-80M. Other DIO modules are similar with the

exception being that some modules do not require the _Config function call (specifically,
if the module’s ports are dedicated as inputs or outputs only).

Figure A-10

Multiple-buffered asynchronous continuous digital output

KDIO_DO_xxxx_Config

xxxx means the card type,

(

e.g. KDIO_DO_DIO32M80_Config

KDIO_DO_ContMultiBufferSetup

KDIO_DO_ContMultiBufferStart

)

KDIO_DO_AsyncMultiBufferNextReady

No

Next half buffer

ready?

Yes

Copy prepared data to the ready
buffer

No

Want to stop

the operation?

Yes

KDIO_DO_AsyncClear

Example Code Fragment

card = KDIO_Register_Card(KPXI_DIO_32_80M, card_number);
…
KDIO_DO_DIO32M80_Config (card, 16, /*TRIG_INT_PACER*/TRIG_CLK_10MHZ,
DIO32M80_WAIT_NO, DIO32M80_TERM_ON, 0, 0x00040004)

//setting the DMA buffers repeatedly

KDIO_DO_ContMultiBufferSetup (card, out_buf, data_size, &BufferId);
KDIO_DO_ContMultiBufferSetup (card, out_buf, data_size, &BufferId);
…
// start multi-buffered DO

A-20 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

KDIO_DO_ContMultiBufferStart (card, 0, 1);
do {

do {
KDIO_DI_AsyncMultiBufferNextReady(card, &HalfReady, &viewidx);
} while (!HalfReady);

// Copy prepared data to the ready buffer
} while (!clear_op);
KDIO_DO_AsyncClear(card, &count);
…
KDIO_Release_Card(card);

DAQ event message programming hints

DAQ Event Message functions are an efficient way to monitor your background data acquisition
processes, without dedicating your foreground process for status checking. There are two kinds of
events, which are DI/DO operation completeness notification event and buffer ready notification
event.

To receive notification from the KDIO-DRVR data acquisition process in case of special events,
you can call KDIO_DI_EventCallBack, or KDIO_DO_EventCallBack to specify an event in
which you are interested.

Event notification is done through user-defined callbacks. When a user-specified DAQ event
occurs, KDIO-DRVR calls the user-defined callback. After receiving the message, the user’s
application can carry out the appropriate task.

The event message mechanism is easy and safe in Windows systems; however, the time delay
between the event and notification is highly variable and depends largely on how loaded your
system is. In addition, if a callback function is called, succeeding events will not be handled until
your callback has returned. If the time interval between events is smaller than the time taken for
callback function processing, the succeeding events will not be handled. Therefore this
mechanism is not suitable for the frequent events occurrence condition.

NOTE The following example uses a KPXI-DIO-32-80M. Other DIO modules are similar with the

exception being that some modules do not require the _Config function call (specifically,
if the module’s ports are dedicated as inputs or outputs only).

Example Code Fragment

card = KDIO_Register_Card(KPXI_DIO_32_80M, card_number);
KDIO_DI_DIO32M80_Config(card, 16, TRIG_CLK_10MHZ, DIO32M80_WAIT_NO,
DIO32M80_TERM_ON, 0, 0, 0);

// Enable half buffer ready event notification

KDIO_DI_EventCallBack (card, 1, DBEvent, (U32) DI_DBCallBack );

//Enable DI completeness event notification
KDIO_DI_EventCallBack (card, 1, DIEnd, (U32) DI_CallBack );

KDIO_DI_ContMultiBufferStart (card, 0, 1);

....

KDIO_Release_Card(card);

//Half buffer ready call back function
void DI_DBCallBack()
{
//half buffer is ready
KDIO_DI_AsyncDblBufferTransfer(card, &HalfReady, &viewidx);
….

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-21

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

}

//DI completeness call back function
void DI_CallBack ()
{
//DI is completed ]
KDIO_DO_AsyncClear (card, &count);
….
}

Interrupt event message programming hints

KDIO-DRVR provides two methods to perform interrupt occurrence notification for Keithley PXI
DIO cards that have dual interrupt system.

The Event Message method handles event notification through user-defined callbacks and/or the
Windows Message queue (for VB5, through user-defined callbacks only). When a user-specified
interrupt event occurs, KDIO-DRVR calls the user-defined callback (if defined) and/or puts a
message into the Windows Message queue, if you specified a window handle. After receiving the
message, the user’s application can carry out the appropriate task.

The event message mechanism is easy and safe in Windows systems; however, the time delay
between the event and notification is highly variable and depends largely on how loaded your
system is. In addition, if a callback function is called, succeeding events will not be handled until
your callback has returned. If the time interval between interrupt events is smaller than the time
taken for callback function processing, the succeeding interrupt events will not be handled.
Therefore this mechanism is not suitable for the frequent interrupt occurrence condition.

The Event Status checking and waiting method handles interrupt event status checking
through Win32 wait functions, such as WaitForSingleObject or WaitForMultipleObjects. This
method is useful for the situation that the interrupt event occurs very often, and the applications
written in the language that doesn’t support function pointers (e.g. VB4).

1. Through user-defined callbacks and the Windows Message queue

Example Code Fragment

card = KDIO_Register_Card(KPXI-DIO-16-16, card_number);

//INT1 event notification is through window message
KDIO_INT1_EventMessage (card, INT1_EXT_SIGNAL, hWnd, WM_INT, NULL);

//INT2 event notification is through a callback function
KDIO_INT2_EventMessage (card, INT2_EXT_SIGNAL, hWnd, NULL, (void *) cbfn);
….
//window message handling function
long PASCAL MainWndProc(hWnd, message, wParam, lParam)
{
switch(message) {
….

case WM_INT: //interrupt event occurring message

….

break;
….
case WM_DESTROY:
//Disable interrupts

KDIO_INT1_EventMessage (card, INT1_DISABLE, hMainWnd, NULL, NULL);

KDIO_INT2_EventMessage (card, INT2_DISABLE, hMainWnd, NULL, NULL);

//Release card

if (card >= 0) KDIO_Release_Card(card);

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KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

PostQuitMessage(0);
break;
….
}
}
….
//call back function
LRESULT CALLBACK cbfn()
{
….
}

2. Through a Win32 wait function

Example Code Fragment

card = KDIO_Register_Card(KPXI-DIO-16-16, card_number);
KDIO_SetDualInterrupt(card, INT1_EXT_SIGNAL, INT2_EXT_SIGNAL, hEvent);
….
//wait for INT1 event
if (WaitForSingleObject(hEvent[0], INFINITE) == WAIT_OBJECT_0) {
ResetEvent(hEvent[0]);
……
}
…..
//wait for INT2 event
if (WaitForSingleObject(hEvent[1], INFINITE) == WAIT_OBJECT_0) {
ResetEvent(hEvent[1]);
……
}
…..
if (card >= 0) KDIO_Release_Card(card);

Continuous data transfer in KDIO-DRVR

The continuous data transfer functions in KDIO-DRVR input or output blocks of data to or from a
plug-in Keithley PXI digital I/O device. For input operations, KDIO-DRVR must transfer the
incoming data to a buffer in the computer memory. For output operations, KDIO-DRVR must
transfer outgoing data from a buffer in the computer memory to the Keithley PXI digital I/O device.
This section describes the mechanism and techniques that KDIO-DRVR uses for continuous data
transfer and the considerations for selecting the continuous data transfer mode (sync. or async.,
double buffered or not, triggered or non-triggered mode).

Continuous data transfer mechanism

KDIO-DRVR uses two mechanisms to perform the continuous data transfer. The first one, interrupt
transfer, transfers data through the interrupt mechanism. The second one is to use the DMA
controller chip to perform a hardware transfer of the data. Whether KDIO-DRVR uses interrupt or
DMA depends on the device. If the device support both of these two mechanisms, KDIO-DRVR
decides on the data transfer method that typically takes maximum advantage of available
resources.

Double-buffered / multiple-buffered DI operation

KDIO-DRVR uses double-buffering / multiple buffering techniques in its driver software for
continuous input of large amounts of data.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-23

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Double/multiple buffer mode principle

The data buffer for double (multiple)-buffered continuous input operation is a circular buffer
logically. It is logically divided into two equal halves. The double-buffered input begins when device
starts writing data into the first half of the circular buffer (
to the second half of the circular buffer, you can copy the data from the first half into the transfer
buffer (user buffer) (

Figure A-11b). You now can process the data in the transfer buffer according

to application needs. After the board has filled the second half of the circular buffer, the board
returns to the first half buffer and overwrites the old data. You now can copy the second half of the
circular buffer to the transfer buffer (

Figure A-11c). The data in the transfer buffer is again available

for process. The process can be repeated endlessly to provide a continuous stream of data to your
application (

Figure A-11d).

Figure A-11

Double/multiple buffer mode principle

Figure A-11a). After device begins writing

a

Incoming DMA
input data

c

> >

Circular Buffer

Transfer Buffer

Empty Buffer Untransferred Data Transferred Data

b

> > >

d

> > >> >

The KDIO-DRVR double buffer mode functions were designed according to the principle described
above. If you use KDIO_DI_AsyncDblBufferMode to enable double buffer mode, the following
continuous AI/DI function will perform double-buffered continuous DI. You can call
KDIO_DI_AsyncDblBufferHalfReady to check if data in the circular buffer is half full and
ready for copying to the transfer buffer. Then you can call
KDIO_DI_AsyncDblBufferTransfer to copy data from the ready half buffer to the transfer
buffer.

Single-buffered versus double (multiple)-buffered data transfer

Single-buffered data transfer is the most common method for continuous data transfer. In single­buffered input operations, a fixed number of samples are acquired at a specified rate and
transferred into user’s buffer. After the user’s buffer stores the data, the application can analyze,
display, or store the data to the hard disk for later processing. Single-buffered operations are
relatively simple to implement and can usually take advantage of the full hardware speed of the
device. However, the major disadvantage of single-buffered operation is that the maximum amount
of data that can be input at any one time is limited to the amount of initially allocated memory
allocated in driver and the amount of free memory available in the computer.

In double (multiple)-buffered operations, as mentioned above, the data buffer is configured as a
circular buffer. Therefore, unlike single-buffered operations, double-buffered operations reuse the
same buffer and are able to input or output an infinite number of data points without requiring an
infinite amount of memory. However, there exits the undesired result of data overwritten for

A-24 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

double-buffered data transfer. The device might overwrite data before KDIO-DRVR has copied it to
the transfer buffer. Another data overwritten problem occurs when an input device overwrites data
that KDIO-DRVR is simultaneously copying to the transfer buffer. Therefore, the data must be
processed by the application at least as fast as the rate at which the device is reading data. For
most of the applications, this requirement depends on the speed and efficiency of the computer
system and programming language.

Hence, double buffering might not be practical for high-speed input applications.

KDIO-DRVR utilities for Win32

This section introduces the tools that accompanied with the KDIO-DRVR package.

KDIO-DRVR configuration utility (configdrv)

configdrv is used for the users to set/modify the allocated buffer sizes of DI and DO. The default

location of this utility is <InstallDir>\Util directory.

[configdrv in Windows XP/2000]

This utility is used to set/modify the allocated buffer sizes of DI and DO. The allocated buffer sizes
of DI, DO represent the sizes of contiguous Initially Allocated memory for continuous analog input,
analog output, digital input, digital output respectively. Its unit is page KB, i.e. 1024 bytes. Device
driver will try to allocate these sizes of memory at system startup time. The size of initially
allocated memory is the maximum memory size that DMA or Interrupt transfer can be performed. It
will induce an unexpected result in that DMA or Interrupt transfer performed exceeds the initially
allocated size.

The “Driver Configuration” window is shown as below.

Figure A-12

Driver configuration window

KPXI-DIO-32-80M

AI:

AO:

DI:

DO:

0

0

32768

1024

perform

Using configdrv to change the buffer allocated settings of one of the KDIO-DRVR drivers,
select the driver from the Card Type combo box.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-25

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

Inside the allocated buffer size fields of AI, AO, DI and DO are the originally set values. Type the
value in the box corresponding to AI, AO, DI, or DO according to the requirement of your
applications, and then click “Apply” button.

KDIO-DRVR data file converter utility (KIDAQCvt)

The data files, generated by the KDAQ-DRVR functions performing continuous data acquisition
followed by storing the data to disk, is written in binary format. Since a binary file can’t be read by
the normal text editor and can’t be used to analyze the accessed data by Excel, KDAQ-DRVR
provides a convenient tool KIDAQCvt to convert the binary file to the file format read easily. The
default location of this utility is <InstallDir>\Util directory. The KIDAQCvt main window is as the
following figure:

Figure A-13

DAQ File Conversion Utility

The KIDAQCvt main window includes two frames. The upper frame, Input File frame is used for
the source data file and the lower frame is used for the destination file.

To load the source binary data file, type the binary data file name in File Path field or click
Browser button to select the source file from Input File frame, and then click Load button. As the
file is loaded, the information related to the data file, e.g. data type, data width, AD Range,
…etc., are shown in the corresponding fields in “Input File” frame, and the default converted data
file path and format are also listed as the figure below.

A-26 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix A: KDIO-DRVR User’s Guide

Figure A-14

Loading source binary data file

KIDAQ Driver Conversion Utility

F:\Keithley\KDIO_DRVR\SAMPLES\KPXI_DIO_32_80M\CAIR

KPXI-DIO-32-80M

F:\Keithley\KDIO_DRVR\SAMPLES\KPXI_DIO_32_80M\CAIR

The default destination file with a .cvt extension is located in the same directory as the source
one. To change the default setting, type the file path you wish or click the Browse button from

Output File frame to select the destination file location.

KIDAQCvt provides three types of data format conversions:

Text file with scaled data:

The data in hexadecimal format is scaled to engineering unit (voltage, amp, etc.) according to the
card type, data width and data range and then written to disk in text file format. This type is
available for the data accessed from continuous AI operation only.

Binary file with scaled data:

The data in hexadecimal is scaled to engineering unit (voltage, amp, etc.) according to the card
type, data width and data range and then written to disk in binary file format. This type is available
for the data accessed from continuous AI operation only.

Text file with binary codes:

The data in hexadecimal format or converted to a decimal value is written to disk in text file format.
If the original data includes channel information, the raw value will be handled to get the real data
value. This type is available for the data accessed form continuous AI and DI operations.

The data separator in converted text file is selectable among space, comma and Tab.

If you want to add title/head which includes the card type information at the beginning of file, check
the “Title/Head” box.

After setting the properties (File Path, Format, etc.) related to the converted file, you can push
Start Convert button from the Output File frame to perform the file conversion.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics A-27

Appendix A: KDIO-DRVR User’s Guide KPXI Ultra-High Speed DIO Card User’s Manual

This page left blank intentionally.

A-28 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

In this appendix:

Top ic Page

Function description......................................................................... B-2

Data types.........................................................................................B-2

Function reference............................................................................B-2

Status Codes..................................................................................... B-38

Data file format ................................................................................. B-40

Header............................................................................................ B-40

ChannelRange................................................................................ B-41

Data Block ...................................................................................... B-42

Function Support.............................................................................B-43

Appendix B

KDIO-DRVR Function Reference

Appendix B: KDIO-DRVR Function Reference KPXI Ultra-High Speed DIO Card User’s Manual

Function description

This section is provided as a function reference. It contains a detailed description of KDIO-DRVR
functions and includes information on KDIO-DRVR

reference (functions are arranged alphabetically in the reference). Syntax is provided for Microsoft

C/C++, and Borland C++, as well as Visual Basic.

Data types

Tab l e B - 1 contains data types defined in kdiodrvr.h. These data types are used by the

KDIO-DRVR library. It is recommended these data types are used in your application programs.

Tab l e B - 1 contains data type names, ranges, and the corresponding data types for C/C++ and

Visual Basic.

NOTE The data types in Tabl e B - 1 are defined in kdiodrvr.h, but are not defined in

kdiodrvr.bas (for .bas definition files, the table is provided only as a reference).

Tab l e B - 1

Suggested data types

Data types as well as a KDIO-DRVR Function

Type

Type
Name Description Range

U8 8-bit ASCII character 0 to 255 unsigned

I16 16-bit signed integer -32768 to 32767 short Integer
U16 16-bit unsigned integer 0 to 65535 unsigned

I32 32-bit signed integer -2147483648 to

U32 32-bit unsigned integer 0 to 4294967295 unsigned

F32 32-bit single-precision

floating

-point

F64 64-bit double-precision

floating

-point

Function reference

KDIO-DRVR is a software driver for Keithley Instruments PXI DIO cards. It is a high performance
data acquisition driver for developing custom applications.

Using KDIO-DRVR also lets you take advantage of the power and features of Microsoft Windows
for your data acquisition applications. These include running multiple applications and using
extended memory. Also, using KDIO-DRVR under environment makes it easy to create custom
user interfaces and graphics.

2147483647

-3.402823E38 to

3.402823E38

-1.797683134862315E308

to

1.797683134862315E309

C/C++
(for 32-bit
compiler) Visual Basic

Byte

char

Not supported by this type,

short

long Long

long

float Single

double Double

use the signed integer (I16)
instead

Not supported by this type,
use the signed long integer
(I32) instead

KDIO_CTR_Clear

Description Turns off the specified counter operation and sets the output of the selected

counter to the specified state. This function is supported by the following models:
KPXI-DIO-48

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KPXI Ultra-High Speed DIO Card User’s Manual Appendix B: KDIO-DRVR Function Reference

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_CTR_Clear (U16 CardNumber, U16 Ctr, U16 State)

Visual Basic

KDIO_CTR_Clear (ByVal CardNumber As Integer,
ByVal Ctr As Integer, ByVal State As Integer) As Integer

Parameters CardNumber: The card id number.

Ctr: The counter number.

Range: 0, 1, 2 for KPXI-DIO-48

state: The logic state to which the counter is to be reset.

Range: 0 or 1.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport, InvalidCounter

KDIO_CTR_Read

Description Reads the current contents of the selected counter without disturbing the counting

process. This function is supported by the following models:
KPXI-DIO-48

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_CTR_Read (U16 CardNumber, U16 Ctr, U32 *Value)

Visual Basic

KDIO_CTR_Read (ByVal CardNumber As Integer, ByVal Ctr As
Integer, Value As Long) As Integer

Parameters CardNumber: The card id number.

Ctr: The counter number.

Range: 0, 1, 2 for KPXI-DIO-48

Value: Returns the current count of the specified counter.

Range: 0 through 65536 for binary mode (default).
0 through 9999 for BCD counting mode.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport, InvalidCounter

KDIO_CTR_Setup

Description Configures the selected counter to operate in the specified mode. This function is

supported by the following models: KPXI-DIO-48

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_CTR_Setup (U16 CardNumber, U16 Ctr, U16 Mode,
U32 Count, U16 BinBcd)

Visual Basic

KDIO_CTR_Setup (ByVal CardNumber As Integer,
ByVal Ctr As Integer, ByVal Mode As Integer,
ByVal Count As Long, ByVal BinBcd As Integer) As Integer

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics B-3

Appendix B: KDIO-DRVR Function Reference KPXI Ultra-High Speed DIO Card User’s Manual

Parameters CardNumber: The card id number.

Ctr: The counter number.

Range: 0, 1, 2 for KPXI-DIO-48

Mode: The mode in which the counter is to operate. Valid values:

TOGGLE_OUTPUT
PROG_ONE_SHOT
RATE_GENERATOR
SQ_WAVE_RATE_GENERATOR
SOFT_TRIG
HARD_TRIG

TOGGLE_OUTPUT: Toggle output from low to high on terminal count. In this
mode, the output goes low after the mode set operation, and the counter begins to
count down while the gate input is high. When terminal count is reached, the
output goes high and remains high until the selected counter is set to a different
mode. The following diagram shows the TOGGLE_OUTPUT mode timing
diagram.

Figure B-1

TOGGLE_OUTPUT mode timing

Clock

WR

Gate

Output

(n = 6)

6 5 4

PROG_ONE_SHOT: Programmable one-shot. In this mode, the output goes low
on the following rising edge of the gate input and goes high on terminal count.
The following diagram shows the PROG_ONE_SHOT mode timing diagram.

Figure B-2

PROG_ONE_SHOT mode timing

Clock

Gate

Output

(n = 4)

RATE_GENERATOR: Rate generator. In this mode, the output goes low for one
period of the clock input. count indicates the period from one output pulse to the
next. The following diagram shows the RATE_GENERATOR mode timing
diagram.

A

A + B = n

4 3 2 1 0

3 2 1 0

B

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KPXI Ultra-High Speed DIO Card User’s Manual Appendix B: KDIO-DRVR Function Reference

Figure B-3

RATE_GENERATOR mode timing

Clock

Gate

Output

4 3 2 1 0 (4) 3 2 1 0 (4)

(n = 4)

SQ_WAVE_RATE_GENERATOR: Square wave rate generator. In this mode, the
output stays high for one half of the count clock pulses and stays low for the other
half. The following diagram shows the SQ_WAVE_RATE_GENERATOR mode
timing diagram.

Figure B-4

SQ_WAVE_RATE_GENERATOR mode timing

Clock

Gate

Output (n = 4)

Output (n = 5)

4 2 4 2 4 2 4 2 4 2 4 2

5 4 2 5 2 5 4 2 5 2 5 4

SOFT_TRIG: Software-triggered strobe. In this mode, the output is initially high,
and the counter begins to count down while the gate input is high. On terminal
count, the output goes low for one clock pulse, then goes high again. The
following diagram shows the SOFT_TRIG mode timing diagram.

Figure B-5

SOFT_TRIG mode timing

Clock

WR

Gate

Output

HARD_TRIG: Hardware-triggered strobe. This mode is similar to SOFT_TRIG
mode except that the gate input is used as a trigger to start counting. The
following diagram shows the HARD_TRIG mode timing diagram.

Figure B-6

HARD_TRIG mode timing

Clock

Gate

Output

n = 4

n = 4

4 3 2 1 0

4 3 2 1 0

Count: The period from one output pulse to the next.

BinBcd: Whether the counter operates as a 16-bit binary counter or as a 4-

decade binary-coded decimal (BCD) counter.
Valid value:
BIN: 16-bit binary counter.
BCD: 4-decade BCD counter.

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics B-5

Appendix B: KDIO-DRVR Function Reference KPXI Ultra-High Speed DIO Card User’s Manual

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport, InvalidCounter

KDIO_CTR_Update

Description A new initial count is written to the selected counter without affecting the counter’s

progrmmed mode. This function is supported by the following models:
KPXI-DIO-48

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_CTR_Update (U16 CardNumber, U16 Ctr, U32 Count)

Visual Basic

KDIO_CTR_Update (ByVal CardNumber As Integer,
ByVal Ctr As Integer, ByVal count As Long) As Integer

Parameters CardNumber: The card id number.

Ctr: The counter number.

Range: 0, 1, 2 for KPXI-DIO-48

count: the new count for the specified counter.

Range: 0 through 65536 for binary mode (default).
0 through 9999 for BCD counting mode.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport, InvalidCounter

KDIO_DI_DIO32M80_Config

Description Informs KDIO-DRVR library of the trigger source, port width, etc. selected for

KPXI-DIO-32-80M card with card ID CardNumber. You must call this function
before calling function to perform continuous digital input operation. This function
is supported by the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_DIO32M80_Config (U16 CardNumber, U16 PortWidth,
U16 TrigSource, U16 WaitStatus, U16 Terminator,
U16 I_Cntrl_Pol, BOOLEAN ClearFifo, BOOLEAN DisableDI)

Visual Basic

KDIO_DI_DIO32M80_Config (ByVal CardNumber As Integer,
ByVal PortWidth As Integer, ByVal TrigSource As Integer,
ByVal WaitStatus As Integer, ByVal Terminator As Integer,
ByVal I_Cntrl_Pol As Integer, ByVal ClearFifo As Byte,
ByVal DisableDI As Byte) As Integer

Parameters CardNumber: The card id number.

PortWidth: The width of digital input port (PORT A). The valid value is 0, 8, 16, or

32.

TrigSource: The trigger mode for continuous digital input.

Valid values:
TRIG_INT_PACER: on-board programmable pacer timer

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KPXI Ultra-High Speed DIO Card User’s Manual Appendix B: KDIO-DRVR Function Reference

TRIG_EXT_STROBE: external signal trigger
TRIG_HANDSHAKE: handshaking
TRIG_CLK_10MHz: 10MHz clock
TRIG_CLK_20MHz: 20MHz clock

WaitStatus: DI Wait Trigger Status. Valid values are:

DIO32M80_WAIT_NO: input sampling starts immediately
DIO32M80_WAIT_TRG: digital input sampling waits rising or falling
edge of I_TRG to start DI

Terminator: PortA Terminator On/Off. Valid values:

DIO32M80_TERM_ON: terminator on
DIO32M80_TERM_OFF: terminator off

I_Cntrl_Pol: The polarity configuration. This argument is an integer expression
formed from one or more of the manifest constants defined in kdiodrvr.h. There
are three groups of constants:

(1) DIREQ

DIO32M80_DIREQ_POS: DIREQ signal is rising edge active
DIO32M80_DIREQ_NEG: DIREQ signal is falling edge active

(2) DIACK

DIO32M80_DIACK_POS: DIACK signal is rising edge active
DIO32M80_DIACK_NEG: DIACK signal is falling edge active

(3) DITRIG

DIO32M80_DITRIG_POS: DITRIG signal is rising edge active
DIO32M80_DITRIG_NEG: DITRIG signal is falling edge active

ClearFifo: FALSE: retain the FIFO data

TRUE: clear FIFO data before perform digital input

DisableDI: FALSE: digital input operation still active after DMA transfer complete.

The input data still put into FIFO

TRUE: disable digital input operation immediately when
DMA transfer complete

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport

KDIO_DI_AsyncCheck

Description Check the current status of the asynchronous digital input operation. This function

is supported by the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_AsyncCheck (U16 CardNumber, BOOLEAN *Stopped,
U32 *AccessCnt)

Visual Basic

KDIO_DI_AsyncCheck (ByVal CardNumber As Integer,
Stopped As Byte, AccessCnt As Long) As Integer

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics B-7

Appendix B: KDIO-DRVR Function Reference KPXI Ultra-High Speed DIO Card User’s Manual

Parameters CardNumber: The card id of the card that performs the asynchronous operation.

Stopped: Whether the asynchronous analog input operation has completed. If

Stopped = TRUE, the digital input operation has stopped. Either the number of
digital input indicated in the call that initiated the asynchronous digital input
operation has completed or an error has occurred. If Stopped = FALSE, the
operation is not yet complete. (constants TRUE and FALSE are defined in
kdiodrvr.h)

AccessCnt: The number of digital input data that has been transferred at the time
the call to KDIO_DI_AsyncCheck(). AccessCnt is of no use (always returns 0)
in KDIO_DI_AsyncCheck() and KDIO_ DI_AsyncClear() with KPXI-DIO-32-80M
board because on-board chip (PLX9080) of KPXI-DIO-32-80M has no function or
register to get the current amount of DMA transfer.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport

KDIO_DI_AsyncClear

Description Stop the asynchronous digital input operation. This function is supported by the

following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_AsyncClear (U16 CardNumber, U32 *AccessCnt)

Visual Basic

KDIO_DI_AsyncClear (ByVal CardNumber As Integer,
AccessCnt As Long) As Integer

Parameters CardNumber: The card id of the card that performs the asynchronous operation.

AccessCnt: The number of digital input data that has been transferred at the time

the call to KDIO_DI_AsyncClear().

If double-buffered mode is enabled, AccessCnt returns the next position after the
position the last data is stored in the circular buffer. If the AccessCnt exceeds the
half size of circular buffer, call "KIO_DI_AsyncDblBufferTransfer " twice to get the
data.
AccessCnt is of no use (always returns 0) in KDIO_DI_AsyncCheck() and
KDIO_DI_AsyncClear() with KPXI-DIO-32-80M board because on-board chip
(PLX9080) of KPXI-DIO-32-80M has no function or register to get the current
amount of DMA transfer.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport

KDIO_DI_AsyncDblBufferOverrun

Description Checks or clears overrun status of the double-buffered/multi-buffered digital input

operation. This function is supported by the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_AsyncDblBufferOverrun (U16 CardNumber, U16 op,
U16 *overrunFlag)

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KPXI Ultra-High Speed DIO Card User’s Manual Appendix B: KDIO-DRVR Function Reference

Visual Basic

KDIO_DI_AsyncDblBufferOverrun (ByVal CardNumber As Integer,
ByVal op As Integer, overrunFlag As Integer) As Integer

Parameters CardNumber: The card id of the card that double-buffered mode to be set.

op: check/clear overrun status/flag.

0: check the overrun status.
1: clear the overrun flag.

overrunFlag: returned overrun status
0: no overrun occurs.
1: overrun occurs.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport

KDIO_DI_AsyncDblBufferTransfer

Description Depending on the continuous DI function selected, half of the data of the circular

buffer will be logged into the user buffer (if continuous DI function is:
KDIO_DI_ContReadPort) or a disk file (if continuous DI function is:
KDIO_DI_ContReadPortToFile). If the data will be saved in a file, the data is

written to disk in binary format, with the lower byte first (little endian).

You can execute this function repeatedly to return sequential half buffers of the
data.

For KPXI-DIO-32-80M, KDIO_DI_AsyncDblBufferTransfer doesn't perform
memory transfer but notifies kdiodrvr.dll the data stored in buffer have been
handled.

This function is supported by the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_AsyncDblBufferTransfer (U16 CardNumber,
void *Buffer)

Visual Basic

KDIO_DI_AsyncDblBufferTransfer (ByVal CardNumber As Integer,
Buffer As Any) As Integer

Parameters CardNumber: The card id of the card that performs the asynchronous double-

buffered operation.

Buffer: The user buffer to which the data is to be copied. If the data will be
saved into a disk file, this argument is of no use.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport, ErrorNotDoubleBufferMode

KDIO_DI_AsyncMultiBufferNextReady

Description Checks whether the next buffer of data in circular buffer is ready for transfer

during an asynchronous multi-buffered digital input operation. The returned
BufferId is the index of the most recently available (newest available) buffer. This
function is supported by the following models: KPXI-DIO-32-80M

KPXI-DIO80-900-01 Rev. A / January 2007 Return to Section Topics B-9

Appendix B: KDIO-DRVR Function Reference KPXI Ultra-High Speed DIO Card User’s Manual

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_AsyncMultiBufferNextReady (U16 CardNumber,
BOOLEAN *NextReady, U16 *BufferId)

Visual Basic

KDIO_DI_AsyncMultiBufferNextReady (
ByVal CardNumber As Integer, NextReady As Byte,
BufferId As Integer) As Integer

CardNumber: The card id of the card that performs the asynchronous multi­buffered operation.

NextReady: Whether the next buffer of data is available. If NextReady = TRUE,
you can handle the data in the buffer. (constants TRUE and FALSE are defined in
kdiodrvr.h)

BufferId: Returns the index of the ready buffer.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport

KDIO_DI_ContMultiBufferSetup

Description This function set up the buffer for multi-buffered digital input. The function has to

be called repeatedly to setup all of the data buffers (at most 8 buffers). This
function is supported by the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_ContMultiBufferSetup (U16 CardNumber,
void *Buffer, U32 ReadCount, U16 *BufferId)

Visual Basic

KDIO_DI_ContMultiBufferSetup (ByVal CardNumber As Integer,
Buffer As Any, ByVal ReadCount As Long,
BufferId As Integer) As Integer

Parameters CardNumber: The card id number.

Buffer: The starting address of the memory to contain the input data.

ReadCount: The size (in samples) of the buffer and its value must be even.

BufferId: Returns the index of the buffer currently set up.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport, ErrorTransferCountTooLarge, ErrorContIoNotAllowed

KDIO_DI_ContMultiBufferStart

Description This function starts multi-buffered continuous digital input on the specified digital

input port at a rate as close to the rate you specified. This function is supported by
the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_ContMultiBufferStart (U16 CardNumber, U16 Port,
F64 SampleRate)

B-10 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix B: KDIO-DRVR Function Reference

Visual Basic

KDIO_DI_ContMultiBufferStart (ByVal CardNumber As Integer,
ByVal Port As Integer, ByVal SampleRate As Double)
As Integer

Parameters CardNumber: The card id number.

Port: Digital input port number. For KPXI-DIO-32-80M, this argument must

be set to 0.

SampleRate: The sampling rate you want for digital input in hertz (samples per
second). Your maximum rate depends on the card type and your computer
system. This argument is only useful if the DI trigger mode was set as internal
programmable pacer (TRIG_INT_PACER) by calling

KDIO_DI_DIO32M80_Config().

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport, ErrorInvalidIoChannel, ErrorContIoNotAllowed

KDIO_DI_ContReadPort

Description This function performs continuous digital input on the specified digital input port at

a rate as close to the rate you specified. This function is supported by the
following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_ContReadPort (U16 CardNumber, U16 Port,
void *Buffer, U32 ReadCount, F64 SampleRate, U16 SyncMode)

Visual Basic

KDIO_DI_ContReadPort (ByVal CardNumber As Integer,
ByVal Port As Integer, Buffer As Any,
ByVal ReadCount As Long, ByVal SampleRate As Double,
ByVal SyncMode As Integer) As Integer

Parameters CardNumber: The card id number.

Port: Digital input port number. For KPXI-DIO-32-80M, this argument must be set

to 0.

Buffer: The starting address of the memory to contain the input data. This
memory must have been allocated for enough space to store input data. If double­buffered mode is enabled, this buffer is of no use, you can ignore this argument.

ReadCount: If double-buffered mode is disabled, ReadCount is the number of
input operations to be performed. For double-buffered acquisition, ReadCount is
the size (in samples) of the circular buffer and its value must be even.

SampleRate: The sampling rate you want for digital input in hertz (samples per
second). Your maximum rate depends on the card type and your computer
system. This argument is only useful if the DI trigger mode was set as internal
programmable pacer (TRIG_INT_PACER) by calling
KDIO_DI_DIO32M80_Config(). For the other settings, you have to set this
argument as CLKSRC_EXT_SampRate.

SyncMode: Whether this operation is performed synchronously or
asynchronously.

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Appendix B: KDIO-DRVR Function Reference KPXI Ultra-High Speed DIO Card User’s Manual

Valid values:
SYNCH_OP: synchronous digital input, that is, the function does not return until
the digital input operation complete.

ASYNCH_OP: asynchronous digital input operation

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport, ErrorInvalidIoChannel, ErrorTransferCountTooLarge ,
ErrorContIoNotAllowed

KDIO_DI_ContReadPortToFile

Description This function performs continuous digital input on the specified digital input port at

a rate as close to the rate you specified and saves the acquired data in a disk file.
The data is written to disk in binary format, with the lower byte first (little endian).

See “Data file format” on page B-40 for more information. This function is

supported by the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_ContReadPortToFile (U16 CardNumber, U16 Port,
U8 *FileName, U32 ReadCount, F64 SampleRate, U16 SyncMode)

Visual Basic

KDIO_DI_ContReadPortToFile (ByVal CardNumber As Integer,
ByVal Port As Integer, ByVal FileName As String,
ByVal ReadCount As Long, ByVal SampleRate As Double,
ByVal SyncMode As Integer) As Integer

Parameters CardNumber: The card id number.

Port: Digital input port number. For KPXI-DIO-32-80M, this argument must

be set to 0.

FileName: Name of data file which stores the acquired data

ReadCount: If double-buffered mode is disabled, ReadCount is the number of

input operations to be performed. For double-buffered acquisition, ReadCount is
the size (in samples) of the circular buffer and its value must be even.

SampleRate: The sampling rate you want for digital input in hertz (samples per
second). Your maximum rate depends on the card type and your computer
system. This argument is only useful if the DI trigger mode was set as internal
programmable pacer (TRIG_INT_PACER) by calling
KDIO_DI_DIO32M80_Config(). For the other settings, you have to set this
argument as CLKSRC_EXT_SampRate.

SyncMode: Whether this operation is performed synchronously or
asynchronously.

Valid values:

SYNCH_OP: synchronous digital input, that is, the function does not return until
the digital input operation complete.

ASYNCH_OP: asynchronous digital input operation

B-12 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007

KPXI Ultra-High Speed DIO Card User’s Manual Appendix B: KDIO-DRVR Function Reference

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport, ErrorInvalidIoChannel, ErrorInvalidSampleRate,
ErrorTransferCountTooLarge , ErrorContIoNotAllowed

KDIO_DI_ContStatus

Description While performing continuous DI conversions, this function is called to get the DI

status. Please refer to the manual for your device for the DI status the device
might meet. This function is supported by the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_ContStatus (U16 CardNumber, U16 *Status)

Visual Basic

KDIO_DI_ContStatus (ByVal CardNumber As Integer,
Status Integer) As Integer

Parameters CardNumber: The card id number.

Status: The continuous DI status returned. The description of the parameter

Status for various card types is the following:

KPXI-DIO-32-80M:

bit 0: '1' indicates DI FIFO is full during input sampling and some data were lost.

bit 1: '1' indicates DI FIFO is full

bit 2: '1' indicates DI FIFO is empty

bit 3 ~ 15: not used

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered

KDIO_DI_EventCallBack

Description Controls and notifies the user’s application when a specified DAQ event occurs.

The notification is performed through a user-specified callback function. The event
message will be removed automatically after calling KDIO_DI_Async_Clear.
The event message can also be manually removed by set the parameter “mode”
to 0. This function is supported by the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_EventCallBack (U16 CardNumber, I16 mode,
I16 EventType, U32 callbackAddr)

Visual Basic

KDIO_DI_EventCallBack (ByVal CardNumber As Integer,
ByVal mode As Integer, ByVal EventType As Integer,
ByVal callbackAddr As Long) As Integer

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Appendix B: KDIO-DRVR Function Reference KPXI Ultra-High Speed DIO Card User’s Manual

Parameters CardNumber: The card id of the card that want to be performed this operation.

mode: add or remove the event message.

Valid values:
0: remove
1: add

EventType: event criteria. Valid values:

DIEnd: Notification for the completeness of asynchronous digital input operation

DBEvent: Notification for the next half buffer of data in circular buffer is ready for

transfer

callbackAddr: the address of the user callback function. KDIO-DRVR calls this
function when the specified event occurs. If you wish to remove the event
message, set callbackAddr to 0.

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered,

ErrorFuncNotSupport

KDIO_DI_InitialMemoryAllocated

Description This function returns the mapped buffer address of the memory allocated in the

driver for continuous DI operation at system startup time. The size of the allocated
memory can be got by using the function KDIO_DI_InitialMemoryAllocated.
This function is supported by the following models: KPXI-DIO-32-80M

Syntax Microsoft C/C++ and Borland C++

I16 KDIO_DI_InitialMemoryAllocated (U16 CardNumber,
U32 *MemSize)

Visual Basic

KDIO_DI_InitialMemoryAllocated (ByVal CardNumber As Integer,
MemSize As Long) As Integer

Parameters CardNumber: The card id number.

MemSize: The available memory size for continuous DI in device driver of this

card. The unit is KB (1024 bytes).

Return Code NoError, ErrorInvalidCardNumber, ErrorCardNotRegistered

KDIO_DI_ReadLine

Description Read the digital logic state of the specified digital line in the specified port. This

function is supported by the following models: KPXI-DIO-16-16, KPXI-DIO-48,
KPXI-RDI-8-16, KPXI-DIO-32-80M, KPXI-DIO-32-32, KPXI-DIO-64-0

Syntax Microsoft C/C++ and Borland C++

I16 DI_ReadLine (U16 CardNumber, U16 Port, U16 Line,
U16 *State)

B-14 Return to Section Topics KPXI-DIO80-900-01 Rev. A / January 2007