Tektronix KPCI-PIO24 User manual

KPCI-PIO24 Parallel Digital I/O Board

User’s Manual

A GREATER MEASURE OF CONFIDENCE

WARRANTY

Hardware

Keithley Instruments, Inc. warrants that, for a period of three (3) years from the date of shipment, the Keithley Hardware product will be free from defects
in materials or workmanship. This warranty will be honored provided the defect has not been caused by use of the Keithley Hardware not in accordance
with the instructions for the product. This warranty shall be null and void upon: (1) any modification of Keithley Hardware that is made by other than Kei­thley and not approved in writing by Keithley or (2) operation of the Keithley Hardware outside of the environmental specifications therefore.

Upon receiving notification of a defect in the Keithley Hardware during the warranty period, Keithley will, at its option, either repair or replace such
Keithley Hardware. During the first ninety days of the warranty period, Keithley will, at its option, supply the necessary on site labor to return the
product to the condition prior to the notification of a defect. Failure to notify Keithley of a defect during the warranty shall relieve Keithley of its obli­gations and liabilities under this warranty.

Other Hardware

The portion of the product that is not manufactured by Keithley (Other Hardware) shall not be covered by this warranty, and Keithley shall have no
duty of obligation to enforce any manufacturers' warranties on behalf of the customer. On those other manufacturers’ products that Keithley pur­chases for resale, Keithley shall have no duty of obligation to enforce any manufacturers’ warranties on behalf of the customer.

Software

Keithley warrants that for a period of one (1) year from date of shipment, the Keithley produced portion of the software or firmware (Keithley Software)
will conform in all material respects with the published specifications provided such Keithley Software is used on the product for which it is intended
and otherwise in accordance with the instructions therefore. Keithley does not warrant that operation of the Keithley Software will be uninterrupted or
error-free and/or that the Keithley Software will be adequate for the customer's intended application and/or use. This warranty shall be null and void
upon any modification of the Keithley Software that is made by other than Keithley and not approved in writing by Keithley.

If Keithley receives notification of a Keithley Software nonconformity that is covered by this warranty during the warranty period, Keithley will review
the conditions described in such notice. Such notice must state the published specification(s) to which the Keithley Software fails to conform and the
manner in which the Keithley Software fails to conform to such published specification(s) with sufficient specificity to permit Keithley to correct such
nonconformity. If Keithley determines that the Keithley Software does not conform with the published specifications, Keithley will, at its option, provide
either the programming services necessary to correct such nonconformity or develop a program change to bypass such nonconformity in the Keithley
Software. Failure to notify Keithley of a nonconformity during the warranty shall relieve Keithley of its obligations and liabilities under this warranty.

Other Software

OEM software that is not produced by Keithley (Other Software) shall not be covered by this warranty, and Keithley shall have no duty or obligation
to enforce any OEM's warranties on behalf of the customer.

Other Items

Keithley warrants the following items for 90 days from the date of shipment: probes, cables, rechargeable batteries, diskettes, and documentation.

Items not Covered under Warranty

This warranty does not apply to fuses, non-rechargeable batteries, damage from battery leakage, or problems arising from normal wear or failure to
follow instructions.

Limitation of Warranty

This warranty does not apply to defects resulting from product modification made by Purchaser without Keithley's express written consent, or by
misuse of any product or part.

Disclaimer of Warranties

EXCEPT FOR THE EXPRESS WARRANTIES ABOVE KEITHLEY DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING WITHOUT LIMITATION, ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PUR­POSE. KEITHLEY DISCLAIMS ALL WARRANTIES WITH RESPECT TO THE OTHER HARDWARE AND OTHER SOFTWARE.

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9/02

KPCI-PIO24

Parallel Digital I/O Board

User’s Manual

©1998, Keithley Instruments, Inc.

All rights reserved.

Cleveland, Ohio, U.S.A.

Third Printing, September 2002

Document Number: 98230 Rev. C

Manual Print History

The print history shown below lists the printing dates of all Revisions and Addenda created for this manual. The Revision
Level letter increases alphabetically as the manual undergoes subsequent updates. Addenda, which are released between Revi­sions, contain important change information that the user should incorporate immediately into the manual. Addenda are num­bered sequentially. When a new Revision is created, all Addenda associated with the previous Revision of the manual are
incorporated into the new Revision of the manual. Each new Revision includes a revised copy of this print history page.

Revision A (Document Number 98230)...............................................................................................August 1998

Revision B (Document Number 98230) ......................................................................................... September 1998

Revision C (Document Number 98230) ......................................................................................... September 2002

All Keithley product names are trademarks or registered trademarks of Keithley Instruments, Inc.
Other brand and product names are trademarks or registered trademarks of their respective holders.

Safety Precautions

The following safety precautions should be observed before using
this product and any associated instrumentation. Although some in­struments and accessories would normally be used with non-haz­ardous voltages, there are situations where hazardous conditions
may be present.

This product is intended for use by qualified personnel who recog­nize shock hazards and are familiar with the safety precautions re­quired to avoid possible injury. Read and follow all installation,
operation, and maintenance information carefully before using the
product. Refer to the manual for complete product specifications.

If the product is used in a manner not specified, the protection pro­vided by the product may be impaired.

The types of product users are:

Responsible body is the individual or group responsible for the use

and maintenance of equipment, for ensuring that the equipment is
operated within its specifications and operating limits, and for en­suring that operators are adequately trained.

Operators use the product for its intended function. They must be

trained in electrical safety procedures and proper use of the instru­ment. They must be protected from electric shock and contact with
hazardous live circuits.

Maintenance personnel perform routine procedures on the product

to keep it operating properly, for example, setting the line voltage
or replacing consumable materials. Maintenance procedures are de­scribed in the manual. The procedures explicitly state if the operator
may perform them. Otherwise, they should be performed only by
service personnel.

Service personnel are trained to work on live circuits, and perform

safe installations and repairs of products. Only properly trained ser­vice personnel may perform installation and service procedures.

Keithley products are designed for use with electrical signals that
are rated Installation Category I and Installation Category II, as de­scribed in the International Electrotechnical Commission (IEC)
Standard IEC 60664. Most measurement, control, and data I/O sig­nals are Installation Category I and must not be directly connected
to mains voltage or to voltage sources with high transient over-volt­ages. Installation Category II connections require protection for
high transient over-voltages often associated with local AC mains
connections. Assume all measurement, control, and data I/O con­nections are for connection to Category I sources unless otherwise
marked or described in the Manual.

Exercise extreme caution when a shock hazard is present. Lethal
voltage may be present on cable connector jacks or test fixtures. The
American National Standards Institute (ANSI) states that a shock
hazard exists when voltage levels greater than 30V RMS, 42.4V
peak, or 60VDC are present. A good safety practice is to expect

that hazardous voltage is present in any unknown circuit before
measuring.

Operators of this product must be protected from electric shock at
all times. The responsible body must ensure that operators are pre­vented access and/or insulated from every connection point. In
some cases, connections must be exposed to potential human con­tact. Product operators in these circumstances must be trained to
protect themselves from the risk of electric shock. If the circuit is
capable of operating at or above 1000 volts, no conductive part of

the circuit may be exposed.

Do not connect switching cards directly to unlimited power circuits.
They are intended to be used with impedance limited sources.
NEVER connect switching cards directly to AC mains. When con­necting sources to switching cards, install protective devices to lim­it fault current and voltage to the card.

Before operating an instrument, make sure the line cord is connect­ed to a properly grounded power receptacle. Inspect the connecting
cables, test leads, and jumpers for possible wear, cracks, or breaks
before each use.

When installing equipment where access to the main power cord is
restricted, such as rack mounting, a separate main input power dis­connect device must be provided, in close proximity to the equip­ment and within easy reach of the operator.

For maximum safety, do not touch the product, test cables, or any
other instruments while power is applied to the circuit under test.
ALWAYS remove power from the entire test system and discharge
any capacitors before: connecting or disconnecting cables or jump­ers, installing or removing switching cards, or making internal
changes, such as installing or removing jumpers.

Do not touch any object that could provide a current path to the com­mon side of the circuit under test or power line (earth) ground. Always
make measurements with dry hands while standing on a dry, insulated
surface capable of withstanding the voltage being measured.

The instrument and accessories must be used in accordance with its
specifications and operating instructions or the safety of the equip­ment may be impaired.

Do not exceed the maximum signal levels of the instruments and ac­cessories, as defined in the specifications and operating informa­tion, and as shown on the instrument or test fixture panels, or
switching card.

When fuses are used in a product, replace with same type and rating
for continued protection against fire hazard.

Chassis connections must only be used as shield connections for
measuring circuits, NOT as safety earth ground connections.

If you are using a test fixture, keep the lid closed while power is ap­plied to the device under test. Safe operation requires the use of a
lid interlock.

5/02

If or is present, connect it to safety earth ground using the
wire recommended in the user documentation.

!

The symbol on an instrument indicates that the user should re­fer to the operating instructions located in the manual.

The symbol on an instrument shows that it can source or mea­sure 1000 volts or more, including the combined effect of normal
and common mode voltages. Use standard safety precautions to
avoid personal contact with these voltages.

The WARNING heading in a manual explains dangers that might
result in personal injury or death. Always read the associated infor­mation very carefully before performing the indicated procedure.

The CAUTION heading in a manual explains hazards that could
damage the instrument. Such damage may invalidate the warranty.

Instrumentation and accessories shall not be connected to humans.

Before performing any maintenance, disconnect the line cord and
all test cables.

To maintain protection from electric shock and fire, replacement
components in mains circuits, including the power transformer, test
leads, and input jacks, must be purchased from Keithley Instru­ments. Standard fuses, with applicable national safety approvals,
may be used if the rating and type are the same. Other components
that are not safety related may be purchased from other suppliers as
long as they are equivalent to the original component. (Note that se­lected parts should be purchased only through Keithley Instruments
to maintain accuracy and functionality of the product.) If you are
unsure about the applicability of a replacement component, call a
Keithley Instruments office for information.

To clean an instrument, use a damp cloth or mild, water based
cleaner. Clean the exterior of the instrument only. Do not apply
cleaner directly to the instrument or allow liquids to enter or spill
on the instrument. Products that consist of a circuit board with no
case or chassis (e.g., data acquisition board for installation into a
computer) should never require cleaning if handled according to in­structions. If the board becomes contaminated and operation is af­fected, the board should be returned to the factory for proper
cleaning/servicing.

Table of Contents

1 Overview

2 General Description

Specifications ...................................................................................................................................................... 2-2

System requirements ........................................................................................................................................... 2-2

Functional description .........................................................................................................................................2-2

Standard digital I/O emulation ..................................................................................................................... 2-2

Other I/O characteristics ..............................................................................................................................2-3

Bus control .......................................................................................................................................................... 2-3

Software .............................................................................................................................................................. 2-3

3 Installation

Installing the software ......................................................................................................................................... 3-2

Software options ..........................................................................................................................................3-2

DriverLINX driver software for Windows 9X/NT/2K/XP .....................................................................3-2

TestPoint .................................................................................................................................................3-3

LabVIEW ................................................................................................................................................ 3-3

Installing DriverLINX ................................................................................................................................. 3-3

Installing TestPoint with your hardware ...................................................................................................... 3-3

Unwrapping and inspecting the KPCI-PIO24 board ........................................................................................... 3-4

Installing and connecting the KCPI-PIO24 board ..............................................................................................3-4

Installing the board ....................................................................................................................................... 3-5

Identifying the I/O connector and pin assignments ..................................................................................... 3-5

Connecting I/O cables and interface accessories ......................................................................................... 3-7

Using locally fabricated cable assemblies ............................................................................................... 3-8

Using manufactured cables and accessories ...........................................................................................3-8

Connecting I/O cables to your external circuit ........................................................................................... 3-9

Monitoring contact closure at an input ....................................................................................................3-9

Eliminating contact bounce.................................................................................................................... 3-10

Boosting relay drive current .................................................................................................................. 3-10

Using +5 VDC from the computer power supply ................................................................................ 3-11

vii

4 I/O Address Mapping

Interrupts ..............................................................................................................................................................4-2

I/O address mapping............................................................................................................................................ 4-2

General memory assignments .......................................................................................................................4-2

Control and data register memory assignments............................................................................................ 4-3

Setting control and data registers ........................................................................................................................4-6

5 Troubleshooting

Identifying symptoms and possible causes ..........................................................................................................5-2

Systematic problem isolation ..............................................................................................................................5-3

General problem isolation procedure ...........................................................................................................5-3

I/O bit tests .................................................................................................................................................5-10

I/O loop-back test ..................................................................................................................................5-10

Output set test ........................................................................................................................................5-15

Technical support ..............................................................................................................................................5-20

Appendix A

Specifications .....................................................................................................................................................A-1

Appendix B

Glossary ..............................................................................................................................................................B-1

viii

List of Illustrations

3 Installation

Figure 3-1 Pin assignments for I/O connector on the KPCI-PIO24 board ................................................................... 3-6

Figure 3 - 2 B o ar d la yo u t ..................... .. .. .......... ... .. .......... .. ... ................... .. ... .......... .. .. ........... .. ......... ... .. .................... .. .. 3- 7

Figure 3-3 Using manufactured cables and accessories ...............................................................................................3-8

Figure 3-4 Contact-c los ure monitoring at a KPCI-PIO24 board input System connections................ ............... ....... 3-10

Figure 3-5 De-bounce circuit for an input of a KPCI-PIO24 board ........................................................................... 3-10

Figure 3-6 NPN transistor relay control for an output of a KPCI-PIO24 board......................................................... 3 - 11

5 Troubleshooting

Figure 5-1 Problem isolation flowchart ........................................................................................................................ 5-4

Figure 5-2 Mating connector wiring for loop-back test .............................................................................................. 5-11

Figure 5-3 IO Control Panel example ......................................................................................................................... 5-12

Figure 5-4 Setting port input and output ‘Configure’ switches..................................................................... .. .......... . 5 - 13

Figure 5-5 Port A ‘write/read’ switch setting ............................................................................................................. 5-13

Figure 5-6 Port A output settings, bit pattern 1 ..........................................................................................................5-14

Figure 5-7 Port A output settings, bit pattern 2 ..........................................................................................................5-14

Figure 5-8 Correct bit patterns when port A is set to bit pattern 2. ...........................................................................5-15

Figure 5-9 PIO Control Panel example ....................................................................................................................... 5-16

Figure 5-10 Setting port ‘Configure’ switches ............................................................................................................. 5-17

Figure 5-11 Port ‘write/read’ switch settings ............................................................................................................... 5-17

Figure 5-12 Port output settings, bit pattern 1 ..............................................................................................................5-18

Figure 5-13 Port output settings, bit pattern 2 ..............................................................................................................5-19

ix

List of Tables

2 General Description

Table 2-1 System requirements.................................................................................................................................. 2-2

3Installation

Table 3-1 Pin descriptions for KPCI-PIO24 I/O connector ............................. ............... ................ ............................ 3-6

Table 3-2 Description of manufactured cables and accessories .................................................................................. 3-9

4 I/O Address Mapping

Table 4-1 Data and control register addresses ............................................................................................................. 4-3

Table 4-2 Control register bit assignments for each port group .................................................................................. 4-4

Table 4-3 Data transfer mode selection............................................................................................................ ... .. ...... 4-5

5 Troubleshooting

Table 5-1 Basic troubleshooting information .............................................................................................................. 5-2

Table 5-2 Loop-back connection summary ............................................................................................................... 5-10

A Specifications

Table A-1 KPCI-PIO24 Specifications ....................................................................................................................... A-2

xi

1

Overview

1-2 Overview KPCI-PIO24 User’s Manual

This manual contains descriptive information and installation and use instructions for the KPCI­PIO24 digital interface board.

The manual is intended for data acquisition sys tem designers, engineers, technicians, scientists,
and other users responsible fo r setting up, cabling, and wir ing signals to KPCI-PIO24 bo ards. It is
assumed that users are familiar with data acquisition princip les and with their
particular application.

In addition to this Overview, the manual is organized as follows:

• Section 2 briefly describes features and characteristics of the KPCI-PIO24.

• Section 3 describes how to unpack, install, and connect the board and outlines software

options and installation.

• Section 4 provides the following information:

a. Describes KPCI-PIO24 interrupt characteristics.
b. Describes memory-mapping information for special situations; you normally can and

should skip that information. Use the DriverLINX driver provided with your board for
virtually all programming situatio ns.

• Section 5 describes how to troubleshoot your system and obtain technical support.

• Appendix A contains KPCI-PIO24 specifications.

• Appendix B is a glossary of some terms used in this manual.

2

General Description

2-2 General Description KPCI-PIO24 User’s Manual

Specifications

General specifications are listed in Appendix A. I/O connections are iden tif ied in Section 3, and
I/O addresses are defined in Section 4.

System r equirements

The system capabilities required to run the KPCI-PIO24 board, and to use the DriverLINX
software supplied with the board, are listed in Table 2-1.

Table 2-1

System requirements

CPU Type Pentium or higher processor on motherboard with PCI bus version 2.1
Operating system Windows® 95 or higher

Windows® NT version 4.0 or higher

Memory 16 MB or greater RAM when running Windows® 95 or 98

32 MB or greater RAM when running Windows® NT

Hard disk space 4 MB for minimum installation

50 MB for maximum installation

Other A CD ROM drive*

A free PCI bus expansion slot
Enough reserve computer power supply capacity to power the KPCI-

PIO24 board, which draws 25 W at 5 VDC

* Any CD ROM drive that came installed with the required computer should be satisfactory.
However, if you have pos t-installed an older CD ROM driv e or arrived at your present syst em by
updating the microprocessor or replacing the motherboard, be aware that some early CD ROM
drives do not support the long file name s often used in 32 bit Windows files.

Functional description

The KPCI-PIO24 is a 24-bit parallel digital interface board designed for the PCI bus. The KPCI­PIO24 works in a Windows 95/98/NT environme nt a nd takes advantage of the 32 bit width and
the Plug and Play feature of the PCI bus. The KPCI-PIO24 also has a n easily accessible interrupt
configuration. The KPCI-PIO24 meets a wide variety of parallel I/O requirements, including
communicating with peripherals, operating relays, and reading switch inputs. All I/O lines are
TTL compatible.

Standard digital I/O emulation

The 24 I/O lines emulate the I/O lines of an Intel 8255 Programmable Peripheral Interface (PPI)
chip configured for control register mode 0, as follows:

• For the emulated 8255 chip there is a PA port, a PB port and a PC port.

• The PA and PB ports are byte-wide (8-bits) and can be set independently under software

control as inputs or outputs.

• The PC port is byte-wide but can be divided into two separate 4-bit ports: PC lower and PC

upper, each of which can be set up as either inputs or outputs.

KPCI-PIO24 User’s Manual General Description 2-3

Most existing application software and data acquis ition packages work with the KPCI-PIO24
board. If you wish to reuse existing por t I/O program s previous ly designe d for ISA boar ds, refer
to information about the Hardware I/O Emulation driver included on your DriverLINX CD­ROM. The Hardware I/O Emulation driver may be us ed only with W indows 95/9 8. Refer also to

“Setting control and data registers” in Section 4 of this manual.

Other I/O characteristics

Additional I/O port characteristics are summarized below:

• The KPCI-PIO24 can output higher currents than the industry standard 8255 chip. Output

current capabilities of 15mA (source) and 64mA (sink) allow it to control many LEDs, Opto
22 modules, and relays directly.

• The PA, PB, and PC ports can always be read/write accessed, regardless of the direction they

were initially configured for, without the external signal level being affected. For example,
when a port is configured as an output, it is still possible to execute a read of that port. The
data returned by the read is the data latched in the I/O register.

• On power-up or whenever the computer’ s hardware reset line is asserted, all por ts are cleared

and set as inputs.

• The PA, PB and PC ports interface to user I/O connections via a standard 37-pin connector.

• Two externally accessible inputs allow for flexible interrupt configuration: INT_EN (exter-

nal interrupt enable, active low) and INT_REQ (external interrupt reque st, edge triggered).

• Computer power supply voltages are made available at the I/O connector for use in

external circuits.

2-4 General Description KPCI-PIO24 User’s Manual

Bus control

The KPCI series of data acquisition boards use the AMCC S5933 PCI bus controller, which is
universally recognized as an industry standard. Its PCI bus interface includes all the components
necessary for optimal PCI bus utilization. The AMCC S5933 provides two modes of operation:
bus mastering and target. The KPCI-PIO24 normally only implements the tar get mode. The target
mode, also referred to as passthrough operation, provides a simple register access port to the PCI
bus. High speed data transfer via bus mastering is unnecessary for the simple digital I/O of the
KPCI-PIO24 board.

The KPCI-PIO24 maps these AMCC S5933 registers as a memory mapped peripheral, though
not all are used for operation of the KPCI-PIO24:

• All sixteen 32 bit operation registers (64 b ytes total)

All eight 32 bit specific functional registers

•

All memory addresses of registers are automatically assigned by the PCI bus Plug and Play
feature upon system power-up.

Software

The user can select a fully integrated data acquisition software package (e.g., TestPoint or
LabVIEW) or write a custom program supported by DriverLINX. DriverLINX software is
included with the hardware.

DriverLINX supports programmers who wish to create custom applications using V isual C/C++,
Visual Basic, or Delph i. DriverLINX accomplishes foregrou nd and backgroun d tasks to perform
data acquisition. TestPoint is a fully featured, integrated application package with a graphical
drag-and-drop interface, which can be used to create data acquisition applications without
programming. LabVIEW is a fully featured graphical programming language used to create
virtual instrumentation.

Refer to Section 3, “Installation,” for more information about those programs.

3

Installation

•

3-2 Installation KPCI-PIO24 User’s Manual

This section describes:

•

Software options and how to install them.

Unwrapping the KPCI-PIO24 board to avoid static damage; inspection of the board

•

before installation.

•

Locating connectors, connecting the board to I/O cables and interface accessories, installing
the board, and connecting to external circuits.

Installing the software

NOTE

Software options

The KPCI-PIO24 has two software options. The user can select a fully integrated data acquisition
software package (e.g., TestPoint or LabVIEW). The user can also run a custom program in
Visual C/C++, Visual Basic, or Delphi using DriverLINX (included with the hardware). A
summary of the pros and cons of using integrated packages or writing custom programs is
provided in the Keithley Full Line Catalog. The KPCI-PIO24 has fully functional driver support
for use under Windows 9X/NT/2K/XP.

DriverLINX driver software for Windows 9X/NT/2K/XP

DriverLINX software, supplied by Keithley with the KPCI-PIO24 board, provides convenient
interfaces to configure and set I/O bits without register-level programming.

Most importantly, however, DriverLINX supports those programmers who wish to create custom
applications using Visual C/C++, Visual Basic, or Delphi. DriverLINX accomplishes foreground
and background tasks to perform data acquisition. The software includes memory and data buffer
management, event triggering, extensive error checking, and context sensitive online help.

More specifically, DriverLINX provides application developers a standardized interface to over
100 services for creating foreground and background tasks for the following:

Install the DriverLINX software before installing the KPCI-PIO24
card. Otherwise, the device drivers will be more difficult to install.

•

Analog input and output

•

Digital input and output

•

Time and frequency measurement

•

Event counting

•

Pulse output

•

Period measurement

In addition to basic I/O support, DriverLINX also provides:

uilt-in capabilities to handle memory and data buffer management

B

•

A selection of starting and stopping trigger events, including pre-triggering, mid­point triggering and post-triggering protocols

Extensive error checking

•

•

Context-sensitive on-line help system

KPCI-PIO24 User’s Manual Installation 3-3

DriverLINX is essentially hardware independent, because its portable APIs work across various
operating systems. This capability eliminates unnecessary programming when changing
operating system platforms.

TestPoint

TestPoint is a fully featured, integrated application package that incorporates many commonly
used math, analysis, report generation, and graphics functions. TestPoint’s graphical drag-and­drop interface can be used to create data acquisition applications, with minimal programming, for
IEEE-488 instruments, data acquisition boards, and RS232-485 instruments and devices.

TestPoint includes features for controlling external devices, responding to events, processing
data, creating report files, and exchanging information with other Windows programs. It provides
libraries for controlling most popular GPIB instruments. ActiveX controls plug directly into
TestPoint, allowing additional features from third party suppliers.

LabVIEW

LabVIEW is a fully featured graphical programming language used to create virtual
instrumentation. It consists of an interactive user interface, complete with knobs, slides, switches,
graphs, strip charts, and other instrument panel controls. Its data driven environment uses
function blocks that are virtually wired together and pass data to each other. The function blocks,
which are selected from palette menus, range from arithmetic functions to advanced acquisition,
control, and analysis routines. Also included are debugging tools, help windows, execution
highlighting, single stepping, probes, and breakpoints to trace and monitor the data flow
execution. LabVIEW can be used to create professional applications with minimal programming.

Check www.keithley.com for current LabVIEW drivers.

Installing DriverLINX

Refer to the manual that accompanies your DriverLINX software for installation instructions.

NOTE

Always install DriverLINX before installing the LabVIEW VIs. Both
TestPoint and the LabVIEW VIs use DriverLINX to access the
board’s hardware resources.

Using TestPoint with your hardware

TestPoint’s Digital I/O object (DIO) cannot be used with the KPCI-PIO96 (KPCI-PIO24) board.
Instead, TestPoint provides a user defined object (UDO) for access to digital I/O channels on plug­in boards supported by DriverLINX.

This UDO (DL_DIO) is installed when the TestPoint application is installed and can be found in
the Dldio.tst example program. This example program is located in the same directory as the
TestPoint application (c:\testpt).

Since this UDO makes calls into the DriverLINX driver, DriverLINX must be installed and
functional.

Once the Dldio.tst example has been opened, either use the ‘Save As’ feature to create your own
application or copy and paste the UDO from the example into your own application.

3-4 Installation KPCI-PIO24 User’s Manual

Unwrapping and inspecting the KPCI-PIO24 board

CAUTION Discharge static voltage differences between the wrapped board

and the handling environment before removing the board from
its protective wrapper. Failure to discharge static electricity
before handling may damage semiconductor circuits on
the board.

Handle the board using the mounting bracket. Do not touch
the circuit traces or connector contacts when handling the board.

After you remove the wrapped board from its outer shipping carton, proceed as follows:

1. Your board is packaged at the factory in an anti-static wrapper. Do not remove the anti-static
wrapper until you have discharged any static electricity voltage differences between the
wrapped board and the environment. Use one of the following methods:

•

Preferably, wear a grounded wrist strap. A grounded wrist strap discharges
static electricity from wrapped board as soon as you hold it. Keep the wrist strap on
until you have finished installing the board.

If you do not have a grounded wrist strap, discharge static electricity by holding the

•

wrapped board in one hand while placing your other hand firmly on a grounded
metal portion of the computer chassis. Your computer must be turned off and be
plugged into a grounded receptacle or otherwise grounded. Touch the computer chassis
again periodically while installing the board.

2. Remove the KCPI-PIO24 board from its anti-static wrapping material. (You may wish to
store the wrapping material for future use.)

3. Inspect the board for damage. If damage is apparent, arrange to return the board to
the factory. Refer to “Technical support.”

4. Check the remaining contents of your package against the packing list, and report
any missing items immediately.

5. If the inspection is satisfactory, proceed to “Installing and connecting the KPCI­PIO24 board.”

NOTE

Install the DriverLINX software before installing the KPCI-PIO96
board.Otherwise, the device drivers will be more difficult to install.

KPCI-PIO24 User’s Manual Installation 3-5

Installing and connecting the KCPI-PIO24 board

The following sections describe how to install and connect the KCPI-PIO24 board. The sections
are ordered in the recommended installation sequence.

Installing the board

CAUTION Ensure that the computer is turned off before installing or

removing a board. Installing or removing a board while power is
ON can damage your computer, the board, or both.

Handle the board at the mounting bracket, using a grounded
wrist strap. Do not touch the circuit traces or connector contacts.
If you do not have a grounded wrist strap, periodically discharge
static electricity by placing one hand firmly on a grounded metal
portion of the computer chassis.

Use the following steps to install a KCPI-PIO24 board in a PCI expansion slot on your computer:

1. Turn power OFF to the computer, and to all external circuits if any are attached to the board.

2. Remove the computer chassis cover.

3. Select an unoccupied PCI expansion slot in the rear panel, and remove the corresponding
dummy mounting plate.

4. Insert and secure the board in the selected PCI expansion slot.

Identifying the I/O connector and pin assignments

Figure 3-1 and Table 3-1 show and describe the pin assignments for the I/O connector, a standard
37-pin D type.

Figure 3-2 shows the location of the I/O connector on the board.

3-6 Installation KPCI-PIO24 User’s Manual

Figure 3-1

Pin assignments for I/O connector on the KPCI-PIO24 board

DIG COM

IBM PC

POWER

SUPPLIES

INTERRUPT ENABLE

INTERRUPT INPUT

DIG COM

DIG COM

DIG COM

DIG COM

PB PORT

+12V

+5V

-12V

N/C

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

19

37

18

36

17

35

16

34

15

33

14

32

13

31

12

30

11

29

10

28

9

27

8

26

7

25

6

24

5

23

4

22

3

21

2

20

1

REAR VIEW

PA0
PA1
PA2
PA3

PA PORT

PA4
PA5
PA6
PA7
PC0
PC1

LOWER

PC2
PC3
PC4
PC5

UPPER

PC6
PC7
DIG COM
+5V

PC PORT

Table 3-1

Pin descriptions for KPCI-PIO24 I/O connector

Pin No. Pin label Description

1 INTERRUPT

INPUT

2 INTERRUPT

ENABLE

External interrupt, edge triggered. By default, triggered by the ris­ing edge of a TTL signal. Can set it to be triggered by the falling
edge of a TTL signal. Refer also to “Interrupts” in section 4.
Latching of input data is available through DriverLINX

1

.

External interrupt enable, active low. To enable the interrupt at pin
1, connect pin 2 to digital common (pin 11, 13, 15, 17, 19, or 21).

3 to 10 PB0 to PB7 The eight I/O bits of port B. PB0 is the least significant bit (LSB)

of port B and PB7 is the most significant bit (MSB).

11, 13,

DIG COM Digital common from the PCI bus.

15, 17,
19, 21

12 N/C No connection

14 -12 V -12 V power from the PCI bus.

16 +12 V +12 V power from the PCI bus

18, 20 +5 V +5 V power from the PCI bus.

22 to 29 PC0 to PC7 The eight I/O bits of port C. PC0 is the least significant bit (LSB)

of port C and PC7 is the most significant bit (MSB).

30 to 37 PA0 to PA7 The eight I/O bits of port A. PA0 is the least significant bit (LSB)

of port A and PA7 is the most significant bit (MSB).

1

Refer to “Advanced Digital I/O Configuration” in the DriverLINX on-line help and to “Inter­rupts” in section 4 of this manual. For additional information, search your DriverLINX manuals
for the term “latching.”

KPCI-PIO24 User’s Manual Installation 3-7

Figure 3-2

Board layout

Mounting

bracket

37 pin D

connector

Connecting I/O cables and interface accessories

The KPCI-PIO24 I/O connectors can be mated directly to your external circuits using a locally
fabricated cable assembly. Alternatively, the connectors can be mated to your circuits via a
manufactured cable assembly and interface accessories, such as screw terminal boards and
relay circuits.

3-8 Installation KPCI-PIO24 User’s Manual

CAUTION If a cable is connected to any external circuits, make sure power

to all external circuits is turned OFF before connecting this cable
to the KPCI-PIO24 board. Connecting a powered external cable
to the board can damage the board, the external circuit, or both.

Handle the board at the mounting bracket, using a grounded
wrist strap. Do not touch the circuit traces or connector contacts.
If you do not have a grounded wrist strap, periodically discharge
static electricity by placing one hand firmly on a grounded metal
portion of the computer chassis.

Using locally fabricated cable assemblies

To mate a locally fabricated cable to an I/O connector, install a female 37-pin “D” type mating
connector (Keithley part no. SFC-37) on the cable.

Using manufactured cables and accessories

Using manufactured cables and accessories is illustrated in Figure 3-3. Each item is described in
Table 3-2. For more information about these products, refer to your Keithley data acquisition or
full line catalog or consult with your Keithley dealer.

Figure 3-3

Using manufactured cables and accessories

KPCI-PIO24 User’s Manual Installation 3-9

Table 3-2

Description of manufactured cables and accessories

Cable/accessory Description

C1800 Ribbon cable, 18 in, with two 37-pin female connectors.
S1800 Shielded version of C1800.
C1800/M Ribbon cable, 18 in, with one 37-pin female connector and one 37-pin male

connector.
S1800/M Shielded version of C1800/M.
STA-U Universal screw terminal board in a box, with female 37 pin connector.

Requires a C1800/M or S1800/M cable.
STP-37 Screw terminal panel. Requires a C1800 or S1800 cable.
STC-37 Screw terminal connector that plugs directly into the KPCI-PIO24.
ERB-24 24-channel DPDT relay output board. Requires a C1800 or S1800 cable.
ERA-01 8-channel SPDT relay output board. Requires a C1800 or S1800 cable.
SSIO-24 24-channel solid state I/O module board. Requires a C1800 or S1800 cable.
SRA-01 8-channel solid state I/O module board. Requires a C1800 or S1800 cable.

NOTE C ompliance to CE Mark emission levels requires use of shielded

versions of Keithley cables, S1800 and S1800/M.

Standard C1800, C-1800/M, S1800, S-1800/M 2000 cables are 18 inches long. Longer cables are
available. If you need a longer cable, refer to the accessories section of your Keithley catalog.

Connecting I/O cables to your external circuit

CAUTION Ensure that both the computer and the external circuit are turned

OFF before making any connections. Making connections while
the computer and external circuits are powered can damage the
computer, the board, and the external circuit.

External circuits must properly match the input and output requirements of the card. For example,
input signals often require pull-up resistors and elimination of contact bounce; output signals
must not draw excessive current. The following section presents pull-up, de-bounce and relay
drive circuits and discusses using +5 VDC power from the board for these and other applications.

Monitoring contact closure at an input

To ensure that the KPCI-PIO24 reliably monitors an open contact as an input-high condition,
connect a 10 k Ω pull-up resistor between the input line and a +5 VDC source. See Figure 3-4.

3-10 Installation KPCI-PIO24 User’s Manual

Figure 3-4

Contact-closure monitoring at a KPCI-PIO24 board input

System connections

+5V

External

Pull-up Resistor

10kΩ

Switch

Digital

Common

GND

Digital

Input

#n

KPCI-PIO24

Board

Eliminating contact bounce

The effects of contact bounce may be eliminated by programming in your application software.
However, it is often desirable to eliminate contact bounce from the signal, using a de-bounce
circuit between the contacts and the KPCI-PIO24 input. Figure 3-5 shows a typical de-bounce
circuit that can be used with Form C contacts.

Figure 3-5

De-bounce circuit for an input of a KPCI-PIO24 board

+5V

10 kΩ

10 kΩ

&

To Digital Input

of a

KPCI-PIO24 Board

&

Digital

Common

GND

TTL

Compatible

AND Gate

KPCI-PIO24 User’s Manual Installation 3-11

Boosting relay drive current

Some relays require higher drive currents than standard solid-state relays. The maximum output
low sink current for each I/O line of a KPCI-PIO24 board is 64mA at 5V. If your relay requires
more than 64mA or more than 5V, you can boost the drive current and/or voltage for relay control
using the circuit shown in Figure 3-6.

Figure 3-6

NPN transistor relay control for an output of a KPCI-PIO24 board

Relay

Digital

Output

KPCI-PIO24

Board

#n

NPN

Transistor

470 Ω

Min.

Digital

Common

GND

Surge

Protection

Diode

+

−

To Relay

DC Power

Supply

For drive-current requirements between 15mA and 100mA, select an NPN transistor
with appropriate current capacity. The power transistor must be rated for the required
supply voltage and must have a collector current rating no higher than 0.5A. If higher current
is needed, substitute a Darlington NPN transistor.

Using +5 VDC from the computer power supply

CAUTION Do not connect the +5 VDC outputs to an external +5VDC supply.

This may damage the external supply, the board, and
the computer.

Do not draw more than 1.0 A, total, from the board to power
external circuits. Drawing more than 1.0 A may damage
the board.

The board extends power from the +5 VDC computer supply to the I/O connector (see
Figure 3-1). This power is convenient for use in light external circuits, such as pull-up resistors.
If you ensure that the following conditions are maintained, this power may also be used to
energize external accessories:

The total current drawn to power the board and all external circuits must not overload the

•

computer power bus.

•

The total current drawn to power all external circuits must be less than 1A.

4

Interrupts and I/O

Address Mapping

4-2 Interrupts and I/O Address Mapping KPCI-PIO24 User’s Manual

Interrupts

Two externally accessible inputs allow for flexible interrupt configuration: INT_EN (external
interrupt enable, active low) and INT_REQ (external interrupt request, edge triggered). The
interrupt pins on the I/O connector are identified in Figure 3-1.

The external interrupt request line can be set in software to trigger on either the positive (rising)
edge or the negative (falling) edge of the signal; positive edge triggering is the default upon
power-up or reset. Also, when one or more ports are configured as inputs, the interrupt request
line can be simultaneously programmed to latch incomin g data on this edge. Refer to the KPCI­PIO24 software manual for more information on setting and configuration of the
external interrupts.

The PCI bus shares a single interrupt line for all cards, INTA, which interrupts the host comput er
every time a transfer is occurring. This interrupt is internal to the PCI bus. It must not be conf used
with the external interrupt line, INT_REQ, even though INT_REQ and INTA are linked
by software.

I/O address mapping

NOTE A typical user of the KPCI-PIO24 board does not need to read this

section. Register level programming of your board is neither practical
nor necessary for most users. Register level interfacing with the PCI
bus is more complex than with the ISA bus. PCI board addresses are
mapped automatically in general memor y, whereas ISA board
addresses are assigned by the user to memory reserved for I/O.

The DriverLINX driver shipped with your board provides a user-friendly Application
Programming Interface (API) that supports Visual C++, Visual Basic, and Delphi programming
languages under Windows 95/98 and Windows NT 4.0. You are strongly encouraged to use the
capabilities of DriverLINX and ignore the rest of the information in this chapter.

However, there are circumstances in which advanced uses may desire or need to bypass
DriverLINX entirely and write their own drivers. Alternatively , advanced users may wish to use
DriverLINX with programming languages other than Visual C++, Visual Basic, or Delphi.

Ways to accomplish these tasks are referenced under “Setting control and data registers.” The
remainder of the chapter summarizes general and relative register addresses and
register assignments.

General memory assignments

The PCI specification allows each card to be assigned up to five distinct memory regions. The
first region, BADDR 0, is mandatory per the PCI specification, as published by the PCI Special
Interest Group (PCISIG). BADDR 0 contains all information needed to identify a PCI device.
BADDR 0 also contains specific operation registers for the AMCC S5933 bus controller. These
operation registers hold all control and status information, as well as FIFOs, for PCI-initiated bus
mastering. The other four memory regions are BADDR1, BADDR2, BADDR3, and BADDR4.
These regions are left for custom designs and operate only in the target mode, also called
passthrough operation (memory access through the CPU). High speed data transfer via bus
mastering is unnecessary for the simple digital I/O of the KPCI-PIO24 board.

KPCI-PIO24 User’s Manual Interrupts and I/O Address Mapping 4-3

Control and data register memory assignments

The KPCI-PIO24 normally operates in the target mode and uses eight consecutive memory
mapped locations at BADDR1 for its control and data ports. The base address for these locations
is automatically assigned by the Plug and Play feature upon power up. Each offset from the base
address is specified as a multiple of four bytes (modulo 4 addressing), because each offset
specifies a four byte (32 bit) wide register. Refer to Table 4-1; the prefix ‘0x’ in Table 4-1
designates hexadecimal.

NOTE

Table 4-1

Data and control register addresses

Address Contents I/O Function

Base + 0x0 offset Port group

*

Base + 0x4 offset Not used N/A

Base + 0x8 offset Not used N/A

Base + 0xC offset Not used N/A

Base + 0x10 offset Control register bits for

Base + 0x14 offset Not used N/A

Base + 0x18 offset Not used N/A

Base + 0x1C offset Not used N/A

1

Contains a PA port, a PB port and a PC port, as in the emulated

8255 chip.

The term “Base” address in Table 4-1 does not have the same
meaning for a PCI board, such as the KPCI-PIO24, as for an ISA
board. The base address for your KPCI-PIO24 is a memory mapped
address, BADDR1, that is assigned by Plug and Play. It is not a fixed,
user assigned I/O address such as 0x300 or 0x310.

1

0 data Read/Write

Write only

port group 0

* Data Register Format, 32 Bit

4 High

Bits of Port C

MSB LSB

The control register bit assignments for each port are listed in Table 4-2.

Not

Used

Not

Used

4 Low

Bits of Port C

8 Bits of

Port B

8 Bits of

Port A

4-4 Interrupts and I/O Address Mapping KPCI-PIO24 User’s Manual

Table 4-2

Control register bit assignments for each port group

Configuration for this port

Bit When bit When bit
Number Function Variable name for bit value = 0

1

value = 1

Bit 7 Transfer method bit 1 ACCESSMODE1 See Table 4-3 See Table 4-3
Bit 6 Transfer method bit 0 ACCESSMODE2 See Table 4-3 See Table 4-3
Bit 5 External interrupt

INT_POLARITY See footnote

2

See footnote

3

polarity

Bit 4 Nonlatching/latching

BUFF_LATCH See footnote4See footnote

5

ports

Bit 3 I/O direction for PC

PCHI0_DIR Input Output

port, upper half

Bit 2 I/O direction for PC

PCLO0_DIR Input Output

port, lower half
Bit 1 I/O direction for PB port PB0_DIR Input Output
Bit 0 I/O direction for PA port PA0_DIR Input Output

1

All bit values default to ‘0’ upon computer reset or power-up.

2

When INT_POLARITY = 0, an interrupt is triggered by the positive (rising) edge of the

external interrup t s ignal at pin 1 of t he I/ O conn ector.This is the defau lt up on reset or po wer- up.

3

When INT_POLARITY = 1, an interrupt is triggered by the negative (falling) edge of the

interrupt signal .

4

When BUFF_LATCH = 0, ports configured for input act as transparent buffers; data is read

from the ports in real time. This is the default upon reset or power-up.

5

When BUFF_LATCH = 1, ports configured for input act as latches; data is latched when an
external interrupt signal is received, at pin 1 of the I/O connector. The polarity is defined
by INT_POLARITY.

Three different data transfer mo des can be specified via appropr iate combinations of bits 6 and 7.
Refer to Table 4-3.

NOTE Some of the terms that follow may not be fully understood without

referring to the AMCC S5933 PCI Bus Controller manual.

KPCI-PIO24 User’s Manual Interrupts and I/O Address Mapping 4-5

Table 4-3

Data transfer mode selection

Bit combinations Data transfer mode Notes

Bit 7

ACCESSMODE1

00

01

10

11

Bit 6

ACCESSMODE0

Data is accessed via the target (pass­through) mode of the AMCC S5933
bus controller. No bus mastering.
Data is accessed via the target (pass­through) mode of the AMCC S5933
bus controller. No bus mastering
Data is accessed via the FIFO of the
AMCC S5933 bus controller. The
FIFO is accessible by the host as
programmed I/O or via
bus mastering.
Data is accessed via the FIFO of the
AMCC S5933 bus controller. The
FIFO is accessible by the host as
programmed I/O or via
bus mastering.

Default upon
reset or
power-up

All ports, of
port group 0,
must be
configured as

inputs

All ports, of
port group 0,
must be
configured as

outputs

When bus mastering is not invoked:

• An interrupt is always generated on the edge of every external interrupt request signal, as

defined by the INT_POLARITY bit.

• An interrupt can be used to interrupt the host comp uter during the tar get mode (pass-throu gh)

access or be used to service the FIFOs for programmed I/O accesses.

When bus mastering is invoked:

• An interrupt is not generated on the edge of an interrupt request signal.

• Only one PCI board can take control of the PCI bus at any given time dur in g a bus-mastered

data transfer, and only one interrupt is permitted during this transfer. Therefore, an interrupt
cannot be generated at an arbitrary time. An interrupt is generated only after a predefined
number of data points have been transferred.

4-6 Interrupts and I/O Address Mapping KPCI-PIO24 User’s Manual

Setting control and data registers

The control registers must first be set by software statements to set each group of A, B, and C
ports for the desired direction (input or output). This is performed by writing to the control
registers located at the Base Address + 0x10, Base Address + 0x14, Base Address + 0x18, and
Base Address + 0x1C. In most applications all 8 bits in each port will be set as either input
or output.

Thereafter, data can be input to or output from the data registers. Data registers configured as
outputs are set by writing ones and zeros to these registers with software statements. Data
registers configured as inputs are set by applying logical high and low signals to the input
terminals; the set values in these registers are retrieved by software statements.

Software manipulation of data registers for an ISA board, via I/O port calls, is straightforward.
However, software manipulation of data registers for a PCI board, such as the KPCI-PIO24, is
more involved. As mentioned in the chapter introduc tion, DriverLINX eliminates the need for
user interaction with control and data registers. However, control and data registers can be
manipulated in the following special situations:

• You are an advanced user needing to use the KPCI-PIO24 with an operating system other

than Microsoft Windows 95/98 or Windows NT 4.0 or greater. In this situation, you must
write a new driver, bypassing DriverLINX entirely. This task requires an in-depth knowledge
both of the AMCC S5933 PCI Bus Controller and your development operating system.

• You wish to program in an Act iveX hosting l anguage ot her than Visual C++, Visual Basic, or

Delphi. In this situation, you may need to use the “Direct I/O ActiveX Autom a tion Object”
that comes with DriverLINX. The Direct I/O ActiveX Automation Object allows you to set
the control and data registers directly and bypass the DriverLINX API, yet avoids the full
complexities of PCI bu s in terfaci ng and th e AMCC S5 933 P CI Bus Co ntrol ler. Refer to your
DriverLINX manual for more information.

• You wish to reuse an existing program that makes port I/O calls to an ISA-bus digital I/O

board, such as the PIO-96 or PIO-24. In this situation, you can reuse your existing program
with the KPCI-PIO24, in Windows 95/98 only, via the Hardware I/O Emulation driver
included on your DriverLINX CD ROM. The Hardware I/O Emulation driver traps the port
I/O calls and applies them properly to the KPCI-PIO24 board. Refer to your DriverLINX
manual for more information.

5

Troubleshooting

5-2 Troubleshooting KPCI-PIO24 User’s Manual

If your KPCI-PIO24 board is not operating properly, use the information in this section to isolate
the problem before calling Keithley Applications Engineering. If you then need to contact an

applications engineer, refer to “Technical support.”

Identifying symptoms and possible causes

Try to isolate the problem using Table 5-1, which lists general symptoms and possible solutions
for KPCI-PIO24 board problems.

Table 5-1

Basic troubleshooting information

Symptom Possible cause Possible cause validation/so lution

Computer does
not boot when
board is installed

Resource conflict. KPCI-PIO
series board is conflicting with
other boards in the system.

1. Validate the cause of the conflict.
Temporarily unplug boards —especially ISA

1

boards

—one at a time, and try booting the

computer. Repeat until a boot is attained.

2. Try resolving conflicts by reinstalling one
PCI board at a time and rebooting after each
reinstallation.

2

However, you may ultimately
need to change ISA board resource allocations,
such as base address or interrupt assignments.

Board not seated properly. Check the installation of the board.

After board &
software are
installed, mouse
control is lost or
system freezes.

Board does not
respond to the
PIO Test Panel.

Data appears to
be invalid.

Intermittent
operation.

The power supply of the host
computer is too small to handle

Check the needs of all system resources and
obtain a larger power supply.

all the system resources.
An interrupt conflict occured. Unplug the board to regain mouse control.

Look closely at the COM ports and at the
interrupts of other devices.

DriverLINX is not
installed properly.

Check the Windows® Device Manager and
follow the installation troubleshooting
instructions in the DriverLINX on-line help.

The board is incorrectly

Check the board for proper seating.

aligned in the expansion slot.
The board is damaged. Contact Keithley Applications Engineering.
An open connection exists. Check screw terminal wiring.
Transducer is not connected

Check the transducer connections.

to channel being read.
One or more external circuits

are not TTL compatible
Vibrations or loose

connections exist.

Check external circuit schematics. Test
external circuits with a logic probe.

Cushion source of vibration and
tighten connections.

The board is overheating. Check environmental and ambient

temperature. See your
computer documentation.

Electrical noise exists. Pr ovide better shielding or reroute unshielded

wiring.

System lockup
during operation.

A timing error occurred. Restart your computer. Then analyze your

program by debugging and narrowing the list
of possible failure locations .

1

Plug and Play cannot tell if an ISA board already uses an address it assigns to a PCI board.

2

Plug and Play may then assign different, nonconflicting addresses to the PCI boards.

KPCI-PIO24 User’s Manual Troubleshooting 5-3

If your board is not operatin g prop erly afte r usin g the inf ormatio n in Table 5-1 , conti nue with t he
next section to further isolate the problem.

Systematic problem isolation

General problem isolation procedure

If you were unable to isolate the problem using Table 5-1, then follow Figure 5-1 and the
accompanying written procedure. The f lowchart in Figure 5-1 sum marizes how to systematically
check and eliminate some problem causes. The corresponding written procedure amplifies the
flowchart steps with more detail.

CAUTION Always turn OFF your computer and any external circuits

connected to the KPCI-PIO24 board before removing or
replacing the board. Removing or replacing a board with the
power ON can damage the board, the computer, the external
circuit, or all three.

Handle the board at the mounting bracket, using a grounded
wrist strap. Do not touch the circuit traces or connector co ntacts.
If you do not have a grounded wrist strap, periodically discharge
static electricity by placing one hand firmly on a grounded metal
portion of the computer chassis.

NOTE In the following procedure, the term “board” always refers to a

KPCI-PIO24 board. The procedure never directs you to install or
remove any type of PCI board other than a KPCI-PIO24 board.

In Figure 5-1 the number in brackets in each flowchart block (e.g
refers to the corresponding step number in the verbal procedure. If
multiple blocks in the flowchart have the same number, each of those
blocks is part of a single verbal step. Conversely , if ther e is a ran ge of

[4, 5, 6]

numbers in the brackets (e.g.
verbal steps.

The logic in this procedure assumes that the problem has only one
cause. Therefore, once a cause is found and corrected, the reader is
instructed to reassemble the system and verify proper operation.

), the block summarizes multiple

. [21]

)

5-4 Troubleshooting KPCI-PIO24 User’s Manual

Figure 5-1

Problem isolation flowchart

KPCI-PIO24 User’s Manual Troubleshooting 5-5

To further isolate the problem to the KPCI-PIO24 board or to the host computer, use the
following steps:

1. Check if board damage is seen on inspection. Proceed as follows:

NOTE If more than one KPCI-PIO24 board is installed in your computer,

disconnect, remove, and check all KPCI-PIO24 boards.

a. Turn power OFF to the host computer.
b. Turn power OFF to all external circuits and accessories connected to the
KPCI-PIO24 board.
c. Unplug all I/O cables from all external circuits or unplug I/O cables from accessory boards

connected to external circuits.
d. Remove the KPCI-PIO24 boa rd from the computer.
e. Visually inspect the KPCI-PIO24 board for damage.

2. Based on the results of step 1, do the following:

• If the board is not obviously damaged, skip to step 3 and check for host computer

malfunction.

• If a board is obviously damaged on inspection, repair or replace the board. Refer to

“T echnical support” for information on returning the board for repair or rep lacement. Skip
to step 27.

3. Check if the computer functions satisfactorily by itself. Proceed as follows:

a. Remove the KPCI-PIO24 board from the host computer.

NOTE If more than one KPCI-PIO24 board is installed in your computer,

remove all KPCI-PIO24 boards before testing the host computer.

b. Turn ON powe r to the host computer.
c. Perform any necessary diagnostics to the computer hardware and operating system.

4. Based on the results of step 3, do one of the following:

• If the computer functions satisfactorily, the problem must lie elsewhere; do the

following steps:
a. If you have another KPCI-24 board that you know is OK, i.e. works properly, then

proceed to step 5.

b. If you do not have another KPCI-24 board that you know is OK, i.e. works properly,

read the instructions in “T echnical support.” Then co ntact Keithley for help in isolating
the cause of your problem.

• If the computer does not function satisfactorily, do the following steps:

a. Diagnose and fix the computer malfunction.
b. Assume that fixing the computer malfunction has solved your problem, and skip to

step 27.

5. Install a board known to be OK, as follows:
a. Turn OFF power to the host computer.
b. Install a KPCI-PIO24 board that you know is OK, i.e. fully functional. Refer to

Section 3, “Installation.”

NOTE Do not make any I/O connections at this point.

5-6 Troubleshooting KPCI-PIO24 User’s Manual

6. Check if the computer finds the OK board to be a PCI resource.
If an OK board is properly installed electrically and th e PCI expansion slot is functio nal, then
Windows 95 Plug and Play should configure the board as a PCI reso urce. Proceed as follows:

a. Determine the number of the expansion slot used by the OK KPCI-PIO24 board. Refer to

the slot numbering information in your motherboard manual.

b. Turn ON the power to reboot the computer and, during boot, determine whether your

operating system has identified the board as a PCI resource. Dur ing boot, the Windows 95
Plug and Play should list the PCI resources found. The bo ard should be listed, likely as an
unidentified peripheral, with same slot number as identified in step 6a.

7. If you had originally installed additional KPCI-PIO24 boards in other PCI slots, then repeat
steps 5 and 6 with the OK board in each of these other slots.

8. Based on the results of steps 5 through 7, do one of the following:

a. If the board is recognized as a PCI component in all slots tested, then there may be software

issues. Skip to step 16.

b. If the OK board is not recognized as a PCI component in a slot(s), then the PCI slot

connector(s) is suspect. Continue with step 9.

9. Make sure that slot and board contacts have wiped adequately and are properly mated. Do
the following:

a. Turn OFF power to the host computer.
b. Remove and reseat the board a few times in the PCI slot connector. This creates a wiping

action to improve the probability of good contact.
c. Make sure that the board is firmly seated in the PCI slot connector.
d. Turn ON power to the host computer.

10. Check if the computer now finds the OK board to be a PCI resource.
Proceed as follows (refer back to similar step 6 for more description):

a. Determine the number of the expansion slot used by the OK board.
b. Boot the computer and, during boot, determine whether your operating system has

identified the OK board as a PCI resource.

11. If KPCI-PIO24 boards were originally instal led in other PCI sl ots, t hen repeat steps 9 and 10
with the OK board in each of these slots.

12. Based on the results of steps 9 through 11, do one of the following:

• If the board is recognized as a PCI resource in all slots tested, then the cause of the

problem was probably high contact resistance, which apparently has been corrected b y the
wiping action. Skip to step 27.

• If the OK board is not identified as a PCI resource in all slots tested, then any slot in which

it is not identified is suspect. Continue with st ep 13.

13. Based on the history of steps 6 through 12, do one of the following actions, to further
determine whether a bad slot connector is causing your problem:

• If, at this point, you’ve only tested the OK board in one slot on this computer AND you

have another slot available, test it in another slot now. Proceed as follows:
a. Turn OFF power to the host computer.
b. Move the OK KPCI-PIO24 board to another available slot.
c. Determine the number of the expansion slot used by the OK board.
d. Turn ON power to the host c omputer.
e. During boot, determine whether your operating system has identified the board as a

PCI resource. (Refer to step 6 for more information.)

f. Continue with step 14.

KPCI-PIO24 User’s Manual Troubleshooting 5-7

• If, at this point, you’ve tested the OK board in more than one slot on this computer,

continue with step 14.

14. Based on the history of steps 6 through 13, do one of the following:

• If, at any point in this procedure, the OK board was identified as a PCI resource in at least

one slot on the host computer, then any slot in which it did not work is likely defective.
Continue with step 15.

• If you only had one slot in wh ich to i nstal l th e OK boar d, assume that this slot is defective.

Continue with step 15.

• However, if you have installed the OK board in more than one slot and the board has not

been identified as a PCI resource in at least one slot, then the cause of your problem may
be outside the scope of these diagnostics: two or more slots are assumed unlikely to be

defective in the same computer. Read the instructions in “Technical support,” and then
contact Keithley for help in isolating the cause of your problem.

15. Replace the defective slot connector, as follows:
a. Turn OFF the computer.
b. Remove the OK board.
c. Have a qualified service person replace the defective PCI slot connector.
d. Skip to step 27.

16. Continuing from step 8, verify that Driv erLINX is ins talled properly:

• If DriverLINX is installed pro perly, continue with step 17.

• If DriverLINX is not installed properly, do the following:

a. Install it now, referring to the DriverLINX installation instructions. Make sure that

DriverLINX installs smoothly and completely.

b. Continue with step 17.

17. Perform I/O bit tests to determine whether you can write and read all I/O bits to and from the

OK board: the I/O loop- back t est an d th e outp ut set test. Per form ei ther or both of th ese t ests ,

outlined separately under the headings “I/O loop-back test” and “Ou tput set test.” However,
only the I/O loop-back test is conclusive and is therefore preferred.

18. Based on the results of step 17, do one of the following:

• If you can write and read all I/O bits to and from the OK board, skip to step 21.

• If you cannot write and read all I/O bits to and from the OK board, there may be data

acquisition program errors or defective I/O slot contacts in the slot; continue with step 19.

19. If you cannot write and read all I/O bits to and from the OK board do the following:

• If you have arrived at step 19 before making corrections, there may be data acquisition

program errors; continue with step 20.

• If you have arrived again at step 19 after apparently correcting all program errors in the

data acquisition program, the cause of your problem may be outside the scope of these

diagnostics. Read the instructions in “Technical support,” and then contact Keithley for
help in isolating the cause of your problem.

20. Check if all data acquisition program lines are OK.

Check the program documentation or use a debugger to look for programming errors that
may be causing the problem.

• If no programming errors are found, then some of the slot connector contacts

corresponding to the I/O bits are likely defective, given that the board is known to be OK.
Do the followi ng:

a. Turn OFF the computer.
b. Remove the OK boa rd.

5-8 Troubleshooting KPCI-PIO24 User’s Manual

c. Have a qualified service person replace the defective PCI slot connector.
d. Skip to step 27.

• If programming errors are found, do the following:

a. Debug and fix all known data acquisition program errors.
b. Repeat steps 17 and 18.

21. Continuing from steps 17 and 18, if you can write and read all I/O bits to and from the OK
board, do the following:

• If you have arrived at step 21 after program correcti ons have b een made, and y ou can now

write and read all I/O bits to and from the OK board, then the problem has apparently been
resolved. Skip to step 27.

• If you have arrived at step 21 without making data acquisition program corrections and

can write and read all I/O bits to and from the OK board, then faulty external I/O
connections may have caused your problem. Continue with step 22.

22. Check each external I/O connection, one at a time, for short circuits and open circuits. If
KPCI-PIO24 boards were installed in more than one PCI slot, check the I/O connections for
all boards.

23. Based on the results of step 22, do the following:

• If any external I/O connections are found to be faulty, assume that the problem was caused

by the faulty connections, then proceed as follows:
a. Correct the faulty external connections.
b. Skip to step 27.

• If all external I/O connections are found to be normal, then, by process of elimination, the

KPCI-PIO24 board(s) originally installed in the computer is likely the cause of the
problem. Continue with step 24.

24. Replace the faulty board. Do one of the following:

• If only one KPCI-PIO24 board was installed when the problem occurred, proceed

as follows:
a. Leave the OK board in the expansion slot as a replacement. To repair or replace the

faulty board, contact Keithley as described in “Technical support.”

b. Skip to step 27.

• If more than one board was installed when the problem occurred, determine which one is

faulty, starting with step 25.

25. Check if one of the original boards is not detected as a PCI resource. Proceed as follows

a. Turn OFF the computer.
b. Remove the OK board.
c. Ins tall o ne of the original boards in a slot known to be satisfactory.
d. Turn ON the computer and, during boot, determine whether your operating system has

identified the board as a PCI resource. See step 6 for more information.

e. Based on the results of step 25d, do one of the following:

• If, in step 25d, the board is not recognized as a PCI resource, you have located the

faulty board; replace it with the OK bo ard. (To rep air th e fau lty board o r obtain a n ew

one, contact Keithley as described in “Technical support.”) Then skip to step 27.

• If, in step 25d, the board is recognized as a PCI resource, repeat steps 25a through 25e

for each board. If you have reached this point after trying multiple boards, and each
board has been recognized as a PCI resource, then continue with step 26.

26. Determine which board has faulty I/O. If the faulty board survived the PCI resource test in
step 25, it should fail the I/O test.

KPCI-PIO24 User’s Manual Troubleshooting 5-9

a. If an origin al board remains installed following step 25, then skip to step 26e.
b. Turn OFF the computer.
c. Install one of the original boards in a slot known to be satisfactory.
d. Turn ON the computer.
e. Perform the I/O tests outlined in the “I/O bit tests” section. Then return to this step (26e).

f. Based on the results of step 26e, do one of the following:

• If, in step 26e, you cannot write and read all I/O bits to and from the board, you have

located the faulty board; replace it with the OK board. (To repair the faulty board or

obtain a new one, contact Keithley as described in “Technical suppo rt.”) Th en skip to
step 27.

• If, in step 25e, you can write and read all I/O bits to and from the board, repeat steps

25b through 25e for each board until you find a faulty board. Rep lace the faulty bo ard
with the OK board. (To repair the faulty board or obtain a new one, contact Keithley

as described in “Technical support.”) Then continue with step 27.

• However, if you have reached this point after trying all boards, and the I/O on each

board has been found satisfactory, then the cause of your problem may be outside the

scope of these diagnostics. Read the instructions in “Technical support,” and then
contact Keithley for help in isolating the cause of your problem.

27. Assuming the problem has been resolved, do the following:
a. Turn OFF the computer.
b. Install the good KPCI-PIO24 boards in good slots.
c. Reconnect all external circuits as discussed in Section 3, “Installation.”
d. Turn ON the computer.
e. Verify that the system now performs satisfactorily.

28. Based on the results of step 27e, do one of the following:

• If the system now performs satisfactorily, you have successfully isolated and corrected

the problem.

• If the system still does not perform satisfactorily, then the cause of your problem may be

outside the scope of these diagnostics. Read the instructions in “Technical support,” and
then contact Keithley for help in isolating the cause of your problem.

5-10 Troubleshooting KPCI-PIO24 User’s Manual

I/O bit tests

The I/O bit tests check whether the input and output functions of the board are operating properly .
They also act as backup tests for a defective slot con nector . Of the two tests outlined below , only
the I/O loop-back test is conclusive and is therefore preferred.

These tests are intended to be used when requested in the “General problem isolation procedure.”
However, they may also be used for general performance checks.

CAUTION The tests outlined in the next two sections involve handling of the

KPCI-PIO24 circuit board. Handle the boar d at the mounting
bracket, using a grounded wrist stra p. Do not touch the circuit
traces or connector contacts. If you d o not have a g ro unded wri st
strap, periodically discharge static electricity by placing one hand
firmly on a grounded metal portion of the computer chassis.

Ensure that the computer is turned OFF before installing or
removing a board. Installing or removing a board while power is
ON can damage your computer, the board, or both.

I/O loop-back test

The I/O loop-back test checks input and output bit performance.
You prepare a specially wired loop-back connector that connects the bits of port A to the

corresponding bits of ports B and C. These connections are summarized in Table 5-2.

Table 5-2

Loop-back connection summary

Connect these bits
configured as an output

to these bits configured
as inputs

You insert this connector into the KPCI-PIO24 I/O connector. Then, you use a DriverLINX
graphical interface to configure the bits of port A as outputs and ports B and C as inputs.
Thereafter, you use this same DriverLINX graphical interface to set two different bit patterns at
port A and to check in each case for corresponding bit patterns at ports B and C.

The card is performing satisfactorily if all 24 bits respond appropriately.
Perform the loop-back test as follows:

1. Prepare a loop-back test connector, using a female 37-pin ‘D’ connector that mates with the
I/O connector on your board. This can be purchased as Keithley part no. SFC-37. Wire the
connector as shown in Figure 5-2.

PA0↓PA1↓PA2↓PA3↓PA4↓PA5↓PA6↓PA7

↓

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC 0

PB 7

PB 6

PB 5

PB 4

PB 3

PB 2

PB 1

PB 0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

DIG COM

N/C

DIG COM

-12V

DIG COM

+12V

DIG COM

DIG COM

+5V

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

DIG COM

+5V Output

Interrupt Enable

Interrupt Input

R=1k ohms

NC* NC*

*Make No Connections To These Pins

NC*

KPCI-PIO24 User’s Manual Troubleshooting 5-11

Figure 5-2

Mating connector wiring for loop-back test

NOTE

2. Turn OFF the host computer.

3. Insert the loop-back test connector, prepared in step 1, into the board connector.

4. Turn ON the host computer and boot Windows 95, 98, or NT.

5. Click the Windows Start tab.

6. Start the PIO Control Panel as follows:

Resistors in the loops are specified for safety. During the loop-back
procedure, some of the interconnected bits could temporarily or inad­vertently be configured both as outputs, and the board could be easily
damaged. These 1K ohm resistors limit the currents between bits to
below 15 mA, which is within the source and sink current specifica­tions for the board. If you wish to use a different resistance value, the
substitute resistance value must be at least 700 ohms.

5-12 Troubleshooting KPCI-PIO24 User’s Manual

a. In the Start menu, click Programs.
b. Find the DriverLINX ➧ Test Panels folder, under which you should find the PIO

Panel entry.
c. Click on the PIO Panel entry.
The PIO Control Panel should appear. See the example in Figure 5-3.

Figure 5-3

IO Control Panel example

NOTE In following steps 7 through 9, graphical slide switches on the PIO

Control Panel are used for all settings. Each click on the button of a
slide switch toggles the button up or down.

7. Using the ‘Configure’ switches on the PIO Control Panel, configure ports A, B, and C for
input or output as shown in Figure 5-4.

KPCI-PIO24 User’s Manual Troubleshooting 5-13

Figure 5-4

Setting port input and output ‘Configure’ switches

PORT A

PORT B

PORT C

Configure

n

Configure

n

Configure

n

Output
Input

Output
Input

Output
Input

8. Using the port A ‘write/read’ switch on the PIO Control Panel, set port A to ‘write’ as shown
in Figure 5-5.

Figure 5-5

Port A ‘write/read’ switch setting

PORT A

n

write
read

NOTE A port configured for output, such as port A in this case, can be set

for either read or write mode. In write mode, you may toggle bit
settings high or low by clicking the DIP sw itches. In read mode,
however, DIP switches only monitor the bit settings currently in the
I O register; you cannot change bit settings.

A port configur ed for input, such as port B or C in thi s case, can only
be used in the read mode. DriverLINX selects the read mode
automatically when the port is configured for input.

9. Using the DIP switches on the PIO Control Panel, set port A to bit pattern 1, shown in
Figure 5-6. Bit pattern 1 corresponds to a byte value of 55 in hexadecimal.

5-14 Troubleshooting KPCI-PIO24 User’s Manual

Figure 5-6

Port A output settings, bit pattern 1

PORT A

76543210

nnnn

On

nnnn

&H55

NOTE Note that the bit is ON when the switch button is DOWN.

10. Click the ‘U

pdate All’ button on the PIO Control Panel.

11. Obs erve the PIO Control Panel DIP switches for ports B and C, which in this case monito r
bit patterns instead of set them. The bit patterns for ports A, B, and C should all be the same,
because the output bits of port A are connected to the corresponding input bits of ports B
and C. The PIO Control Panel example, Figure 5-3, shows the results of a successful loop­back test for bit pattern 1.

• If the bit patterns for p orts A, B, and C do not agr ee, the board is not functioni ng pr operly.

Stop here, and return to the step in the “General problem isolation procedure” where you
were directed to do I/O bit tests (step 17 or step 26e in the “General problem
isolation procedure”).

• If the bit patterns for ports A, B, and C do all agree, continue with step 12.

12. Using the DIP switch on the PIO Control Panel, set port A to the bit pattern 2, as shown in
Figure 5-7. Bit pattern 2 corresponds to a byte value of AA in hexadecimal.

Figure 5-7

Port A output settings, bit pattern 2

PORT A

76543210

nnnn

On

nnnn

&HAA

13. Click the ‘U

pdate All’ button on the PIO Control Panel.

14. Again, observe the PIO Control Panel DIP switches for ports B and C. The bit patterns for
ports A, B, and C should again all be the same, as illustrated in Figure 5-8.

KPCI-PIO24 User’s Manual Troubleshooting 5-15

Figure 5-8

Correct bit patterns when port A is set to bit pattern 2.

PORT A

76543210

nnnn

On

nnnn

&HAA

PORT B

76543210

nnnn

On

nnnn

&HAA

PORT C

76543210

nnnn

On

nnnn

&HAA

15. Based on the observations in step 14, do the following:

• If the bit patterns for ports A , B, and C do not all agree, the board is not functioning

properly. Stop here, and return to the step in the “General problem isolation procedure”
where you were directed to do I/O bit tests (step 17 or step 26e in the “General problem
isolation procedure”).

• If the bit patterns for ports A, B, and C do all agree, the board is functioning properly. Stop

here, and return to the step in the “General problem isolation procedure” where you were
directed to do I/O bit tests (step 17 or 26e in the “General problem isolation procedure”).
Or, optionally, now perform the output set test, as discussed in the next section, if you
have not already done so.

Output set test

The output set test checks whether logic levels measured at all KPCI-PIO24 output pins agree
with output bit patterns set by software, using a DriverLINX graphical interface.

NOTE This test is performed w ithout user circuits being connected to

the outputs.

Perform the output set test as follows:

1. Ready the following equipment:

• A digital voltmeter (DVM) or a digital multimeter (DMM) set to measure voltages, or a

logic probe capable of reading TTL logic levels.

• A means to reliably and safely connect the DMM/DVM or logic probe input to each I/O

pin. The following alternatives are suggested:
a. A screw terminal-female connector combination, Keithley pa rt number STC-37, that

plugs directly into the I/O connector on your board. Refer to your Keithley catalog for
more information.

b. A cable assembly and terminal accessory (refer to “Using manufactured cables and

accessories” in Section 3).

c. A female 37-pin ‘D’ connector that mates with I/O connector on your board and is wired

such that the meter or logic probe can be clipped to exposed conductors. An
appropriate connector can be purchased as Keithley part no. SFC-37.

5-16 Troubleshooting KPCI-PIO24 User’s Manual

2. Turn OFF the host computer.

3. Insert the test connector or cable assembly/terminal accessory into the board connector.

4. Turn ON the host computer and boot Windows 95, 98 or NT.

5. Click the Windows Start tab.

6. Start the PIO Control Panel as follows:

a. In the Start menu, click Programs.
b. Find the DriverLINX ➧ Test Panels folder, under which you should find the PIO

Panel entry.
c. Click o n the PIO Panel entry.
The PIO Control Panel should appear. See the example in Figure 5-9.

Figure 5-9

PIO Control Panel example

NOTE In the following steps 7 through 10, graphical slide switches on the

PIO Control Panel are used for all settings. Each click o n the button
of a slide switch toggles the button up or down.

7. Using the ‘Configure’ switches on the PIO Control Panel, configure ports A, B, and C for
output as shown in Figure 5-10.

KPCI-PIO24 User’s Manual Troubleshooting 5-17

Figure 5-10

Setting port ‘Configure’ switches

PORT A

PORT B

PORT C

Configure

n

Configure

n

Configure

n

Output
Input

Output
Input

Output
Input

8. Using the port ‘write/read’ switches on the PIO Control Panel, set ports A, B and C to ‘write’
as shown in Figure 5-11.

Figure 5-11

Port ‘write/read’ switch settings

PORT A

n

write
read

PORT B

n

write
read

PORT C

n

write
read

NOTE A port configured for output, such as port A in this case, can be set

for either read or write mode. In write mode, you may toggle bit
settings high or low by clicking the DIP sw itches. In read mode,
however, DIP switches only monitor the bit settings currently in the
I/O register; you cannot change bit settings.

9. Using the DIP switches on the PIO Control Panel, set ports A, B, and C to bit pattern 1, as
shown in Figure 5-12. Bit pattern 1 corresponds to a byte value of 55 in hexadecimal.

5-18 Troubleshooting KPCI-PIO24 User’s Manual

Figure 5-12

Port output settings, bit pattern 1

PORT A

7 6 5 4 3 2 1 0

n n n n

On

n n n n

PORT B

7 6 5 4 3 2 1 0

n n n n

On

n n n n

PORT C

76543210

n n n n

On

n n n n

&H55

&H55

&H55

NOTE Note that the bit is ON when the switch button is DOWN.

10. Click the ‘U

pdate All’ button on the PIO Control Panel.

11. Measure the voltage between signal ground and each bit of ports A, B, and C with a DMM or
DVM or check the logic level for each bit of ports A, B, and C bit with a TTL logic probe.
Connect these instruments to the terminal accessory or ribbon cable that is connected to the
selected KPCI-PIO I/O connector.

Each bit set to ON in the PIO Control Panel should output a logic-h igh signal at the
corresponding I/O terminal, corresponding roughly to 4 volts at a DMM/DVM. Each bit set
to OFF in the PIO Control Panel should output a logic-low signal at the corresponding I/O
terminal, corresponding roughly to 0 volts at a DMM/DVM.

• If the bit patterns set on the PIO Control Panel do not agree with the logic levels measured

at the I/O terminals, the board is not functioning properly. Stop here, and return to the step

in the “General problem isolation procedure” where you were directed to do
I/O bit tests (step 17 or step 26e in the “General problem isolation procedure”).

• If the bit patterns set on the PIO Control Panel agree with the logic levels measured at the

I/O terminals, then continue with step 12.

12. Using the DIP switches on the PIO Contro l Panel, set ports A, B, and C to the bit patterns
shown in Figure 5-13, which correspond to byte values of AA in hexadecimal.

KPCI-PIO24 User’s Manual Troubleshooting 5-19

Figure 5-13

Port output settings, bit pattern 2

PORT A

7 6 5 4 3 2 1 0

n n n n

On

n n n n

&HAA

PORT B

7 6 5 4 3 2 1 0

n n n n

On

n n n n

&HAA

PORT C

7 6 5 4 3 2 1 0

n n n n

On

n n n n

&HAA

13. Click the ‘U

pdate All’ button on the PIO Control Panel.

14. Again, measure the voltage between signal ground and each bit of ports A, B, and C with a
DMM or DVM or check the logic level for each bit of ports A, B, and C bit with a TTL logic
probe. Connect these instruments to the terminal accessory or ribbon cable that is connected
to the selected KPCI-PIO I/O connector.

Again, each bit set to ON in the PIO Control Panel should output a logic-high signal at the
corresponding I/O terminal, corresponding roughly to 4 volts at a DMM/DVM. Each bit set
to OFF in the PIO Control Panel should output a logic-low signal at the corresponding I/O
terminal, corresponding roughly to 0 volts at a DMM/DVM.

• If the bit patterns set on the PIO Control Panel do not agree with the logic levels measured

at the I/O terminals, the board is not functioning properly. Stop here, and return to the step

in the “General problem isolation procedure” where you were directed to do I/O bit tests
(step 17 or step 26e in the “General problem isolation procedure”).

• If the bit patterns set on the PIO Control Panel do agree with the logic levels measured at

the I/O terminals, and you have performed an output set test for all four port groups, the

board is functioning properly. Stop here, and return to the step in the “General problem
isolation procedure” where yo u were directed to do I/O bit tests (step 17 or step 26e in the
“General problem isolation pro cedur e”). Or, optionally, perform the I/O loop-back test, as
discussed in the previous section, if you have not already done so.

5-20 Troubleshooting KPCI-PIO24 User’s Manual

Technical support

Before returning any equipment for repair, call Keithley for technical support at:

1-888-KEITHLEY
Monday - Friday, 8:00 a.m. - 5:00 p.m., Eastern Time

An applications engineer will help you diagnose and resolve your problem over the telephone.
Please make sure that you have the following information available before you call:

KPCI-PIO24 board
configuration

Computer Manufacturer

Operating system DOS version

Software package Name

Compiler
(if applicable)

Accessories Type

Model
Serial #
Revision code
Base address setting
Interrupt level setting
Number of channels

CPU type
Clock speed (MHz)
KB of RAM
Video system
BIOS type

Windows version
Windows mode

Serial #
Version
Invoice/Order #

Language
Manufacturer
Version

Type
Type
Type
Type
Type
Type
Type

____________________
____________________
____________________
____________________
____________________
____________________

____________________
____________________
____________________
____________________
____________________
____________________

____________________
____________________
____________________

____________________
____________________
____________________
____________________

____________________
____________________
____________________

____________________
____________________
____________________
____________________
____________________
____________________
____________________
____________________

If a telephone resolution is not possible, the applications engineer will issue you a Return Material
Authorization (RMA) number and ask you to return the equipment. Include the RMA number
with any documentation regarding the equipment.

KPCI-PIO24 User’s Manual Troubleshooting 5-21

When returning equipment for repair, include the following information:

• Your name, address, and telephone number.

• The invoice or order number and date of equipment purchase.

• A description of the problem or its symptoms.

• The RMA number on the outside of the package.

Repackage the equipment, using the original anti-static wrapping, if possible, and handle it with
ground protection. Ship the equipment to:

ATTN: RMA #_______
Repair Department
Keithley Instruments, Inc.
28775 Aurora Road
Cleveland, Ohio 44139

Telephone 1-888-KEITHLEY
FAX [phone]

NOTE If you are submitting your equipment for repair under warranty, you

must include the invoice number and date of purchase.

To enable Keithley to respond as quickly as possible, you must include
the RMA number on the outside of the package.

A

Specifications

A-2 Specifications KPCI-PIO24 User’s Manual

Specifications for the KPCI-PIO24 board are listed in the following table.

Table A-1
KPCI-PIO24 Specifications

Number of

24, bi-directional, non-isolated, TTL compatible

I/O Lines
I/O interface The group of 24 I/O lines, emulates one 8255A chip configured for Mode O
External

One 37 pin ‘D’ type connector

connections
Signal parameters Parameter Descriptions Min. Typ. Max. Unit

Data
lines

Interrupt
lines

Power

V
V
I

IH

I

IL

I

OZH

I

OZL

V
V
V
I

OL

I

OH

I

OS

I

OFF

I

IL

I

IH

V
V
I

OL

I

OH

IH

IL

OH

OH

OL

OL

OH

Voltage, Input High
Voltage, Input Low
Current, Input High, at VIN = 2.7V
Current, Input Low, at VIN = 0.5V
High Impedance Output Current, at V
High Impedance Output Current, at V
Voltage, Output High, at IOH = -8mA
Voltage, Output High, at IOH = -15mA
Voltage, Output Low, at IOL = 64mA
Current, Output Low
Current, Output High
Short Circuit Current
Input/Output Power-Of f Leaka ge
Current, Input Low
Current, Input High
Voltage, Output Low, at IOL = Maximum
Voltage, Output High, at IOH = Maximum
Current, Output Low
Current, Output High

out

out

+5 VDC, 25 W maximum

= High
= Low

2.0 - - V

--0.8V

--±1µA

--±1µA

--±1µA

--±1µA

2.4 3.3 - V

2.0 3.0 - V

-0.30.55V

-- 64mA

---15mA

-60 -120 -225 mA

--±1µA

- - -100 µA

---10µA

-0.30.5V

2.4 3.3 - V

-- 16mA

---3.2mA

Requirements
Additional power

to external circuits

+5 VDC, 1A maximum, total

Environmental Operating temperature 0 to 50° C

Storage temperature 0 to 70° C
Relative humidity 20 to 90% noncondensing

Physical

175 mm long × 107 mm wide × 19 mm high (6.88 in × 4.2 in × 0.75 in)

dimensions
Weight 116 g (4.1 oz)

B

Glossary

B-2 Glossary KPCI-PIO24 User’s Manual

Address

1

A number specifying a location in memory where data is stored.

API

See application programming interface.

Application programming interface

1

A set of routines used by an application program to direct the per formance of a pr ocedure by the

computer’s operating system.

Bus mastering

On a microcomputer bus such as the PCI bus, the ability of an expansion board to take control of
the bus and transfer data to memory at high speed, independently of the CPU. Replaces direct
memory access (DMA).

Bus

An interconnection system that allows each part of a computer to communicate with the
other parts.

Byte

A group of eight bits.

Contact bounce

The intermittent and undesired openi ng of relay contacts during closure, or closing of relay
contacts during opening.

Crosstalk

The coupling of a signal from one input to another (or from one channel to another or to the
output) by conduction or radiation. Crosstalk is expressed in decibels at a specified load and up
to a specific frequency.

Darlington

A high gain current amplifier composed of two bipolar transis tors, typically integrated in a
single package.

DLL

See Dynamic Link Library.

Direct memory access

See DMA mode.

DMA mode

Direct memory access mode. Mode in which data transfers directly between an I/O device and
computer memory. In the most general sense, PCI bus mastering is a DMA mode. More
commonly, however, DMA mode refers to data transfers across the ISA bus, using a special
circuitry on the computer motherboard. See also bus mastering.

Driver

Software that controls a specific hardware device, such as a data acquisitio n board.

Dynamic Link Library (DLL)

A software module in Microsoft W indows containing executable code and data th at can be called
or used by Windows applications or other DLLs. DLL functions and data are loaded and linked
at run time when they are referenced by a Windows application or other DLLs.

1

Expansion slot

A socket in a computer designed to hold expansion boards and connect them to the system bus
(data pathway).

KPCI-PIO24 User’s Manual Glossary B-3

External trigger

An analog or digital hardware event from an external source that starts an operation. See also
internal trigger.

Foreground task

An operation, such as a task that occurs in the single or synchronous mod e, that cannot take place
while another program or routine is

running.

FIFO

First-in/first-out memory buffer. The first data into the buffer is the first data out of the buffer.

GPIB

Abbreviation for General Purpose Interface Bus. It is a standard for parallel interfaces.

IEEE-488

See GPIB.

Input/Output (I/O)

The process of transferring data to and from a computer-controlled system using its
communication channels, operator interface devices, data acquisition devices, or
control interfaces.

Input/output port

1

A channel through which data is trans ferred between an input or output device and the proces sor.

Internal tigger

A software-generated event that starts an operation. See also external trigger.

Interrupt

A signal to the CPU indicating that the board detected the occurrence of a specified condition
or event.

Interrupt level

A specific priority that ensures that high priority interrupts get serviced b e fore low
priority interrupts.

Interrupt-mode operation

Mode in which a data acquisition boar d acquires or generat es samples using an Interrupt Service
Routine (ISR).

Interrupt service routine (ISR)

A software program that handles interrupts.

ISA Bus

Industry Standard Architecture. The 16-bit wide bus architecture used in most MS-DOS and
Windows computers. Sometimes called the AT bus.

1

Map

Any representation of the structure of an ob ject. For example, a memory map describes the layout
of objects in an area of memory, and a symbol map lists the association between symbol names
and memory addresses in a program.

OCX

Abbreviation for OLE Custom Control.

Pass-through operation

See target mode.

PCI

Abbreviation for Peripheral Component Interconnect. It is a standard for a local bus.

B-4 Glossary KPCI-PIO24 User’s Manual

Port

See input/output port.

Port group

For digital I/O emulating the I/O of an 8255 programmable peripher al inter face chip , a gro up o f
three 8 bit ports, commonly labeled PA, PB and PC. Digital I/O that emulates multiple 8255 chips
is typically divided into multiple port groups.

Port I/O call

A software program statement that assigns bit values to an I/O port or retrieves bit values from
an I/O port. Examples include a C/ C++ statement containing an inp or outp function or a Basic
statement containing a peek or poke function.

Register

1

A set of bits of high speed memory within a microprocessor or other electronic device, used to
hold data fo r a particular purpose.

Shielding

A metal enclosure for the circuit being measured or a metal sleeve surrounding wire conductors
(coax or triax cable) to lessen interference, interaction, or current leakage. The shield is
usually grounded.

Target mode

A PCI bus mode in which data from a data acquisition card is transferred indirectly to the
computer memory in the foreground, via the host computer CPU, instead of directly, via Bus
mastering. Sometimes referred to as pass-through operation. See also bus mastering and
foreground task.

1

(verb)

Trap

To intercept an action or event before it occurs, us ually in order to do something else.

TTL

Abbreviation for transistor-transistor-logic. A popular logic circuit family that uses multiple­emitter transistors. A low signal state is defined as a signal 0.8 V and below. A high signal state
is defined as a signal +2.0 V and above.

1

Microsoft Press Computer Dictionary, Third Edition. Refer to “Sources” below.

Sources:

Keithley Instruments, Inc., Catalog and Reference Guide (full line catalog),
glossary, 1998

Microsoft Press Computer Dictionary, Third Edition (ISBN: 1-57231-446-X) by Microsoft
Press. Reproduced by permission of Microsoft Press. All rights reserved.

Index

A

Accessories

relay boards 3-7
terminal boards 3-7

Address

base 4-3
base, assignment 2-4, 4-3
data and control r egisters 2-4, 4-3
definition B - 2

AMCC S5933 bus controller 2-4, 4-2, 4-6
AND gate, in debounce circuit 3-9
API

definition B - 2

Application program

ISA card port I/O call, using with KPCI-PIO
series 4-6
TestPoint or LabVIEW 2-4, 3-2

Application programming interface

definition B-2

Applications for board, examples 2-2

B

Bad board

checking for 5-3, 5-4

Base ad d r ess 4-3

assignment 2-4, 4-3

Board

bad, checking for 5-3, 5-4
handling 3-4
installing 3-4
returning to Keithley 5-20
spare, using in troubleshooting 5-3, 5-4
unwrapping and inspecting 3-4

Boards, multiple

problems, checking for 5-3, 5-4

Bus

control 2-3
definition B-2
memory assignments 4-2

Bus controller , AMCC S5933 2 -4, 4-2, 4-6
Bus mastering 2-4, 4-2

definition B-2

Byte

definition B-2

C

Cable

for loop-back connecti ons 5-11

Common, digital See grounding, signal, I/O
pin assignment
Computer requirements See system requirements
Computer, required 2-2
Connection points, locating and identifying 3-5
Connections

external circuits 3-8
external, checking duri ng troubleshooting 5-3, 5-4
pin assignments, I/O connectors 3-5
to external circuits 3-6, 3-8
using I/O conditioning 3-6, 3-8
using pullups 3-8

Connector

expansion slot, troubleshooting 5-3, 5-4
I/O, mating, type to use 3-5, 3-7, 5-10
loop-back, precautions 5-11

Connectors, I/O

locations 3-6

Contact bounce

definition B-2
elimination, circuit 3-9

Contacts

bounce elimination 3-9
monitoring closure 3-8

Control register

modes 2-2, A-2
CPU, required 2-2
Crosstalk

definition B-2

i-1

Current (continued)

boost, relay 3-9
I/O, rating A-2
output, boost ing 3-9
output, capacity 2-3, A-2

Current, I/O rating 2-3, A-2

D

Darlington

definition B-2

Data

transfer modes 4-5

Delphi

DriverLINX driver for 3-2, 4-2

Digital common See grounding, signal, I/O
pin assignment
Direct I/O See ports, configura tion, direct
Direct Memory Access

definition B-2
Division, PC ports 2-2
DMA mode

definition B-2
Driver

definition B-2

for board See DriverLINX

programming language support See

programming languages

writing your own 4-6
DriverLINX

description 3-2

installing 3-3

PIO Control Panel See PIO control panel
DriverLINX software 3-2
Dynamic Link Library (DLL)

definition B-2

E

Emulation, 8255 chip 2-2, A-2
Expansion Slot

definition B-2
Expansion slot

connector problems, checking for 5-4

requirement 2-2
External tr igger

definition B-3

F

FIFO

definition B-3
Flowchart

problem isolation 5-4
Flowchart, troubleshooting 5-4

Foreground task

definition B-3

G

GPIB

definition B-3

Grounding

signal, I/O pin assignment 3-5
to protect board 3-4, 3-5

H

Help, getting Keithley See technical support
Humidity range, board A-2

I

I/O

8255 PPI chip emulation 2-2
current capability 2-3, A-2
Emulation, chip 2-2

I/O bits

board capacity 2-2, A-2
testing, loop-back test 5-10
testing, out put set tests 5-15

I/O connector

mating, type to use 3-5, 3-7, 5-3, 5-10

I/O, configuring and setting

PIO Control Panel, using, examples See I/O
bit tests

IEEE-488

definition B-3

Input/Output (I/O)

definition B-3

Input/output port

definition B-3
Inspecting board 3-4
Installation

board 3-5

DriverLINX 3-3

external circuits 3-8

TestPoint 3-3
Internal trigger

definition B-3
Interrupt

connector pins 3-5

definition B-3

description 2-3
Interrupt level

definition B-3
Interrupt mode operation

definition B-3
Interrupt service routine

definition B-3

i-2

ISA Bus

definition B-3

L

LabVIEW software 3-3
Logic levels

checking, using DMM or DVM 5-15

Loop-back test 5-10

M

Map

definition B-3
Mapping, memory 4-2
Mating connector, I/O See connector, I/O, mating, type
to use
Memory

control and data register setting 4-6
Mode

control registe r 2-2, A-2
Mult ip le boar ds

problems, checking for 5-3, 5-4

O

OCX

definition B-3
Operating system (OS), required 2-2

OS requirements See operating system, required
Output set tes t

procedure 5-15

P

Passthrough operation 2-3, 4-2
PCI

bus See under bus

definition B-3

resource, checki ng for board as 5-3, 5-4

slot See expansion slot
PIO Control Panel

example 5-12

starting 5-11, 5-16

using, in bit tests 5-11, 5-16
Plug and Play 2-2, 2-3, 4-3
Port group

assignments 4-3, 4-4
Port I/O call

definition B-4
Port I/O See ports, configuration, direct

Portgroup

definition B-4

Ports

configuration, direct 4-2, 4-6
configuration, on power-up/reset 2-3
configuration, PIO Control Panel See PIO control
panel, using, in bit tests

PC, division 2-2

read/ w rit e access 2 -3
width 2-2

Power

5 VDC for external circuits 3-10
board requirements A-2

Power, board

circuits, for external 3-10
Power-up/reset confi guration, ports 2-3
Precautions

base address, differe nt meaning 4-3

board, power OFF when servicing Se e

board handling

board, unwrapping and handling See

board handling

cable for loop-back connections 5-11

installing DriverLINX before board 3-2, 3-4

installing DriverLINX before TestPoint

or L abVIEW 3-3

register level programming 4-2

testing, multiple boards 5-5

using board power 3-10, A-2
Problem isolation

flowchart 5-4

systematic 5-3
Problems See troubleshooting 1-2
Program

checking during tro ubleshooting 2-3, 5-3
Program, application

ISA card port I/O call, using with

KPCI-PIO series 4-6

TestPoint or LabVI EW 3-2
Programming

register level, avoiding 4-2

register level, special situations 4-6
Programming languages

DriverLINX driver for,

compatibility 3-2, 4-2, 4-6

DriverLINX driver fo r, us ing with other than

Visual C/C++, Visual Basic, and Delphi 4-6
Pullup, circuit 3-8

R

Read/wr ite access, ports 2-3
Register

definition B-4

i-3

Register le vel programming

avoiding 4-2
specia l s i tu ations 4 - 6

Registers

AMCC S5933 2-3
data and control, addresses 2-3, 4-2, 4-3
data and control, assignments 2-3, 4-2, 4-4
programming See register level progra mming
setting 4-6

Relay

circuit, output 3-9

drive current, boosting 3-9
Repairs, board 5-21
Returning board 5-21
Returning board to Keithley 5-20

Tests

I/O bit, in problem isolation scheme 5-3, 5-4
I/O bit, procedures 5-10
troubleshooting 5-3

Trap

definition B-4

Troubleshooting

first basic checks 5-2
flowchart 5-4
symptoms and possible causes 5-2

TTL

definition B-4

U

Unwrapping board 3-4

S

Safety Precautions 3
Shielding

definition B-4
Signal

conditioning, input and output 3-8

parameters, board A-2
Size, board A-2
Software

descriptions 3-2

included with board 2-4, 3-2

installation, DriverLINX 3-2, 3 -3

ISA card port I/O call, using with

KPCI-PIO series 4-6

options 3-2

options synopsis 2-3
Softw a r e installa tion

TestPoint 3 -3
Symptoms and possib le causes 5-2
System requirements 2-2
Systematic problem isolation 5-3

T

Target mode 2-4, 4-2

definition B-4
Technical support 5-20

Temperature range, board A-2
Test

loop-back 5-10

output set 5-15
TestPoint

installing 3-3
TestPoint softwa r e 3-3

V

Visual Basic

DriverLINX driver for 3-2, 4-2

Visual C++

DriverLINX driver for 4-2

Visual C/C++

DriverLINX driver for 3-2

W

Weight, board A-2
Windows version, required 2-2
Wiring

external circuit See under connections

loop-back connector See under connections
Wrist strap, to protect board See grounding to
protect board
Write/read port configuration See PIO control panel,

using in bit tests

i-4

Specifications are subject to change without notice.
All Keithley trademarks and trade names are the property of Keithley Instruments, Inc.

All other trademarks and trade names are the property of their respective companies.

Keithley Instruments, Inc. 28775 Aurora Road • Cleveland, Ohio 44139 • 440-248-0400 • Fax: [phone]

1-888-KEITHLEY (534-8453) • www.keithley.com

Sales Offices: BELGIUM:

Bergensesteenweg 709 • B-1600 Sint-Pieters-Leeuw • 02-363 00 40 • Fax: [phone]

CHINA:

Yuan Chen Xin Building, Room 705 • 12 Yumin Road, Dewai, Madian • Beijing 100029 • 8610-8225-1886 • Fax: [phone]

FINLAND: Tietäjäntie 2 • 02130 Espoo • Phone: [phone] • Fax: [phone]
FRANCE: 3, allée des Garays • 91127 Palaiseau Cédex • 01-64 53 20 20 • Fax: [phone]
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GREAT BRITAIN: Unit 2 Commerce Park, Brunel Road • Theale • Berkshire RG7 4AB • 0118 929 7500 • Fax: [phone]
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© Copyright 2002 Keithley Instruments, Inc.

Printed in the U.S.A.

9/02