Tektronix Keithley WAV1 Waveform Generator Module Rev. A User manual

WAVI

Waveform Generator Module

Introduction

The WAVl Waveform Generator Module provides one

channel of sine, square or triangle waveform output. The
module is comparable to a standard function generator in
which the adjustment knobs and switches have been re­placed by programmable D/A converters and software
switches. The main WAVl functions of frequency, duty
cycle <symmetry), amplitude and DC offset are program­mable to 1 part in 4096 ( 12-bit resolution). Output voltage
range is switch-selectable at 1V or 1OV.

The WAVl’s output waveform is available on a standard
BNC connector. The main output as well as T&level

trigger outputs are also available from an on-board screw
terminal block.

Available frequencies cover O.lHz to 2OOKHz in six dec­ade-weighted ranges. Accuracy is typically 5% of setting

(10% on Wz and 20Hz ranges). For optimum accuracy, the
WAVl should be operated in the upper 90% of any given
frequency range. Amplitude accuracy is 5% (to 20V P-I?
into 500 ohms). Peak output current is 2OmA. The WAVl

duty cycle is programmable from 5% to 95%. Sine wave

distortion is typically less than 3%.

DC output and offset function may be used to bias output
waveforms. Alternately, the WAVl may be used as a
general-purpose bipolar bias source of flOV at 2OmA. The
WAVl can also be used to pace the conversion rate of the
AMMlA or AMM.2 modules at rates other than those
provided by the AMM module crystal oscillator.

Hardware Compatibility

TheWAVlcanbeoperatedinslots2through10ofthe500A

or 5OOP mainframe, or in the option slot of the Model 570
or 575. If the WAVl will be used to control an AMM
module via its trigger input, the AMM module must have
PAL revision D or later. If an AMMlA or AMM2 is not
resident in the system, resistor R53 must be installed on the
WAVl to supply a system reference voltage.

Software Compatibility

All WAVl functions can be accessed by writing control
information directly to the WAVl’s slot-dependent Com­mand A (CMDA) and Command B (CMDB) registers.
These functions include frequency, duty cycle, range,

function, amplitude, offset, synchronous stop enable/dis­able, and global strobe enable/disable.

The WAVl includes a selectable synchronous stop feature.

Synchronous stop allows the waveform output to com-

plete the current output cycle, even though the WAVl

output may have been disabled before this point. Alter-

nately, the WAVl output can be set up to return to 0

immediately when the output is disabled. A waveform

always starts at the lowest amplitude point of the triangle
and sine waves.

Document Number: 501-921-01 Rev. A / 7-90
CopyrightQ 1990 KeithIey Instruments, Inc. Cleveland, OH 44139 [phone]

Control can also be exercised through any high- or low­level language which permits writes to memory addresses

(e.g. BASIC POKES). The WAVl registers are write-only.

See the WAVl register map information later in this manual.

If you are using third-party software, be certain that the
software is compatible with the WAVl.

WAVI-1

WAVl

Waveform Generator Module

Figure 1. WAVI Module

Jumper Wl

Optional Resistor R53

Mounting Bracket

Specifications

Programmable Features:

Functions: waveform, frequency, amplitude, duty cycle,
DC offset, haver waveforms.

Waveforms: sine, square, triangle, pulse, or DC output.
Frequency: O.lHz to 2OOkHz in six overlapping ranges.

Frequency ranges: 2,20,200,2k, 2Ok, 200k Hz

Frequency resolution: 12 bits (1 part in 4096)

Frequency accuracy: (upper 90% of range) f5% of setting,
except +lO% on 2kHz and 2OkHz ranges.

Amplitude ranges: IV, IOV peak, switch selectable

Amplitude resolution: 12 bits (1 part in 4096)

,

Amplitude accuracy: rt5% of setting to 5OkHz’

Offset ranges: +lV, +lOV (tied to amplitude ranges)

Offset resolution: 13 bits (12 data + 1 polarity)

Offset accuracy: .(5% of setting + 1OmV)’

Maximum output: rtlOV (2OV p-p) into 5OOQ 2OmA

Waveform symmetry: 5% to 95% (duty cycle) to 1OOkHz

Sine wave distortion: 1st harmonic down 35dB

Square wave rise time: lp

Triangle linearity: ~3% error

* Total error is the sum of amplitude and offset errors. For DC-only
operation, set waveform amplitude to 0 and use offset error, only.

WAVl-2

WAVl

Waveform Generator Module

Sync output: high and low true, TTL level, ps pulse width.
Sync pulse occurs at minima of sine and triangle waves, or
at falling edge of square wave.

General:

Operating temperature: 0°C to 7O”C, 80% RH non-con-

densing down to 35°C

Storage temperature: -25°C to 80°C

Power-up condition: OV output

Rower consumption: 65mA for 5V dig&d, 85rd for +15V
analog

Signal connections: BNC for main output, quick-discon­nect screw terminals for main and sync output.

Accessories: 2 ft. BNC to BNC cable, Model 7051-2,3 ft.
BNC to BNC cable, Model 7054-3

--- -.

_--_

ing the cover retaining screws located in the upper corners
of the rear panel. Slide the cover back about one inch and
then lift it off. Insert the module in the desired slot with the
component side facing the system power supply. Replace

the system cover.

For a Model 570, install the module in the option slot with
the component side of the board facing upward. Close and
secure the cover.

For a Model 575, first attach the supplied right-angle
bracket to the module (see Figure 2). Plug the module into
the option dot with the components facing upward, and
secure the bracket to the rear panel of the system. Close and
secure the cover.

Connections

The output waveform is available on a standard BNC
connector or from outputs on a screw terminal block.

Installation

The WAVl can be placed in any slot in the system. If the
trigger output is to be used to control the operation of an

ATiBaI,,TDPI --2--l-

I+IVLIVL ~1 I AU I ~~uuure, ule vv n v 1 muss ue placea aajacenr
to that module, in the next higher-numbered slot.

Turn off power to the data acquisition system
before you insert or remove any module. To
minimize the possibility of EM1 radiation,
always operate the data acquisition system
with the cover in place and properly secured.

Make sure you have discharged any static
charges on your body before handling the
module. You can do this most easily by simply
touching the chassis of a computer or data
acquisition mainframe which is plugged into
a grounded, 3-wire outlet. Avoid touching
components or the card edge connector of the
module.

L~^T*fA~fl----rL--l---=-=~ ----. I

CAUTION

CAUTION

A quick-disconnect terminal block can be removed from
the module to facilitate making connections. PuB the block
straight off the board with a firm, even pressure. Do not pry
the terminals with a screwdriver or sharp object, or you

-_- --- J-.-- - - .I- -? ~~ . . 1~

may aamage me cucun ooara.

Each individual terminal consists of a small metal block
with a wire receptacle containing a metal compression tab.

To make connections to a terminal block, first strip 3/16 of

insulation from the end of the wire which you want to

attach. Loosen the desired terminal screw on the block and
insert the bare end of the wire into the corresponding
receptacle. Tighten the screw securely to compress the tab
against the wire.

After you have attached all the desired signal wires to a
terminal block, replace the block by lining it up with the
mating pins on the module and pressing it back into place.

1

Table 1. WAVl User-Configured Components

For a compatible multi-slot data acquisition system (Model
5OOA, 5OOl?), remove the top cover of the system by loosen-

Cl

WAVI-3

WAVl

Waveform Generator Module

Command Locations

The WAVl is controlled by writing to the Command A
(CMDA) and Command B (CMDB) addresses for the slot in
which the module is mounted. Programmable parameters
include function, range, frequency/duty cycle, amplitude,
and offset. Refer to your data acquisition system hardware
manual for the addresses associated with the slot where the
module is mounted.

Table 2. Slot-Dependent Memory Locations (hex)

1 rigure 3. WAVI Connecfions

NOTE

To minimize the possibility of EMI radiation,
use shielded cable for the WAVl output.

Output Limitations

There are certain restrictions as to the output capability of
the WAVL The output load should be greater than 5OOQ
with less than 100pF of shunt capacitance. The load resis­tance can be reduced if the peak output current does not

exceed 2OmA (i.e. 1V into 5052).

Jumper WI is provided to enable the user to add a series
resistance to match the characteristic impedance of the
WAVl’s output to that of the cable and load. The addition

of a series resistor can also provide a higher degree of

amplifier output protection. However, the resistance will
increase source impedance and can thus decrease output
amplitude. If the output load capacitance exceeds 1OOpF

(50 ohm coax adds BOpF/foot) Wl should be replaced with

a minimum 1OOQ resistor to prevent output amplifier

stability problems or spurious oscillations.

500,570,575
I I

SLOT

1* xxx80
2

3” xxx84 xxx85
4
5 xxx88 xxx89
6
7 xxx8C xxx8D
8”*
9 xxx90 xxx91

10 xxx92 xxx93

*=Model575 Physical (Option) Slots
**=Model570 Option Slot
xxx=First three digits of IBIN address, e.g. “CFF’

CMDA CMDB

xxx81

xxx82 xxx83

xxx86 xxx87

xxx8A xxx8B

xxx8E xxx8F

GPIB

I I

CMDA CMDB

0 1

2 3
4 5
6 7
8 9

A

C

E F
10 11

12 13

B

D

Table 3. WAVl Command Locations and Functions

Read Functions:

COMMAND

CMDA
CMDB

Write Functions:

FUNCTION
None
None

WAVl-4

COMMAND

CMDA

CMDB
xxx9D

FUNCTION
Select Control Register
Offset Polarity
Data high nibble
Data low byte
Global Strobe

WAVI

Waveform Generator Module

8038 -_I___
Waveform
Generator

2/

AU-L

Waveform

Select

I----

CMDNCMDB

(WRITE)

To ND ‘Module

L

e Data Bus

‘igure 4. WAVI Block Diagram and Register Funcfions

- Control Line
Analog Pathway

WAVl-5

WAVl
Waveform Generator Module

Control I Data

SET FUNCTION :

CMDA

I

D7 D6 D5 C

0 0 0

Register
Select

0

SET RANGE :

CMDA

I

D7 D6 D5 I

0 0 1

Register

Select
1

14 I D3 D2 Dl DO

I I LI-’

L

I

I D2 Di DO

-c F2:: E:i

Data

CMDB (not used)

I

I

D7 D6 D5 D4 D3 D2 Dl Do

Function Select : 00 - DC
Function Select : 01 - Sine
Function Select :
Function Select : 11 - Square
output : 0 - Disable, 1 - Enable
Sync Stop : 0 - Disable, 1 - Enable
Not used

I

D7 D6 I

Range Select
Range Select
Range Select
Range Select : 101 -2Hz
Range Select :

Range Select : 111 -NotUsed
Global Strobe : 0 - Disable, 1 - Enable
Not used

10 - Triangle

CMDB (not used)

x

i D4 D3 D2 Dl DO

- 200 kHz

000

- 20 kHz

001

- 2k Hz

010

-200 Hz

011

-20 Hz

100
110-Notused

I

I

Register Select 2 & 3 - NOT USED

CMDA CMDB (not used)

I

D7 D6 D5

0 1
0 1

WAVZ Block Diagram and Register Funcfions (Cont.)

WAV1-6

0 Register
1 Register

D4 D3 D2 Di DO D7 D6 D5 D4 D3 D2 Dl DO

Select 2 is not
Select 3 is not

I I I

used
used

WAVI

Waveform Generafor Module

Control / Data

SET AMPLITUDE :

CMDA

I

07 D6 D5 D4 D3 D2 Dl DO

Register
Select

’ O O

4

SET OFFSET :

CMDA

I

D7 D6 D5

D4 D3 D2 Dl DO

Data

CMDB

I I

D7 D6 D5 D4 D3 D2 Di DO

CMDB

I I I

D7 D6 D5 D4 D3 D2 Di DO

I

SET OFFSET :

CMDA

I

D7 D6 D5

Regmter
Select

’ -’ O

6

D4 D3 D2 Di DO

WAVZ Block Diagram and Register Functions (Cont.)

CMDB

I I I

D7 D6 D5 D4 D3 02 Dl DO

WAVI-7

WAVl

Waveform Generator Module

Control / Data

SET RAMP-DOWN :

CMDA

I

D7 D6 D5

1 0 0

Register

Select

7

NOTES :

I I I

D4 D3 D2 Dl DO

IV I

D7 D6 D5 D4 D3 D2 Dl DO

Data

CMDB

Ramp-Down LSB
Ramp-Down MSN
Not used

1. The upper 3 bits of the CMDA register select registers within the WAVI .

2. The DAC’s require 12 bits of data, and thus, 2 successive 8-bit writes. The first write must be to
CMDA (MSB), and the second to CMDB (LSB). The CMDA write selects the proper DAC register
pair to be updated. After the CMDB write, the last register select remains in effect until the next
CMDA write operation selects a different register. This allows for faster successive updates of the
DAC LSB last written.

3. The MSB contains 3 bits of register select information and 4 bits of actual DAC data (Most Sig­nificant Nibble, or MSN). Data bit D4 is used only for polarity selection as part of offset program­ming. When D4 is not used, it may be assigned a value of 0 or 1 with the same results. The 3
register select bits, bit D4, and DAC MSN data must be combined before writing to CMDA of the
WAVl . Frequency, amplitude and DC offset functions are controlled by four 1 e-bit DAC’s.

4. The WAVI function, range, output enable/disable, synchronized stop enable/disable and global
strobe enable are controlled by CMDA-only writes. The subsequent CMDB write will have no effect.
CMDAICMDB reads are not supported by the WAVl .

1 NAVl Block Diaqam and Register Functions (Cont.)

WAVI-8

WAVI

Wavefom Generafor Module

Using the WAVI

Typically, the WAVl will be used in conjunction with other
modules in a Keithley data acquisition system. Once pro­grammed, the WAVl will continue to output a waveform
with no additional intervention from the computer. The
full facilities of the computer can thus be used to control
analog and digital I/O. Alternately, the WAVl can be
programmed repetitively within a program to change
frequency, amplitude, waveform type, etc. This permits
complex waveforms to be generated and reproduced each
time the program is run.

To program the WAVI, note the slot in which the module
resides, and write to the corresponding CMDA and CMDB
registers (see Table 4). A complete configuration of the
WAVl requires 10 writes. For subsequent minor changes
such as a new frequency, duty, or amplitude, one or two
writes will generally be sufficient.

In each case, the appropriate bit values DO-D7 must be
chosen and assembled into byte values which are written
to the CMDA and CMDB slot-dependent addresses. The
function of each write is further defined by the WAVl
register select bits (bits 7,6, and 5) written to CMDA.

Before writing any data to the WAVl, set the amplitude
switch on the connector-end of the module for 1V or 1OV
full-scale. The maximum available offset of 1V or 1OV is
also controlled by this switch, and will be the same as the
amplitude.

By using the following sequence of writes, you will be able
to set up the WAVl with the desired operating parameters,
and then switch on the output. Depending on the program­ming language, these operations can be performed in a
subroutine or subprogram which can be executed each
time a change in the WAVl’s output is desired.

1. Select desired frequency (freq), duty cycle (duty), am­plitude (amp), offset (offs), and sync stop mode (ss).
Assign necessary values for function select, range se­lect, sync stop, and enable bits.

rs = range select (0 for 2OOkHz,l for 2OkHz,2 for 2kHz,
3 for 2OOHz, 4 for 2OHz,5 for 2H.z).

mg = range full-scale in Hz (200000,20000,2000,200,20,
or 2).

duty = desired duty cycle in percent (5-95).

amp = desired amplitude in volts (O-10, or 0-lV, de­pending on setting of the range switch).

offs = desired offset and polarity in volts (-10 to +lO).

ss = sync stop bit (1 for synchronous waveform stop, or
0 for immediate stop).

en = output enable. Will normally be set to 1 to enable
output when the last write is made to CMDA. 0 disables
output.

2. Calculate high byte and low byte for frequency DAC
up/down ramps according to selected range, desired
frequency, and duty cycle.

’ Calculate-ramps:

ramp-up = INT((freq * 2*11- 1) / (rng * (1 - (duty /
1om

ramp-dn = lNT((freq * 2*11- 1) / (mg * (duty / 100)))

’ Test if either ramp > 4095 and recalculate if necessary

IF ramp-up > 4095 OR ramp-dn > 4095 THEN

rng=rng”lO
13% = rs% - 1
GOT0 “calculate_ramps” (beginning of step 2)
and recalculate...

’ Calculate high/low byte values for frequency DACs

ruh = ramp-up \ 256
ml= ramp-up MOD 256

rdh = ramp-dn \ 256
rdl = ramp-dn MOD 256

’ Integer division

‘ Integer division

fs = function select (0 for DC, 1 for sine, 2 for triangle, 3
for square wave.

freq = desired frequency in Hz (0.1 - 200000).

3. Calculate high byte and low byte for amplitude DAC.

bits = (amplitude / F.S. output) * 4095
ah = bits \ 256
al = bits MOD 256

WAVl-9

WAVl

Waveform Generator Module

(F.S. output = 1 or 10, depending on range switch
position.)

4. Calculate high byte and low byte for offset DAC .

bits = tabs. value (offs / F.S. offset)) * 4095
oh=bits\256
01 = bits MOD 256
op = offset polarity (0 for pos, 1 for neg)

(F.S. offset = 1 or 10, depending on range switch posi­tion.)

5. Do the POKES

’ POKE high and low bytes to the ramp-down DACs.
’ Register select = 7

POKE cmda, (7 * 32) + rdh
POKE cmdb, rdl

’ POKE high and low bytes to the ramp-up DACs
’ Register select = 6

POKE cmda, (6 * 32) + rub
POKE cmdb, rul

’ POKE high and low bytes to the offset DACs
’ Register select = 5

POKE cmda, (5 * 32) + (op * 16) + oh
POKE cmdb, 01

’ POKE high and low bytes to the amplitude DACs
’ Register select = 4

Frequency and Duty Cycle

The frequency and duty cycle are simultaneously con­trolled by the values loaded into the frequency ramp-up
and ramp-down DACs for one cycle. The up and down
terminology relates best to the triangle waveform upon
which the sine wave can be superimposed. The duty cycle
parameter can be understood more easily as the positive
portion of a square wave in relation to one complete cycle.
See Figure 5 for waveform relationships. For optimum
accuracy, select the lowest range which accommodates the
desired frequency.

Full-scale for frequency range is obtained by programming

both the “up” and “down” DAC’s with 4095 (FFF hex).

Programming both DACs to the same value will result in
a 50% duty cycle. Some typical frequency DAC values for

50% duty cycle are shown in Table 4.

Table 4. DAC Values and Programming

Equivalents

% of

F.S. Decimal Hex

4095

100

3276

80

2457

60

1638

40

819

20

0

0

Note: For 50% duty cycle, program “w” and “DN” DAC’r
same values.

&HFFF
&HCCC
c&H999
&H666
&H333
&HO00

&HCF
&HCC
&HC9
&HC6
&HC3
&HCO

&HFF
M-ICC
&H99
@I66
c&H33
&HO0

&HEF
&HEC
&HE9
&HE6
&HE3
&HE0

DAC
CMDB

&HFF
&HCC
&H99
&H66
&H33
&HO0

1

POKE cmda, (4 * 32) + ah
POKE cmdb, al

’ POKE range and global strobe values
’ Register select = 1

l?OKEcmda,(1*32)+gs*8+rs

’ POKE sync stop, output enable, and function
’ Register select = 0

POKE cmda, (0 * 32) + (ss * 8) + (en * 4) + fs

The following discussions cover a few of the operating
parameters where necessary details are not immediately
obvious.

WAVl-10

The duty cycle is controlled by the ratio of values written
to the frequency up and frequency down DACs. kogram­ming both DACs to the same value will result in a 50% duty
cycle since up and down times will be equal.

Note that as a frequency increases toward 100% full-scale,
the range of permissible duty cycles narrows toward 50%.
The duty cycles available for a given frequency and range
can be calculated as follows:

low-duty (%) = 100 * ( freq/rng > / 2
high-duty (%) = 100 - low-duty

At some duty cycles and frequencies, the ramp calcula­tions will produce a ramp-up or ramp-down value greater