AMMI F
Master Analog Measurement Module
TheAMMlFAnaIogMeasurementModuIecombinesthree
important Series 500 functions into a single module. First,
the AMMlF functions as a standard analog input module,
and wiII accept up to 16 single-ended or eight differential
analog input signals. It contains signal conditioning and
switching circuitry for these channels. Second, the AMMlF
selects and conditions analog signals from other analog
input models in a Series 500. Last the AMMlF serves as a
12-bit A/D converter for its own analog input channels, as
well as any other analog signals which have been processed by the global select/conditioning circuitry. After
analog conditioning, signals are routed to the A/D converter section of the module for the analog-to-digital conversion process.
Input signals are applied to the AMMlF’s analog input
channels through on-card quick-connect screw terminals.
The AMMlF has a total of 16 local single-ended, or eight
differential inputs. The input configuration is controlled
through software, rather than with hardware switches.
These analog input channels can be conditioned with
programmable local gains of either xl or x10.
CAUTION
Always turn off the system power before installing or removing modules. To minimize
the possibility of EMI radiation, always operate
the system with the top cover in place and
properly secured.
The AMMlF is designed to be used only in slot 1 of the 500series system baseboard. To install the module, first remove the baseboard top cover and install the module in
slot 1 with the component side facing the power supply.
High-speed Acquisition Mode with AMMl F
and ANINQ (SOFT500 and QUICK500)
The ANINQ command can operate the AMMlF module in
high-speed “auto-acquire” mode at an aggregated
throughput rate of up to 1OOkHz. Auto-acquire applies to
single or multiple channels. For multiple channels, the perchannel scan rate equals 1OOkHz divided by the number of
channels.
Global conditioning consists of a high-speed softwarecontroIIed gain amplifier with programmable xl, x2, x5
and x10 gain values. AlI analog inputs connected to the
Series
500
pass through the global circuitry, whether the
signals originate on the AMMlF or some other analog
input module. Therefore, these gain values can be applied
to any analog input in the system.
For A/D conversion, the AMMlF uses a 12-bit successive
approximation converter. A maximum conversion time of
only 1Oi.t~~ allows sampling rates as high as 1OOkHz. To
maximize resolution, the AMMlF has 0-1OV and +lOV
A/D converter ranges which are software selectable.
Document Number: 501-924-01 Rev. A
The analog input module AIM2 can also provide up to
1OOkH.z throughput when used in a system containing an
AMMlE Other modules wiII give inaccurate results due to
slower settling times.
To operate the AMMlF in auto-acquire mode, you must
satisfy the following requirements:
1. The analog input channels sampled by ANINQ may be
on an AMMlF or AIM2.
2. Ah the channels sampled by the specific ANINQ command must be on one module.
3. The AMMlF’s input filter must be set to 2OOkHz.
AMMlF/l
AMMlF
Master Analog Measurement Mode
If any of these conditions cannot be met, the speed of the
ANINQ command will revert to the speed of an ANIN
command. Under these circumstances, it is better to use
ANIN in order to take advantage of foreground/background operating mode.
NOTE
TheANlNQcommandinSoft5OOandQuick500
has been optimized for auto-acquire (1OOkHz)
operation with the AMMlF. If you attempt
auto-acquiremodewithBASIC’sPEEK/POKE,
or the memory READ/WRlTE commands of
other languages, you may receive incorrect data.
If you do not use Soft500 or Quick500, Keithley
suggests that you run the AMMlF only in
“regular acquisition mode”. This mode is described under the heading “SELECT ACQLBSITION MODE” later in this manual.
Self-calibrating During “CALL INIT”(SOFT500
and QUCK500)
The AMMlF module performs a self-calibration each time
a CALL INlT is issued. Soft500 executes a CALL INIT each
time it is run in the non-resident mode, or just once when
it is loaded into memory in resident mode. Quick500
executes a CALL INIT each time it is loaded under the
QuickBASIC environment or with the “QRUN” option, or
just once when it is made resident with the “QLOAD”
option. Therefore, you need not issue a separate CALL
INlT specifically to calibrate the AMMlF.
single-ended local input configurations. These local input
signals are applied to screw terminals located toward the
rear portion of the AMMlF. Single-ended and differential
inputs use the same screw terminals.
The channel numbers are shown in Figure 2, which also
shows typical connections for channels 0 through 7 in
differential mode. For differential mode, connect the high
(+> side of an input signal to the (+> terminal, and the low
f-1 side of the signal to the corresponding (-> terminal.
When the AMMlF is configured for single-ended input,
connect the high (+> side of the input signal to one of the
terminals 0 through 15, and the low (-) side to either of the
two input low (-> terminals shown for single-ended inputs.
In Figure 2, the numbers listed in parentheses above the
lower connector are the single-ended local channels 9
through 15.
CAUTION
The AMMlF inputs
ended mode, one side of the input is connected to power line ground. Any signal connected to the AMMlF must also be referenced
to power line ground, or module or system
damage may occur. Also not that inaccuracies
on other channels may result. When used in
differential mode, the AMMlF local inputs
must both be within HOV of module ground
for proper operation. If either signal exceeds
k3OV module damage may result.
are non-isolated.
Insingle-
Soft500 and Quick500 will expect an AMMlF in the system
if the configuration file (CONFiG.TBL) shows an AMMlF
in slot 1. If the software cannot complete the calibration, it
will issue an error message such as “Unable to calibrate
A/D module”. If this occurs, check that:
1. The Series 500 is turned on.
2. The cable between Series 500 and IBIN interface is connected.
3. An AMMlF is mounted in slot 1 of the Series 500.
Connections and Operation
Signal Connection
The AMMlF can be programmed for either differential or
AMMlF/2
In many situations, shielded cable may be required to
minimize EMI radiation, or to keep noise to a minimum. If
shielded cable is used, connect the shield to ground only,
and do not use the shield as a signal-carrying lead. Usually,
a module ground terminal should be used, but in some
cases better results may be obtained by using one of the
baseboard ground posts. Use the configuration that results
in the lowest noise.
For shielding to be effective, the shield must contain both
high and low signal wires, and must not carry any other
signals. If a number of AMMlF signal input lines are
shielded, all shields should be connected to the same
ground terminal.
AMMlF
Master Analog Measurement Mode
Figure 2. Ah&W F Component Bayou t
Signal ground
-u-•
‘ilrrrrrlrmooooooooo
ICH7 CHOl
I
Shield ground
.
ID
:
: .
:
:
:
:
.
i
Single-ended
-IN (Input Low)
Figure 2. TypicaZ Difjerential Connection (Channel 0 Shown)
Module
GND
- 2 Measured
+ Voltage
Shield
(Optional)
I
AMMlF/3
AMMlF
Master Analog Measurement Mode
Signal Conditioning
Figure 3 shows a simplified block diagram of the AMMlF.
The module is divided into six general sections: a local
multiplexer, a local programmable gain amplifier, a global
multiplexer, a global programmable gain amplifier, a
programmable low-pass filter, and a 12-bit A/D converter.
Local input signals from channels 0 to 15 are applied to the
local multiplexer for selection. At any given time, only one
channel will be selected, as determined by the SELECT
CHANNEL command (covered later in this section). The
signal from the selected channel is then routed through a
local programmable gain amplifier to the global multiplexer for further signal selection and conditioning.
The global multiplexer selects a single signal from among
the 10 slots in the system. In this manner, signals from any
of the 10 slots can be selected by software. The global
multiplexer is controlled by the SELECT SLOT command,
discussed later in this section.
After the signal is selected, the Global PGA applies software-selectable gains of xl, x2, x5, or x10. The signal finally
passes through a one-pole filter with software selectable -
3dB frequencies of either 2OOkHz or 2kHz. When this
signal conditioning process is complete, thesignalis routed
to the 12-bit A/D converter for digitization. After the
conversion process, digital data representing the applied
signal travels via the baseboard and interface card to the
host computer.
Input Filtering
Noise introduced into the input signal can corrupt the
accuracy of the measurement. Such noise will usually be
seen as an unsteady reading, or, in some cases, as a constant
offset. In the former case, the effects of noise will usually be
quite obvious, but may not be noticeable in the steady-state
offset situation.
Frequently, noise is introduced into the signal from 50 to
60Hz power sources. In many cases, noise can be attenuated by shielding or relocating the input signal lines, as
discussed earlier. It may also be possible to reject unwanted
60Hz noise by using the AMMlF in differential mode.
Since the 60H.z noise may also be present on the low side of
the signal, the differential amplifier will reject the common
signal. In more difficult situations, however, it may be
necessary to filter the input signal to achieve the necessary
noise reduction.
Programmable
Channel
Selection
Figure 3. AMMlF Signal Conditioning
AMMlF/4
-
’ - Programmable
Filter
2ookHz OR
PkHZ)
AMMIF
Master Analog Measurement Mode
When noise is a problem, a single-pole low-pass filter like
the one shown in Figure 4 can be connected between the
input signal and the corresponding AMMlF channel. Note
that the filter is made up of a single capacitor and resistor
with the capacitor connected between the AMMlF channel
input terminal and the module ground terminal. The resistor is then placed in series with the high input signal lead.
A common reference point for a simple filter like the one in
Figure 4 is the -3dB or half-power point, which is given as
follows:
f-=
1/(2zRC)
where f is in Hz, C is in farads, R is in ohms. Above this
frequency, filter response will roll off (decrease) at a rate of
-20dB per decade. Thus, each time the frequency increases
by a factor of 10, filter output voltage decreases by a factor
of 10 (-20dB).
To determine the relative RC values, the above equations
can be rearranged to solve for either R or C. If we wish to
choose a nominal capacitor value and then solve for the
resistance, we have:
R = 1/(2nCF~,)
Choosing a nominal value of 2l.tF for C, the necessary
resistance is:
R=1/(2nx(2x1O-?x6I-Iz)
R = 13.263k
The resulting response times with these R and C values
would be:
t(l%) = 4.6RC = 122ms
t(O.l%) = 6.9RC = 183ms
t(O.Ol%> = 9.2RC = 244ms
Note that there are a number of RC values that can be used
in a given situation. To
minimize the effects of the series
resistance, however, it is recommended that the value of R
be kept under 2OkQ.
Figure 4. Input Filtering
Although such filtering can quiet down a noisy signal,
there is a trade-off in the form of slower response. This
response time may be important in the case of a rapidly
changing input signal. For the filter in Figure 4, the response time to 1% of final value is 4.6RC, while the response times to 0.1% and 0.01% of final value are 6.9RC and
9.2RC, respectively.
As an example, assume that 10 counts of 6OHz noise is
present in the input signal. To reduce the noise to one
count, an attenuation factor of 10 (-20dB) at 6OHz will be
necessary. Thus, the filter should have a -3dB point of 6Hz.
Current-to-Voltage Conversion
AMMlF local inputs are designed to accept voltages in the
range of HOV. Thus, the AMMlFcan be directly connected
to many signal sources. Some transducers and instrumentation, however, provide current outputs that must be
converted into voltages in order to be measured through
an AMMlF input channel.
When connecting current inputs to the AMMlF, a resistor
should be installed across the input to make the necessary
current-to-voltage conversion. J4, J5, and J6 provide locations for installing these resistors on the Ah4MlF. Refer to
the circuit schematic and board layout diagrams for header
information.
The value of the resistor can be determined from Ohms
law as follows:
R=E/I
AMMlF/5
AMMZF
Master Analog Measurement Mode
Where R is the resistance in ohms, E is the maximum
desired voltage in volts (usually the upper range limit of
the A/D converter), and I is the maximum anticipated
current in amps.
As a example, assume the A/D converter is zero to +lOV
and that the expected current lies in the range of four to
40mA. The required resistance is:
R = lo/O.04
R=250
Thus, a 25OQ resistor should be installed across the input of
the channel in question (note that a 25Ofi value is required
when using Soft500 engineering units conversion). Since
current measurement accuracy is directly related to the
accuracy of the resistor, use the smallest tolerance resistor
available (typically 0.1%). Suitable 250&? precision resistors
can be purchased from Dale Resistors (P/N RN55E25OOB),
or from Keithley (P/N 500~RES-250).
Analog-to-Digital Converter Timing
When the AMMlF is in 1OOkHz auto acquire mode, the
trigger source can be set to either external or internal by the
J3 jumper. Place the jumper on pins 2 and 3 for internal
triggering. When set for internal triggering, the AMM2
continuously converts analog signals as described below
in the SET. ACQUISITION MODE command discussion.
When the J3 jumper is removed, a TTL-level signal can be
attached to pin 2 of the jrm-tper header with pin 3 used as a
ground. A low level applied to pin 2 will enable the
continuous conversion process, a high level applied to pin
2 will suspend the continuous conversion process. Place
the jumper on pins 1 and 2 to allow use of the TRGl
module. Models 575 and 576 have built-in TRGl modules,
or a TRGl may be placed in slot 2 of a 500A. In any case, the
application program must synchronize itself to the conversion process by polling the conversion status as explained
in the SELECT ACQUISITION MODE command discussion.
The pin configuration of the jumper header is as follows:
pin1 Path through backplane to TRGl module
pin2
pin 3 OV (ground)
trigger input with pull-up resistor to +5V
When programming high-speed sampling sequences,
certain timing constraints concerning the A/D conversion
cycle should be observed. Depending on the AMMlFs
acquire mode, the scenario for receiving converted values
from the A/D is very different. Refer to the discussion of
the acquire modes below for specific instruction on how to
process analog signals.
To increase system throughput, data latches have been
provided on the AMMlF, making data from the last conversion available while the converter is busy processing
another reading. The data is refreshed (updated) every
time a conversion has been completed.
External Trigger Operation
The AMMlF has the capability of triggering an acquisition
from an external ‘ITL-level source or from a TRGl module.
The jumper on the AMMlF fJ3) dictates the triggering
source. The external trigger can only be used in lOOkl!Iz
auto acquire mode which is explained below in the SET
ACQUISHION MODE command discussion.
The J3 jumper should be across pins 2 and 3 for internal
trigger operation. The jumper should be removed and the
external trigger source should be connected to pin 2 for
external rigger operation. The jumper should be across
pins 1 and 2 for operation with a TRGl module.
Commands
Table 1 summarizes the commands used with the AMMlF.
Note that several commands share the CMDA and CMDB
locations. Some commands use only selected bits in the
command byte, others are differentiated by whether a read
or write operation is performed.
The “xxx” in the address column signifies the three hexa-
decimal digits that make up the base hardware address
which is either switch selected or programmed on the
interface card. The suggested address is &HCFF80, so
h/,&./ = “&HCFF”.
AMMlF/6
Table 1. Commands Used with the AMMlF
AMMIF
Masfer Analog Measurement Mode
Command
SELECT CHANNEL
SELECT LOCAL CHANNEL MODE
SELECT LOCAL GAIN
SELECT ACQUJSITION MODE
SELECT FILTER
SELECT SLOT
SELECT CMDA READ MODE
SELECT RANGE
SELECT GLOBAL GAIN
RESET AND RECAL
A/D LOW DATA*
A/D STATUS*
A/D HIGH DATA
A/D START
EOC (end-of-conversion) STATUS
The information read from CMDA is selected by the SELECT CMDA READ MODE command. Refer to the
sections below for the foil description of their operations.
SELECT CHANNEL
Address Signal Line Bits Used
xxx80
xxx80
xxx80
XXX80
xxx80
xxx81
xx481
xxx81
xxx81
xxx9A
xxx80
xxx80
xxx81
xxx9B
xxx9B
CMDA (Write>
CMDA (Write)
CMDA (Write)
CMDA (Write)
CMDA (Write)
CMDB (Write)
CMDB (Write)
CMDB (Write)
CMDB (Write)
CMDC (Write)
CMDA (Read)
CMDA (Read)
CMDB (Read)
CMDD (Write)
CMDD (Read)
DO-D3
D4
D5
D6
D7
DO-D3
D4
D5
D6-D7
ALL
ALL
ALL
ALL
ALL
ALL
SELECT CHANNEL must be used in conjunction with the
SELECT SLOT command to select the channels on slot one
Location: xxx80
of the chassis.
The SELECT CHANNEL command is used to control the
local signal multiplexer on the AMMlF, thus determining
which of the local input channels is selected for A/D
conversion. This command affects only those signals connetted to the AMMlF local inputs, and does not affect
input channels connected to modules located in other slots.
D7 D6 D5 D4 D3 D2 Dl DO Byte
L Channel Select: SE (O-15), DIFF (O-7)
Channel Mode: Single-ended (l), DIFF (0)
ACQ Mode: BOkHz Auto Acquire (i), Regular Acquire (0)
Filter Mode: 1OOkHz (0), 2kHz (1)
Note that the channel number occupies the least significant
four bits of CMDA. Make sure that the channel number is
combined with the appropriate upper four bits, as shown
in Figure 5, before it is sent.
Format
Figure 5. CMDA Wife Format (Address xxx80)
AMMlF/7
AMMlF
Master Analog Measurement Mode
Select Range: -lOV flOV (l), 0 flOV (0)
Select Global Gain: Xl (0), X2 (l), X5 (2), X10 (3)
Figure 6. CMDB Write Format (Address 23~81)
SELECT LOCAL CHANNEL MODE
Location: xxx80
The SELECT LOCAL CHANNEL MODE command con-
trols the configuration of the local input channels on the
AMMlF. The AMMlF input channels can be configured as
either 16 single-ended or eight differential input channels.
This command is selected by assigning a value to the D4 bit
position of CMDA as shown in Figure 5. A value of 1 will
set the inputs to single-ended, a value of 0 will set them to
differential.
Make sure that the other bits in the CMDA byte represents
the desired selection before it is sent.
SELECT LOCAL GAIN
Status (0), Low Data (1)
SELECT ACQUISITION MODE
The AMMlF has the capability of operating in either of two
modes; the regular acquisition mode, and the 1OOkHz auto
acquisition mode. As shown in Figure 5, the acquisition
mode is set by assigning a value to bit position D6 in
CMDA. Assigning a value of 0 enables regular acquisition
mode, a value of 1 enables 1OOkHz auto acquisition mode.
To acquire an analog reading when in the regular acquisition, the slot, channel, and gain must be selected. Then
after the appropriate settling time, the AMMlF is issued a
START CONVERSION command. At the time, the AMMlF
latches the signal and starts the digitization process. The
EOC STATUS command can be polled for end-of-conversion WC) after which the digitized value can be read.
The conversion process will consume approximately 1 Oj.lsec.
Location: xxx80
The gain applied to the local channels of the AMMlF is
programmable and can be set by assigning a value to bit
position D5 in CMDA. As shown in Figure 5, a value of 0
will apply a local gain of Xl and a value of 1 will apply a
local gain of X10 to the AMMlF input channels.
The local gain can be changed at any time as long as the
channel settling time is satisfied before the conversion is
started.
Make sure that the other bits in the CMDA byte represent
the desired selections before it is sent.
AMMlF/B
Since the incoming signal is latched when the START
CONVERSION command is issued, the slot, channel, and
gain selections can be changed immediately after the command is issued. This will allow the settling time for the new
selections to be satisfied concurrently with the conversion
of the previous selection. This type of operation is not
required but will increase the throughput capability of
regular acquisition mode.
The 1OOkHz auto acquisition mode allows full 1OOkHz
acquisition speed on analog signals. Upon placing the
AMMlF in this mode, the A/D enters a free-running
1OOkHz conversion process. Do not attempt to issue the
START CONVElWON command in this mode.
AMMlF
Master Analog Measurement Mode
Some microcomputers may not be capable of keeping up
with the AMMlF in auto acquire mode. If the AMMlF out-
paces your microcomputer, the data points will be unreliable. In general, a 1OMHz or faster 286,386, or 486 microprocessor is required to keep up with the AMMlF using
ANINQ. Other software may require even faster microprocessors, depending on how the code is written.
After the completion of a conversion, the AMMlF begins
the next conversion immediately. The EOC STATUS
command can be used to synchronize your program with
the conversions. The conversions will take place on the slot
-1 -L----l LL^L-----^^-l, ---,,- I.,-1 ^A^ ..^L. ,c,nn,,u,
anu UliilLlltx LllM ale y1esc11Lly btxtxKx,L CLL CL 1cLLt: “I J.““lu u.
The conversion status bit will be reset by the reading of
either the high or low A/D data bytes. Figure 7 shows the
timing for single channel auto acquire operation.
While in auto acquire mode, the EOC status bit will become
true (low) after the first A/D conversion. Even though the
next conversion begins immediately, the status bit remains
true until the A/D data is read, it is over-written.
Figure 8 shows an example of the EOC status being polled
only after one or more conversions have taken place. Even
though the EOC status bit indicates that the conversion is
complete, there is no way of telling if another conversion is
about to be completed. Trying to read the data while the
latches are being updated will cause unreliable results. To
guarantee reliable readings, your program should synchronize itself with the AMMlF by taking a dummy read-
ing to clear the conversion status bit. The next time the
status bit indicates the end of a conversion, the data at the
A/D latch will be valid for the full 10psec.
For multichannel auto acquisition operation, all of the
settling times for the new channel must be satisfied 2.8usec
before the EOC takes place. If it is not settled, it may be
necessary to throw away a reading or two until it has
settled. To
maximiz e the available settling time, it is recommended that slot selection, gain selection, and channel
selection take place directly after the EOC becomes true.
1. Monitor the EOC status bit until an end-of-conversion is
sensed.
2.Select a new gain, a new slot, and a new channel, as
needed.
3. Read the latched data from the last conversion.
A timing diagram for multichannel operation is shown in
Figure 9.
Even though the AMMlF is capable of digitizing analog
signals at lOOkHz, most modules in the Series 500 module
library are not capable of settling at these speeds. When
doing multichannel acquisition, consult the individual
module’s hardware manual for appropriate settling times.
EC0 Status
Bit (CMDD)
Poll EOC
Bit Status (CMDD)
1 I 1
Read Low
We
Read High
Byte
! I
I
i I
!V /y!
Figure 7. Single Channel Aufo Acquire Timing
Conversion
Completed
!
I
I
AMMlF/9
AMMlF
Master Analog Measuretnent Mode
1st
Conversion
EOC Status
Bit (CMDD)
Poll EOC
Bit Status (CMDD)
J
1
I
1
Although the converter status indicates
a completed conversion here, reading the data
might be coicident with an update of the
data from the converter
Figure 8. Polling the Status Bit After One or More Conversions
EC0 Status
Bit (CMDD)
Poll EOC
Bit Status (CMDD)
aain
p
~ts~t.sbL
Slot
Select
Channel
Select
l-l
I !
I
I
slot mux
settlina time
I
2nd 3rd
Conversion Conversion
Data in the ND
Latch is Updated Here.
The EC0 status bit
remains low until the
High or Low data are read.
I
I
i
\\l r
I
Read Low
We
Read High
We
Channel Read Channel
A Data Ready Channel B Data Ready
I
I
I _
1
I
Setup
for Channel
I ”
B
Figure 9. Multichannel Operation in Auto Acquire Mode
Channel
A
B
AMMlF/lO
AMMlE
Master Analog A4easurernent Mode
SELECT FILTER
Location: xxx80
Two filters are available in the AMMlF; a 2OOkHz filter,
and a2kHz filter. These filters restrict the bandwidth of the
incoming signal, rejecting either noise or unwanted high
frequency components that may create alias@
It is desirable to reject all signal frequency components that
are greater than l/2 the sampling frequency. These frequency components cause aliasing which produces inaccurate waveform representation. The filters are designed
to reject frequencies above 200kHz or above 2kHz, depending on the filter used. The 200kHz filter, while not
providing complete protection against aliasing, does reduce the system noise with
a minimal
effect on settling
time.
Assign a value of 0 to bit position D7 in CMDA to select the
200kHz filter, assign a value of 1 to select the 2kHz filter.
Table 2. Values Written to the SELECT SLOT Location
Function
Ground (0 volts)
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9
Slot 10
RC3?l-Vt?d
Reserved
+lOV Reference
Reference voltage (approx 7.OV)
+5V Digital Power Supply
SELECT CMDA READ MODE
Binary
bbbbOOO0
bbbbOOO1
bbbbOOl0
bbbbOOl1
bbbbOlO0
bbbbOlO1
bbbbOll0
bbbbOll1
bbbblOO0
bbbblOO1
bbbblOl0
bbbblOl1
bbbbllO0
bbbbllO1
bbbblll0
bbbbllll
Make sure that the other bits in the CMDA byte represent
the desired selection before it is sent.
SELECT SLOT
Location: xxx81
The SELECT SLOT command controls the global multi-
plexer on the AMMlF, selecting the appropriate slot on the
Series 500 baseboard from which to read the input channel.
The value to be written to the SELECT SLOT location
occupies the four least significant binary digits of the
command. Make sure that the channel number is combined
with the appropriate upper four bits as shown in Figure 6
before it is sent.
As indicated in Table 2, there are other values besides slot
numbers that can be written to this location. These values
select ground, +5V, the heated zener reference voltage, and
+lOV sources and are intended primarily for diagnostic
purposes.
Location: xxx81
This command selects the usage of the CMDA read. Two
types of information can be read from CMDA (note that
this affects only the read operation of CMDA), these are,
the low data bytes of the A/D or the A/D status. In the low
data byte mode, CMDA supplies the low data byte of the
A/D readings. In the A/D status mode, CMDA supplies
status directly from the A/D. The A/D status is described
further in the sections below.
NOTE
When the CMDA read mode is set to A/D
status, a reset and recal sequence will be initi-
ated by any start conversion command. The
start conversion
comman
d can come either from
a write to CMDD, or from the auto acquire
mode hardware if this mode has been enabled
by a value of 1 in bit position D6 of CMDA. To
avoid accidentally initiating a reset and recal
sequence, be sure bit position D6 of CMDA is
set to a value of 0 before changing the CMDA
readmodetoA/Dstatus.DonotwritetoCMDD
or change D6 of CMDA to a value of 1 as long as
the CMDA read mode is set to A/D status.
AMMlF/ll
AMMlF
Mm ter Analog Measurement Mode
Assign a value of 0 to bit position D4 in CMDB to read A/
D status from CMDA, assign it a value of 1 to read the A/
D low data byte.
Make sure that this bit is combined with the other appropriate bits as shown in Figure 6 before it is sent.
SELECT RANGE
Location: xxx81
The AMMlF has two programmable ranges; +lOV (bipolar
1OV) and zero to +lOV (rmipolar 1OV). Assigning a value of
0 to bit position D5 in CMDB will select the AMMlF
unipolar 1OV range, assigning a value of 1 will select the
bipolar 1OV range.
Make sure that this bit is combined with the other appropriate bits as shown in Figure 6 before it is sent.
SJXECT GLOBAL GAIN
RESET AND RECAL
Location: xxx9A
The RESET AND RECAL command starts the internal A/
D calibration process. The process takes approximately
9.lmsec and should be completed once every time the
system is powered up.
After issuing this command, wait at least 9.lmsec before
any conversions are attempted. To make sure that the
calibration has taken place, set the CMDA read-mode to
A/D status, as described above. The bit configuration of
the calibration status is described below. This bit can be
polled to make sure calibration has been completed.
This command has no specific data associated with it, any
value sent will start the calibration process.
A/D LOW DATA -A/D STATUS
Location: xxx80
Location: xxx81
The GLOBAL GAIN command controls the PGA (Pro-
grammable Gain Amplifier) located on the AMMlF module. Since all analog inputs are processed by the PGA, the
GLOBAL GAIN command affects every analog input
connected to the Series 500. This command is issued in
conjunction with other commands on CMDB. The GLOBAL GAIN value occupies the two most significant bits of
CMDB and must be combined with the other bits of the
CMDB byte before it is issued.
Four programmable gain values, xl, x2, x5, and x10, are
available with the PGA. These gains are selected by setting
the appropriate bits in CMDB before it is issued.
Table 3. Values Written to the GLOBAL GAIN Location
PGA Gain Binary
xl
k2
x5
x10
OObbbbbb
Olbbbbbb
1Obbbbbb
llbbbbbb
The contents of CMDA depends on the state of the AMMlF
set by the SELECT CMDA READ MODE command. If D4
of CMDB has been set to 0, CMDA returns the A/D status
of the AMMlF. If D4 has been set to 1, the low byte of the
A/D counts is returned in CMDA. Only the upper 4 bits of
the low data byte are significant. The lower 4 bits always
return zeros.
When AMMlF is in the A/D status mode, the bit con-
figuration of the CMDA byte is as follows:
DO none
Dl none
D2 none
D3 none
D4 none
D5 TRACKING
(l=traclcing in process, 0 = tracking stopped)
D6 CONVERTING
(l=conversion is process, O=no conversion in
process)
D7 CALIBRATING
(l=calibration in process, O=calibration not in
process)
AMMlF/12
AMMlF
Master Analog Measurement Mode
EOC Bit
in CMDD
Tracking Bit
in CMDA
Converting Bit
in CMDA
k
I
I
I
I
- \ Conversion
lops
7.2~s
Begins
Figure 10. Time Relationship of Status Bits
After the A/D completes a digitization of an analog signal,
it begins a process called tracking. The A/D consumes
2.8ltsec for the analog signal at its input to be tracked to the
specified accuracy. The time relationship between the
TRACKING bit and the EOC bit in CMDD is shown in
Figure 10.
The converting bit indicates the actual A/D conversion
status. The time relationship between the CONVERTING
bit and the EOC bit in CMDD is shown in Figure 10.
Won’t Reset Until
Once both the low and the high data bytes have been
obtained, the total number of counts representing A/D
converter data can be determined with the following BASIC formula:
CO = DL + 256*DH
CO represents the number of counts, and DL and DH are
thelowandhighbytesrespectively.SincetheAMMlFuses
a 12-bit converter, and the 4 least significant bits always
read zero, the number of counts will lie in the range of zero
to 65,520.
The CALlBRATING bit returns the status of a RESET AND
RECAL command as described above.
If the AMMlF is in the low data mode, the byte received is
the low byte of the 12-bit A/D conversion. Since the
module incorporates data latches, one conversion may be
read while another conversion is in progress. To find out
when data from one covnersion is available, use the A/D
START/EOC STATUS command, discussed below.
Reading this location resets the EOC status.
ND HIGH DATA
Location: xxx81
The A/D HIGH DATA command performs essentially the
same function as the A/D LOW DATA command, except
that the high data byte is returned. All of the bits in the high
data byte are significant.
Reading this location resets the EOC status.
A/D START
Location: xxx9B
The A/D START COMMAND starts the A/D conversion
process. Writing to the A/D START location will trigger
(start) the A/D conversion cycle. Although any value (O-
255) can be written to trigger a conversion, a value of 255
should be used to
minimize noise. DO not issue an A/D
command while in auto acquisition mode or the internal
timing of the A/D will be skewed.
The A/D conversion cycle takes approximately 7.2pec.
During this period, the converter should not be re-triggered. Status of the conversion process can be checked by
accessing the EOC STATUS command.
AMMlF/13
AMMIF
Mm ter Analog Measurement Mode
EOC STATUS
The EOC STATUS command returns a byte of data which
indicates the state of the conversion process. The returned
value will depend on whether a conversion has been
completed (see Table 4).
Table 4. Values Read from the A/D START/
STATUS Location
EOC Status Binary
Conversion in process 1XXXXXXX
End-of-conversion
OXXXXXXX
Calibration
This section contains calibration procedures for the AMM2
module. Note that these procedures for the AMMlF
modules. Note that these procedures are intended for the
field and may not be as accurate as those used in the
factory. Calibration accuracy depends both on the accuracy
of the equipment used in the procedure as well as the skill
of the individual. If you are not familiar with calibration
equipment, do not attempt AMMlF calibration.
This procedure presumes that the unit is in working con-
dition and at least one factory calibration has been done in
the past. An additional procedure is necessary to select
R25, R26, R27 and R28 if the voltage reference U13 has been
replaced. The procedure for replacing U13 is described
after the section on troubleshooting.
Environmental Conditions
corresponding specifications are at least
as good as those
given below.
1. Key specs needed on DMM.
DC accuracy of 60 ppm on a IOV reading.
Sufficient resolution to read one microvolt offsets.
2. EDC Model ElOOC Millivolt Reference Source (0.005%
accuracy).
Key specs needed on source:
Provides an output between 0.5 and 0.99 volts.
Maintains its output stable to 10 ppm for five
minutes.
Overview of Adjustment Sequence
1. Adjust 1OV reference.
2. Adjust 4V reference.
3. Adjust Global Amp offset.
4. Adjust attenuator offset.
5. Adjust both Local amp offsets.
6. Adjust Local amp X10 gain.
7. Tweak A/D gain with 4V reference adjustment.
Calibration Procedure
The test points, potentiometers, and connectors referenced
in the procedure are shown in Figure 1.
Adjust 1OV reference
1. Connect the DMM high lead to TP7 (1Ov). Connect the
DMM low lead to TP4 (AGND). Select DCV and
autoranging.
2. Adjust pot R7 for 10.0000 volts &-1OOpV.
Calibration should be performed at an ambient temperature of 23°C (k5”). Turn on the system power and allow it
to warm up for at least 10 minutes before beginning the
calibration procedure.
Recommended Calibration Equipment.
The following equipment is recommended for AMMlF
calibration. Other equipment may be used as long as the
AMMlF/l4
Adjust 4V reference
The following procedure will bring the 4V reference within
range so that it can be calibrated accurately later.
1. Connect the DMM high lead to TP8 (4V). Connect the
DMM low lead to TP4 (AGND). Select DCV and
autoranging.
2. Adjust pot R8 for 4.000 volts +lmV. This adjustment will
be tweaked later.
AMMlF
Master Analog Measurement Mode
Adjust Global
1.
Connect the DMM high
Amp
offset
lead
to TP9. Connect the DMM
low lead to Tl?4 (AGED). Select DCV and autoranging.
2. Select the PGA gain of X10 and the zero voltage reference
input by POKEing a value of 192 to CMDB of slot 1 and
a value of 0 to CMDA of slot 1.
3. Adjust pot R9 for zero volts rtlOpV.
Adjust attenuator offset
1
1. Select the Xl global gain and the zero voltage reference
input by POKEing a value of zero to both CMDA and
CMDB of slot 1.
2. Connect the DMM high lead to TPlO. Connect the DMM
low lead to Tl?9. Select DCV autoranging.
Adjust both Local amp offsets
1.
Connect a short jumper wire between differential
channel 0 high input and signal common (terminals 9
and 10 on Jl). Connect a short jumper wire between
differential channel 0 low input and signal common
(terminals 1 and 2 on J2).
Connect the DMM high lead to TP3. Connect the DMh4
' 2.
low lead to TP4. Select DCV and autorange.
Select differential input and Xl gain by POKEing a
3.
value of 0 to CMDA of slot 1.
Record the DMM reading as Vout(l) f6r use later.
4.
5.
SelectagainofXlObyPOKEingavalueof32toCMDA
of slot 1.
6.
Record the DMM reading as VoutQ).
Compute the offset contribution of U6 as follows: VOS
7.
= (lO*Vout(l) - VOUT (2))/9.
Adjust pot R5 so that the DMM reads the voltage
8.
computed for VGS.
9. Select the Xl gain again by POKEing a value of zero to
Ch4DA of slot 1.
10. Adjust pot R6 for a DMM reading of zero volts HOpV.
If desired, the adjustment can be checked by once
again outputting data: CMDA = 32. The DMM should
read zero volts +lOOpV.
Adjust Local amp X10 gain
1. Remove the jumper between terminals 9 and 10 of Jl that
was installed in previous step. Connect voltage source
(+> output to terminal 9 of Jl, and the voltage source (-1
output to terminal 10 of Jl. Leave the jumper installed
between terminals 1 and 2 of J2.
2. Connect the high lead of the DMM to TP3. Connect the
lowleadoftheDMMtoTP4.SelectDCVandautoranging.
3. Set the voltage source to a value of 0.99 volts.
4. Select the X10 gain by POKEing a value of 32 to CMDA
of slot 1.
5. Adjust pot R4 for a reading of 9.9 volts.
Tweak AID gain with 4V reference adjushnent
l.Use the test setup from the previous step. The DMM
should be reading a voltage of approximately 9.9 volts on
Tl?3.
2.Select channel 0, local gain of X10, differential input,
filter on (2kHz), slot 1, unipolar 10 V range, and global
gain of Xl by POKEing values of 224 and 17 to CMDA
and CMDB respectively.
3.Run the following BASIC program. This program assumes that the hardware address in CFFO, if this isnot the
case, adjust line 10 for the proper address.
4. Adjust pot R8 so that the displayed voltage equals the
DMM reading.
AMMlF/l5
AMh+flF
Master AnaZog h4Ieasurement Mode
10
DEF SEG = &hCFFO
20 CMDA = d&80: Ch4DB = &h81
30
CMDC = &h9A: CMDD = &h9B
40
POKE CMDA, 160
50
POKE CMDB, 17
60 POKE CMDD, 255
70 WHILE PEEK (CMDD) > 127 :WEND
80 TOTAL = I’EEK(CMDA) + PEEK
(CMDBP256
90 VOLTS = TOTAL * 0.00015258
100 LOCATE 1,l:pRTNT VOLTS,
110 GOT0 60
*Presumes interface is set to address CFWO(h).
‘hardware segment*
‘set up from step 2 above
‘set up from step 2 above
‘start conversion
‘wait until conversion is complete
‘get high and low data and combine
‘print value in volts
Theory of Operation
For the following discussion, please refer to the schematic
diagram, drawing number 501-406.
AMMlF circuitry is divided into the following sections:
local input multiplexer, programmable gain, global input
multiplexer, global gain amplifier, filter, A/D converter,
A/D voltage reference amplifier, and the lo-volt global
reference.
Local Input Multiplexer
The local input multiplexer is made up of two 8 to 1 analog
muliiplexers Ul and U2, a dual switch U3, and input
protection resistor networks Rl and R2. The digital control
signals for the input multiplexer are latched by U19, and
additional digital logic to control the differential/singleended mode selection is in the PAL, U18. When the singleended mode is programmed, U3 grounds the inverting
input of the differential instrumentation amplifier (pin 3 of
U7), and connects the output of both Ul and U2 to the non-
inverting input of the differential instrumentation amplifier (pin 3 of U5). The selected input is switched through
the appropriate 8 to 1 multiplexer to the differential amplifier input while the output of the other 8 to 1 multiplexer is
open circuited. When the differential input mode is selected, U3 connects the output of U2 to the inverting input
of the differential instrumentation amplifier (pin 3 of U7).
The output of Ul is always connected to the non-inverting
input of the differential instrumentation amplifier (pin 3 of
U5). The selected input channel -CH terminal is connected
throughU2 and the +CH terminal is connected through Ul
to the local amplifier inputs.
Local Programmable Gain Amplifier
U4, U5, U6 and U7 make up the local programmable gain
amplifier. U5 and U7 provide the high input impedance,
and also provide the voltage gain when the X10 gain is
selected. When Xl gain is selected, U4 (a dual analog
switch) connects both U5 and U7 in the voltage follower
configuration. When Xl0 gain is selected, U4 connects the
inverting inputs of U5 and U7 to the taps on a voltage
divider connected across the outputs of U5 and U7. The
voltage difference between the inverting inputs of U5 and
U7 OS l/10 the voltage difference between the outputs of
U5 and U7. This arrangement gives a voltage gain of 10 for
differential input signals and a voltage gain of 1 for common mode input signals. The common input signal is
defined as the average of the +CH and -CH input signals.
The voltage gain in the X10 mode is adjusted with R4,
which adjusts the voltage divider ratio. The voltage gain in
the Xl mode is not adjustable. The outputs of U5 and U7 are
connected to the precision resistor network RI1 and amplifier U6. Rll and U6 make up a unity gain differential
amplifier, which amplifies the differential signal and rejects the common mode signal. The output of U6 is the
overall amplifier output, and consists only of the differential signal between U5 pin 3 and U7 pin 3.
Global Input Multiplexer
The global multiplexer selects which signal is measured by
the A/D converter. U8 is a 16 to 1 analog signal multiplexer. Inputs 0 and 14 of U8 are connected to ground.
Input 1 is connected to the output of the local amplifier.
Inputs 2 through 10 go to pins on P14, and by external
connections, are connected to slots 2 through 10 of a Series
500 mainframe. These connections will carry the output
AMMlF/16
AMhIlF
Master AnaZog Measuremenf Mode
signals of other signal processing cards to the global multiplexer, where they can be routed to the A/D converter for
measurement. Inputs 11 and 12 also go to J14, but are
typically not used. Input 13 is connected to the IO-volt
reference, and input 15 is connected to the +5-volt digital
power supply. The output of the multiplexer is connected
to the Global Amplifier input.
Global Programmable Gain Amplifier and Filter
The global programmable gain amplifier is made up of U9,
UlO, and Ull. The voltage gain of U9 is determined by
which tap on the precision resistor network R14 is selected
by the analog multiplexer Ul 1. The available gains are Xl,
X2, X5, and X10. R14 is a voltage divider connected to the
output of U9, and the tap determined by Ull is connected
to the inverting input of U9. The non-inverting input of U9
is the overall input of the circuit. At the output of U9,lO
volts represents a full scale input. The A/D converter used
cannot convert an input above 4 volts, so the output of U9
is reduced to 40% of its full scale output by a divider made
up of R15, R16, and R17. The analog filter is applied after
this divider, and is made up of C7 and R18 along with the
combined resistances of the divider. For the 2kHz pole, all
resistors are in the circuit, but when the 2OOkHz pole is
programmed, FET Q3 is turned on and bypasses R18. The
2OOkHz pole is determined by the equivalent output re-
sistance of the 40% divider and C7. UlO buffers the filter
output and provides the low drive impedance required by
the A/D converter. At the output of UlO, 4 volts represents
a
full scale input. CRl, CR2, CR3, and CR4 make up a
clipping circuit to prevent overscale inputs from saturating the A/D, thus allowing immediate overload recovery.
A/D Converter
The A/D converter, U12, is a 12-bit successive approxi-
mation converter with an internal sample and hold. U12
operates on +5 volts and -5 volts. These supplies are
derived from the +15 and -15 volt analog supplies by U21
and U22 respectively. The A/D determines the ratio of the
analog input to the voltage reference input. The voltage
reference used is 4 volts. The digital outputs of the A/D are
buffered by U16 and U17. The logic control for the A/D is
in the PAL, U18.
A/D Voltage Reference Amplifier
The A/D converter requires a voltage reference source
with a low output impedance from dc up to several mega-
hertz. U15, Ql, R8 and the associated components comprise an amplifier with the needed characteristics. The
reference voltage is derived from the heated zener reference U13 and divided down to 4 volts by the divider made
up of R8, R21, R22, and R24. Resistors R27 and R28 are used
to restrict the adjustment range of R8, and are either
installed or not used based upon the zener voltage of Y13
at the time of factory calibration. If U13 is replaced, it may
be necessary to either install or remove either one or both
of these resistors. R31 and C6 frequency compensate the
amplifier loop, and C9 is a filter for zener noise.
10 Volt Global Reference
U13, U14 and the associated components form the 10 volt
reference circuit. The zener voltage of approximately 7
volts is amplified by U14 to 10 volts. R7, R19, R20, and R23
determine the output voltage by adjusting the gain of U14.
R25 and R26 serve a function similar to R27 and R28 in the
A/D reference circuit. R30 and C8 filter the zener noise,
and D7 assures that the circuit will start properly when
power is first applied.
AMMlF Troubleshooting Information
Diagnosing trouble with the AMMlF is best done in several steps. If the AMMlF is not functioning at all, the
following tests should be performed in the sequence indi-
cated. It may be possible to skip some of the tests if the
AMMlF is partially functional.
A BASICA test program is listed at the end of this section
which is used to setup the hardware for these tests. Change
line 10, if necessary, to the address segment used by your
system. Each test is independent, and can be run by itself
if needed, as long as the first 3 lines of the program are also
entered.
The overall test sequence is:
1. Check power supplies
2. Check reference voltages
3. Test digital control circuitry
4. Test local mux
5. Verify operation of local amplifier
6. Check operation of global amp
7. Test global mux
8. Verify operation of A/D converter
AMMlF/17
Ah4MlF
Master Analog Measurement Mode
The only additional equipment needed for these tests is a
digital multimeter (DMM), and two jumper leads. When
performing these tests, refer to schematic diagram 501-406,
component layout 501-400, and the following instructions
for the connections to use while running the test program.
Test Sequence:
1. Check power supplies
Us&g a DMM on the 20-volt range, connect the minus
lead to Tl?4 (AGND). The positive lead should be used to
test for the following voltages within ti.5 volts:
U7pin7
U7pin4
TJ?6 (DIG GND) 0
U18 pin 24
u12 pin 25
u12 pin 11
u12 pin 30
U12 pin 36 -5
2. Check reference voltages
With the DMM minus lead connected to TP4 (AGND),
use the 20-volt range to read the following voltages:
Tr14 (Vz)
Tl?7 (1OVref) 10.00 volts
Tl?8 (4V) 4.0 ti.2 volts Ul5 output, A/D
3. Test digital control circuitry
Use the test program lines 300-395 to verify that the
control registers are capturing the correct data. Connect
the minus lead of the DMM to TP6 (DGND) and touch
the DMM plus lead to the pins indicated by the program.
If this test is completely unsuccessful, first verify that the
rest of the system is functioning properly before proceeding. The computer, IBJN interface card, 500 mainframe, and hardware address segment should be checked.
If the rest of the system is functioning properly, or if only
some of the pins on Ul9 or U20 are not functional, check
U18, U19,U20 and the K’s connected to the nonfunctional
pins.
4. Test local mux
7 a.25 volts zener reference voltage
+15
-15
+5
+5
+5
-5
u14 output
reference voltage
reference tested in step 2. The test program lines 400-490
will help perform the test. Connect a test lead to TP8 (4V)
and connect the other end of this test lead to the input on
Jl or J2 as indicated by the program. Connect the DMM
- lead to TJ?4 (AGND), and the + lead to Tl?l or TP2 as
indicated by the program. Run the program. The DMM
should show the 4-volt signal on the indicated test point
when the input pin indicated by the program is touched
with the 4V test signal.
5. Verify operation of local amplifier
Proper operation of the local amplifier can be tested by
applying a voltage difference of one volt to its input and
1ookingforanoutputofonevoltontheXlgainrangeand
10 volts on the X10 gain range. A one volt signal can be
obtained by connecting +4V reference TP8 (4V) to -CHO
onJ2 pin 2, and +5V supply TP12 (+5V) to +CHO on Jl pin
9. Connect the DMM + lead to TP3 and the - lead to TP5
(AGND). Lines 500-580 provide the setup for this test.
6. Check operation of global amp
The global amp can be tested by using the one volt signal
generated in step 5 above, and checking that the correct
output at TP9 occurs for each gain setting. The global
mux channel 1 of U8 must be functional for this test to
work, so it is checked first. Connect a test lead from TP8
(4V) to J2 pin 2 and a second test lead from TP12 (+5V) to
Jl pin 9. The Dh4M - lead connects to TP4 (AGND), and
the + lead to the TP indicated as the output in the test
program. Lines 600-690 of the test program are used.
7. Test global mux
The global mux is tested by applying a signal to each
input and verifying that the signal appears at the output.
Since the global amp was tested in the previous step, any
signal applied to the global mux should show up at TE’9.
The slot inputs can be tested by applying the 4-volt
reference signal to the input under test. Other inputs to
the global mux are hardwired to various signals as
indicated by the program. Setup the test as follows:
Connect a test lead fromTP8 (4V) to J2 pin2 and a second
test lead from TP12 (+5V) to Jl pin 9. The DMM - lead
connects to Tl?4 (AGND), and the + lead to TP9. At the
point in the program where a signal is required as an
input to a pin on U8, disconnect the end of the test lead
on J2 pin 2 and use this end to touch the pin indicated by
the program on U8. Lines 700-790 of the test program are
used.
Thelocalmuxcanbecheckedbyputtingasignalthrough
each of its channels. A convenient signal is the 4-volt
AMMlF/18
AMMIF
Master Analog Measurement Mode
8. Verify operation of A/D converter
The A/D converter is tested by inputting a signal from
the local amp and displaying the reading. The test setup
uses the one volt test signal derived in step 5. The
displayed voltage should be about one volt. Connect a
test lead from TP8 (4V) to JZ pm 2 and a second test lead
from TIT12 (+5V) to Jl pm 9. Lines 800-890 of the test
program are used.
Replacement Procedure for U13
The heated zener voltage reference U13 requires a special
calibration procedure if it is replaced. The LM399 used for
U13 has a wide tolerance for its initial zener voltage, but
drifts very little with time or temperature. Resistors R25,
R26, R27 and R28 are used to trim out a large portion of the
initial zener voltage tolerance, with the balance of the
adjustment done by potentiometers R7 and R8. The adjust-
ment range of R7 and R8 is large enough to compensate for
any drift in TJl3 over the life of the module, but has been
purposely restricted to improve the stability and
adjustability of the voltage reference. When U13 is replaced, the following procedure must be used to determine
which two of the four resistors (R25, R26, R27, or R28) must
be installed.
The procedure is to measure the zener voltage, + lead to
Tl?14,-leadtoTJ?4(AGND),findtherangeonthefollowing
table that includes this voltage, then install or remove the
resistors indicated in the table as required.
Zener Voltage R25 R26 R27 R28
6.78 to 6.90 open 61.9K 383K open
6.90 to 7.01 49.9K 61.9K open open
7.01 to 7.11
7.11 to 7.23
open open 383K 267K
49.9K open open 267K
AMMlF/19
AMMIF
Master AtmZog Measurement Mode
Troubleshooting Test Program
10
20
30
300
310
320
330
335
340
350
355
360
370
375
380
390
395
400
405
410
415
420
425
430
435
440
445
450
455
460
465
470
475
480
485
490
500
510
520
530
540
550
560
570
580
600
605
610
620
630
635
640
DEF SEG = &HCFFO
CMDA = &H80: CMDB = &H81
CMDC = &H9A: CMDD = &H9B
CLS
PRINT “3. TEST DIGITAL CONTROL CIRCUITRY”
POKE CMDA, 255
PRINT “MEASURE > 3 VOLTS ON FINS 2,5,6,9,12,15,19 OF Ul9”
INPUT “PRESS RETURN TO CONTINUE”,A$
POKE CMDA,O
J?RINT “MEASURE > 1 VOLT ON MNS 2,5,6,9,12,15,19 OF Ul9”
LNI’UT “PRESS RETURN TO CONTINUE”,A$
POKE CMDB,255
PRINT “MEASURE > 3 VOLTS ON FINS 2,5,6,9,12,15,19 OF U20”
INPUT. “PRESS RETURN TO CONTINUE”,A$
POKE CMDB,O
PRINT “MEASURE < 1 VOLT ON FINS 2,5,6,9,12,15,19 OF U20”
INPTJT “PRESS RETURN TO CONTINUE”,A$
CLS
PRINT “4a. TEST LOCAL MUX SINGLE ENDED MODE”
FORN=OTO15
IFN,8THENPIN=9-NELSEFLN=N-6
IFN<8THENJ=lELSEJ=2
POKE CMDA, 16 + N
LOCATE 6,l
PRINT “INMJT”;N;“ON PIN”;l?IN;“OF J”;J;‘IS CONNECTED TO T.l?l”
INPUT “PRESS RETURN TO CONTINUE”,A$
NYEXTN
PRINT “4b. TEST LOCAL MUX DIFFERENTIAL MODE”
FORN=OTO7
PORE CMDA, N
LOCATE 6,l
J?RINT “+INlWT”;N;“ON FIN”;9-N;“OF Jl IS CONNECTED TO Tl’l”
PRINT “-lNPUT”;N;“ON PIN”;N+2;“0F J2 IS CONNECTED TO TF2”
INPUT “PRESS RETURN TO CONTINUE”,A$
NEXTN
CLS
PRINT “5. TEST LOCAL AMP”
POKE CMDA,O
FRINT “LOCAL GAIN = Xl, 1 VOLT INFU’T GIVES 1 VOLT OUTFUT AT TP3”
INPUT “PRESS RETURN TO CONTINUE”,A$
CLS
POKE CMDA,32
PRINT “LOCAL GAIN = X10,1 VOLT INFUT GIVES 10 VOLT OUTPUT AT TP3”
INPUT “PRESS RETURN TO CONTINUE”,A$
CLS
PRINT “6. TEST GLOBAL AMY
POKE CMDA,O ‘SETUF LOCAL AMF
POKE CMDB,l
PRINT “READ 1 VOLT AT PIN 28 OF U8”
INPUT “PRESS FWUJRN TO CONTINUE’,A$
FORN=OTO3
‘HARDWARE SEGMENT
‘SELECT GLOBAL INPUT AND GAIN
AIviMlF/20
AMMIF
Master Analog Measurement Mode
650
655
660
670
680
685
690
700
710
715
720
730
740
750
760
765
770
775
780
785
790
800
810
820
830
840
850
860
870
875
880
890
895
9ocl
910
CLS
PRINT “6. TEST GLOBAL AMP”
POKE CMDB,1+(64*N)
‘SELECT GLOBAL GAIN
IF N < 2 THEN V=N+l ELSE V=(N-1)*5 ‘DETERMINE VOLTAGE GAIN
PRINT “READ”;V;“VOLTS AT TP9”
INPUT. “PRESS RETURN TO CONTINUE’,A$
NEXTN
POKE CMDA,O
‘SETUP LOCAL AMI? FOR 1V OUT
FORN=OTO15
CLS
PRINT “7. TEST GLOBAL MUX”
LOCATE 6,l
IFN<8THENPIN=N+19ELSEl’IN=19-N
POKE CMDB,N
lFN=OORN=14THENPRiNT”OVOLTSATTP9”
IF N = 1 THEN PRINT “1 VOLT FROM LOCAL AMP AT TP9”
IF N = 13 THEN PRINT “10 VOLT REFERENCE AT TP9”
IF N = 15 THEN PRINT “5 VOLT DIGITAL SUPPLY AT TP9”
IF N > 1 AND N < 13 THEN PRINT “SIGNAL AT PIN”;PIN;“OF U8 AT TP9”
INPUT “PRESS RETURN TO CONTINUE”,A$
NEXTN
CLS
PRINT “8. TEST A/D CONVERTER”
POKE CMDA,O
POKE CMDB,17
POKE CMDD,255
WHILE PEEK (CMDD) > 127:WEND
TOTAL = PEEK (CMDA) + PEEK (CMDBj”256
VOLTS = TOTAL*1.5259E-O4
‘SETUP LOCAL AMP
‘SETUP GLOBAL CHANNEL
‘START CONVFRSION
‘WAIT FOR CONVERSION DONE
‘GET READING AND COMBINE BYTES
‘CONVERT READING TO VOLTS
LOCATE 6,l
PRINT VOLTS
A$ = INKEY$
IF A$ = ” ” THEN GOT0 840
PRINT “TEST DONE”
AMMlF/21
AMMlF
Master Analog Measurement Mode
SPECIFKATIONS
INTWTCHANNELS
Local: 8 differential or 16 single-ended inputs.
Global: 9 inputs from slots 2-10.
Multiplexing 1OOkHzsamplingratecompatiblewith AlM2.
Slower rates with AlM3A-AIM9 due to longer settling
time.
LOCAL PROGRAMMA BLE GAIN AMPLIFIER
Programmable Gains: xl, x10.
Lnput Resistance: >lOOMSX
Input Bias Current: <InA.
Input Protection: &3OV max powered, rtl5V max
unpowered.
Temp. Coefficient: +o.OOl%/‘C @ xl gain;
ti.O017%/“C @x10 gain.
Gain Accuracy: xl &0.016%
x10 I!dl.O25%
Non Linearity: ti.01 %
Input Noise: (O.lHz-2OOkHz) <75pVp-p
CMRl? (dc to 60Hz) >80db
10 VOLT REFERENCE
Accuracy: &0.02%
Temperature Coefficient: H.O012%/“C
Noise: (O.l-1OHz) aOpVp-p
GLOBAL AMPLIFIER AND A/D CONVERTER
Resolution (bits): 12,l in 4096
Noise (rms): <l/2 LSB
Gain Accuracy*: xl gain +(0.02% + 1 LSB)
x2, x5, xl0 gain &(0.03% + 1 LSB)
Nonlinearity? 1 LSB
Temp. Coefficient: &O.O02%/“C
Settling Time”*: (w/2OOkHz filter) 7~
(w/2kHz filter) 600~
A/D Converter: Self-calibrating, successive approxi-
mation
A/D Range: Software selectable, 0 to +lOV (unipolar), and
-lOV to +lOV (bipolar).
Conversion Time: 10~ including acquisition time.
Global Amp Gains: xl, x2, x5, x10; software selectable.
Filter: Single-pole low-pass, 2OOkHz or 2kHz, software
selectable.
*Includes input mux, amplifiers and A/D errors.
““to 0.05% of final reading.
AMMlF/22
PARTS LIST
CIRCUIT
DESIG.
C1,2,36
ClO-11
C12-15
(X6-35
C3,4
C37,38
c5
C6
c7
C8,9
CRl-6, CR8,9
CR7
JL2
J3,7
J4-6
:i
43
R1,2
RI1
R13
R14
R15
R16
R17
Rl8
R19
R20
R21
R22
R23
R24
%fi
R27
R28
R29
R3
R30
R31
R32
R33
R36,43-45,47
R37
R38
R39
R4-6,9,10
R40
DESCRIPTION
CAP,22PF,10%,1000V,CERAMIC
CAl?,1UF,2o%~ov, CERAMIC
CAP,lOUF,20%,2OV,TANTALUM
CAP, .lUF,20%,50V,CERAMIC
CAP,10PF,10%,1000V,CERAMIC
CAl?,270PF,20%,lOOV,CERAMIC/FERRITE
CAP,lOOl?F,lO%,lOOOV,CERAMIC
CAJ.?,470PF,10%,1000V CERAMIC
CAP, .0047UF,10%,100V,POLYPROl?YLENE
CAP,lUF,20%,50V,l?OLYESTER
DIODE, SITaICON,lN4148 (DO-351
DIODE,SILICON,lN4148 (DO-351
corn, STRIP, lOPIN
CONN,BERG
CONNECTOR
TRANS,NPN SILICON,2N3904 (TO-921
TRANS,P-CHANNEL DMOSFET,VP0104NE(TO-92)
TRANS,N CHANNEL JFET,SELECTED J210
TRANS,N CHANNEL JFET,SELECTED J210
RES NET, lK, 2%, 2.25W
RES NET, lOK, .Ol%, .lW
RES, 2.274K, .l%, l/lOW, METAL FILM
RES NET, 2K, 6K, lOK, .l%, .lW
RES, 2.87K, .l%, l/low, METAL FILM
RES, 130,1%, 1/8W, METAL FILM
RES, 2K, .I%, l/lOW, METAL FILM
RES, 15OK, l%, 1/8W, METAL FILM
RES, 2.74K, .l%, l/lOW, METAL FILM
RES, 6.65K, .l%, l/lOW, METAL FILM
RES, 14.7K, .l%, l/lOW, METAL FILM
RES, 2OK, .l%, l/lOW, METAL FILM
RES, 121,1%,1/8W, METAL FILM
RES, 499,1%, 1/8W, METAL FILM
RES, 49.9K,1%,1/8W,METAL FILM
RES, 61,9K, l%, 1/8W, METAL FILM
RES, 383K, I%, 118W, METAL FILM
RES, 267K, I%, 1/8W, METAL FILM
RES, 3.01K, l%, 1/8W METAL FILM
RES, 86.6K, I%, 1/8W, METAL FILM
RES,2K,l %,1/8, METAL FILM
RES, 8.2K, .5%, 1/4W, COMPOSITION OR FILM
RES, 1OO,5%,1/4W,COMI’OSITION OR FILM
RES,390,5%,1/4W, COMPOSITION OR FILM
RES, 4.7K,5%,1/4W, COh4l’OSITION OR FILM
RES, lOOK, 1 %,I /8W, METAL FILM
RES, 22K,5%,1/4W, COMPOSITION OR FILM
RES, 5.6K, 5%,1/4W, COMPOSITION OR FILM
POT,20K,lO%, .75W,NON-WIREWOUND
RES,845, .1%,1/8W,METAL FILM
KEITHLEY
PART NO.
C-64-22P
C-237-l
c-179-10
C-365-.1
C-64-1OP
C-386-270P
c-64-1OOP
C-64-47OP
C-306-.0047
c-350-1
RF-28
RF-28
CS-521-2
cs-339
CS-480
TG-47
TG-193
TG-167-l
TG-167
TF-177-1
TF-175
R-263-2.274K
TF-174
R-263-2.87K
R-88-130
R-263-2K
R-88-150K
R-263-2.74K
R-263-6.65K
R-263-14.7K
R-263-20K
R-88-121
R-88-499
R-88-49.9K
R-88-61.9K
R-88383K
R-88-267K
R-88-3.01K
R-88-86.6K
R-88-2K
R-76-8.2K
R-76-100
R-76-390
R-76-4.7K
R-88-100K
R-76-22K
R-76-5.6K
RP-89-20K
R-176-845
R41,42
R46,48
R7,8
RES,lOK,.l %,l /lOW,MBTAL FILM
RES,lK,5%,1/4W,COMPOSITION OR FILM
POT, 2K, lo%, .75W,NONWIREWOUND
R-263-IOK
R-76-1K
RP-89-2K
TPl-8,
TPlO-14
u1,2,11
u12
u13
u14,15
U16,17
U18
u19,20
u21
U22
u3,4
u5-7,9,10
U8
Wl
Yl
PIN, TEST POINT
IC, 8 CH CMOS ANALOG MULTI,6108
IC, 12 BIT A/D CONVERTER CS5012AKD7
IC, VOLTAGE REFERENCE, 399
IC, 22v or-AMP,OP-o7
INTEGRATED CIRCUIT
INTEGRATED CIRCUIT PAL
IC OCTAL,EDGE TRIG BLIP FLOP 75HCT374
IC, +5V REGULATOR, 78LO5AC, (TO-92)
INTEGRATED CIRCTJIT
IC DUAL SPST CMOS ANALOG SWlTCH DG-390
INTEGRATED CIRCUlT
IC, 16 CHAN CMOS MULTIPLEXER 6116
JUMl?ER,CIRCUIT
CRYSTAL, 6.4MHZ
CS-463
IC-267
IC-855
IC-217
IC-207
IC-607
IC-605
IC-397
IC-603
IC-604
IC-455
IC-600
IC-365
J-3
CR-28-4
1 OUREF
-5U
I- +5u
r---f=
r-‘”
LTR.ECO NO. REVISION ENG .
E 910621 RELERSED
/.?p
cl
ORTE
6-21-91
MC-285
(SOLDER SIDE 1
DO NOT SCRLE THIS DRAWING
pTEmEY]
KEITHLEY SNSTRUHENTS INC.
CLEUELRND, DHID 44139
0.0.0.0.0.0.
P14
b-14
DIBENGIONAL TOLERFlNCES
UNLESS OTHERUISE SPECIFIED DATE 6-21-91 SC
tag
xx-+_.015
xxx-+.005
SURFACE MAX. 8W
RNG.-ilo
FRAC.-+I/G, MRTE RTRL
DRN. RJS
FINISH
;i,4iT’1TLE AMNlF
firm.
I----- 500-323
500-322
6-32xl/2PPH (2 REQ’I’D 1
I I
RMMlFl
~DEL [NEXT RSSEMBLY IPTY.
--~~-J
COflPONENT LAYOUT,
I
- INO. -_
,,ccn nu
VdLY VI7
klOl-
400
I
I
I
8
I
7
I
6
-
I
5
I
4 3 2
I
1
fiik
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