Tektronix Keithley AMM1 Analog Measurement Module Rev. B User manual

AMMI
Analog Measurement Module

The AMMl Analog Measurement Module combines two important Series 500 functions
into a single module: the AMMl performs analog signal conditioning and switching,
and A/D conversion. The analog section of the module provides signal selection and
programmable gain for both local and global analog signals connected to the Series 500.
After analog conditioning, signals are routed to the AID converter section of the
module for the analog-to-digital conversion process.

The AMMl has a total of eight local single-ended inputs with unity (xl) local gain. In­put signals are applied through on-card screw terminals. Global conditioning consists of
a high-speed software-controlled gain amplifier with programmable xl, x2, x5, and x10
gain values. Since all analog inputs connected to the Series 500 pass through the global
circuitry, these gain values can be applied to any analog input in the system.

For A/D conversion, the AMMl utilizes a K&bit successive approximation converter that
provides fast, accurate measurement and conversion. A maximum conversion time of
only 25psec and a sample-and-hold acquisition time of 3~s allow sampling rates as high
as 35.7kHz. To maximize resolution, the AMMl has five A/D converter ranges (three
bipolar, two unipolar) that can be selected by on-card DIP switches.

The AMMl is designed to be used only in slot 1 of the system baseboard. To install the
module, first remove the baseboard top cover and install the module in slot 1 with the
component side facing the power supply.

CAUTION: Always turn off the system power before installing or removing modules.
To minimize the possibility of EM1 radiation, always operate the system with the top
cover in place and properly secured.

User-Configured Components

User-configured components for the AMMl include the input screw terminals and the
switches that control A/D converter ranges, as surnmarized in Table 1. For the locations
of these components, refer to Figure 1.

Table 1. AMMl User-Configured Components
Description Designation Function

Screw Terminals
DIP Switch Set SlOl A/D Converter range

All local input signals are applied to screw terminals, which are designed to accept
16-24 gage wire stripped 3116 of an inch.

Local inputs, channels O-7

Document Number: 500-910-01 F&v. B

AMMl-1

A/D CONVERTER

RANGE SELECTION

I

6

ii

D

AMMI LOCAL

INPUT TERMINALS

END
C’H7
‘i-IS
c’ti5
C’H4

dH3

di2
C-H 1
C’HO

END

PI77

\ /

PI78

Switch SlOl controls the input range of the A/D converter located on the module.
Available bipolar ranges include
unipolar ranges are 0 to +lOV and 0 to +5V.

Connection
Local input signals for channels 0 through 7 of the AMMl are applied to screw ter-

minals located at the back edge of the board. The channel numbers are marked on the
board and are shown in Figure 1. Typical connections for channel 0 are shown in
Figure 2. Note that the high side of the input signal is applied to the channel 0 ter­minal, and the low side of the signal is connected to module ground.

-10 to +lOV, -5 to +5V, and -2.5 to +2.5V. The

0

0
0
0
0
0
0
0

I

Figure 2. Typical Connection (Channel 0 Shown)

CAUTION: AMMl inputs are non-isolated, meaning that one side of the input is con­nected to power line ground. Any signal connected to the AMMl must also be
referenced to power line ground, or module or system damage may occur. Also note
the inaccuracies on other channels may result.

In many situations, shielded cable may be required to minimize EM1 radiation, or to
keep noise to a minimum. If shielded cable is used, connect the shield to ground only,

and do not use the shield as a signal carrying lead. Usually, a module ground terminal
should be used, but in some cases better results may be obtained by using one of the
baseboard ground posts instead. Use the configuration that results in the lowest noise.

For shielding to be effective, the shield must contain both high and low signal wires,

and must not carry any other signals. If a number of AMMl signal input lines are
shielded, all shields should be connected to the same ground terminal.

AMMl-3

A/D Converter Range Selection
As shipped, the Ah&I1 is set up for the i-1OV range, but the module may be recon-

figured to one of four other ranges by setting the five DIP switches located on SlOl to
the correct positions, as summarized in Table 2. To set the A/D converter to a specific
range, first turn off system power and then set the switches to the correct positions,
either open (off) or closed (on). For example, for the 0 to +5V range, switches 1, 3 and
4 should be closed (on), and switches 2 and 5 should be open (off).

NOTE: The module must be recalibrated if the range is changed. Turn to the Calibra­tion Section of this chapter for AMMl calibration information.

Table 2. 901 Settings for the A/D Converter Ranges

DIP Switches

Input Range 1

-10 to +lov*

-5 to +5v Open Open Closed Open Closed

-2.5 to +2.5V Open
0 to +5v
0 to +lov

*Factory default value
NOTE: A/D converter must be recalibrated if range is changed.

Open Closed Open Open Closed

Closed Open
Closed Open Closed Open Open

2

Open Closed Closed Closed

3

Closed Closed Open

4 5

Signal Conditioning
A simplified block diagram of the AMMl is shown in Figure 3. The module is divided

into four general sections: a local multiplexer, a global multiplexer, a programmable gain
amplifier (PGA) and a XI-bit AID converter.

Local input signals from channels 0 to 7 are applied to the local multiplexer for selec­tion. At any given time, only one channel will be selected, as determined by the
SELECT CHANNEL command (covered later in this section). The signal from the
selected channel is then routed to the global multiplexer for further signal selection and
conditioning.

The global multiplexer selects a single signal from among the 10 slots in the signal. In
this manner, signals from any of the Xl slots can be selected by software. The global
multiplexer is controlled by the SELECT SLOT command, discussed later in this
section.

After the signal is selected, the PGA applies software-selectable gains of xl, x2, x5, or
x10. When this signal conditioning process is complete, the signal is routed to the l2-bit
AID converter for digitization. After the conversion process, digital data representing
the applied signal travels via the baseboard and interface card to the host computer.

AMMl-4

INPUTS

FROM OTHER
AIM MODULES
(9 MAXIMUM)

AMMI
LOCAL

INPUTS (8)

1.

\‘.

\

\

r
\

/

\

\-

GLOBAL

- MUX

,

xl, x2, x5OR x10

SOFTWARE

CONTROLLED GAIN

DIGITAL
INFORMATION
TO COMPUTER

Input Filtering
Noise introduced into the input signal can corrupt the accuracy of the measurement.

Such noise will usually be seen as an unsteady reading that jumps around, or, in some
cases, as a constant offset. In the former case, the presence of noise will usually be
quite obvious, but its effects may not be noticeable in the steady-state offset situation.
Regardless of the type of noise, however, such unwanted signals can degrade measure­ment accuracy considerably if enough of the unwanted signal is present.

Frequently, noise is introduced into the signal from 50 or 6OHz power sources. In many
cases, such noise can be attenuated by shielding the input signal lines, as discussed
earlier. In more difficult situations, however, it may be necessary to filter the input
signal to achieve the necessary noise reduction.

When noise is a problem, a single-pole low-pass filter like the one shown in Fiie 4

can be conntected between the input signal and the corresponding AMMl channel.
Note that the filter is made up of a single capacitor and resistor with the capacitor con­nected between the AMMl channel input terminal and the module

The resistor is then placed in series with the high input signal lead.

ground terminal.

1

27iRC

TO AMMl INPUT

7

FROM SIGNAL C

f

-3dB = -

T

Figure 4. Input Filtering

A common yardstick for a simple filter like the one in Figure 4 is the -3dB or half­power point, which is given as follows:

1

f-J, = -

2nRC

AMMl-6

where f is in Hz, C is in farads, and R is in ohms. Above this frequency, filter response
will roll off (decrease) at a rate of -2OdB per decade. Thus, each time the frequency in­creases by a factor of lo, the filter output voltage decreases by a factor of 10 (-20dB).

Although such filtering can quiet down a noisy signal, there is a trade-off in the form
of increased response time. This response time may be important in the case of a rapid­ly changing input signal. For the filter in Figure 4, the response time to 1% of final
value is 4.6RC, while the response time to 0.1% and 0.01% of final value are 6.9RC and

9.2RC, respectively.

As an example, assume that 10 counts of 6OHz noise is present in the input signal. To
reduce the noise to one count, an attenuation factor of I.0 (-20dB) at 6OHz will be
necessary. Thus, the filter should have a -3dB point of 6Hz.

To determine the relative RC values, the above equations can be rearrange to solve for
either R or C. If we wish to choose a nominal capacitor value and then solve for the
resistance, we have:

1

R=

PnCf+fB

Choosing a nominal value of 2$ for C, the necessary resistance is:

1

R=

2n(2

x 10-6)x 6Hz

I? = 13.263k3

The resulting response times with these R and C values would be:

t(l%) = 4.6RC = 122ms
t(O.l%) = 6.9RC = 183ms
t(O.Ol%) = 9.2RC = 244ms

Note that there are a number of RC values that can be used in a given situation. To
minimize the effects of the series resistance, however, it is recommended that the value
of R be kept under 20kQ.

Current-to-Voltage Conversion
AMMl local inputs are designed to accept voltages in the range of flOV. Thus, the

AMMl can be directly connected to many signal sources. Some transducers and in­strumentation, however, provide current outputs that must be converted into voltages in
order to be measured through an AMMl input channel.

When connecting current inputs to the AMMl, a resistor should be installed across the
input to make the necessary current-to-voltage conversion. One end of the resistor
should be connected to the channel input terminals and the other end of the resistor
should be connected to module ground.

AMMl-7

The value of the resistor can be determined from Ohms law as follows:
R = E/I

Where R is the resistance in ohms, E is the maximum desired voltage in volts (usually
the upper range limit of the A/D converter), and I is the maximum anticipated current
in amps.

As an example, assume the AID converter range is 0 to +5V and that the expected cur­rent lies in the range of 4 to 2OmA. The required resistance is:

R

= S/O.02

R

= 25061

Thus, a 25OB resistor should be installed across the input of the channel in question
(note that a 2500 value is required when using Soft500 engineering units conversion).
Since current measurement accuracy is directly related to the accuracy of the resistor,
use the smallest tolerance resistor available (typically &O.l%). Suitable 2503 precision
resistors can be purchased from Dale Resistors, RN. RN55E25008.

Analog-to-Digital Converter Timing
When programmin g high-speed sampling sequences, certain timing constraints concern-

ing the A/D conversion cycle should be kept in mind. When the A/D START command
is issued, the converter immediately begins to assess the value of the signal, a process
that takes from 20 to 25~s to complete. During this period, the sample-and-hold cir­cuitry remains in the hold mode, freezing the signal for the duration of the analog-to­digital conversion process. When the conversion has been completed, the new data is
available for reading, and the sample-and-hold circuitry returns automatically to sample
mode and begins to track the signal once again.

Because the signal may have changed significantly since the beginning of the last con­version, the sample-and-hold circuitry requires some time to adjust to the new signal
voltage level. This time period is known as the “acquisition time” of the sample-and­hold circuitry and is typically 3~ for the AMh41 module. Thus, to ensure accuracy, a
new conversion should not be triggered for at least 3~ following completion of the last
conversion, and a total of 28~s must be allowed from the start of each conversion to the
start of the next one (note that these times are automatically taken into account when
using Soft500).

To increase system throughput, data latches have been provided on the AMMl, making
data from the previous conversion available while the converter is busy processing
another reading. The data is refreshed (updated) as soon as the converter has finished
its current assessment (25~s after a conversion is triggered).

AMMl-8

Using Additional Analog-to-Digital Modules
Some situations may call for the use of an additional A/D converter module in the

system to supplement the A/D capabilities of the AMMl. In particular, it may be
desirable to increase the resolution of the system by using a 14-bit ADM2 A/D converter

in slot 2.

Note that only one AMMl can be used in a given system since that module must be
placed in slot 1.

When using an additional A/D converter module, the analog signal output of the
AMMl will be routed to that module via the daisy chain pathway on the system
baseboard. Thus, it would be possible to process certain analog channels through the
built-in l2-bit A/D converter of the AMMl, and route other, more critical signals
through a separate U-bit ADM2 module located in slot 2.

Commands

Commands used with the AMMl are summarized in Table 3. Note that several com­mands share the CMDA and CMDB locations. The selected command will depend on
whether a read or write operation is performed, as indicated in the table.

Table 3. Commands Used with the AMMl
Command

SELECT CHANNEL
SELECT SLOT CFF81 CMDB (Write)
GLOBAL GAIN CFF9A CMDC
A/D LOW DATA CFFBO CMDA (Read)
AID HIGH DATA CFF81 CMDB (Read)
A/D ST4RT/STATUS CFF9B CMDD

SELECT CHANNEL
Location: CFFBO
The SELECT

AMMl, thus determining which of the local input channels is selected for A/D conver­sion. This command affects only those signals connected to the AMMl local inputs,
and does not affect input channels connected to modules located in other slots.
SELECT CHANNEL must be used in conjunction with the SELECT SLOT command
(discussed below) issued with a value of 1 in order to select slot 1.

To select the desired channel, write the appropriate value to the SELECT CHANNEL
location, as sumfnarize
that value to the SELECT CHANNEL location, from BASIC, this value can be written
with the POKE statement.

CHANNEL command is used to control the local signal multiplexer on the

Address Signal line
CFFBO CMDA (Write)

d in ‘lhble 4. For example, if channel 7 is to be selected, write

Table 4. Values Written to the SELECT CHANNEL Location
Function Binary Hex

Channel0
Channel 1

Channel 2

Channel 3
Channel 4
Channel 5
Channel 6
Channel 7

00000 HO
00001 Hl

00010 H2

00011 H3
00100 H4
OOlOl H5
00110 H6
00111 H7

Decimal

0

1

z
4
5

6
7

AMMl-9

SELECT SLOT
Location: CFF81
The SELECT SLOT command controls the global multiplexer on the AMMl, selecting

the appropriate slot on the Series 500 baseboard from which to read the input channel.

The value to be written to the SELECT SLOT location is always the same as the
number of the slot to be selected, as summarized in Table 5. For example, if a signal
connected to a channel on the AhMl in slot 1 is to be selected, a value of 1 would be
written to SELECT SLOT (the channel must also be selected with SELECT CHANNEL
as discussed previously). Similarly, the values 2-10 would be written for slots 2-10
respectively. The BASIC POKE statement can be used to write the appropriate value to
the SELECT SLOT location.

As indicated in Table 5, there are other values besides slot numbers that can be writeen
to this location. These values select ground, +5V, and +lOV sources and are intended
primarily for diagnostic purposes.

Table 5. Values Written to the SELECT SLUT’ Location
Function.

Ground (0 volts) 0000
Slot 1 0001
Slot 2 oolo
Slot 3 OOll­Slot 4 0100
Slot 5 0101
Slot 6 %l
Slot 7
Slot 8 lOW
Slot 9
Slot l.0

+lOV Reference ml HD 13

Ground (0 volts)

+5V Digital Power Supply 1111

GLOBAL GAIN
Location: CFF9A
The GLOBAL GAIN command controls the PGA (Progammable Gain Amplifier) located

on the AMMl module. Since all analog inputs are processed by the PGA, the GLOBAL

GAIN command affects every analog input connected to the Series 500. To avoid ran-

dom gain factors, this command must be issued at least once after the Series 500 has
been powered on. Once the gain value has been selected, it is not necessary to reissue

GLOBAL GAIN unless a different PGA gain is desired. The gain factor may, however,
be updated before each A/D conversion, as required.

Binary Hex Decimal

HO 0
Hl 1
H2 2
H3 3
H4 4
H5 5
H6 6
H7 7
H8 8

9

E
lllo HE 14

FE lo

HE 15

Ahall-10

Four programmable gain values, xl, x2, x5, and x10, are available with the PGA. These
gains are selected by writing the appropriate number to the GLOBAL GAIN location, as

summarized in Table 6. The BASIC POKE statement can be used to write to the desired

GLOBAL GAIN location. For example, to select a PGA gain of x5, the value 2 would be
written to the GLOBAL GAIN location.

Table 6. Values Written to the GLOBAL GAIN Location
PGA Gain Binary Decimal

xl 00 0
x2 01 1
x5 10

Xl0

11

2
3

A/D LOW DATA
Location: CFFSO
The A/D LOW DATA location is used to read the low byte of the results of the A/D

conversion process. Since the module incorporates data latches, one conversion may be
read while another conversion is in progress. To find out when data from one conver­sion is available, use the A/D S‘IARTKMTLJS command, discussed below.

A/D LOW DAL4 shares the CMDA location with the SELECT CHANNEL command.
Thus, A/D LOW DAM is a read-only command; do not attempt to write to A/D LOW
DAYI& as this may change the selected channel. To read AID LOW DATA from BASIC,
use the PEEK statement with the appropriate address in the argument.

AID HIGH DNA
Location: CFF8l
The A/D HIGH DATA command performs essentially the same function as the A/D

LOW DATA command, except that the high data byte is returned.

A/D HIGH DATA is a read-only command that shares the CMDB location with SELECT

SLOT. Any attempt to write to A/D HIGH DATA may alter the selected slot and give er-

roneous results.

Since the AMMl has a l2-bit converter, the four most significant bits of the high byte

returned by A/D HIGH DATA are not used. These four most significant bits will always
be set high and should be masked out when interpreting the reading. From Pascal or
BASIC, masking can be done by subtracting 240 from the high byte value (240 is the
value of the four most significant bits when all are high). From assembly language,

masking the high byte of the returned data can be performed by ANDing with HOE

Doing so will change the four most significant bits form ls to OS.

Once both the low and the high data bytes have been obtained, the total number of

counts representing A/D converter data can be determined with the following BASIC
formula:

CO = DL + 256*(DH-240)

CO represents the number of counts, and DL and DH are the low and high bytes

respectively. Since the AMMl uses a l2-bit converter, the number of counts will lie in

the range of 0 to 4095.

AMMl-11

A/D START/STATUS
Location: CFF9B
The A/D START/ST4TLJS command has two functions: to start the A/D conversion pro-

cess, and to determine whether or not the AID converter is busy processing a reading.

Writing to the A/D START/S’IATLJS location will trigger (start) the A/D conversion cycle.
Although any value (O-255) can be written to trigger a conversion, a value of 255 should

be used to

The A/D conversion cycle takes approximately 25~s. During this period, the converter

should not be re-triggered. Status of the converter can be checked by reading the A/D
START/STATLJS location. The returned value will depend on whether the converter is

ready or busy (see Table 7). To allow sufficient sample-and-hold settling time, a new

conversion should be triggered less than 3~s after the previous conversion has been

completed.

Table 7. Values Read from the A/D START/STATUS Location

minimize noise.

Calibration

,

Converter Status
Busy

Ready 01111111

This section contains calibration procedures for the AMMl module. Note that these pro­cedures are intended for use in the field and may not be as accurate as those used at
the factory. Calibration accuracy depends both on the accuracy of the equipment used
in the procedure as well as the skill of the individual. If you are not familiar with
calibration equipment, do not attempt AMMl calibration.

Environmental Conditions
Calibration should be performed at an ambient temperature of 23°C (f5”). Turn on the

system power and allow it to warm up for at least 10 minutes before beginning the
calibration procedure.

Recommended Calibration Equipment

The following equipment is recommnded for AMMl calibration. Other equipment may
be used as long as the corresponding specifications are at least as good as those given
below.

Binary HeX Decimal
llllllll 255

H7F 127

AMMl-12

1. Keithley Model 192 DMM (0.005% basic DC accuracy).

2. EDC Model ElOOC Millivolt Reference Source (0.005% accuracy).

Calibration Procedures

Use the following procedures to calibrate the PGA, A/D converter, and lOV reference

source located on the AMMl card. Note that the PGA must be properly calibrated

before attempting A/D converter calibration. Adjustments, test points, and input con-

nections axe shown in Figure 5.

PGA Offset Adjustment
Use the following procedure to null out any offset present in the PGA.

1. Connect a jumper wire between the channel 0 input terminal and a module ground
terminal.

2. Connect the DIviM high input lead to TP1 (output of the PGA). Connect the DMM
low lead to a module ground terminal. Select DCV and autoranging.

3. POKE the SELECT CHANNEL location (CFFBO) with a value of 0 in order to select
channel 0. POKE the SELECT SLOT location (CFR31) with a value of 1 in order to
select slot 1.

4. Select a PGA gain of xl.0 by POKEing a value of 3 to the GLOBAL GAIN location
(=W

5. Adjust the PGA offset control (Rll5) for a reading of 0.08OV on the DMM.

6. Remove the jumper wire connected between channel 0 and ground.

A/D Converter Calibration
Use Program 1 below as an aid in the following A/D converter calibration procedure.

Note that the converter must be recalibrated if the range is changed. Switch positions,
and applied signals for the offset and gain calibration points are summarized in Table 8.

1. Select the A/D converter range to be calibrated by setting the switches to the correct

positions, as indicated in Table 8.

2. Connect the DC calibrator high signal lead to the channel 0 input terminal. Connect
the low calibrator signal lead to module ground. Use shielded cable, but do not use
the shield as a signal-carrying lead. Connect the shield to module ground only.

3. Enter and run Program 1 below.

4. Set the calibrator output voltage to the offset calibration voltage for the selected
range, as outlined in Table 8. For example, on the 0 to +lfJV range, apply 0.0024V.

5. Adjust the A/D conveter offset control 01107) for a reading of 1 count on the com­puter CRT.

6. Set the DC calibrator to the gain calibration voltage listed in Table 8 for the selected
range. For example, on the 0 to +lOV range, the correct value is 9.9951V.

7. Adjust the A/D control (RlO8) for a reading of 4094 counts on the computer CRT.

8. Re 2 eat steps 4 through 7 until no further change is seen when changing from the
o set value to the gain value.

AMM14.3

PGA OFFSET

1 OV REFERENCE

DC CALIBRATION

VOLTAGE

TPI (PGA OUTWT)

TP3 (1OV REFERENCE)

Program L AMMl A/D Converter Calibration

10

20 POKE A,O:POKE B,l:POKE C,O
30 POKE D,255
40 DL = PEEK(A):DH = 256 * (PEEK(B) - 240)
50 R = DL + DH
60 PRINTR
70 GOID 30

l’hble 8. A/D Converter Ranges and Calibration Values

Ranfze

-10 to +lov

-5 to +5v 0 0 C 0 C -4.9976V

-2.5 to +2.5V 0 0 C C C -2.4988V
0 to +5v C 0 C C 0 +O.OOUV
0 to +lov c 0 c 0 0 +o.O024v

*C = Closed; 0 = Open

l(rv Reference Source Calibration

The XIV reference source is used by some other modules in the system as an accurate

DC reference. Thus, n&calibration of this source could affect measurement accuracy of
those modules. Use the following procedure to adjust the XIV reference.

DEF SEG = &HCFFO:A = &HBO:B = &HBl:C = &H9A:D = &H9B

DIP

Switches* Offset

1 2 3 4 5 (1 count)

ocooc

Applied Voltage

Gain
a094 counts)

-9.9951v +9.9902V
+4.9951V
+2.4976V
+4.9976V
+9.9951v

1. Connect the DMM high lead to Tl?3 on the module. Connect
the DMM low lead to module ground.

2. Select DCV and set the DMM to the 2OV or similar range.

3. Adjust the +lOV source adjustment (Rll6) for a reading of exactly lO.OOOV on the
DMM.

Theory of Operation

For the following discussion, please refer to the schematic diagram located on drawing
number 500446.

AMMl circuitry is divided into four sections: local analog selection circuitry, global
selection and conditioning circuitry, analog-to-digital conversion circuitry, and 1OV
reference.

Local circuitry

Local selection circuitry is made up of ICs UlO9 and Ullg. Ull.8 is an eight channel
analog multiplexer IC (6108). Local analog inputs from channels O-7 are applied to the
screw terminals through input protection resistors (Rll7) to the Sl-S8 inputs of UlB.
The output of the local multiplexer is applied to the global multiplexer discussed below.

AMMl-15

The local multiplexer is controlled by Ul.09, a quad transparent latch (74LS75). This latch
is controlled by both the CMDA and R/W lines. When both these lines are low

(as
when the SELECT CHANNEL command is executed), data contained on the DO
through D2 lines is latched into UllB, thus selecting the channel determined by the
condition of those three data lines.

Global Circuitry
Global circuitry on the AMMl consists of a &channel analog multiplexer and a pro-

grammable gain amplifier @‘GA). The multiplexer selects among the 10 slots in the
system, while the PGA applies selectable xl, x2, x5, or xl0 gain values to all analog
signals input to the system.

Ul19, a l6-channel multiplexer (6ll6), provides the global selection for the Series 500.
Ten Ull9 inputs are from slots 1 to 10, while other inputs allow selection of analog
ground, +5V digital, or +lOV reference signals. The multiplexer IC is controlled by

U117, a quad transparent latch (74LS75). This latch is controlled by the CMDB and R/W
lines through Ull2. When CMDB and R/W are both low (as when the SELECT SLUT
command is executed), the data contained on the DO and D3 data lines will be latched
into U117, selecting the appropriate slot or signal via Ul19.

The output of the global multiplexer is applied to the PGA, Ulll. The gain of this
operational amplifier can be set to one of four values: xl, x2, x5, or xl0. The gain of the
amplifier is given by:

A

= 1 + R&

where RF and RI are elements of Rll3. The exact configuration of these elements is
determined by Ull5. For example, when x5 gain is selected, only S3 in Ul’l5 is closed.
Thus, Rx has a value of 16k0, and R1 has a value of 4kQ. From the above formula, it
can be seen that the correct gain value of x5 will be applied under these conditions.

The gain circuitry is controlled by U116, a quad transparent latch (74LS75). This latch is
controlled by the CMDC lines of the baseboard. When the GLOBAL GAIN command is
issued, the data contained on DO and Dl is latched into Ull5, thereby setting the PGA
gain to the programmed value.

AID Converter
The ou

ut of the PGA is applied to the sample-and-hold circuitry (U107). The hold
this IC is triggered on receipt of the A/D STARTISTATUS command. It stays in

tp mode o
hold until the status line of the A/D converter goes low, indicating conversion is
complete.

From the sample-and-hold circuitry, the signal is routed to S101, which sets the A/D
converter range. From SlOl, the signal travels to the A/D converter input terminals

(UlOl) .

AMMl-16

The l2-bits of the converter outputs are inverted by elements of U102 and UlO5 and ap­plied to t&state latches, Ul.03 and Ul.06 (74LS374). These latches are controlled by the
R/W, CMDA, and CMDB lines via elements of Ull3. When R/W is high, the appropriate
latch will be enabled, depending on whether CMDA or CMDB is low. U103 will be
enabled when CMDA is low, thus allowing the low data byte to be placed on the data
bus. In a similar manner, the high data byte (of which only four bits are
used) will be placed on the data bus when U106 is enabled by setting CMDB low.

Calibration potentiometers Rl(n and R108 provide the offset and gain, respectively, of
the A/D converter. The sample-and-hold needs no offset adjustment because the A/D
converter offset adjustment has sufficient range to compensate for both offsets.

lOV Reference
The lOV source located on the AMMl is used by other Series 500 modules, such as the

AIM3 and AIM7 The reference circuitry consists of U114 and associated components.
The output of the lOV reference is applied to the slot connector as well as to the global

multiplexer located on the AMMl.

VRlOl, a zener diode, provides a stable voltage reference for the 1OV reference circuitry.
Ul14 acts as a constant current source to keep zener voltage variations to a minimum.
Adjustment of the voltage output is performed by Rll6, which has a limited range of

adjustment.

Troubleshooting Information

Use the information contained in Table 9 to troubleshoot the AMMl. To read back
digital data from the module, use the program located in the calibration section. The in-

formation contained on the component layout drawing (500440) and schematic diagram

(500446) will also be an essential aid in troubleshooting.

Replacement parts for the AMMl can be obtained from Keithley Data Acquisition and

Control. Part numbers are listed on the component layout drawing.

AMMl-l7

Table 9. AMMl Troubleshooting

Step Item/Component Required Condition

1

AMMl module

2

Computer
Computer

ii

Computer

5

Channel 0
Tl?l

6
7

Channel 0

8

Computer

9

Tl?l

10

Channel 0 input

11

Computer

12

TPl

13

Channel 0

14

Computer

15

TPl

lf-

Channel l-7
inputs

17

TI?l

18

Channel 0 input

19

Computer

20

Computer

21

Channel 0
Computer Read back 0 counts

Channel 0 value Apply 4095 count converter

24 Computer

Install in slot 1
POKE SELECT CHANNEL
with 0
POKE SELECT SLOT with 1 Select slot 1
POKE GLOBAL GAIN with 0
Apply +lOV input

+lOV
Apply +5V input
POKE GLOBAL GAIN with 1

+lov
APPlY +2V

POKE GLOBAL GAIN with 2

+lov
Apply +lV input
POKE GLOBAL GAIN with 3

+lOV
Apply +lV

+lOV

Repeat steps 5-17 with negative
voltages
POKE GLOBAL GAIN with 0
POKE SELECT CHANNEL
with 0
Apply 0 count value

range
Read back 4095 counts

Remarks
Turn power on

Select channel 0

xl gain
Reference to ground
Reference to ground

x2 gain

x5 gain

x10 gain

POKE SELECT CHANNEL

xl gain
Select channel 0

Depends on A/D converter
range
Use Program 1
Depends on A/D

Use Program 1

AMMl-18

AMMl Specificatilons

Input channels

Global: 8 inputs from slots 34.0

Local: 8 single-ended

Global programmable gain amplifier:

Software Programmable gains: xl, x2, x5, xl0

Input range:

xl, flov
x2, i5V
6 *w

x10, *lV
Accuracy: f(0.0146 + 5OpV)
Non-Iinearity: *0.005% of fuII scale
Temperature coefficient: *(O.OOl% + 2OpVPC
Input noise voltage: 3O$J p-p, O.lHz to 1OkHz
Settling time to 0.01%: 6~s
SmaII signal bandwidth: 28OkHz

Analog-to-Digital converter

Resolution: 12 bits, 1 part in 4096
Input ranges: f2.5V, f5V &XIV, 0 to +5V, 0 to +lOV
Nonlinearity: rtO.O2!5% (kl lsb)
Nonlinearity temperature coefficient: ltO.O03%PC
Accuracy*: &(0.03% + 1 lsb)
Accuracy temperature coefficient: 1t(O.O035% fO.ll 1 Isb)/“C

Sample-and-hold acquisition time: 5~s
Conversion time: 25p max

Global lO.OOOV reference

Accuracy: i-0.01%
Temperature coefficient: fO.O02%/“C
Load current: 1OmA max
Noise:

20/.&v p-p, o.lHz to lOH2

lopv RMS, loHz to 3okHz

NOTE: Ah amplifier specifications are with respect to input.
*Includes nonlinearity.

AMMl-19

AMM1-20

AMMI COMPONENT LAYOUT

PART IQ. ITEM PUT “0.

SC”EY.

OESl6.

.?OflE

86 DENOTES SELECTED Y&WE.

I

iG IIC-371

60

IIC-I86 1 1 83

I
1 UIOI / EZ

UlO2

94 I

95 IMC-285

nC I I 4

11s 1

I19 I

120 1

I I
1 IREQ’DI F2

I !I’

I

AMMl SCHEMATIC DIAGRAM

AhthCl-23/AMM1-24