Tektronix Fully Buffered DIMM (FB-DIMM) User manual
Reference
Fully Buffered DIMM (FB-DIMM)
Methods of Implementation (MOI)
071-1773-00
www.tektronix.com
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Table of Contents
1 Introduction to RT-Eye FB-DIMM Compliance Module......................1
2 FB-DIMM Compliance Measurements...................................................1
2.1 Common Specifications between Transmitter and Receiver.................1
2.2 Differential Transmitter (TX) Output Specifications ............................2
2.3 Differential Transmitter (TX) Compliance Eye Diagrams....................4
2.4 Differential Receiver (RX) Input Specifications..................................... 5
2.5 Receiver Compliance Eye Diagrams........................................................7
2.6 Reference Clock Specifications ................................................................8
3 Preparing to Take Measurements..........................................................11
3.1 Required Equipment............................................................................... 11
3.2 Probing Options for Transmitter testing ..............................................11
3.2.1 SMA Connection...........................................................................11
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3.2.2 AMB Ball connection....................................................................12
3.3 Initial Oscilloscope Setup........................................................................ 13
3.4 Running the RT-Eye Software............................................................... 13
3.5 Clock Recovery........................................................................................14
4 FB-DIMM Receiver (RX) Compliance Testing....................................14
4.1 Probing the Link for RX Compliance ...................................................14
4.2 Running a Complete RX Compliance Test ...........................................15
4.2.1 RX Differential Pk-Pk Input Voltage MOI ................................16
4.2.2 Minimum RX Eye Width MOI.................................................... 17
4.2.3 RX AC Common Mode Input Voltage MOI...............................18
4.2.4 RX DC Common Mode Input Voltage MOI...............................18
4.2.5 RX Waveform Eye Diagram Mask Test MOI............................19
4.2.6 RX Input Rise/Fall Time test MOI..............................................20
4.2.7 RX Tj Test MOI............................................................................ 21
4.2.8 RX Dj Test MOI (Using Dual-Dirac Method)............................22
5 FB-DIMM Transmitter (TX) Compliance Testing ..............................23
5.1 Probing the Link for TX Compliance.................................................... 23
5.1.1 TX Compliance Test Load ...........................................................23
5.2 Running a TX Compliance Test.............................................................24
5.2.1 TX Differential Pk-Pk Output Voltage MOI..............................26
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5.2.2 TX De-Emphasized Differential Output
Voltage (Ratio) MOI
5.2.3 Minimum TX Eye Width MOI.................................................... 31
5.2.4 TX Output Rise/Fall Time MOI.................................................. 32
5.2.5 TX AC Common Mode Output Voltage MOI............................34
5.2.6 TX DC Common Mode Voltage MOI ......................................... 35
5.2.7 TX Waveform Eye Diagram Mask Test MOI............................36
5.2.8 TX Dj Dual-Dirac MOI ................................................................37
.....................................................................29
6 FB-DIMM Reference Clock Compliance Testing ................................38
6.1 Probing the Link for Reference Clock Compliance............................. 38
6.2 Running a Complete Reference clock Compliance Test...................... 38
6.2.1 Reference Clock Frequency Measurement Test MOI............... 40
6.2.2 Reference Clock Differential Voltage Hi and Lo Test MOI......41
6.2.3 Reference Clock Differential rise and fall edge rates test
MOI
................................................................................................42
6.2.4 Reference clock Duty cycle test MOI ..........................................43
6.2.5 Reference Clock Jitter RMS Test MOI....................................... 43
7 Giving a Device an ID..............................................................................44
8 Creating a Compliance Report...............................................................44
ii Fully Buffered DIMM (FB-DIMM)
Methods of Implementation
1 Introduction to RT-Eye FB-DIMM Compliance Module
This document provides the procedures for making FB-DIMM compliance measurements with
Tektronix TDS6604B, TDS6804B, TDS7704B, TDS6124C, and TDS6154C oscilloscopes. The
FB-DIMM Compliance Module (
Data Compliance and Analysis application (
Module provides amplitude, timing, and jitter measurements described in Section 3 of Revision 0.7 of
the FB-DIMM Draft Specification dated May 10, 2005. (For Compliance testing of FB-DIMM signals
(3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s) a minimum oscilloscope BW of 12 GHz is required. Using an
8 GHz BW oscilloscope, you can test the 3.2 GB/s FB-DIMM signals for compliance)
All references to the Draft Specification are to Revision 0.7 of the FB-DIMM Draft Specification. In
the subsequent sections, step-by-step procedures are described to help you perform FB-DIMM
measurements. Each measurement is described as a Method of Implementation (MOI). For further
information, refer the Compliance checklists offered to JEDEC members at
Opt. FBD) is an optional software plug-in to the RT-Eye Serial
Opt. RTE-Version 2.0). The FB-DIMM Compliance
www.jedec.org.
2 FB-DIMM Compliance Measurements
Electrical Specifications for FB-DIMM are provided in Section 3 of the Draft Specification. Most of
the measurements are available in the FB-DIMM Compliance Module.
2.1 Common Specifications between Transmitter and Receiver
The TX and RX PLLs shall obey the bandwidth and jitter peaking specifications in the following
table for continuous transmission operation.
Table 1: PLL Specification for TX and RX
Fully Buffered DIMM (FB-DIMM) 1
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2.2 Differential Transmitter (TX) Output Specifications
See the Draft Specification for additional notes and a test definition.
Table 2: Summary of Differential Transmitter Output Specifications (Sheet 1 of 2)
2 Fully Buffered DIMM (FB-DIMM)
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Table 2: Summary of Differential Transmitter Output Specifications (Sheet 2 of 2)
NOTES:
1. Specified at the package pins into a timing and voltage compliance test load. Common-mode measurements to be
performed using a 101010 pattern.
2. The transmitter designer should not artificially elevate the common mode in order to meet this specification.
3. This is the ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of
the first bit after a transition.
4. De-emphasis will be disabled in the calibration state.
5. Includes all sources of AC common mode noise.
6. Single-ended voltages below this value that are simultaneously detected on D+ and D- are interpreted as the electrical
idle condition.
7. Specified at the package pins into a voltage compliance test load. Transmitters must meet both single-ended and
differential output EI specifications.
Fully Buffered DIMM (FB-DIMM) 3
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8. This specification, considered with VRX-IDLE-SE-DC, implies a maximum 15 mV single-ended DC offset between TX
and RX pins during the electrical idle condition. This in turn allows a ground offset between adjacent FB-DIMM agents
of 26 mV when worst case termination resistance matching is considered.
9. The maximum value is specified to be at least (VTX-DIFFp-p L / 4) + VTX-CM L + (VTX-CM-ACp-p / 2)
10. This number does not include the effects of SSC or reference clock jitter.
11. Defined as the Dual-Dirac deterministic jitter as described in Section 4.
12. Pulse width measured at 0 V differential.
13. One of the components that contribute to the deterioration of the return loss is the ESD structure, which needs to be
carefully designed.
14. The termination small signal resistance; tolerance across voltages from 100 mV to 400 mV shall not exceed ± 5 and
with regard to the average of the values measured at 100 mV and at 400 mV for that pin.
15. Lane to lane skew at the transmitter pins for an end component.
16. Lane to lane skew at the transmitter pins for an intermediate component (assuming zero Lane to Lane skew at the
receiver pins of the incoming PORT).
17. This is a static skew. An FB-DIMM component cannot change its lane to lane phase relationship after initialization.
18. Measured from the reference clock edge to the center of the output eye. This specification must be met across
specified voltage and temperature ranges for a single component. Drift rate of change is significantly below the
tracking capability of the receiver.
19. BER per differential lane. Refer to Section 4 for a complete definition of Bit Error Ratio.
2.3 Differential Transmitter (TX) Compliance Eye Diagrams
Refer Section 3.3.1 of the Draft Specification for eye diagram definition.
Figure 1: Transmitter output eye specifications, with and without de-emphasis
4 Fully Buffered DIMM (FB-DIMM)
2.4 Differential Receiver (RX) Input Specifications
See the Draft Specification for additional notes and test definitions.
Table 3: Summary of Differential Receiver Input Specification (Sheet 1 of 2)
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Fully Buffered DIMM (FB-DIMM) 5
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Table 3: Summary of Differential Receiver Input Specification (Sheet 2 of 2)
NOTES:
1. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be
lower than at the pin.
2. Single-ended voltages below that value that are simultaneously detected on D+ and D- is interpreted as the Electrical
Idle condition. Worst case margins are determined by comparing EI levels with common mode levels during normal
operation for the case with transmitter using small voltage swing. See Figure 3-16 and Figure 3-17.
3. Multiple lanes need to detect the EI condition before the device can act upon the EI detection.
4. Specified at the package pins into a timing and voltage compliance test setup.
5. Receiver designers may implement either single-ended or differential EI detection. Receivers must meet the
specification that corresponds to the implemented detection circuit.
6. This specification, considered with V
and RX pins during the electrical idle condition. This in turn allows a ground offset between adjacent FB-DIMM agents
of 26 mV when worst case termination resistance matching is considered.
7. See Figure 3-13 and Figure 3-14. The single-pulse mask provides sufficient symbol energy for reliable RX reception.
Each symbol must comply with both the single-pulse mask and the cumulative eye mask.
8. See Figure 3-15. The relative amplitude ratio limit between adjacent symbols prevents excessive inter-symbol
interference in the Rx. Each symbol must comply with the peak amplitude ratio with regard to both the preceding and
subsequent symbols.
9. This number does not include the effects of SSC or reference clock jitter.
10. This number includes setup and hold of the RX sampling flop.
11. Defined as the Dual-Dirac deterministic timing error as described in Section 4.
12. Allows for 15 mV DC offset between transmit and receive devices.
13. The received differential signal must satisfy this ratio as well as the absolute maximum AC peak-to-peak common
mode specification. For example, if VRX-DIFFp-p is 200 mV, the maximum AC peak-to-peak common mode is the
lesser of (200 mV *0.45 = 90 mV) and VRX-CM-ACp-p.
14. One of the components that contribute to the deterioration of the return loss is the ESD structure that needs to be
carefully designed.
TX-IDLE-SE-DC, implies a maximum 15 mV single-ended DC offset between TX
6 Fully Buffered DIMM (FB-DIMM)
15. The termination small signal resistance; tolerance across voltages from 100 mV to 400 mV shall not exceed ± 5 Ω with
regard to the average of the values measured at 100 mV and at 400 mV for that pin.
16. This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter output
skew from the component driving the signal to the receiver. This is one component of the end-to-end channel skew in
the AMB specification.
17. Measured from the reference clock edge to the center of the input eye. This specification must be met across
specified voltage and temperature ranges for a single component. Drift rate of change is significantly below the
tracking capability of the receiver.
18. This bandwidth number assumes that the specified minimum data transition density. Maximum jitter at 0.2 MHz is 0.05
UI, see Section 4 for full jitter tolerance mask.
19. The specified time includes the time required to forward the EI entry condition.
20. BER per differential lane. Refer to Section 4 for a complete definition of Bit Error Ratio.
2.5 Receiver Compliance Eye Diagrams
See Section 3.4.1 of the Draft Specification for eye diagram definition.
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Figure 2: Receiver input eye voltage and timing specifications
Fully Buffered DIMM (FB-DIMM) 7
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2.6 Reference Clock Specifications
See the Draft Specification for additional notes and test definitions.
Table 4: Summary of Reference Clock Input Specifications (Sheet 1of 2)
8 Fully Buffered DIMM (FB-DIMM)
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Table 4: Summary of Reference Clock Input Specifications (Sheet 2 of 2)
NOTES:
1. The nominal reference clock frequency is determined by the data frequency of the link divided by 2 times the fixed
PLL multiplication factor for the FB-DIMM channel (6:1). f
on.
2. Measured with SSC disabled. Enabling SSC will reduce the reference clock frequency as described in Section 3.1.2.
3. Not all FB-DIMM agents will support all frequencies; compliance to the frequency specifications is only required for
those data rates that are supported by the device under test.
4. Measurement taken from single-ended waveform.
5. Measurement taken from differential waveform.
6. Defined as the maximum instantaneous voltage including overshoot. See Figure 3-3.
7. Defined as the minimum instantaneous voltage including undershoot See Figure 3-3.
8. Measured at the crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the
falling edge of REFCLK-. See Figure 3-3.
9. Refers to the total variation from the lowest crossing pint to the highest, regardless of which edge is crossing. Refers
to all crossing points for this measurement. See Figure 3-3.
10. Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the maximum
allowed variance in for any particular system. See Figure 3-4.
11. The majority of the reference clock AC common mode occurs at high frequency (that is the reference clock
frequency).
12. Measured from -150 mV to + 150 mV on the differential waveform. The signal must be monotonic through the
measurement region for rise and fall time. The 300 mV measurement window is centered on the differential 0 V
crossing. See Figure 3-5.
13. Edge rate matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using
a ± 75 mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median
crosspoint is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. The rising
edge rate of REFCLK+ should be compared to the falling edge rate of REFCLK-. The maximum allowed difference
should not exceed 20% of the slowest edge rate. See Figure 3-6.
14. See Figure 3-7. Tstable is the time the differential clock must maintain a minimum ± 150 mV differential voltage after
rising / falling edges before it is allowed to drop back into the ± 100 mV differential range.
15. Measured with a single-ended input voltage of 1 V.
data = 2000 MHz for a 4.0 Gbps FB-DIMM channel and so
Fully Buffered DIMM (FB-DIMM) 9
Methods of Implementation
16. Applies to RefClk and RefClk#.
17. This parameter is not a direct clock output parameter but it indirectly determines the clock output parameter TREFJITTER. This number is valid for 3.2 Gb/s and 4.0 Gb/s operation.
18. Implies a -3 dB bandwidth of 11 MHz and jitter peaking of 3 dB.
19. Implies a -3 dB bandwidth of 33 MHz and jitter peaking of 3 dB.
20. The net transport delay is the difference in time of flight between associated data and clock paths. The data path is
defined from the reference clock source, through the TX, to data arrival at the data sampling point in the RX. The
clock path is defined from the reference clock source to clock arrival at the same sampling point. See Figure 3-8. The
path delays are caused by copper trace routes, on-chip routing, on-chip buffering, etc. They include the time-of-flight
of interpolators or other clock adjustment mechanisms. They do not include the phase delays caused by finite PLL
loop bandwidth because these delays are modeled by the PLL transfer functions. This bandwidth number assumes
the specified minimum data transition density.
21. Direct measurement of phase jitter records over NSAMPLE periods may be impractical. It is expected that the jitter will
be measured over a smaller, yet statistically significant, sample size and the total jitter at NSAMPLE samples
extrapolated from an estimate of the sigma of the random jitter components. For details on this measurement, refer to
Section 4.
22. Measured with SSC enabled on reference clock generator.
23. As “measured” after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the
TRX-Total-MIN parameters.
10 Fully Buffered DIMM (FB-DIMM)
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3 Preparing to Take Measurements
3.1 Required Equipment
The following equipment is required to take measurements:
• TDS6604B or TDS6804B or TDS7704B or TDS6124C or TDS6154C oscilloscope with the
RT-Eye software (Opt. RTE- version 2.0) and FB-DIMM Compliance Module (FBD) installed.
• Probes – probing configuration is MOI specific. Refer to each MOI for correct probe
configuration.
• Test fixture −Tektronix differential probing fixture- NEX-TDSFBDP. To order, click
http://www.busboards.com/products/scopeAccessories/tdsfbdp/index.html.
3.2 Probing Options for Transmitter testing
The first step is to probe the link. Currently, the FB-DIMM specifications have defined the ball of
the AMB as the test point.
3.2.1 SMA Connection
1. Two TCA-SMA inputs using SMA
cables (Ch1) and (Ch3)
The differential signal is created by
the RT-Eye software from the math
waveform Ch1-Ch3. The Common
mode AC measurement is also
available in this configuration from
the common mode waveform
(Ch1+Ch3)/2. This probing technique
requires breaking the link and
terminating into a 50 Ω/side
termination of the oscilloscope. While
in this mode, the FB-DIMM Serdes
will transmit the compliance test
pattern (IBIST Pattern) to maximize
data dependent jitter. Ch-Ch de-skew
is required as two channels are used.
This configuration does not
compensate for cable loss in the SMA
cables. The measurement reference
plane is at the input of the TCA-SMA
connectors on the oscilloscope. Any
cable loss should be measured and
entered into the vertical attenuation
menu for accurate measurements at
the SMA Cable attachment point.
Probe Configuration A
SMA Psuedo-differential
Fully Buffered DIMM (FB-DIMM) 11
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