Tektronix DPO70404, DPO70604, DPO70804, DSA70404, DSA70604 Reference manual

Technical Reference

RT-Eye PCI Express Compliance Module

Methods of Implementation (MOI)

071-2041-00

www.tektronix.com

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Table of Contents

Table of Contents

1 Introduction to the RT-Eye PCI Express Compliance Module.............1

2 PCI Express Compliance Specifications..................................................2

2.1 Differential Transmitter (TX) Output Specifications............................. 3

2.2 Differential Transmitter (TX) Compliance Eye Diagrams ....................4

2.3 Differential Receiver (RX) Input Specifications .....................................5

2.4 Differential Receiver (RX) Compliance Eye Diagrams.......................... 5

2.5 Add-In Card Transmitter Path Compliance Specifications ..................6

2.6 Add-In Card Compliance Eye Diagrams ................................................7

2.7 System Board Transmitter Path Compliance Eye Diagrams ................7

2.8 System Board Compliance Eye Diagrams............................................... 8

2.9 PCI ExpressModule™ Compliance Specifications................................. 8

2.9.1 ExpressModule Add-In Card Transmitter Path Specifications.. 8

2.9.2 ExpressModule System Board Transmitter Path Compliance

Eye Diagrams .............................................................................................9

2.9.3 Express Module System Board Compliance Eye Diagrams...... 10

2.10 PCI Express External Cabling Specifications....................................... 11

2.10.1 External Cabling Transmitter Path Specifications ....................11

2.10.2 Cable (Transmitter Side) Eye Diagrams..................................... 11

2.10.3 External Cabling Receiver Path Specifications ..........................12

2.10.4 Cable (Receive Side) Eye Diagrams............................................. 12

2.11 PCMCIA ExpressCard

2.11.1 ExpressCard - Module Transmitter Path Specifications........... 13

2.11.2 ExpressCard Transmitter Path Eye Diagrams .......................... 13

2.11.3 ExpressCard - Host System Transmitter Path Specifications... 14

2.11.4 ExpressCard – Host System Eye Diagrams ................................14

2.12 Reference Clock Compliance Specifications .........................................15

TM

Specifications ...............................................13

3 Preparing to Take Measurements..........................................................16

3.1 Required Equipment ...............................................................................16

3.2 Probing Options for Transmitter Testing .............................................16

3.2.1 SMA Input Connection................................................................. 17

3.2.2 ECB pad connection...................................................................... 18

3.3 Initial Oscilloscope Setup........................................................................ 19

3.4 Running the RT-Eye Software ...............................................................19

RT-Eye PCI Express Compliance Module i

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3.5 Configuring the Software to take measurements..................................20

4 PCI Express Transmitter Compliance Testing.....................................28

4.1 Probing the link for TX compliance.......................................................28

4.2 TX Compliance Test Load ......................................................................28

4.3 Running a Transmitter (TX) Compliance Test..................................... 29

3.5.1 Select Standard.............................................................................. 20

3.5.2 Select Test Point ............................................................................20

3.5.3 Select Probe Type.......................................................................... 21

3.5.4 Select Measurements..................................................................... 21

3.5.5 Configure Source of Waveforms.................................................. 24

3.5.6 Configure Clock Recovery ...........................................................25

3.5.7 Configure Plots .............................................................................. 27

4.3.1 TX Unit Interval Measurement MOI ..........................................31

4.3.2 TX Differential Pk-Pk Output Voltage MOI.............................. 32

4.3.3 TX De-Emphasized Differential Output Voltage (Ratio) MOI. 34

4.3.4 Minimum TX Eye Width MOI ....................................................35

4.3.5 TX Median-to-Max Jitter MOI.................................................... 36

4.3.6 TX Output Rise/Fall Time MOI ..................................................37

4.3.7 TX AC Common Mode Output Voltage MOI ............................39

4.3.8 TX Delta DC Common Mode Voltage MOI ...............................40

4.3.9 TX Total Jitter@BER MOI .........................................................41

4.3.10 Spectrum Analysis Based Rj/Dj Separation on

Repeating Pattern .................................................................................... 41

4.3.11 Arbitrary Pattern Analysis Based Rj/Dj Separation .................43

4.3.12 TX Deterministic MOI (Using Dual-Dirac Model) ....................44

4.3.13 Rj/Dj Separation Based on Dual Dirac Model............................ 44

4.3.14 TX Waveform Eye Diagram Mask Test MOI ............................45

5 PCI Express Receiver (RX) Compliance Testing..................................46

5.1 Probing the Link for RX Compliance.................................................... 46

5.2 Running a Complete RX Compliance Test ...........................................46

5.2.1 RX Unit Interval Measurement MOI.......................................... 47

5.2.2 RX Differential Pk-Pk Input Voltage MOI................................. 47

5.2.3 Minimum RX Eye Width MOI ....................................................48

5.2.4 RX Median-to-Max Jitter MOI ...................................................49

5.2.5 RX Total Jitter@BER MOI .........................................................50

ii RT-Eye PCI Express Compliance Module

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5.2.6 RX Deterministic Jitter@BER using Dual-Dirac model ...........51

5.2.7 RX Waveform Eye Diagram Mask Test MOI ............................52

6 PCI Express Interconnect Test Point Testing .......................................53

6.1 Unit Interval Measurement MOI ........................................................... 54

6.2 Transition and Non-Transition Bit Eye Height Measurement MOI ..54

6.3 Eye Width Measurement MOI ............................................................... 56

6.4 Interconnect Median-to-Max Jitter and Total Jitter@BER MOI ......58

7 PCI Express Reference Clock Compliance Measurements .................59

7.1 Probing the Link for Reference Clock Compliance .............................59

7.2 Running a Complete Reference Clock Compliance Test ..................... 59

7.2.1 Reference Clock Frequency Measurement Test MOI ...............60

7.2.2 Reference Clock Differential Voltage Hi and Lo Test MOI...... 61

7.2.3 Reference Clock Differential rise and fall edge rates test MOI 62

7.2.4 Reference clock Duty cycle test MOI........................................... 63

7.2.5 Reference Clock Jitter Test MOI................................................. 64

8 Using SigTest............................................................................................65

9 Using Dynamic Test Points .....................................................................68

9.1 Test Point File Syntax.............................................................................. 69

9.2 Creating the New Test Point................................................................... 71

9.3 Running a test with the new DTP........................................................... 72

10 Giving a Device an ID..............................................................................73

11 Creating a Compliance Report...............................................................73

12 Further Analysis Techniques..................................................................73

13 Ensuring Compliance over specified population ..................................74

RT-Eye PCI Express Compliance Module
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Table of Contents

iv RT-Eye PCI Express Compliance Module

Methods of Implementation

1 Introduction to the RT-Eye PCI Express Compliance

Module

1

This document provides the procedures for making PCI Express compliance measurements with Tektronix
TDS6000 Series and TDS7704B, real time oscilloscopes (6 GHz models and above), DPO/DSA70000 series
and probing solutions.

The PCI Express (PCI-E) Compliance Module Version 2.0 (Opt. PCE) is an optional software plug-in to the
RT-Eye Serial Data Compliance and Analysis software (Opt. RTE). The PCI Express Compliance module
provides transmitter path measurements (amplitude, timing, and jitter), waveform mask testing, and
Reference Clock (RefClk) compliance measurements described in multiple variants of the PCI Express
specifications. Specifications covered in this document and the PCE module includes a total of eighteen data
and reference clock test points defined in the following specifications.

Additional test points can also be added by the user, or provided by Tektronix representatives, using
Dynamic Test Point (DTP) definition, described in detail in Section 9. Refer to the release notes (readme.txt)
for information on the additional test point files that may have been added after this release.

Table 1 – Supported Specifications

Test Methods Spec

Revision

Rev1.0a

Rev1.0a Base Specification Transmitter and Receiver

PCI Express Specification Title Test Points Defined

(Section 4.3)

Rev 1.0 Mobile Graphics Lower Power Addendum Transmitter (Section 2.2)

Rev1.0a CEM (Card Electro-Mechanical) Specification System and Add-In Card

(Section 4.7)

Rev 1.0a PCMCIA Express Card Standard Host System Transmitter

Express Card Transmitter

(Section 4.2.1.2)

Rev1.1

1

Disclaimer: The tests provided in the PCI Express compliance module (which are described in this document) do not guarantee PCI Express

compliance. The test results should be considered “Pre-Compliance”. Official PCI Express compliance and PCI-SIG Integrator List qualification
is governed by the PCI-SIG (Special Interest Group) and can be achieved only through official PCI-SIG sanctioned testing.

Rev1.1 Base Specification Transmitter & Receiver

(Section 4.3)

Rev1.1 CEM Specification System and Add-In Card

(Section 4.7)

Reference Clock (Section 2.1)

Rev1.0 Express Module Specification Transmitter Path and System

Board (Section 5.4)

Rev0.4C External Cabling Specification Transmitter and Receiver Path

(Section 3.3)

RT-Eye PCI Express Compliance Module 1

Methods of Implementation

Test Methods Spec

Revision

Gen2

TBD Future 2.5 Gb/s Variants Dynamic Test Points as

Rev0.9 Base Specification Transmitter & Receiver

TBD Future 5 Gb/s Variants Dynamic Test Points as

PCI Express Specification Title Test Points Defined

specifications are defined

(Section 4.4)

Mobile Low Power Transmitter
(Section 4.4)

Reference Clock (Section 4.4)

specifications are defined

Refer to http://www.pcisig.com/specifications/pciexpress/ for the latest specifications.

The PCE module can also be used to automate setup procedures for SigTest by using its SigTest Import
feature (Refer to Section 8).

In this document, for all references to the PCI Express Base Specification and Card Electrical Mechanical
(CEM) specification, refer to all versions of the Spec. (Rev 1.0a, 1.1, and Gen2). Differences between the
specifications are specifically called out when appropriate.

In the subsequent sections, step-by-step procedures are described to help you perform PCI Express
measurements. Each measurement is described as a Method of Implementation (MOI). For further reference,
consult the Compliance checklists offered to PCI-SIG members at www.pcisig.com

.

2 PCI Express Compliance Specifications

As shown in Table 1, Electrical Specifications for PCI Express are provided in multiple documents. This
section provides a summary of the measurement parameters measured in the RT-Eye PCE module and how
they are related to the symbol and test limits in the specification.

2 RT-Eye PCI Express Compliance Module

Methods of Implementation

2.1 Differential Transmitter (TX) Output Specifications

The following table shows the available measurements in the PCE Module and their test limits defined in
each of the Base specifications.

Table 2- Supported base specification transmitter measurements

Parameter Symbol(s)

Specification

Gen1

Rev1.0a

Unit interval UI 400 ps

+/- 300 ppm

Differential p-p TX voltage
swing

Low power differential p-p

V

V

TX-SWING

V

TX-SWING-LOW

pDIFFpTX

−−

Not Specified Not Specified

0.8 V (min)

1.2 V (max)

TX voltage swing

De-emphasized output
voltage ratio

Instantaneous lane pulse

2

width

Transmitter eye including all
jitter sources

Maximum time between the
jitter median and maximum
deviation from the median

Deterministic jitter

RATIODETXV−−

T

t

TX-EYE_TJ

T

T

Not Specified Not Specified 0.9UI (min)

MIN-PULSE

EYETXT−

TX-EYEMEDIAN-to-MAXJITTER

TX-DJ-DD

-3.0 dB (min)

-4.0 dB (max)

.70 UI (min) .75 UI (min) .75 UI (min)

.125 UI (max) .125 UI (max) Not Specified

0.15 UI (max)

Gen1

Rev1.1

400 ps

+/- 300 ppm

0.8 V (min)

1.2 V (max)

-3.0 dB (min)

-4.0 dB (max)

Gen2

Rev0.9

200 ps

+/- 300 ppm

0.8 V (min)

1.2 V (max)

0.4 V (min)

0.7 V (max)

-5.5 dB (min)

-6.5 dB (max)

or

-3.0 dB (min)

-4.0 dB (max)

D+/D- TX output rise/fall
Time 3

AC RMS common mode
output voltage

Absolute delta of DC
common mode voltage
between D+ and D-

T

RISETXT−

V

−

FALLTX

ACpCMTXV−−

DELTALINEDCCMTX

−−−−

0.125 UI (min) 0.125 UI (min) 0.15 UI (min)

20 mV (max) Not Specified Not Specified

0 V (min)

0 V (min)

25 mV (max)

25 mV (max)

25 mV (max)

0 V (min)

2

Instantaneous lane pulse width defined in the Gen2 specification is not supported in the RT-Eye PCI Express Compliance

module. It is recommended that TDSJIT3 Advanced Jitter Analysis Data Period (Min) be used for this measurement.

3

Rise/Fall time measurements in RT-Eye PCI Express Module are compliant to the Rev1.0a and Rev1.1 specification. For Gen2,

rise and fall time is limited to TF2 and TR2 as defined in section 4.3.3.8 of the Base Specification

RT-Eye PCI Express Compliance Module 3

Methods of Implementation

2.2 Differential Transmitter (TX) Compliance Eye Diagrams

Figure 1a shows the eye mask definitions for the Rev1.1 Base specification. It provides an example of a
transmitter mask for a signal with de-emphasis. Transition and non-transition bits must be separated to
perform the mask testing. The amplitude and jitter mask geometries are derived from the amplitude and
jitter specifications. Low power transmitter variants in both Gen1 and Gen2 do not use de-emphasis (This
is shown in Figure 1b).

Figure 1a: Transmitter eye masks for transition and non-transition bits

Figure 1b: Transmitter eye mask for low power variant where de-emphasis is not used

4 RT-Eye PCI Express Compliance Module

Methods of Implementation

2.3 Differential Receiver (RX) Input Specifications

The following table shows the available measurements in the PCE Module and their test limits defined in
each of the Base specifications.

Table 3 – Supported base specification receiver measurements

Parameter Symbol

Gen1

Rev1.0a

Gen1

Rev1.1

Gen2

Rev0.9

Unit interval UI 400 ps

+/- 300 ppm

Minimum receiver eye height

Minimum receiver eye width

Receiver deterministic jitter –
Dj

Maximum time between the
jitter median and maximum
deviation from the median.

V

RX_EYE

EYERXT−

T

RX_DJ_DD

T

TX-EYEMEDIAN-to-MAXJITTER

.175 V (min)

1.2 V (max)

.40 UI (min) .40 UI (min) .40 UI (min)

Not Specified Not Specified .44 UI (max)

.30 UI (max) .30 UI (max)

400 ps

+/- 300 ppm

.175 V (min)

1.2 V (max)

200 ps

+/- 300 ppm

.120 V (min)

1.2 V (max)

Not

Specified

2.4 Differential Receiver (RX) Compliance Eye Diagrams

Figure 2 shows the receiver eye mask definitions for the Rev1.1 Base specification. The amplitude and
jitter mask geometries are derived from the amplitude and jitter specifications.

Figure 2: Receiver input eye mask

RT-Eye PCI Express Compliance Module 5

Methods of Implementation

2.5 Add-In Card Transmitter Path Compliance Specifications

Table 4 is derived from the Electrical Mechanical Specifications (CEM). See the CEM Specification for
additional notes and test definitions.

Table 4 – Supported CEM add-in card measurements

Parameter Symbol Gen1

Gen1

Gen2

Rev1.0a

Unit interval UI 400 ps

+/- 300 ppm

V

V

TXA

TXA_d

.514 V (min)

1.2 V (max)

.360 V (min) .360 V (min) TBD

Eye height of transition
bits

Eye height of non-

Rev1.1

400 ps

+/- 300 ppm

.514 V (min)

1.2 V (max)

TBD

200 ps

+/- 300 ppm

TBD

transition bits

T

Eye width across any
250 UIs

Eye width with sample
size of 106 UI

Jitter eye opening at

-12

BER 10

Maximum median-max

TXA

In Rev1.0a

T

TXA

In Rev1.1

J

TXA-MEDIAN-to-MAX-JITTER

237 ps (min) Not

Specified

Not Specified 287 ps (min) TBD

Not Specified 274 ps (min)

Not Specified 56.5 ps (max) TBD

TBD

TBD

jitter outlier with sample
size of 10

Maximum median-max
jitter outlier with sample
size of 106 UI

6

UI

Not Specified 63 ps (max)

TBD

6 RT-Eye PCI Express Compliance Module

Methods of Implementation

2.6 Add-In Card Compliance Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 4.

Figure 3: Add-in card compliance eye masks

2.7 System Board Transmitter Path Compliance Eye Diagrams

Table 5 is derived from the Electrical Mechanical Specifications (CEM). See the CEM Specification for
additional notes and test definitions.

Table 5 – Supported CEM System Board Measurements

Parameter Symbol Gen1

Rev1.0a

Unit interval UI 400 ps

+/- 300 ppm

V

Eye height of transition bits

TXS

.274 V (min)

1.2 V (max)

V

Eye height of non-transition

TXS_d

.253 V (min) .253 V (min) TBD

Gen1

Rev1.1

400 ps

+/- 300 ppm

.274 V (min)

1.2 V (max)

Gen2

TBD

200 ps

+/- 300 ppm

TBD

bits

T

Eye width across any 250
UIs

Eye width with sample size of

6

10

UI

Jitter eye opening at BER 10

12

Maximum median-max jitter
outlier with sample size of

6

UI

10

Maximum median-max jitter
outlier with sample size of
106 UI

-

TXS

183 ps (min) Not Specified TBD

In Rev1.0a

T

TXS

Not Specified 246 ps (min) TBD

In Rev1.1

Not Specified 233 ps (min)

J

TXA-MEDIAN-to-MAX-

JITTER

Not Specified 77 ps (max) TBD

Not Specified 83.5 ps (max)

TBD

TBD

RT-Eye PCI Express Compliance Module 7

Methods of Implementation

2.8 System Board Compliance Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 5.

Figure 4: System Board Compliance Eye Masks

2.9 PCI ExpressModule™ Compliance Specifications

The specifications in this section are taken from the PCI Express ExpressModule™ specification, which is
a companion specification to the PCI Express Base specification. Its primary focus is the implementation
of a modular I/O form factor that is focused on the needs of workstations and servers. Measurements in the
PCE module support add-in card and system transmitter path measurements at the PCI Express connector.

2.9.1 ExpressModule Add-In Card Transmitter Path Specifications

Table 6 is derived from Section 5.4.1 of the ExpressModule Electro-Mechanical Specifications Rev. 1.0.

Table 6 – Supported ExpressModule Add-In Card Measurements

Parameter Symbol Rev1.0

Unit interval UI 400 ps

+/- 300 ppm

V

Eye height of transition Bits

Eye height of non-transition Bits

Eye width with sample size of 106 UI

Jitter eye opening at BER 10

-12

Maximum median-max jitter outlier
with sample size of 106 UI

Maximum median-max jitter outlier
with sample size of 106 UI

TXA

V

TXA_d

T

TXA

In Rev1.1

J

TXA-MEDIAN-to-

MAX-JITTER

.514 V (min)

1.2 V (max)

.360 V (min)

287 ps (min)

274 ps (min)

56.5 ps (max)

63 ps (max)

8 RT-Eye PCI Express Compliance Module

Methods of Implementation

Figure 5: ExpressModule add-in card compliance eye masks

2.9.2 ExpressModule System Board Transmitter Path Compliance Eye Diagrams

Table 7 is derived from Section 5.4.3 of the ExpressModule Electro-Mechanical Specifications Rev. 1.0.

Table 7 – Supported ExpressModule system board measurements

Parameter Symbol Gen1

Rev1.0

Unit interval UI 400 ps

+/- 300 ppm

V

Eye height of transition bits

TXS

.274 V (min)

1.2 V (max)

V

Eye height of non-transition bits

Eye width with sample size of 106

TXS_d

T

246 ps (min)

TXS

.253 V (min)

UI

Jitter eye opening at BER 10

-12

233 ps (min)

Maximum median-max jitter outlier
with sample size of 10

6

UI

Maximum median-max jitter outlier
with sample size of 10

6

UI

J

TXA-MEDIAN-

to-MAX-JITTER

77 ps (max)

83.5 ps (max)

RT-Eye PCI Express Compliance Module 9

Methods of Implementation

2.9.3 Express Module System Board Compliance Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 7.

Figure 6: ExpressModule system board compliance eye masks

10 RT-Eye PCI Express Compliance
Module

Methods of Implementation

2.10 PCI Express External Cabling Specifications

The specifications in this section are taken from the PCI Express External Cabling Specification. Its
primary focus is the implementation of a cabled interconnect. Measurements in the PCE module support
transmitter path and receiver path measurements. These measurements represent the test points at the
transmitter end of the cable and the receiver end of the cable respectively.

2.10.1 External Cabling Transmitter Path Specifications

Table 8 is derived from Section 3.3.1 of the External Cabling Specification Rev. 0.4C.

Table 8 – Supported external cabling transmitter path measurements

Parameter Symbol Rev0.4C

Unit interval UI 400 ps

+/- 300 ppm

V

V

T

TXA

TXA_d

TXA

.659 V (min)

1.2 V (max)

.456 V (min)

309 ps (min)

296 ps (min)

Eye height of transition bits

Eye height of non-transition bits

Eye width with sample size of

6

10

UI

Jitter eye opening at BER 10

-12

2.10.2 Cable (Transmitter Side) Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 8.

Figure 7: Cable (transmitter side) compliance eye masks

RT-Eye PCI Express Compliance Module
11

Methods of Implementation

2.10.3 External Cabling Receiver Path Specifications

Table 9 is derived from Section 3.3.2 of the External Cabling Specification Rev. 0.4C.

Table 9 – Supported CEM system board measurements

Parameter Symbol Gen1

Rev1.0

Unit interval UI 400 ps

+/- 300 ppm

V

Eye height of transition bits

Eye height of non-transition bits

Eye width with sample size of 106
UI

Jitter eye opening at BER 10

-12

234 ps (min)

RXA

V

RXA_d

T

247 ps (min)

RXA

.219 V (min)

.200 V (min)

1.2 V (max)

2.10.4 Cable (Receive Side) Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 9.

Figure 8: Cable (receiver side) compliance eye masks

12 RT-Eye PCI Express Compliance
Module

Methods of Implementation

2.11 PCMCIA ExpressCard

TM

Specifications

The specifications in this section are taken from the PCMCIA ExpressCard Standard (Release 1.0). Its
primary focus is a small modular add-in card technology based on PCI Express and USB interfaces.
Measurements in the PCE module support host system and ExpressCard transmitter path measurements.

2.11.1 ExpressCard - Module Transmitter Path Specifications

Table 10 is derived from Section 4.2.1.3.2 of the ExpressCard Specification Release 1.0.

Table 10 – Supported ExpressCard transmitter path measurements

Parameter Symbol Release 1.0

Unit interval UI 400 ps

+/- 300 ppm

V

Eye height of transition bits

Eye height of non-transition bits

Eye width across any 250 UIs T

TXA

V

TXA_d

237 ps (min)

TXA

538 V (min)

1.2 V (max)

.368 V (min)

2.11.2 ExpressCard Transmitter Path Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 10.

Figure 9: ExpressCard Module Transmitter compliance eye masks

RT-Eye PCI Express Compliance Module
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Methods of Implementation

2.11.3 ExpressCard - Host System Transmitter Path Specifications

Table 11 from Section 4.2.1.3.2 of the ExpressCard Specification Release 1.0.

Table 11 – Supported ExpressCard Host System Transmitter Path Measurements

Parameter Symbol Release 1.0

Unit interval UI 400 ps

+/- 300 ppm

V

Eye height of transition bits

Eye height of non-transition bits

Eye width across any 250 UIs T

txS

.262 V (min)

1.2 V (max)

V

txS_d

183 ps (min)

TxS

.247 V (min)

2.11.4 ExpressCard – Host System Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 11.

Figure 10: ExpressCard Host System compliance eye masks

14 RT-Eye PCI Express Compliance
Module

Methods of Implementation

2.12 Reference Clock Compliance Specifications

Table 12 is derived from Section 2.1 of the Gen1 Rev1.1 Electrical Mechanical Specifications (CEM) and
Gen2 Base specifications.

Table 12 – Supported reference clock measurements

Parameter Symbol Gen1

Rev1.1

Rise edge rate

Rise Edge Rate

0.6 V/ns (min)

4.0 V/ns (max)

Fall edge rate

Fall Edge Rate 0.6 V/ns (min)

4.0 V/ns (max)

Differential input high voltage

V

IH

150 mV (max) 150 mV (max)

Differential input low voltage VIL -150 mV (min) -150 mV (min)

Absolute period (including jitter
and spread spectrum)

T

PERIOD_ABS

9.847 ns (min)

10.203 ns (max)

Duty cycle Duty Cycle 40% (min)

60% (max)

Maximum peak-peak filtered

Jitter @ 10

-12

BER 108 ps (max) Not

phase jitter

Gen2

Rev0.9

0.6 V/ns (min)

4.0 V/ns (max)

0.6 V/ns (min)

4.0 V/ns (max)

9.997 ns (min)

10.053 ns (max)

40% (min)

60% (max)

Specified

Maximum peak-peak filtered
phase jitter

RMS jitter T

Jitter @ 10-6 BER 86 ps (max) Not

Specified

3.1 ps (max)

CLK_RJ

RT-Eye PCI Express Compliance Module
15

Methods of Implementation

3 Preparing to Take Measurements

3.1 Required Equipment

The following equipment is required to take the measurements:

• Oscilloscope Selection:
ο Gen1 (2.5 Gb/s) – The PCI-SIG recommends a minimum of 6 GHz system BW for Gen1

Measurements. Tektronix models that meet this recommendation include: All the TDS6000B/C
series instruments, TDS7704B, and the DPO/DSA70000 series.

ο Gen2 (5 Gb/s) – It is recommended that >12 GHz system BW is used for Gen2. This ensures that

• RT-Eye software (Opt. RTE) and PCI Express Compliance Module (PCE) installed.

• Probes – Probing configuration is MOI specific. Refer to each MOI for proper probe configuration.

• Test fixture breakout from transmitter to differential SMA connectors. A Compliance Base Board

(CBB) used for add-in card compliance tests and a Compliance Load Board (CLB) used for system
compliance tests are available through the PCI-SIG at the following URL:

http://www.pcisig.com/specifications/ordering_information/ordering_information

• Test fixtures for ExpressCard testing are available from the following URL:

http://www.expresscard.org/web/site/testtools.jsp

th

the 5

harmonic is represented in the measurements. Tektronix models that meet this

recommendation are TDS6000C models.

3.2 Probing Options for Transmitter Testing

The first step is to probe the link. Use one of the following four methods to connect probes to the link.

Table 13 – Example Probing configurations for a PCI express link

16 RT-Eye PCI Express Compliance
Module

Methods of Implementation

3.2.1 SMA Input Connection

1. Two TCA-SMA inputs using SMA
cables (Ch1) and (Ch3)

The differential signal is created by
the RT-Eye software from the math
waveform Ch1-Ch3. The Common
mode AC measurement is also
available in this configuration from
the common mode waveform
(Ch1+Ch3)/2. This probing technique
requires breaking the link and
terminating into a 50 Ω/side
termination of the oscilloscope.
While in this mode, the PCI Express
SerDes will transmit the compliance
test pattern. Ch-Ch de-skew is

Probe Configuration A

SMA Psuedo-differential

required using this technique because
two channels are used. This
configuration does not compensate
for cable loss in the SMA cables. The
measurement reference plane is at the
input of the TCA-SMA connectors
on the oscilloscope. Any cable loss
should be measured and entered into
the vertical attenuation menu for
accurate measurements at the SMA
cable attachment point.

2. One P7300SMA series differential
active probe (Ch1)

The differential signal is measured
across the termination resistors inside
the P7300SMA series probe. This
probing technique requires breaking
the link. While in this mode, the PCI
Express SerDes will transmit the
compliance test pattern. Matched
cables are provided with the probe to
avoid introducing de-skew into the
system. Only one channel of the
oscilloscope is used. The P7300SMA
provides a calibrated system at the

Probe Configuration B

SMA Input Differential Probe

Test Fixture attachment point,
eliminating the need to compensate
for cable loss associated with the
probe configuration A.

RT-Eye PCI Express Compliance Module
17

Methods of Implementation

3.2.2 ECB pad connection

3. Two P7300 series or P7260 active
probes (Ch1) and (Ch3)

The differential signal is created by the
RT-Eye software from the math
waveform Ch1-Ch3. The Common mode
AC measurement is also available in this
configuration from the common mode
waveform (Ch1+Ch3)/2. This probing
technique can be used for either a live
link that is transmitting data, or a link that
has terminated into a “dummy load.” In
both cases, the single-ended signals
should be probed as close as possible to
the termination resistors on both sides
with the shortest ground connection
possible. Ch-Ch de-skew is required
using this technique because two
channels are used.

4. One P7300 series Differential probe

(Ch1)

The differential signal is measured
directly across the termination resistors.
This probing technique can be used for
either a live link that is transmitting data,
or a link that is terminated into a “dummy
load.” In both cases, the signals should be
probed as close as possible to the
termination resistors. De-skew is not
necessary because a single channel of the
oscilloscope is used.

Probe Configuration C

Two Single-Ended Active Probes

Probe Configuration D

One Differential Active Probe

18 RT-Eye PCI Express Compliance
Module

Methods of Implementation

3.3 Initial Oscilloscope Setup

After connecting the DUT by following the proper probing configuration for the test, click DEFAULT
SETUP and then Autoset to display the serial data bit stream.

3.4 Running the RT-Eye Software

1. On non-B or non-C model oscilloscopes (Example: TDS6604), Go to File > Run Application > RT­Eye Serial Compliance and Analysis. For B and C models (Example: TDS7704B, TDS6154C), go to
App > RT-Eye Serial Compliance and Analysis. On DPO/DSA7000 series, go to Analysis> RT- Eye

Serial Compliance and Analysis.

Figure 11: Default menu of the RT-Eye software

Figure 11 shows the oscilloscope display. The default mode of the software is the Serial Analysis module
(Opt.RTE). This software is intended for generalized Serial Data analysis on copper serial data links.

2. Select the PCI Express Compliance Module from the Modules pull-down list.

Figure 12: Choosing PCI Express Compliance Module.

RT-Eye PCI Express Compliance Module
19

Methods of Implementation

Note: If PCI Express does not appear in the list (as in Figure 12), the PCI Express Compliance Module
(Opt. PCE) has not been installed.

The rest of this MOI document details the use of the PCI Express Compliance Module to perform
electrical compliance measurements.

For additional information, refer to the online help for the RT-Eye software available through the Serial
Analysis Module help menu.

3.5 Configuring the Software to take measurements

Before you take compliance measurements, configure the software as follows:

3.5.1 Select Standard

Using the Specification pull-down menu, select the desired specification to be measured.

The selections are:

• Rev1.0a – 2.5 Gb/s

• Rev1.1 – 2.5 Gb/s

• Gen2 – 5 Gb/s

• Use SIG-TEST – refer to Section 8

3.5.2 Select Test Point

Use the Test Point pull-down list to select the desired test point.

Selections in the Test Point menu are dependent on which specification is selected. The selections are as
follows:

If Rev1.0a – 2.5 Gb/s is selected as Standard:

• Receiver

• Driver

• CEM: Add-In

• CEM: System

• ExpressCard Module Tx

• ExpressCard Host Tx

• Mobile LP: Transmitter

• User Defined – Using Dynamic Test Points – See Section 9 for definition

20 RT-Eye PCI Express Compliance
Module

Methods of Implementation

If Rev1.1 – 2.5 Gb/s is selected as Standard:

• Base: Transmitter

• Base: Receiver

• CEM: Add-In

• CEM: System

• Cable: Transmitter

• Cable: Receiver

• ExpressModule: System TX

• ExpressModule: TX Path

• User Defined – Using Dynamic Test Points – See Section 9 for definition

• Reference Clock

If Gen2 – 5Gb/s is selected as Standard:

• Base - Tx -6dB DeEmph

• Base - Tx -3.5dB DeEmph

• Base: Receiver

• User Defined – Using Dynamic Test Points – See Section 9 for definition

• Reference Clock

3.5.3 Select Probe Type

Using the Probe Type pull-down menu, select the desired probing configuration.

The selections are:

• Single-Ended – Select if Pseudo-differential (probing configurations A or C from Section 3.2) is

being used.

• Differential – Select use if true differential (probing configurations B or D from Section 3.2) is being

used.

3.5.4 Select Measurements

In the Measurement > Select menu, select the desired measurements. Measurements can be selected
either manually or as a group by using Select Required. If a measurement has a pass/fail limit associated
with it in the test point file, it will be selected when Select Required is clicked. Measurements with
pass/fail limits will show up in the Results Summary panel when the compliance test is run.
Measurement results of selected measurements, which do not have limits associated with them can be
viewed in the Results Details panel.

RT-Eye PCI Express Compliance Module
21

Methods of Implementation

Figure 13: Measurement Select menu

For Compliance measurements, the following table indicates the PCI Express parameter (listed by
symbol in the specification), the measurement to select in the Measurement Select Menu, and the results
that appear in the Results Summary panel after the compliance test is complete. Refer to the tables in
Section 2 for Pass/Fail limit criteria by specification.

Table 14 – Measurement Select/Result Cross Reference (Transmitter Test Points)

Parameter to

measure

Unit interval UI Unit Interval Unit Interval (Min)

Symbol(s)

Selection in

Measurement > Select

Menu

Results in

Measurement Results Summary

Unit Interval (Max)

Differential p-p TX
voltage swing

Low power
differential p-p TX
voltage swing

De-emphasized
output voltage ratio

Instantaneous lane
pulse width

4

Transmitter eye
including all jitter
sources

Maximum time
between the jitter
median and
maximum deviation
from the median

V

V

TX-SWING

V

TX-SWING-LOW

T

MIN-PULSE

t

TX-EYE_TJ

T

TX-EYEMEDIAN-to-

MAXJITTER

−−

RATIODETXV−−

Not supported in RT-Eye

EYETXT−

pDIFFpTX

Differential Voltage Differential Voltage (Min)

Differential Voltage (Max)

Differential Voltage

Differential Voltage (Min)

Differential Voltage (Max)

De-Emphasis De-Emphasis (Min)

De-Emphasis (Max)

Data Period (Min)

PCI-E Compliance Module

use TDSJIT3 Data Period

measurement

For Gen1: Eye Width

For Gen2: Jitter@BER

For Gen1: TIE Jitter

For Gen2: Not Specified

Gen1: Eye Width (Min)

Gen2: Jitter Eye Opening (Min)

Gen1: TIE Jitter (Min) or TIE Jitter

(Max); whichever value has the

maximum deviation from the

Median.

4

Instantaneous lane pulse width defined in the Gen2 specification is not supported in the RT-Eye PCI Express Compliance

module. It is recommended TDSJIT3 Advanced Jitter Analysis Data Period (Min) be used for this measurement.

22 RT-Eye PCI Express Compliance
Module

Methods of Implementation

Deterministic jitter

D+/D- TX output
rise/fall Time5

AC RMS common
mode output voltage

Absolute delta of DC
common mode

T

V

TX-DJ-DD

RISETXT−

T

−

FALLTX

ACpCMTXV−−

For Gen1: Not Specified

For Gen2: Jitter@BER

Rise Time

Fall Time

Gen1: AC CM Voltage

Gen1: Not Specified

Gen2: Deterministic Jitter (Max)

Rise Time (Min)

Fall Time (Min)

AC CM Voltage (Max)

Gen2 : Not Specified

DELTALINEDCCMTX

−−−−

Differential Average DifferentialAverageVoltage(Max)

voltage between D+
and D-

Table 15 – Measurement Select/Result Cross Reference (Eye Diagram Testing for all test points)

Parameter Symbol

Measurement > Select

Selection in

Measurement Results Summary

Results in

Menu

Unit interval UI Unit Interval

Unit Interval (Min)

Unit Interval (Max)

V

Eye height of
transition bits

Eye height of non­transition bits

Receiver or all bits
eye height

Eye width across
any 250 UIs

Eye width with

6

sample size of 10
UI

Jitter eye opening at

-12

BER 10

TXA

V

TXA_d

V

RX_EYE

T

TXA

In Rev1.0a

T

TXA

In Rev1.1

T

TXA

In Gen2

Eye Height EyeH: TransBits (Min)

EyeH: TransBits (Max)

Eye Height EyeH: NonTrBits (Min)

EyeH: NonTrBits (Max)

Eye Height EyeH: All Bits (Min)

EyeH: All Bits (Max)

Rev1.0a Only: Eye Width

Eye Width (Min)

(for each 250 bit window)

Rev1.1 Only; Eye Width

(sampled over 10

6

UIs)

Rev1.1 and Gen2:

Eye Width (Min)

Jitter Eye Opening (Min)

Jitter@BER

Maximum median­max jitter outlier
with sample size of

J

TXA-MEDIAN-to-MAX-

JITTER

Rev1.1 Only: TIE Jitter

6

(sampled over 10

UIs)

TIE Jitter (Min) or TIE Jitter (Max);

whichever value has the maximum

deviation from the Median.

106 UI

5

Rise/Fall time measurements in RT-Eye PCI Express Module are compliant to the Rev1.0a and Rev1.1 specification. For Gen2,

rise and fall time is limited to TF2 and TR2 as defined in the Base Specification.

RT-Eye PCI Express Compliance Module
23

Methods of Implementation

3.5.5 Configure Source of Waveforms

Use the Measurements > Configure > Source menu to select the source of the measured data.

Figure 14: Configure Source menu

Source selections are dependent on which probe type is selected. The selections are as follows:

If Differential is selected as Probe Type:

• Live/Ref source selection (uses single differential signal as data source)

o Live channel selections–Ch1, Ch2, Ch3, Ch4

o Reference waveform selections–Ref1, Ref2, Ref3, Ref4

• File source selection

o File selection – Uses one saved .csv as file as differential data source

If Single-Ended is selected as Probe Type:

• Live/Ref source selection (uses two single-ended signals as data source)

o Live channel selections–(Ch1-Ch3), (Ch1-Ch4), (Ch2-Ch3), (Ch2-Ch4)

o Reference waveform selections –Refx-Refy, where x and y are integers 1-4

• File source selection

o File selection–Uses two saved .csv files as single-ended data source

24 RT-Eye PCI Express Compliance
Module

Methods of Implementation

3.5.6 Configure Clock Recovery

Use the Measurements> Configure> Meas Config menu to select the type of clock recovery to be used.

Figure 15: Measurement Configuration menu

Selections in the General Config panel depend on the specification that has been chosen. The selections
are defined as follows:

If Rev1.0a – 2.5 Gb/s is selected as Standard:

• SSC (Scan Off) – 3500:250 clock recovery with no waveform scanning is used.

• SSC (Scan On) – 3500:250 clock recovery with waveform scanning is used.

If Rev1.1 – 2.5 Gb/s is selected as Standard:

• SSC (Scan Off) – 3500:250 clock recovery with no waveform scanning is used.

• SSC (Scan On) – 3500:250 clock recovery with waveform scanning is used.

• Clean Clock – A 1st Order SW PLL with a corner frequency of 1 MHz is used to recover the clock.

If Gen2 – 5 Gb/s is selected as Standard:

• SSC (Scan Off) – 3500:250 clock recovery with no waveform scanning is used.

• SSC (Scan On) – 3500:250 clock recovery with waveform scanning is used.

• Clean Clock – A 1st Order SW PLL with a corner frequency of 667K Hz is used to recover the clock.

RT-Eye PCI Express Compliance Module
25

Methods of Implementation

When to use SSC selection:

SSC is the only selection in Rev1.0a and is optional in the Rev1.1 and Gen2. It is to be used when a clean
clock source is not available or if SSC is turned on in a system. The following describes how the clock is
recovered using this technique:

• The “SmartGating” feature of the RT-Eye application is used to set up a software clock recovery

window and an analysis window. This feature is available (and configurable) outside the PCI Express
Compliance Module in the Measurements> Configure> SmartGating menu of the Serial Analysis
module.

• The clock recovery window is 3500 consecutive UIs and the Mean of the UIs is used as the reference

clock. The first 3500 UIs in the acquisition are used.

• An analysis window is established to be 250 UIs centered in the 3500 UI clock recovery window.

The placement of mask is based on the median of the 250 UI analysis windows.

• Optionally, the “Scan On” check box can be selected. When checked, the clock recovery and analysis

waveform will scan the waveform by stepping the 3500:250 window across the waveform in 100 UI
steps. This technique is same as the PCI-SIG SigTest software, used to determine compliance over a
single shot waveform.

When to use the Clean Clock selection:

• The clean clock selection is not available when Rev1.0a specification is selected. It is optional when

Rev1.1 or Gen2 Specification is selected. It should be used when a clean reference clock is available.
This is usually in the case while testing PHY components and Add-In cards. As defined in the base
specification, if a clean clock is available, the clock recovery function to be used is a TIE filter
function (Figure 16) with a corner frequency of 1.5 MHz (Rev1.1) and 1 MHz (Gen2). The RT-Eye
PCI Express compliance module implements a first order SW PLL. The SW PLL BW is dependent
on the edge density of the signal under test; for which the algorithm assumes an edge density of 50%.
If the edge density of the DUT were 50%, the PLL BW frequency would be set to correspond to the
frequencies in Figure 16. However, for compliance testing, the transmitter is required to transmit the
PCI Express Compliance Pattern that has an edge density of 75%. Thus the loop BW of the SW PLL
is set to [(0.5/0.75) x specified frequency]. This results in a PLL loop BW of 1MHz for Gen1 and a
frequency of 667kHz for Gen2. The loop BW of the SW PLL can be changed in the test point file. If
the edge density of signal under test is different than 75%, the loop BW should be changed to be
compliant with the specification. Refer to Section 9 for additional information on using Dynamic
Test Points.

Figure 16: Clock recovery mask function in Gen2 base specification

26 RT-Eye PCI Express Compliance
Module

Methods of Implementation

3.5.7 Configure Plots

The plots in the PCI Express Module are configured automatically. If the Jitter@BER measurement is
not selected, eye diagrams with masks will be displayed in the Plot Summary window (Figure 17a). The
eye diagram can either be a double plot showing transition bit and non-transition bit or can be a single
plot showing all bits depending on the test point selected.

Figure 17a: Plot Summary when Jitter@BER measurement is not selected

If the Jitter@BER measurement is selected, then a Jitter Spectrum and Bathtub Curve are added to the
Plot Summary window.

Figure 17b: Plot Summary when the Jitter@BER measurement is selected

RT-Eye PCI Express Compliance Module
27

Methods of Implementation

4 PCI Express Transmitter Compliance Testing

This section provides the Methods of Implementation (MOIs) for Transmitter tests using a Tektronix real­time oscilloscope, probes, and the RT-Eye PCI Express compliance software.

4.1 Probing the link for TX compliance

Use probing configuration B from Section 3. Connect the positive leg of the differential signal to the ‘+’
SMA connector and the negative leg of the differential signal to the ‘– ‘SMA connector on the P7300SMA
series differential probing system.

Alternatively, use probe configuration A, to connect Ch1 and Ch3 to the inputs of an oscilloscope that has
20 GS/s sample rate available on two channels (TDS6604 or TDS6000B Series).

Since the link is broken and terminated into a 50 Ω load, the compliance pattern is defined in the base
specification will be transmitted automatically.

4.2 TX Compliance Test Load

The compliance test load for driver compliance is shown in the base specification.

Figure 18: Driver compliance test load

28 RT-Eye PCI Express Compliance
Module

Methods of Implementation

4.3 Running a Transmitter (TX) Compliance Test

The MOI for each of the transmitter measurements is documented in the following sections. All transmitter
compliance measurements can be selected and run simultaneously with the same acquisition. See Section 3
for more info on configuring the module to make measurements.

To perform a compliance test of all transmitter measurements:

1. Select the desired Specification from the Specification pull-down list.

2. Select the desired Test Point from the Test Point pull-down list.

3. In the Measurement Select menu (Figure 19), choose Single-Ended (for probe configuration A defined
in Section 3) or Differential (for probe configurations B defined in Section 3) as the probe type.

4. Click Configure to configure the source and clock recovery method to be used.

5. Click Source tab to configure the data source.

6. Click General Config tab to select the desired clock recovery method.

7. Return the Measurement Select menu by clicking Select.

Figure 17: Measurements Select menu setup

8. Click Select Required and/or select desired measurements manually.

9. Click Autoset in the RT-Eye Measurement Select menu. This will automatically set up the
oscilloscope vertical, horizontal, and measurement reference levels for the compliance test.

10. Click Start.

Figure 20 shows the result of a Transmitter Compliance test on a signal that passes the driver tests at all
three TX compliance test points.

RT-Eye PCI Express Compliance Module
29

Methods of Implementation

Figure 20: Result of a successful transmitter compliance test

30 RT-Eye PCI Express Compliance
Module

Methods of Implementation

4.3.1 TX Unit Interval Measurement MOI

Test Definition Notes from the Specification:

- UI (Unit Interval) is specified to be +/- 300 ppm

- UI does not account for SSC dictated variations

Definition: UI is defined in the base specification.

Limits:

Refer to Table 2 for specified limits on UI measurement.

Test Procedure:

Ensure that Unit Interval is selected in the Measurements> Select menu.

Measurement Algorithm:

This measurement is made over the Analysis Window of 250 consecutive bits (or over the entire record if
the sw PLL is used) as defined in the Base Specification.

The Unit Interval measurement calculates the cycle duration of the recovered clock.

)()1()( ntntnUI

CLKRCLKR −−

AVG

−+=

=

))(( nUIMeanUI

Where:

CLKRt−

is a recovered clock edge

n is the index to UI in the waveform

RT-Eye PCI Express Compliance Module
31

Methods of Implementation

4.3.2 TX Differential Pk-Pk Output Voltage MOI

Definition:

V

pDIFFpTX

−−

(Differential Output Pk-Pk Voltage) is defined in the base specification. This measurement is
solved by two measurements. One is Differential Peak Voltage measurement and the other is Eye Height:
Transition Bits measurement. If you select Differential Voltage and Eye Width/Eye Height, you will get
five measurements: Eye Height, Eye Height: Transition Bits, Eye Height: Non-Trans Bits, Eye Width
and Differential Peak Voltage.

Test Definition Notes from the Specification:

-

−∗=

VV

|V |2

−−+−−−

DTXDTXpDIFFpTX

- Specified at the measurement point into a timing and voltage compliance test load as shown in the base
specification and measured over specified number of UIs. Also refer to the transmitter compliance eye
diagram shown in the base specification.

Limits:

Refer to Table 2 for specified limits on the

V

pDIFFpTX −−

measurement.

Test Procedure:

Ensure that Differential Voltage and Eye Width/Eye Height are selected in the Measurements> Select
menu.

Measurement Algorithm:

Differential Peak Voltage Measurement: The Differential Peak Voltage measurement returns two

times the larger of the Min or Max statistic of the differential voltage waveform.

)))(());(((2 ivMinivMaxMaxV

DIFFDIFFPKDIFF∗=−

Where:

i is the index of all waveform values

v

DIFF

is the differential voltage signal

32 RT-Eye PCI Express Compliance
Module

Methods of Implementation

−

−

=

Eye Height Measurement: The measured minimum vertical eye opening at the UI center as shown in
the plot of the eye diagram. There are three types of eye height values:

Eye Height:

VVV

−=

MAXLOEYEMINHIEYEHEIGHTEYE

−−−−−

Where:

MINHIEYEV−−

is the minimum of the high voltage at mid UI

MAXLOEYEV−−

is the maximum of the low voltage at mid UI

Eye Height – Transition:

=

Where:

V

V

Eye Height – Non-Transition:

Where:

V

V

MINTRANHIEYE

−−−

is the minimum of the high transition bit eye voltage at mid UI

MAXTRANLOEYE

−−−

is the maximum of the low transition bit eye voltage at mid UI

MINNTRANHIEYE

−−−

is the minimum of the high non-transition bit eye voltage at mid UI

MAXNTRANLOEYE

−−−

is the maximum of the low non-transition bit eye voltage at mid UI

VVV

VVV

MAXTRANLOEYEMINTRANHIEYETRANHEIGHTEYE

−−−−−−−−

MAXNTRANLOEYEMINNTRANHIEYENTRANHEIGHTEYE

−−−−−−−−

RT-Eye PCI Express Compliance Module
33

Methods of Implementation

4.3.3 TX De-Emphasized Differential Output Voltage (Ratio) MOI

Definition:

RATIODETXV−−

(De-Emphasized Differential Output Voltage (Ratio)) is defined in the base specification.

Test Definition Notes from the Specification:

- This is the ratio of the

V

of the first bit after a transition.

pDIFFpTX

−−

V of the second and following bits after a transition divided by the

pDIFFpTX −−

- Specified at the measurement point into a timing and voltage compliance test load as shown in the base
specification over the specified number of UIs. Also refer to the transmitter compliance eye diagram
shown the base specification.

Limits:

Refer to Table 2 for specified limits on the

V measurement.

RATIODETX −−

Test Procedure:

Ensure that De-Emphasis is selected in the Measurements > Select menu.

Measurement Algorithm:

The de-emphasis measurement calculates the ratio of any non-transition eye voltage (2
voltage succeeding an edge) to its nearest preceding transition eye voltage (1

st

eye voltage succeeding an

nd

, 3rd, etc. eye

edge). In Figure 21, it is the ratio of the black voltages over the blue voltages. The results are given in dB.

Figure 21: De-emphasis measurement

34 RT-Eye PCI Express Compliance
Module

Methods of Implementation

−

=



)(



dBmDEEM

=




−−

NTRANHIEYE

−−

TRANHIEYE



)(

mv





)(

nv



or




)(

dBmDEEM

=




−−

NTRANLOEYE

−−

TRANLOEYE



)(

mv





)(

nv



Where:

TRANHIEYEv−−

is the high voltage at mid UI following a positive transition

TRANLOEYEv−−

is the low voltage at mid UI following a negative transition

NTRANHIEYEv−−

is the high voltage at mid UI following a positive transition bit

NTRANLOEYEv−−

is the low voltage at mid UI following a negative transition bit

m is the index for all non-transition UIs

n is the index for the nearest transition UI preceding the UI specified by m

4.3.4 Minimum TX Eye Width MOI

Definition:

EYETXT−

(Minimum TX Eye Width) is defined in the base specification. Note that the definition of this
parameter Eye width changes from Rev1.x to the Gen2. See Section 4.3.9 for the Gen2 definition. For
Gen1, the Eye width is a waveform histogram-based measurement that is defined as follows. For Gen2

Test Definition Notes from the Specification:

- The maximum Transmitter jitter can be derived as

- Specified at the measurement point into a timing and voltage compliance test load as shown in the base
specification and measured over the specified number of UIs. Also refer to the transmitter compliance
eye diagram shown in the base specification.

Note: The median is not the same as the mean. The jitter median describes the point in time where the
number of jitter points on either side is approximately equal as opposed to the averaged time value.

Limits:

EYETXT−

is defined to be the Jitter Eye Opening which is described later.

T

T

1

EYETXJITTERTXMAX

−−

Refer to Table 2 for specified limits on the

T measurement.

EYETX −

RT-Eye PCI Express Compliance Module
35

Methods of Implementation

Test Procedure:

Ensure that Eye Width is selected in the Measurements> Select menu.

Measurement Algorithm:

The measured minimum horizontal eye opening at the zero reference level as shown in the eye diagram.

TIEUIT

−=

PkPkAVGWIDTHEYE

−−

Where:

UI is the average UI

AVG

TIE

is the Peak-Peak TIE

PkPk

−

4.3.5 TX Median-to-Max Jitter MOI

Definition:

T

MAXJITTERtoEYEMEDIANTX

−−−

median.) is defined in Rev1.0a of the base specification.

Limits:

Refer to Table 2 for

Test Procedure:

Ensure that TIE is selected in the Measurements> Select menu.

Measurement Algorithm:

The measured time difference between a data edge and a recovered clock edge.

Where:

(maximum time between the jitter median and maximum deviation from the

T measurement.

)()()( ntntntie

DATDATR−=−

MAXJITTERtoEYEMEDIANTX −−−

t

DAT

is the original data edge

DATRt−

is the recovered data edge (for example, the recovered clock edge corresponding to the UI

t

boundary of

DAT

)

n is the index of all edges in the waveform

36 RT-Eye PCI Express Compliance
Module

Methods of Implementation

4.3.6 TX Output Rise/Fall Time MOI

Definition:

,

RISETXT−

(D+/D- TX Output Rise/Fall Time) is defined in the base specification.

FALLTXT−

Test Definition Notes from the Specification:

- Specified at the measurement point into a timing and voltage compliance test load as shown in the base
specification and measured over the specified number of TX UIs.

- Measured between 20-80% at transmitter package pins into a test load for both

V and V

+−DTX −−DTX

Limits:

Refer to Table 2 for specified limits on

T ,

RISETX − FALLTXT−

measurements.

Test Procedure:

Ensure that Rise Time and Fall Time are selected in the Measurements> Select menu.

Note: Rise/Fall time D+ and D- measurements show up when the probe type is single-ended. Rise Time

measurements show up when differential probe type is used. Error in Rise/Fall time measurements
includes bandwidth limitations of the system in some cases.

Measurement Algorithm:

Rise/Fall time measurement supported in the RT-Eye PCI Express Compliance Module is currently
limited to only rising or falling edges of consecutive transitions (T
measurements as defined in the Gen1 specification. The Gen2 specification introduces T

and TR2 in Figure 22) for transmitter

F2

and TF2 in

F1

Figure 22. Rise/Fall Time is taken independently on each single-ended waveform sources when you use
two single-ended probes as the signal source. Differential signal Rise/Fall Time show up when you select
Differential probe type.

Figure 22: Rise/Fall Time measurement Gen2 specification. Only TR2 and TF2 are supported

RT-Eye PCI Express Compliance Module
37

Methods of Implementation

−

−

Rise Time: The Rise Time measurement is the time difference between when the V
is crossed and the V

reference level is crossed on the rising edge of the waveform.

REF-LO

−=

)()()( jtitnt

LOHIRISE ++

Where:

t is a Rise Time measurement

RISE

t is a set of for rising edges only

+HI

t is a set of for rising edges only

+LO

i and j are indexes for nearest adjacent pairs of

t

HI

t

LO

t and t

+LO +HI

n is a the index of rising edges in the waveform

Rise Time for

D +++++

RISE

v is as follows: )(t

D+

−=

)()()( jtitnt

LODHID

reference level

REF-HI

and for

t

D–FALL

(n) = t

D−

)(tv

D–LO–

(i) – t

D–HI–

(j)

Fall Time: The Fall Time measurement is the time difference between when the V
crossed and the V

=

reference level is crossed on the falling edge of the waveform.

REF-LO

)()()( jtitnt

HILOFALL −−

Where:

t

is a Fall Time measurement

FALL

t

is set of tHI for falling edge only

HI–

t

is set of tLO for falling edge only

LO–

i and j are indexes for nearest adjacent pairs of t

LO–

and t

HI–

n is the index to falling edges in the waveform

Fall Time for v

D

FALL

(t) is as follows:

D+

D

++

LO

−

−=

D

+

HI

)()()( jtitnt

−

reference level is

REF-HI

and for vD–(t),

t )()()( jtitn

D −−

FALL

=

D

−−

LO

−

HID

38 RT-Eye PCI Express Compliance
Module

Methods of Implementation

4.3.7 TX AC Common Mode Output Voltage MOI

Definition:

(RMS AC Pk Common Mode Output Voltage) is defined in Rev1.0a Base Specification. The

ACpCMTXV−−

nomenclature ACp is retained to be consistent with the specification. However, the measurement is
defined and reported by the PCI Express module as an RMS value, not a Pk value.

Test Definition Notes from the Specification:

+

VV

DTXDTX

=

ACpCMTX

−−

(|

RMSV

2

−−+−

=−

−−−−

|)|

ofDCVV

avgDCCMTXDCCMTX

)(

+

VV

DTXDTX

−−+−

|

2

- Specified at the measurement point into a timing and voltage compliance test load as shown in the base
specification and measured over the specified number of TX UIs.

Limits:

Refer to Table 2 for specified limits on

V

measurement.

ACpCMTX −−

Test Procedure:

Ensure that AC CM Voltage is selected in the Measurements> Select menu.

Note: This measurement is available only when the probe type is single-ended.

Measurement Algorithm:

AC CM RMS Voltage: The AC Common Mode RMS Voltage measurement calculates the RMS

statistic of the common mode voltage waveform with the DC value removed.

=

))(()( ivRMSiv

MACCMRMSAC −−−

Where:

i is the index of all waveform values

is the RMS of the AC common mode voltage signal

CMRMSACv−−

is the AC common mode voltage signal

MACv−

RT-Eye PCI Express Compliance Module
39

Methods of Implementation

4.3.8 TX Delta DC Common Mode Voltage MOI

Definition:

V

−−−−

(Absolute Delta of DC Common Mode Voltage between D+ and D-) is defined in

DELTALINEDCCMTX

the base specification.

Test Definition Notes from the Specification:

mVVV

25||

≤−

−−−−+−−−

DDCCMTXDDCCMTX

=

=

VofDCV

)(

)(

+−+−−

DTXavgDDCTXCM

VofDCV

−−−−−−

DTXavgDDCCMTX

||

||

- Specified at the measurement point into a timing and voltage compliance test load as shown in the base
specification and measured over the specified number of UIs.

Limits:

Refer to Table 2 for specified limits on

V

measurement.

DELTALINEDCCMTX −−−−

Test Procedure:

Ensure that Differential Average is selected in the Measurements> Select menu.

Measurement Algorithm:

The Differential Average measurement returns the mean of the differential voltage waveform.

))(( ivMeanV

DIFFAVGDIFF=−

Where:

i is the index of all waveform values

v

DIFF

is the differential voltage signal

40 RT-Eye PCI Express Compliance
Module

Methods of Implementation

4.3.9 TX Total Jitter@BER MOI

Definition:

The jitter eye opening

is re-defined Gen2 specification to statistical relevance to 10

EYETXT−

-12

BER. A

detailed definition can be found in the Gen2 base specification.

Test Definition Notes from the Gen2:

- Does not include SSC or Refclk. Jitter Includes Rj at 10

-12

.

- Transmitter jitter is measured by driving the transmitter under test with a low jitter “ideal” clock and
connecting the DUT to a reference load.

- Transmitter jitter must be post-processed with a filtering function that represents the worst case CDR
tracking BW.

Limits:

Refer to Table 2 for specified limits on the

T measurement.

EYETX −

Test Procedure:

Ensure that Jitter@BER is selected in the Measurements> Select menu.

Measurement Algorithm:

Total jitter in the PCI Express Compliance Module uses the Arbitrary Pattern Jitter Algorithm in RT-Eye
to establish

T . To understand the complete algorithm, one must understand RT-Eye’s spectrum

EYETX −

approach to jitter measurements. The RT-Eye PCI Express Compliance Module uses Spectral Analysis to
estimate the Total Jitter. The Arbitrary Pattern method is used such that a repeating pattern is not required
to achieve a jitter measurement result.

4.3.10 Spectrum Analysis Based Rj/Dj Separation on Repeating Pattern

Dj components can be identified in a jitter spectrum under a set of conditions. PJ will appear as spectral
impulses regardless of conditions. DDJ and DCD will appear as spectral impulses provided that the data
signal is a repeating pattern. The frequencies of DDJ and DCD spectral impulses are at harmonics of the
(Bit Rate/Pattern length). The remaining spectral energy is attributed to Rj. Dj components are spectrally
separated from Rj.

The Dj measurement is the peak-to-peak value of the inverse Fourier transform of the deterministic jitter
spectral components, Tj is the total jitter which is composed of Dj and Rj. The Tj measurement calculates
the peak-to-peak value of the total jitter. Rj is assumed to be near-Gaussian. The Rj measurement is the
calculated RMS value of random jitter.

A Jitter PDF is formed by convolving a Gaussian distribution of Rj and Histograms of Dj. A Bathtub
curve is calculated from the left and right side CDFs of the Jitter PDF. The Bathtub curve will yield TJ

T

and Eye Opening (

RT-Eye PCI Express Compliance Module
41

OPENEYE −

).

Methods of Implementation

(

)

∗

The application calculates the measurements using the following equations:

TimeTime

)()(

DjMinDjMaxDj −=

Time

DjtieRMSRj −=

=

PDF

TJTJTJ −=

MINMax

TJUIT

OPENEYE−=−

)()( RjFGaussianPDDjHistogramnormalizedTJ

Where:

Dj is the deterministic jitter

Rj is the random jitter

TJ is the total jitter

TJ is the PDF of the total jitter

PDF

TJ is the minimum value at the bathtub curve at a given BER

MIN

TJ is the maximum value at the bathtub curve at a given BER

Max

Time

Dj is the is the time domain record of the component of jitter obtained by performing an inverse

Dj

FFT of the

components of the TIE spectrum

Dj

tie

is the time domain record of measured TIE jitter

Additionally,

is further decomposed as follows:

Dj

TimeTime

PJMinPJMaxPJ −=

Time
Rise

)()(

DCDDDJMeanDCDDDJMeanDCD −=

TimeTime

Time

)()(

Fall

DCDDCDDDJMinDCDDDJMaxDDJ

−−= )()(

Where:

PJ is the periodic jitter

DCD is the duty cycle jitter

42 RT-Eye PCI Express Compliance
Module

Methods of Implementation

DDJ is the data dependent (or ISI) jitter

Time

PJ is the time domain record of the component of jitter obtained by performing an inverse FFT

of the

components of the TIE spectrum

PJ

PJ

DCDDDJ is the time domain record of the + component of jitter obtained by

performing an inverse FFT of the

DCDDDJ is on rising edges only

DCDDDJ is on falling edges only

Time

Time

Rise

Time
Fall

DCDDDJ

DCDDDJ

DCD DDJ

Time

Time

DCD

+ components of the TIE spectrum

4.3.11 Arbitrary Pattern Analysis Based Rj/Dj Separation

When data pattern is non-repeating, PJ still has a spectrum of impulses, while DCD+DDJ no longer has a
spectrum of impulses. Therefore, Dj no longer has a spectrum of impulses.

The DCD+DDJ value is obtained through the arbitrary data pattern analysis method that is based on the
assumption that any given bit is affected by a finite number of preceding bits. By averaging all events
where the current bit is preceded by a particular bit sequence, for example the current bit is preceded by
the bit sequence 1001101, the DCD+DDJ with such a pattern is obtained since PJ and RJ are not
correlated to a particular data sequence and thus are averaged out.

If each bit is assumed to be affected by N preceding bits, there are a total of 2
The sequence length N is set to 5 in the PCI Express module (user configurable in the Serial Analysis
module) because PCI Express is 8b/10b encoded. To get statistically sound average values, a population
limit of 50 is set in the PCI Express module (user configurable in the Serial Analysis module) that
prevents using an average value without enough population. Only DCD+DDJ values obtained from data
sequences with a population above the limit are used to calculate DCD+DDJ values.

DDJ

N

possible data sequences.

After each edge is associated with a DCD+DDJ value, with known total jitter, the PJ+Rj value for each
bit is then obtained by subtracting DCD+DDJ from TJ.

Separation of DDJ and DCD from DCD+DDJ is the same as that in the spectrum based Rj/Dj separation
method.

PJ and Rj are then separated from PJ+Rj and use the spectrum analysis method. PJ has a spectrum of
impulses, and Rj has a flat spectrum. All the edges whose DCD+DDJ can not be determined because of
their associated data sequences have low populations and are treated as if there are no edges when
performing PJ and Rj separation.

The histogram of Dj is a convolution of the histogram of DCD+DDJ and the histogram of PJ.

All other aspects of the arbitrary pattern analysis based Rj/Dj separation are the same as those of the
spectrum analysis based Rj/Dj separation.

RT-Eye PCI Express Compliance Module
43

Methods of Implementation

4.3.12 TX Deterministic MOI (Using Dual-Dirac Model)

Definition:

Deterministic jitter

t

using the Dual-Dirac model is defined in the Gen2 Base Specification.

TX-DJ-DD

Limits:

Refer to Table 2 for specified limits on Common the

Test Procedure:

Ensure that Jitter@BER is selected in the Measurements> Select menu.

4.3.13 Rj/Dj Separation Based on Dual Dirac Model

Dual Dirac model based Rj/Dj separation method fits the Bathtub curve to a theoretical model of Rj and
Dj where Rj is assumed to have a Gaussian distribution, Dj is assumed to have a distribution of two Dirac
impulses with the same height. Curve fitting at different BER levels in Bathtub curve yields the standard
deviation value of Rj and peak-to-peak value of Dj. The Bathtub curve is obtained from the spectrum
analysis based or the arbitrary pattern analysis based Rj/Dj separation methods. Rj and Dj based on the

Dual-Dirac model can be denoted as

RJ

After and are obtained, Tj can be calculated using

g

DJ

dd

DJRJBERQBERTJ +×= )(2)(

RJ

ddg

and .

g

DJ

dd

t

TX-DJ-DD

measurement.

1210−

where Q is the function of BER that has a value of about 7 when

=BER

. Eye opening is

computed in the same way as it is computed in the spectrum analysis based Rj/Dj separation.

Dual Dirac model based Rj/Dj separation method is used in PCI-Express module and FB-DIMM module.

Usually, actual Dj does not have a pure Dual-Dirac distribution. So the value of

is often greater than

RJ

g

the value of Rj obtained from the spectrum analysis based or the arbitrary pattern analysis based Rj/Dj
separation. The value of

is often less than that of its corresponding one.

DJ

dd

44 RT-Eye PCI Express Compliance
Module

Methods of Implementation

4.3.14 TX Waveform Eye Diagram Mask Test MOI

Test Definition Notes from the Specification:

- The TX eye diagram is defined in the base specification is specified using the passive compliance/test
measurement load in place of any real PCI Express interconnect + RX component.

- There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending on whether it is a transition bit or a de-emphasized bit. The exact reduced voltage
level of the de-emphasized bit will always be relative to the transition bit.

- The eye diagram must be valid for the specified number of UIs.

Limits:

Mask geometries for each specification are defined by the limits in Table 2.

Test Procedure:

Waveform masks are plotted with eye diagrams for the selected test point. Mask violations are
highlighted and counted by the application.

RT-Eye PCI Express Compliance Module
45

Methods of Implementation

5 PCI Express Receiver (RX) Compliance Testing

This section provides the Methods of Implementation (MOIs) for receiver tests using a Tektronix real-time
oscilloscope, probes, and the RT-Eye compliance software solution.

5.1 Probing the Link for RX Compliance

Use probing configuration (D) to probe the link differentially at a point close to the pins of the receiver
device. Alternatively, use probing configuration (C) using the Ch1 and Ch3 inputs of an oscilloscope that
has 20 GS/s sample rate available on two channels (TDS6604 and TDS6000B/C Series only).

5.2 Running a Complete RX Compliance Test

The MOIs for each RX test are documented in the following sections. All RX measurements can be
selected and run simultaneously with the same acquisition. To perform a compliance test of all receiver
measurements:

1. Select desired Specification from the Specification pull-down list.

2. Select desired Test Point from the Test Point pull-down list.

3. In the Measurement Select menu (Figure 23), choose Single-Ended (for probe configuration C defined
in Section 3) or Differential (for probe configurations D defined in Section 3) as the Probe Type.

4. Click Configure to configure the source and clock recovery method to be used.

5. Click the Source tab to configure the data source.

6. Click the General Config tab to select the desired clock recovery method.

7. Return the Measurement Select menu by clicking Select.

Figure 23: Measurements Select menu setup

8. Click Select Required and/or select desired measurements manually.

9. Click Autoset in the RT-Eye Measurement Select menu. This will automatically set up the
oscilloscope vertical, horizontal, and measurement reference levels for the compliance test.

10. Click Start.

46 RT-Eye PCI Express Compliance
Module

Methods of Implementation

Figure 24 shows the result of a transmitter compliance test on a signal that passes the driver tests at all
three RX compliance test points.

Figure 24: Result of a successful Compliance Test at the Receiver Pins

5.2.1 RX Unit Interval Measurement MOI

Refer to Unit Interval measurement in Section 4 of this MOI document. The MOI for the measurement of
UI at the receiver is identical to measuring it at the transmitter, with the exception of the test point.

5.2.2 RX Differential Pk-Pk Input Voltage MOI

Definition:

V

solved by two measurements: Differential Peak Voltage and Eye Height measurement.

Test Definition Notes from the Specification:

- Specified at the measurement point and measured over the specified number of UIs. The test load
(defined in the base specification) should be used as the RX device when taking measurements. Also
refer to the Receiver compliance eye diagram shown in the base specification. If the clocks to the RX and
TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UIs must
be used as a reference for the eye diagram.

pDIFFpRX

−−

(Differential Input Pk-Pk Voltage) is defined in the base specification. This measurement is

−∗=

VVV

| |2

−−+−−−

DRXDRXpDIFFpRX

Limits:

Refer to Table 3 for specified limits applicable to the

V

pDIFFpRX −−

measurement.

RT-Eye PCI Express Compliance Module
47

Methods of Implementation

Test Procedure:

Ensure that Differential Voltage and Eye Height/Eye Width are selected in the Measurements> Select
menu.

Measurement Algorithm:

Refer to Section 4 of this MOI document for differential voltage measurement and eye height
measurement algorithms.

Note: For receiver testing, eye height is measured on all UIs. There are no Eye Height: Transition Bits
measurement and Eye Height: Non-Trans Bits measurement.

5.2.3 Minimum RX Eye Width MOI

Definition:

T

(Minimum RX Eye Width) is defined in the base specification.

EYERX

−

Test Definition Notes from the Base Specification:

- The maximum interconnect media and transmitter jitter that can be tolerated by the Receiver can be

derived as

T UIT

−−−

6.1=−=

EYERXJITTERMAXRX

.

- Specified at the measurement point and measured over the specified number of UIs. The test load in the
base specification should be used as the RX device when taking measurements. Also refer to the Receiver
compliance eye diagram shown in the base specification.

- A

T

EYERX

−

UI

40.=

provides for a total sum of 0.60 UI deterministic and random jitter budget for the

Transmitter and interconnect collected over the specified number of UIs. The

T

MAXtoMEDIANEYE −−−− JITTERRX

−

specification ensures a jitter distribution in which the median and the
maximum deviation from the median is less than half of the total .6 UI jitter budget collected over the
specified number of TX UIs.

Note: The median is not the same as the mean. The jitter median describes the point in time where the
number of jitter points on either side is approximately equal as opposed to the averaged time value.

Limits:

Refer to Table 3 for specified limits applicable to the

T measurement.

EYERX −

Test Procedure:

Ensure that Eye Height/Eye Width is selected in the Measurements> Select menu.

Measurement Algorithm:

Refer to Section 4 of this MOI document for Eye Width measurement algorithm.

48 RT-Eye PCI Express Compliance
Module

Methods of Implementation

5.2.4 RX Median-to-Max Jitter MOI

Definition:

T

MAXJITTERtoEYEMEDIANRX

−−−

(Maximum time between the jitter median and maximum deviation from the

median.) is defined in the Gen1base specification.

Test Definition Notes from the Specification:- Jitter is defined as the measurement variation of the

crossing points (

V

V

pRXDIFFp0=−

) in relation to a recovered RX UI:

- The test load in the base specification should be used as the RX device when taking measurements.
Also refer to the receiver compliance eye diagram shown in the base specification.

- A

T

EYERX

−

UI

40.=

provides for a total sum of 0.60 UI deterministic and random jitter budget for the

transmitter and interconnect collected over the specified number of UIs.

T

-

JITTERMAXtoMEDIANEYERX

−−−−−

specification ensures a jitter distribution in which the median and the
maximum deviation from the median is less than half of the total .6 UI jitter budget collected over the
specified number of UIs. It should be noted that the median is not the same as the mean. The jitter
median describes the point in time where the number of jitter points on either side is approximately equal
as opposed to the averaged time value.

Limits:

Refer to Table 3 for specified limits applicable to the

T measurement.

MAXJITTERtoEYEMEDIANRX −−−

Test Procedure:

Ensure that TIE Jitter is selected in the Measurements> Select menu.

Measurement Algorithm:

Refer to Section 4 of this MOI document for RX Median-to-Max Jitter measurement algorithm.

RT-Eye PCI Express Compliance Module
49

Methods of Implementation

5.2.5 RX Total Jitter@BER MOI

Definition:

The jitter eye opening

T is re-defined Gen2 Base Specification to statistical relevance to 10

EYERX −

-12

BER. A detailed definition can be found the Gen2 base specification.

Test Definition Notes from the Gen2:

- Minimum eye time at RX pins to yield a 10

Receiver eye margins are defined into a 2x50 Ω reference load. A receiver is characterized by driving it

-

-12

BER.

with a signal whose eye opening is TRX_EYE, which is equivalent to generating a signal with a Tj of

1.0 UI – T

(

-

T

EYERX −

and T

minimum eye that the receiver is expected to decode correctly. Another way of viewing

consider that the amount of Tj that can be present is 1.0 UI - T = 120 ps. T

maximum amount of Dj that may be present in the Tj number of 120 ps implied byV .

T defines an eye opening, while T

Note:

). The receiver under test then replaces the reference load, and the BER is observed.

RX_EYE

are defined as tolerance parameters. In other words, T

DDDJRX −−

EYERX − DDDJRX −−

EYERX −

defines an eye closure.

defines the

EYERX −

DJRX −−

DD

RX

−

T

EYERX −

defines the

EYE

is to

Limits:

Refer to Table 3 for specified limits on the

T measurement.

EYERX −

Test Procedure:

Ensure that Jitter@BER is selected in the Measurements> Select menu.

Measurement Algorithm:

Refer to Section 4 for the Jitter@BER algorithm.

50 RT-Eye PCI Express Compliance
Module

Methods of Implementation

5.2.6 RX Deterministic Jitter@BER using Dual-Dirac model

Definition:

The jitter eye opening

T is re-defined in Gen2 Base Specification to statistical relevance to10

DDDJRX __

BER A detailed definition can be found in the Gen2 Base specification.

Test Definition Notes from the Gen2:

- Maximum Dj applied to receiver test circuit.

Limits:

Refer to Table 3 for specified limits on the

T measurement.

DDDJRX __

Test Procedure:

Ensure that Jitter@BER is selected in the Measurements> Select menu.

Measurement Algorithm:

Refer to Section 4 of this MOI document for the algorithm.

-12

RT-Eye PCI Express Compliance Module
51

5.2.7 RX Waveform Eye Diagram Mask Test MOI

Test Definition Notes from the Specification:

- The RX eye diagram in the base specification is specified using the passive compliance/test
measurement load in place of any real PCI Express RX component.

Note: In general, the minimum receiver eye diagram measured with the compliance/test measurement
load will be larger than the minimum Receiver eye diagram measured over a range of systems at the
input Receiver of any real PCI Express component. The degraded eye diagram at the input receiver is due
to traces internal to the package as well as silicon parasitic characteristics, which cause the real PCI
Express component to vary in impedance from the compliance/test measurement load. The input receiver
eye diagram is implementation specific and is not specified. RX component designer should provide
additional margin to adequately compensate for the degraded minimum receiver eye diagram expected at
the input receiver-based on some adequate combination of system simulations and the return loss
measured looking into the RX package and silicon.

- The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye
diagram.

Limits:

Methods of Implementation

Mask geometries for each specification are defined by the limits in Table 3.

Test Procedure:

Waveform masks are plotted with eye diagrams for the selected test point. Mask violations are
highlighted and counted by the application.

RT-Eye PCI Express Compliance Module
52

Methods of Implementation

6 PCI Express Interconnect Test Point Testing

This section provides the Methods of Implementation (MOIs) for the test points outlined in Tables 4-9.
These test points are defined at different interconnect points in the system between the transmitter and
receiver. Interconnects supported are add-in card and system board test points for both desktop and
ExpressModule; the cabling specification, and the ExpressCard specification. To perform a compliance test
of all interconnect specific measurements:

1. Hook up the device to connector specific test fixture. For example Compliance Load Board (CLB) or
Compliance Base Board (CBB).

2. Select the desired Specification from the Specification pull-down list.

3. Select the desired Test Point from the Test Point pull-down list.

4. In the Measurement Select menu (Figure 25), choose Single-Ended (for probe configuration A defined
in Section 3) or Differential (for probe configurations B defined in Section 3) as the Probe Type.

5. Click Configure to configure the source and clock recovery method to be used.

6. Click the Source tab to configure the data source.

7. Click the General Config tab to select the desired clock recovery method.

8. Return the Measurement Select menu by clicking Select.

Figure 25: Measurements Select menu for add-in card test point

9. Click Select Required and/or select desired measurements manually.

10. Click Autoset in the RT-Eye Measurement Select menu. This will automatically set up the oscilloscope
vertical, horizontal, and measurement reference levels for the compliance test.

11. Click Start.

Figure 26 shows the result of a Transmitter Compliance test on a signal that passes the driver tests at all
three RX compliance test points.

RT-Eye PCI Express Compliance Module
53

Methods of Implementation

Figure 26: Successful add-in card compliance test

6.1 Unit Interval Measurement MOI

Refer to Section 4 of this MOI document. The MOI for the measurement of UI at the receiver is identical
to measuring it at the transmitter, with the exception of the test point.

6.2 Transition and Non-Transition Bit Eye Height Measurement MOI

Definition:

V

V

TxA

, ,

specifications.

V

dTxA

_

TxS

V

are defined at the receiver end of the cable.

Test Definition Notes from the Specification:

Rev1.0a CEM Specification:

- All links are assumed active while generating this eye diagram. Transition and non-transition bits must be
distinguished in order to measure compliance against the de-emphasized voltage level.

V

dTxS

, and are defined in the PCI Express CEM, Express Module, and cable

RxA

and

_

V

RxA _

d

in the cabling specification also fall under the same definition, only they

- The values are initially referenced to an ideal 100 Ω differential load at the end of the interconnect path
on the edge-finger boundary of the add-in card [for add-in card measurement] or where the add-in card is
mated with the connector [for system measurement]. The eye diagram is defined and centered with respect
to the jitter median. The jitter median should be calculated across any 250 consecutive UIs.

54 RT-Eye PCI Express Compliance
Module

Methods of Implementation

Rev1.1 CEM and Rev 1.0 ExpressModule Specification:

-An ideal reference clock without jitter is assumed for this specification. All links are assumed active while
generating this eye diagram.

- Transition and non-transition bits must be distinguished to measure compliance against the de­emphasized voltage level.

- The values are referenced to an ideal differential load at the end of the interconnect path at the edge­finger boundary on the add-in card or the add-in card when mated to the connector. The eye diagram is
defined and centered with respect to the jitter median. Exact conditions required for verifying compliance
while generating this eye diagram are given in the PHY Electrical Test Considerations for PCI Express
Architecture document.

Cabling Specification Rev0.4C:

- Rev1.1 CEM Notes plus:

- Transition and non-transition bits must be distinguished to measure compliance against the de­emphasized voltage level.

- Transmitter path sdd21 is currently specified as 1.5 dB (1.25 GHz), which translates to a time domain
equivalent of 1.67 dB (2.5 Gb/sec).

Limits:

Refer to Tables 4 to 11 for specified limits on

Table 9 for

V

RXA

V

dRXA

and measurements.

_

V

V

TxA

,

V

dTxA _

TxS

,

, and

V

dTxS _

for all interconnect and

Test Procedure:

Ensure that Eye Height/Eye Width and differential voltage are selected in the Measurements> Select menu.

Measurement Algorithm:

Refer to Section 4 of this MOI document for measurement algorithms of eye height and differential
voltage.

RT-Eye PCI Express Compliance Module
55

Methods of Implementation

6.3 Eye Width Measurement MOI

Definition:

T , T for all interconnects are defined in the PCI Express CEM, Express Module, and Cable

TxA

TxS

Specifications.

the receiver end of the cable.

Test definition notes from the specification:

Rev1.0a CEM Specification:

-All links are assumed active while generating this eye diagram. Transition and non-transition bits must be
distinguished in order to measure compliance against the deemphasized voltage level.

- The values are initially referenced to an ideal 100 Ω differential load at the end of the interconnect path
on the edge-finger boundary of the add-in card [for add-in card measurement] or where the add-in card is
mated with the connector [for system measurement]. The eye diagram is defined and centered with respect
to the jitter median. The jitter median should be calculated across any 250 consecutive UIs.

T in the cabling specification also falls under the same definition, only it is defined at

RxA

Rev1.1 CEM and Rev 1.0 ExpressModule Specification:

- An ideal reference clock without jitter is assumed for this specification. All links are assumed active
while generating this eye diagram.

T, T

TxA TxS

-

is the minimum eye width. The sample size for this measurement is 106 UI. This value can be

reduced to the [1UI -Jitter@BER] for simulation purposes at BER 10-12.

- The values are referenced to an ideal 100 Ω differential load at the end of the interconnect path at the
edge-finger boundary on the add-in card or the add-in card when mated to the connector. The eye diagram
is defined and centered with respect to the jitter median. Exact conditions required for verifying
compliance while generating this eye diagram are given in the PHY Electrical Test Considerations for PCI
Express Architecture document.

Cabling Specification Rev0.4C:

- An ideal reference clock without jitter is assumed for this specification. All Links are assumed active
while generating this eye diagram.

T

TxA RxA

-

T

and is the eye width.

- The values are referenced to an ideal 100 Ω differential load at the end of the interconnect path at the
edge-finger boundary on the add-in card or the add-in card when mated to the connector. The eye diagram
is defined and centered with respect to the jitter median. Exact conditions required for verifying
compliance while generating this eye diagram are given in the PHY Electrical Test Considerations for PCI
Express Architecture document.

Limits:

Refer to Tables 4 to 11 for specified limits on

T

RxA

measurements.

T

TxA TxS

T

and for all interconnects and Table 9 for cable

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Test Procedure:

Ensure that Eye Width is selected in the Measurements> Select menu.

Measurement Algorithm:

Refer to Section 4 of this MOI document for measurement algorithms of Eye Width measurement.

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6.4 Interconnect Median-to-Max Jitter and Total Jitter@BER MOI

Definition:

J

JITTERMAXtoMEDIANTX

−−−−

is defined in Rev1.1 of the CEM specification. It is not explicitly defined in the
Rev1.0a specification but can be derived by [1UI – Eye Width]. Jitter@BER is introduced in Rev1.1 as
discussed in the notes below.

Test definition notes from the specification:

Rev1.1 CEM Specification:

J

­Specification, Revision 1.1. The sample size for this measurement is 106 UI. This value can be increased
to [Jitter@BER] for simulation purpose at BER 10

JITTERMAXtoMEDIANTX

−−−−

is the maximum median-to-max jitter outlier as defined in the PCI Express Base

-12

.

Limits:

Refer to Table 4 for limits on measurement.

J

JITTERMAXtoMEDIANTX

−−−−

Test Procedure:

-Ensure that TIE is selected in the Measurements> Select menu for

J

-Ensure that Jitter@BER is selected in the Measurement > Select menu for 10

Measurement Algorithm:

Refer to Section 4 of this MOI document for jitter measurement algorithms.

JITTERMAXtoMEDIANTX

−−−−

.

-12

BER jitter estimation.

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7 PCI Express Reference Clock Compliance

Measurements

This section provides the Methods of Implementation (MOIs) for reference clock tests.

7.1 Probing the Link for Reference Clock Compliance

Use probing configuration (B or D) to probe the link differentially at a point close to the pins of the
reference clock. Alternatively, use probing configuration (A or C) using the Ch1 and Ch3 inputs of an
oscilloscope can be used for reference clock measurements.

7.2 Running a Complete Reference Clock Compliance Test

The MOIs for each reference clock test is documented in the following sections. All reference clock
measurements can be selected and run simultaneously with the same acquisition. To perform a compliance
test of all receiver measurements:

1. Select Measurements> Select.

2. Select Differential (or Single-Ended) as the Probe Type, depending on your probe configuration.

3. Select Reference clock from the Test pull-down list.

o

Figure 27: Measurements Select menu for reference clock test point

4. Select all or required measurements.

5. Click Configure to access the Configuration menus and set up signal source.

6. Click Autoset to set the horizontal scale, vertical scale, and reference levels for the reference clock

measurements.

7. Click Start.

Figure 28 shows the result of a Reference clock Compliance test on a signal that passes the reference clock
tests.

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Figure 28:

Result of a completed compliance test at the reference clock test point

7.2.1 Reference Clock Frequency Measurement Test MOI

Test Definition Notes from the Specification:

-Measurement is taken from differential waveform.

-Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter,
relative PPM tolerance, and spread spectrum modulation.

Limits:

Refer to Table 12 for specified limits on absolute period measurement (

Test Procedure:

Ensure that Period is selected in the Measurements> Select menu.

T

PERIOD_ABS

)

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Measurement Algorithm:

Measurement of period is defined in the specifications is as follows:

Figure 29: Reference clock period

7.2.2 Reference Clock Differential Voltage Hi and Lo Test MOI

Test Definition Notes from the Specification:

Measurement is taken from differential waveform.

Limits:

Refer to Table 12 for specified limits on absolute period measurement (

Test Procedure:

Ensure that High Voltage and Low Voltage are selected in the Measurements> Select menu.

Measurement Algorithm:

The High Amplitude measurement calculates the mode of all differential waveform values greater than
zero.

Where:

VIH, V

)

IL

v

is differential voltage signal

DIFF

i is the index of all waveform values

The Low Amplitude measurement calculates the mode of all differential waveform values greater than
zero.

Where:

v

is differential voltage signal

DIFF

i is the index of all waveform values

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7.2.3 Reference Clock Differential rise and fall edge rates test MOI

Test Definition Notes from the Specification:

-Measurement is taken from differential waveform.

-Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus
REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The
300 mV measurement window is centered on the differential zero crossing.

Figure 30: Ref Clock Rise/Fall time calculation

Limits:

Refer to Table 12 for specified limits on Absolute Period Measurement (

Rise Edge Rate, Fall Edge Rate)

Test Procedure:

Ensure that Rising Edge and Falling Edge are selected in the Measurements> Select menu.

Measurement Algorithm:

The Rise and Fall Time are calculated over the 300mV window, which is centered at differential 0 V.
The rise/fall edge rate V/ns = 300 mV/rise/fall Time.

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7.2.4 Reference clock Duty cycle Test MOI

Test Definition Notes from the Specification:

Measurement is taken from differential waveform.

Limits:

Refer to Table 12 for specified limits on absolute period measurement (

Duty Cycle)

Test Procedure:

Ensure that Duty Cycle is selected in the Measurements> Select menu.

Measurement Algorithm:

The Duty Cycle measurement calculates the ratio of the positive of the cycle relative to the period.

Where

Where: D+ is the positive duty cycle.

+

is the positive pulse width.

W

Clock

is the period.

P

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7.2.5 Reference Clock Jitter Test MOI

Test Definition Notes from the Specification:

Reference clock jitter is assumed to be entirely random in nature, so there is no need to define separate Dj
or Tj terms.

Limits:

Refer to Table 10 for specified limits on random and Total Jitter Measurement values on reference clock
(Jitter @ 10

-12

BER, Jitter @ 10-6 BER, TCLK_RJ)

Test Procedure:

Ensure that Jitter@BER is selected in the Measurements> Select menu.

Measurement Algorithm:

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8 Using SigTest

The SigTest import feature in the PCI Express module allows the user to take advantage of the Autoset
features of RT-Eye and automate the process of performing a compliance test using the SigTest software
offered by the PCI SIG. SigTest Software is available at the PCI-SIG web site at:

http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library

After downloading the SigTest software and installing it on your TDS oscilloscope, the SigTest software
appears in C:\Program Files\SigTest or a similarly named directory.

To use SigTest, to perform the compliance test, follow these steps:

1. Select Use SigTest from the Specification pull-down list.

2. Select Differential or Single-Ended from the Probe Type pull-down list.

3. Go to the Configure > SigTest Version tab to import and name the SigTest version you would like to
use. Note that you can import multiple versions of SigTest as they become available from the PCI SIG.
The Output Directory field is where the SigTest results will be saved.

Figure 31: SigTest Version tab in the configure menu

4. To import and name a new SigTest version, click Import New Version using the browser to locate the
version of SigTest to import.

Figure 32: SigTest Import dialog box

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5. Click Browse and select the SigTest Executable to be used.

Figure 33: SigTest Import Dialog

6. Click the Source tab to select the data file input format. The source type is Live/Ref or File.

Figure 34: Configure > Source Tab

7. Click Select to return to the Measurement > Select menu.

8. Click Autoset to optimize vertical and horizontal scope settings for SigTest.

9. Click Run. Run launches SigTest and automatically imports data waveforms into SigTest. Figure 32
shows the result after data is verified and run through SigTest.

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Figure 35: Result of running SigTest on live channel input

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9 Using Dynamic Test Points

The Dynamic Test Point files used in the PCI Express module are designed to provide a means for advanced
users to develop their own test points in the module. Usage of the dynamic test point will be demonstrated in
the form of an example.

PCI Express Gen2 is at Rev0.3. But it is likely that masks and measurement limits may change before this
specification reaches maturity. In PCI Express Gen2 Specification, it is required that measurements must de­convolve effects of compliance test board to yield an effective measurement at the TX pins. In the absence
of de-convolving the test fixture from the measurement using some sort of equalization function,
measurement masks and limits need to be de-rated to consider the effects of the loss characteristics in both
the test fixture and the cables being used to make the measurement. In the following example, the transmitter
test point in the Gen2 – 5 Gb/s (Base: Transmitter) will be modified to account for loss in the test system.
The waveform masks and jitter limits will be de-rated and the test point file will be renamed
Base_TX_2.0_Derated. Once the test point file is modified and saved in the proper folder, the new test point
will show up in the Test Point menu pull-down in the PCI Express Compliance module. The following
shows the format of the Gen2 TP file found at:

C:\Program Files\TekApplications\tdsRT-Eye\modules\PCIExpress\TestPoint

on the instrument where the module is installed.

Figure 36 – Standard Gen2 TX test point file

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9.1 Test Point File Syntax

The test point file can be broken down into the following syntax:

Header Information (comment lines) used to document description and date of test point file:

#PCI-Express Test Point file

#11-Jul-05 15:52:20

Test Point display name that shows up in the test point pull-down list:

TestPointDisplayName = Base: Transmitter

Standard Version that determines in which standard version list, the test point will appear:

StandardVersion = Gen2 - 5 Gb/s

Test point short name that determines whether or not transition and non-transition bits will be
separated. Choices are TX (Tbits and NTbits separated) and RX (Tbits and NTbits not separated):

TestPointShortName = TX

Measurement limits that determine pass/fail criteria and whether the measurement will show up as
selected when Select Required is pressed:

EyeHeightTransitionBitsMin = 0.8

EyeHeightNon-TransBitsMin = 0.3785

EyeWidthMin = 150E-12

RiseTimeD+Min = 30E-12

RiseTimeD-Min = 30E-12

RiseTimeMin = 30E-12

FallTimeD+Min = 30E-12

FallTimeD-Min = 30E-12

FallTimeMin = 30E-12

TIEJitterMin = -25E-12

TIEJitterMax = 25E-12

JitterTJ-DD-Max10-12 = 50E-12

JitterDJ-DD-Max10-12 = 30E-12

De-EmphasisMeanLower = -6.5

De-EmphasisMeanUpper = -5.5

UnitIntervalMeanLower = 199.94E-12

UnitIntervalMeanUpper = 200.06E-12

DifferentialPeakVoltageMax = 1.2

DifferentialAverageVoltageMax = 25E-03

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Number and location of Masks:

MaskCount = 2

Mask0 = PCE_Rev20_TxTbit.msk

Mask1 = PCE_Rev20_TxNTbit.msk

Note: PCI Express Mask files are located at:

C:\TekApplications\tdsrt-eye\Masks\PCI Express on the instrument that the module is installed. The
following is the contents of PCE_Rev20_TxTbit.msk. Note that .msk file format is used by both RT-Eye
and the instrument firmware in mask testing. The only parameters in the .msk file that RT-Eye uses are the
highlighted mask vertices shown in bold font.

:MASK:USER:AMP 100.0000E-3;

:MASK:USER:PATTERNBITS 1;

:MASK:USER:PRESAMPBITS 0;

:MASK:USER:WID 400.0000E-12;

:MASK:USER:HSCA 62.5000E-12;

:MASK:USER:HTRIGPOS 500.0000E-3;

:MASK:USER:LAB "User Mask";

:MASK:USER

:TRIGTOSAMP 0.0000;

:MASK:USER:RECO 5000;

:MASK:USER:VSCA 200.0000E-3;

:MASK:USER:VPOS 0.0000;

:MASK:USER:VOFFS 0.0000;

:MASK:USER

:BITR 5.000E+9;

:MASK:USER

:SERIALTRIG NRZ;

:MASK:USER:SEG1:POINTS -100.0000E-12,600.0000E-3,100.0000E-12,600.0000E-3,100.0000E­12,800.0000E-3,-100.0000E-12,800.0000E-3;

:MASK:USER:SEG2:POINTS -75.0000E-12,0.0000,0.0000,-400.0000E-3,75.0000E
12,0.0000,0.0000,400.0000E-3;

:MASK:USER:SEG3:POINTS -100.0000E-12,-800.0000E-3,100.0000E-12, 800.0000E-3,100.0000E-12,-

600.0000E-3,-100.0000E-12,-600.0000E-3;

:MASK:AUTOSET:STANDARD PCIEXPRESS_Xmit;

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Clock recovery and windowing parameters when SSC is selected in the Measurement Configuration
menu:

SSCClockRecoveryMethod = Minimum Deviation

SSCScanStateOn = false

SSCClockRecoveryWindow = 3500

SSCAnalysisWindow = 250

Clock recovery and pattern length used when Clean Clock is selected in the Measurement
Configuration menu:

CleanClockRecoveryMethod = 1st Order PLL

CleanScanStateOn = false

CleanClockLoopBW = 6670000

RjDjPatternLength = 640

9.2 Creating the New Test Point

In this example, the Test Point and mask files will be copied and given new names. Then a text editor is
used to modify their contents.

The new TP file (Figure 34) is saved to the folder:

C:\Program Files\TekApplications\tdsRT-Eye\modules\PCIExpress\TestPoint

Figure 37: De-rated transmitter test point file – Base_TX_2.0_Derate.tp

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The following changes are made to SEG2 of the Mask file:

:MASK:USER:SEG2:POINTS -70.0000E-12,0.0000,0.0000,-350.0000E-3,70.0000E-
12,0.0000,0.0000,350.0000E-3;

This de-rates the horizontal mask limit from 150 ps to 140 ps and the vertical mask limit from 800 mV to
700 mV.

The new mask file is saved to the folder:

C:\TekApplications\tdsrt-eye\Masks\PCI Express as filename <PCE_Rev20_TxTbit_derate.msk>

9.3 Running a test with the new DTP

After the preceding file changes are made, when RT-Eye software is run, the new DTP is loaded into the
PCI Express Compliance Module.

Figure 38: “De-rated Transmitter” DTP is now in the test point menu

To run the test, perform the following steps:

1. Go to the PCI Express Module

2. Select Gen2 – 5 Gb/s as the specification.

3. Select the new Test Point De-rated Transmitter from the Test Point pull-down list.

4. Click Select Required – Notice that measurements removed from the Test Point file are no longer
selected.

5. Click Start; the results appear as shown in Figure 39. Notice that the new de-rated mask now appears
as the Tbit mask and the upper and lower limits are the new values entered into the DTP file.

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Figure 39: Result of de-rated transmitter test

10 Giving a Device an ID

The PCI Express Compliance module provides a graphical user interface (See Figure 38) for entering a
device ID and description. Data entered here will appear on the compliance report and is recommended for
device tracking.

11 Creating a Compliance Report

To create a compliance report, select Utilities > Reports. The Report Generator utility can create a complete
report of the compliance test.

12 Further Analysis Techniques

Refer to the RT-Eye Quick Start Guide or Online Help for additional analysis techniques.

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13 Ensuring Compliance over specified population

The Rev1.0a specification states that measurements are to pass the compliance statements over any 250
consecutive UIs. The Rev1.0a was ambiguous about the number of UIs needed to achieve compliance. The
3500:250 scan mode on a single acquisition has become the standard way of achieving compliance at
industry plug fests. Rev1.1 of the specification has explicitly called out 10
achieve compliance. High statistical certainty whether its over “and 250 bits”, 10
achieved in the PCI Express compliance module by changing the sequence mode from Single Run to Free
Run. For example, Figure 40 shows a measurement population of 22 Million UIs for unit interval
measurement where 50,000 is from the current acquisition, and 22 Million is accumulated over a long period
of time.

6

as the population needed to

6

UI, or much more, can be

Figure 40: Result from a population of 22 million UIs

74 RT-Eye PCI Express Compliance
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