Theory
of
Operation-DM
505
The output voltage of
U1311
is applied across sections
of
the
attenuator
R1312
(and
R1412for
the
200
kn range)
which
serves
as a current setting resistance. The voltage
across
R1312
and
R1412
is equal to
the
voltage
across
R1304.
The current through
R1312
flows through lamp
DS1410
and out
the
VO
LTS/R terminal through the
unknown resistance. The range switches select sections
of
the attenuator
so
that different values of current can
be
sourced out
of
the VOLTS/I1 terminal.
The
voltage
developed across the unknown resistance
is
then
measured by the
ASD
converter.
Diodes
CR1301
and
CR1302
and
lamp
DSt4lO
protect
the
ohms converter from
excessive
dc
and
ac
input
voltages. If
an
excessive voltage is applied to a resistance
range, the voltage is clamped by
CR1302
and
GR1301
and
appears across lamp
PS1410.
As
the filament
of
DS1410
warms
up,
the rmistance of thefilament increases, limiting
the current through the diode clamps.
DS1410
is rated
to
handle
125
V
rms indefinitely and
250
V
rms for a Fimited
time. Voltages in
excess
of these ratings cause
DSI410
to
act
as a
fuse. Diode
CR1301
also limits
the
open
circuit
voltage
at
the VOLTS/R input connector to approximately
+6
V.
Current
Shunts
@
The
current shunts in the
DM
505
consist of
R1425,
Rl426,
and t hick-film resistor network
R1521,
connected
between
the
mR
and LOW input terminals.
These
resistors
convert the input current to
a
voltage for measurement by
the
DM
505
circuitry. The maximum full
scale
voltage
developed across the current shunts
at
the
maximum full
scale current
is
0.2
volt. In the
dc
current mode, this
voltage is switched directly to the
ND
converter. In the ac
current
mode,
the current shunt voltage is first routed
through the
ac converter. The current shunts
are
protected by the diodes in
CR1621.
If
the
voltage across
the current shunts exceeds approximately
1.2
V,
the
diodes in
CR1621
begin
conducting, shunting current
around the resistors. The maximum voltage drop across
the current shunts in
an
overload condition is
ap-
proximately
1.5
V.
An input current exceeding
2
A opens
fuse
F1521.
The
DM
505
measures
voltages
up to
1
kV
peak above
chassis
ground
(200
V
peak above ground
at
the rear
interface input). Isolation
is
accomplished with power
transformer
Tl001,
which is powered from
the
25
Vac
floating windings
13A
and
138
of the power module.
Transformer
Kl 001
converts the
25
Vac to a secondary
output of
47
V
rrns, center-tapped, across pins
7
to
9,
and
12
V
rms across pins
lOto 12.
The 47 Y rms is rectified
by
CR1111
and filtered by capacitors
C1012
and
Clll
f
to
provide approximately + and
-
26
V
unregulated. The
positive voltage across
ClOl2
is
regulated
to
+15.75
V
by
U1022,
and
shunt resistors
R1122
and
R1021.
Resistor
R1021
adjusts the output voltage
for
the
minimum
+15.75
V required for proper ohms converter operation.
The
negative
voltage
across
Cllll
is
regulated to
-12
V
by
Uf 121.
The
current pulled from
each
of these supplies
is approximately
40
rn
A.
Capacitor
C1021
equalizes un-
balanced capacitance between the secondary windi ngs of
T1001,
pins
7,
8, and
9.
Capacitor
C1021
reduces any
60
Hz
common
mode
signal appearing between the front
panel input terminals of the
DM
505
and chassis ground.
The
12
V
rrns
from the secondary
of
TI
001,
pins
10
to
12,
is rectified
by
CRfOll
to provide approximately
+I2
Y
unregulated to the display anode drivers. The
+12
V
across
ClOf
I
is regulated to
+5
V
by
U1021.
Clock
9
The clock signals for
U1303
are generated
by
U1301,
a
free-running multivibrator
wit
h
a
frequency determined by
C1203, R1205, R1204,
and
R1202.
CLOCK
FREQ
ADJ
R1202
sets the clock frequency to
20.48
kHz,
a
multipEe
of
the
line frequency. Components
of
50
Hz or 60 Hz
at
the
input terminals are rejected since they
are
of
equal
magnitude during the up and down portions
of
the
measurement cycle,
Analog
to
Digital Converter
@
Integrated circuit
U1201
comprises
the
analog section
of the analog-to-digital
(#D)
converter
and
U1303
con-
tains the necessary control logic.
The
A/D
converter in the
DM
505
operates
on
the charge balancing principle. The
input voltage is converted to
a
current that charges
capacitor
Cf 101
in an integrator circuit. Charging con-
tinues until the capacitor voltage crosses afixedthreshold
level. Then
a
reference current larger than
the
maximum
input current
is
subtracted from the input current and the
capacitor discharges until
the
threshold level is crossed
again. This process
is
repeated until the measurement
interval is over. During the measurement interval,
a
counter in
U1303
accumulates clock pulses from clock
generator
U1301
when only the input signal
is
applied to
the integrator,
and
subtracts clock pulses
when
both the
input
signal and the reference current are applied to
the
integrator, resulting in a net count proportional to the
input voltage. This conversion occurs in
U1201
and
is
controlled
by
U1303.
Refer
to
Fig.
8-2
in the Diagrams
section.
Integrated circuit
U1201
also contains automatic zero-
ing
circuitry. Between meaurement intervals, the input of
U1201
is
switched to ground and an auto-zero voltage,
related
to
the offset voltages
in
U1201,
is stored across
auto-zero capacitor
C1102.
This auto-zero voltage is
converted to
a
current and subtracted from the input
current
at
the integrator
so
that errors due to
offset