Data Pattern Generator
DG2040 •DG2030 • DG2020A
DG2000 Series.
The DG2000 Series of pattern generators
provide digital designers with the high
performance tools needed to evaluate
advanced digital semiconductors and logic
circuits. Whatever you call your design
process – characterization, debug, validation
or verification – as a digital designer you
must have a state-of-the-art digital pattern
generation as you push the edge of the
technology envelope and race to market.
Choose the Best Fit
The DG2000 Series is remarkable for its
balanced approach to providing the appro-
priate class of instrument for a wide variety
of digital design applications. Performance
ranges from 1.1 Gb/s to 200 Mb/s and
from 2 to 36 channels. The table illustrates
the principal specifications for members of
the DG2000 Series.
Features & Benefits
Data Rate to 1.1 Gb/s Tests
High-speed Logic Devices
and Circuits
Data Pattern Depth to
256 K/Channel Speeds
Characterization
Multiple Output Channels
Increases Flexibility
– DG2040: 2
– DG2030: 4 or 8
– DG2020A: 12, 24, or 36
Control of Edge Timing
(DG2040) Permits Jitter
Simulation in Serial Data
Streams
Precise Control of Output
Parameters Include:
– Variable Output Delay
– Variable Output Level
– Variable Rise and Fall Time
Control (DG2030)
– Tri-state Output Control
(DG2020A, DG2030)
Fast Transition Times to
150 ps (DG2040) Aids Fast
Logic Evaluation
Complementary Output
(DG2040) Assures Excellent
Signal Fidelity
Flexible Sequence Control
with Jump, Event and
Nested Loops
Import Pattern Data with
DG-link Software Utility
Applications
Ultra Low Jitter for
Clock Substitution
Characterize Device Timing
for TTL, CMOS, ECL Families
Simulate Missing Functions
in System or Subsystem
Evaluation
Create Complex Data
Patterns with Sophisticated
Sequence, Looping, Jump
on Event and Tri-state
Output Control
Characterize and Verify ASIC,
FPGA and DACs
Test Printer Engines or
LCD Display Drivers
Use in Conjunction with
TLA Logic Analyzer to
Provide Digital Stimulus
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Data Pattern Generator
•
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Data Pattern Generator
DG2040 •DG2030 •DG2020A
DG2000 Series Principal Specifications
DG2040 DG2030 DG2020A
Data Rate 1.1 Gb/s 400 Mb/s 200 Mb/s
Pattern Depth 256 K/CH. 256 K/CH. 64 K/CH.
Rise & Fall Time 150 ps at 1 V
(20% to 80%)
No. of Channels 2 4 or 8 12, 24 or 36
Features Edge control Variable tr & tf time Bus wide testing
Critical Timing
p-p
The DG2000 Series is the ideal solution for
applications where you must characterize
device or circuit timing and amplitude margins.
The DG2000 Series is perfect for simulating
setup and hold violations or conditions of
metastability. The DG2000 graphical user
interface allows you to quickly create complex
data patterns with a few keystrokes on the
front panel. Use the advanced sequence
editing capability of the DG2000 Series to
insert infrequent faults or glitches in your
data patterns to verify device or circuit
recovery. The DG2000 Series is an invaluable
tool, allowing you to simulate missing system
functionality while meeting critical market
windows. With the introduction of the
DG2040, new capabilities are available to
control clock and data jitter or modulate
pulse edges on a selective basis (Figure 1).
Figure 1. The DG2040 allows specific edges to be identified and time adjusted or jittered by
±100 ps. An external modulation source can be used to provide continuously variable jitter.
1.5 ns at 2.5 V
p-p
2 ns at 5 V
p-p
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Data Pattern Generator
•
www.tektronix.com/signal_sources
Data Pattern Generator
DG2040 •DG2030 •DG2020A
Characteristics
Output Data
DG2040 DG2030 DG2020A
Data Rate 0.1 b/s to 1100 Mb/s 0.1 b/s to 409.6 Mb/s 0.1 b/s to 200 Mb/s
Sampling Rate 0.1 Hz to 1100 MHz 0.1 Hz to 409.6 MHz 0.1 Hz to 200 MHz
Resolution 7 digits 7 digits 4 digits
Clock Output Period Jitter <30 ps
CH0 Period Jitter (Clock Pattern) <20 ps
Accuracy PLL On, ±0.0001% PLL On, ±0.0001%; PLL Off, ±3% PLL On, ±0.005%; PLL Off, ±3%
Pattern Depth 360 to 256 Kbits (4 increment) 90 to 256 Kbits (1 increment) 64 to 64 Kbits (1 increment)
Data Width 2-Bits (complementary outputs) via Standard: 4-Bits via front-panel Standard: 12-Bits
at 1100 MHz. Typical <50 ps
p-p
at 1100 MHz. Typical <200 ps
p-p
at 200 MHz. Typical <50 ps
p-p
at 400 MHz. Typical <35 ps
p-p
at 200 MHz. Typical
p-p
at 200 MHz. Typical
p-p
front-panel SMA connectors BNC connectors Optional: 24- or 36-Bits
Optional: 8-Bits via 4 front-panel,
4 rear-panel BNC connectors
Sequencer
Maximum Number of Blocks – 256.
Maximum Number of Sequence Steps –
DG2040: 4000.
DG2030: 4000.
DG2020A: 2048.
Block Repeats Per Line – 1 to 65536 or infinite.
Internal Trigger Generator
(DG2030, DG2040)
Range – 1.0 µs to 10.0 s.
Resolution – 3 digits, 0.1 µs minimum.
Accuracy – ±0.01%.
Data and Clock Output
(DG2040)
Data –
Output:
Standard: CH 0 & CH 1 at front-panel SMA and
Clock at rear panel SMA connectors.
: – 0.875 V to +3.5 V into 50 Ω.
V
OH
V
: –1.125 V to +3.25 V into 50 Ω.
OL
Resolution: 5 mV.
Maximum Swing: 2.5 V
Minimum Swing: 250 mV
into 50 Ω.
p-p
into 50 Ω.
p-p
DC Accuracy: ±3% of set value ± 50 mV.
Aberrations:
Overshoot <5% at 1.5 V
Undershoot: <5% ±1.5 V
at 10 MHz.
p-p
at 10 MHz.
p-p
Impedance: 50 Ω.
Rise/Fall Time (20 to 80%): <150 ps at 1 V
10 MHz.
Delay Function:
Delay Channel: CH 0 or CH 1.
Delay Time: –1 ns to +2 ns.
Delay Resolution: 10 ps.
Accuracy: < (±3% of setting) ± | 25 ºC – T
15 ps ±100 ps (where T
is the ambient
a
temperature ºC).
Channel Skew: (<± | 25 ºC – T
is the ambient temperature ºC.
where T
a
|*15 ps ±100 ps)
a
and
p-p
|
a
*
Data Pattern Generator
•
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