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DDR Analysis
User manual
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Tektronix DDR Analysis User manual

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DDR Analysis Memory Interface Electrical Verification and Debug Solution
Printable Application Help
*P077023110*
077-0231-10
DDR Analysis Memory Interface Electrical Verification and Debug Solution
Printable Application Help
www.tektronix.com
077-0231-10
Copyright © Tektronix. All rights reserved. Licensed software products are owned by Tektronix or its subsidiaries or suppliers, and are protected by national copyright laws and international treaty provisions. Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. Specifications and price change privileges reserved.
TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.
Contacting Tektronix
Tektronix, Inc.
14150 SW Karl Braun Drive P.O. Box 500 Beaverton, OR 97077 USA
For product information, sales, service, and technical support:
■
In North America, call 1-800-833-9200.
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Worldwide, visit www.tektronix.com to find contacts in your area.

Table of Contents

Welcome ............................................................................................................................................................. xi
Introduction to the application
Related documentation .................................................................................................................................. 1
Conventions ................................................................................................................................................... 1
Technical support ........................................................................................................................................... 2
Customer feedback ........................................................................................................................................ 2
Getting started
Product description ........................................................................................................................................ 5
DDRA prerequisites ....................................................................................................................................... 6
Requirements and restrictions ....................................................................................................................... 6
Supported probes ........................................................................................................................................... 6
Installing the application ................................................................................................................................. 7
About DDRA ................................................................................................................................................... 8
Operating basics
About basic operations ................................................................................................................................... 9
Starting the application ............................................................................................................................. 9
Menu controls ........................................................................................................................................... 9
Virtual keypad ........................................................................................................................................... 9
Tips on the DDRA user interface ............................................................................................................ 10
Basic oscilloscope functions ........................................................................................................................ 11
Application directories ............................................................................................................................ 11
File name extensions ............................................................................................................................. 11
Returning to the application .................................................................................................................... 11
Control panel .......................................................................................................................................... 11
Saving and recalling setups ......................................................................................................................... 12
Saving a setup ........................................................................................................................................ 12
Recalling a saved setup ......................................................................................................................... 12
Recalling the default setup ..................................................................................................................... 13
Search and mark .......................................................................................................................................... 13
Limits ............................................................................................................................................................ 14
Dynamic limits .............................................................................................................................................. 15
DDR Analysis Printable Application Help
i
Table of Contents
Setting up DDR for analysis ......................................................................................................................... 16
DDR standards and their measurements ............................................................................................... 16
Derating .................................................................................................................................................. 25
About DDR analysis ............................................................................................................................... 28
Step 1: Generation rate and levels ......................................................................................................... 28
Step 2: Interposer filter ........................................................................................................................... 31
Step 3: Measurements and sources ....................................................................................................... 33
Step 4: Burst detection method .............................................................................................................. 38
Step 5: Burst detection settings .............................................................................................................. 42
Step 6:Thresholds and scaling ............................................................................................................... 42
DQ-DQS phase alignment ...................................................................................................................... 44
Chip select latency + DQ-DQS phase alignment ................................................................................... 46
Logic state + burst latency ...................................................................................................................... 47
Visual search .......................................................................................................................................... 50
Measurement levels ............................................................................................................................... 53
Hints ....................................................................................................................................................... 54
Results as statistics ................................................................................................................................ 54
Plots ....................................................................................................................................................... 55
Reports ................................................................................................................................................... 55
Switching between the DDRA and DPOJET applications ...................................................................... 55
Salient features of MSO-DDRA integration ............................................................................................ 56
Tutorial
Introduction to the tutorial ............................................................................................................................. 57
Setting up the oscilloscope .......................................................................................................................... 57
Starting the application ................................................................................................................................. 57
Waveform files ............................................................................................................................................. 57
Recalling a waveform file ............................................................................................................................. 57
Taking a measurement ................................................................................................................................ 58
Parameters
About parameters ......................................................................................................................................... 61
Step 1: Generation rate and levels parameters ........................................................................................... 61
Step 2: Interposer filter parameters .............................................................................................................. 62
Step 3: Measurement and sources parameters ........................................................................................... 62
Step 4: Burst detection method parameters ................................................................................................. 63
Step 5: Burst detection settings parameters ................................................................................................ 63
Step 6: Thresholds and scaling parameters ................................................................................................. 65
ii DDR Analysis Printable Application Help
Table of Contents
Reference
DDR measurement sources ......................................................................................................................... 67
DDR2 measurement sources ....................................................................................................................... 69
DDR3 measurement sources ....................................................................................................................... 73
DDR3L measurement sources ..................................................................................................................... 77
DDR4 measurement sources ....................................................................................................................... 81
GDDR5 measurement sources .................................................................................................................... 84
LPDDR measurement sources .................................................................................................................... 86
LPDDR2 measurement sources .................................................................................................................. 88
LPDDR3 measurement sources .................................................................................................................. 92
LPDDR4 measurement sources .................................................................................................................. 96
Measurement range limits ............................................................................................................................ 99
Dynamic limits for DDR measurements ..................................................................................................... 100
Dynamic limits for DDR2 measurements ................................................................................................... 101
Dynamic limits for DDR3 measurements ................................................................................................... 101
Dynamic limits for DDR3L measurements ................................................................................................. 102
Dynamic limits for DDR4 measurements ................................................................................................... 103
Dynamic limits for LPDDR measurements ................................................................................................. 104
Dynamic limits for LPDDR2 measurements ............................................................................................... 104
Dynamic limits for LPDDR3 measurments ................................................................................................. 105
Dynamic limits for LPDDR4 measurements ............................................................................................... 106
Vih-Vil reference levels .............................................................................................................................. 107
Using digital channels ................................................................................................................................ 109
Error codes and warnings .......................................................................................................................... 116
Algorithms
About algorithms ........................................................................................................................................ 121
Write measurements .................................................................................................................................. 121
Data eye height .................................................................................................................................... 121
Data eye width ...................................................................................................................................... 122
DDRARXMask ...................................................................................................................................... 122
tDQSS .................................................................................................................................................. 123
tDQS2DQ ............................................................................................................................................. 123
VIHL_AC .............................................................................................................................................. 124
SRIN_dIVW_Rise ................................................................................................................................. 124
SRIN_dIVW_Fall .................................................................................................................................. 124
TdIPW-High .......................................................................................................................................... 124
DDR Analysis Printable Application Help iii
Table of Contents
TdIPW-Low ........................................................................................................................................... 124
Differential DQS measurements ................................................................................................................ 124
Input Slew-Diff-Rise(DQS) ................................................................................................................... 124
Input Slew-Diff-Fall(DQS) ..................................................................................................................... 125
tDH-Diff(base) ...................................................................................................................................... 125
tDH-Diff(derated) .................................................................................................................................. 126
tDH-Diff(Vref-based) ............................................................................................................................. 126
tDS-Diff(base) ....................................................................................................................................... 126
tDS-Diff(derated) .................................................................................................................................. 127
tDS-Diff(Vref-based) ............................................................................................................................. 127
tDQSH .................................................................................................................................................. 127
tDQSL ................................................................................................................................................... 128
tDSS-Diff .............................................................................................................................................. 128
tDSH-Diff .............................................................................................................................................. 128
tDQSS-Diff ............................................................................................................................................ 128
Single ended DQS ..................................................................................................................................... 128
Slew Rate-Hold-SE-Fall(DQS) ............................................................................................................. 128
Slew Rate-Hold-SE-Rise(DQS) ............................................................................................................ 129
Slew Rate-Setup-SE-Fall(DQS) ........................................................................................................... 129
Slew Rate-Setup-SE-Rise(DQS) .......................................................................................................... 129
tDS-SE(base) ....................................................................................................................................... 129
tDIPW-SE ............................................................................................................................................. 129
tDSS-SE ............................................................................................................................................... 129
tDSH-SE ............................................................................................................................................... 129
tDQSS-SE ............................................................................................................................................ 130
tDH-SE(base) ....................................................................................................................................... 130
tDVAC(CK) ................................................................................................................................................. 130
tWPRE ....................................................................................................................................................... 130
tWPST ........................................................................................................................................................ 131
tWRPDE ..................................................................................................................................................... 132
tWRSRE ..................................................................................................................................................... 132
Differential DQS read measurements ........................................................................................................ 132
tDQSCK-Diff ......................................................................................................................................... 132
tDQSQ-DBI ........................................................................................................................................... 133
tDQSQ-Diff ........................................................................................................................................... 133
tAC-Diff ................................................................................................................................................. 133
tQH ....................................................................................................................................................... 133
SRQdiff-Rise(DQS) .............................................................................................................................. 134
SRQdiff-Fall(DQS) ................................................................................................................................ 134
iv DDR Analysis Printable Application Help
Table of Contents
Single-ended DQS read measurements .................................................................................................... 135
tDQSQ-SE ............................................................................................................................................ 135
tDQSCK-SE .......................................................................................................................................... 135
DDR2-tDQSCK ..................................................................................................................................... 135
Slew rate DQ .............................................................................................................................................. 136
SRQse-Fall(DQ) ................................................................................................................................... 136
SRQse-Rise(DQ) .................................................................................................................................. 136
tRDPDE ...................................................................................................................................................... 137
tRDSRE ...................................................................................................................................................... 137
tRPRE ........................................................................................................................................................ 137
tRPST ......................................................................................................................................................... 138
DQ measurements ..................................................................................................................................... 139
Slew Rate-Hold-Fall(DQ) ...................................................................................................................... 139
Slew Rate-Hold-Rise(DQ) .................................................................................................................... 139
Slew Rate-Setup-Fall(DQ) .................................................................................................................... 139
Slew Rate-Setup-Rise(DQ) .................................................................................................................. 139
Clock(Diff) measurements .......................................................................................................................... 139
SSC Downspread(CK) ......................................................................................................................... 139
SSC mod Freq(CK) .............................................................................................................................. 140
SSC Profile(CK) ................................................................................................................................... 140
tCH ....................................................................................................................................................... 140
tCK ....................................................................................................................................................... 140
tCL ........................................................................................................................................................ 140
tCH(abs) ............................................................................................................................................... 140
tCH(avg) ............................................................................................................................................... 141
tCK(abs) ............................................................................................................................................... 141
tCK(avg) ............................................................................................................................................... 141
tCL(abs) ................................................................................................................................................ 141
tCL(avg) ................................................................................................................................................ 142
tHP ....................................................................................................................................................... 142
tERR ..................................................................................................................................................... 142
tJIT(cc) ................................................................................................................................................. 143
tJIT(duty) .............................................................................................................................................. 143
tJIT(per) ................................................................................................................................................ 144
VID(ac) ................................................................................................................................................. 144
Input Slew-Diff-Rise(CK) ...................................................................................................................... 144
Input Slew-Diff-Fall(CK) ........................................................................................................................ 144
Clock (Single ended) .................................................................................................................................. 145
AC-Overshoot(CK#) ............................................................................................................................. 145
DDR Analysis Printable Application Help v
Table of Contents
AC-Overshoot(CK) ............................................................................................................................... 145
AC-OvershootArea(CK#) ...................................................................................................................... 145
AC-OvershootArea(CK) ........................................................................................................................ 146
AC-Undershoot(CK#) ........................................................................................................................... 146
AC-Undershoot(CK) ............................................................................................................................. 146
AC-UndershootArea(CK#) .................................................................................................................... 147
AC-UndershootArea(CK) ...................................................................................................................... 147
CKslew-Fall(CK) ................................................................................................................................... 148
CKslew-Fall(CK#) ................................................................................................................................. 148
CKslew-Rise(CK) ................................................................................................................................. 148
CKslew-Rise(CK#) ............................................................................................................................... 148
VIN(CK) ................................................................................................................................................ 148
VIN(CK#) .............................................................................................................................................. 148
Vix(ac)CK ............................................................................................................................................. 148
Vox(ac)CK ............................................................................................................................................ 149
VSWING(MAX)CK# .............................................................................................................................. 149
VSWING(MAX)CK ................................................................................................................................ 149
VSEH(AC)CK ....................................................................................................................................... 149
VSEH(AC)CK# ..................................................................................................................................... 150
VSEH(CK#) .......................................................................................................................................... 150
VSEH(CK) ............................................................................................................................................ 150
VSEL(AC)CK# ...................................................................................................................................... 151
VSEL(AC)CK ........................................................................................................................................ 151
VSEL(CK#) ........................................................................................................................................... 151
VSEL(CK) ............................................................................................................................................. 151
DQS(Single ended) measurements ........................................................................................................... 151
Vix(ac)DQS .......................................................................................................................................... 151
Vox(ac)DQS ......................................................................................................................................... 151
AC-Overshoot(DQS) ............................................................................................................................ 152
AC-Overshoot(DQS#) .......................................................................................................................... 152
AC-OvershootArea(DQS#) ................................................................................................................... 152
AC-OvershootArea(DQS) ..................................................................................................................... 153
AC-Undershoot(DQS) .......................................................................................................................... 153
AC-Undershoot(DQS#) ........................................................................................................................ 153
AC-UndershootArea(DQS#) ................................................................................................................. 154
AC-UndershootArea(DQS) ................................................................................................................... 154
WCK (Diff) .................................................................................................................................................. 155
SSC Downspread(WCK) ...................................................................................................................... 155
SSC mod Freq(WCK) ........................................................................................................................... 155
vi DDR Analysis Printable Application Help
Table of Contents
SSC Profile(WCK) ................................................................................................................................ 155
tDVAC(WCK) ........................................................................................................................................ 155
tWCK .................................................................................................................................................... 155
tWCK-DJ .............................................................................................................................................. 155
tWCKH ................................................................................................................................................. 156
tWCKHP ............................................................................................................................................... 156
tWCKL .................................................................................................................................................. 156
tWCK-Rise-Slew ................................................................................................................................... 156
tWCK-Fall-Slew .................................................................................................................................... 156
tWCK-RJ .............................................................................................................................................. 156
tWCK-TJ ............................................................................................................................................... 156
VWCK-Swing ........................................................................................................................................ 157
WCK (Single ended) .................................................................................................................................. 157
VIN(WCK) ............................................................................................................................................. 157
VIN(WCK#) ........................................................................................................................................... 157
Vix(ac)WCK .......................................................................................................................................... 157
VOL(WCK) ........................................................................................................................................... 157
VOH(WCK) ........................................................................................................................................... 157
VOL(WCK#) ......................................................................................................................................... 158
VOH(WCK#) ......................................................................................................................................... 158
WCKslew-Fall(WCK) ............................................................................................................................ 158
WCKslew-Fall(WCK#) .......................................................................................................................... 158
WCKslew-Rise(WCK) ........................................................................................................................... 158
WCKslew-Rise(WCK#) ......................................................................................................................... 158
Address-Command measurements ........................................................................................................... 159
AC-Overshoot ....................................................................................................................................... 159
AC-OvershootArea ............................................................................................................................... 159
AC-Undershoot ..................................................................................................................................... 160
AC-UndershootArea ............................................................................................................................. 160
Slew Rate-Hold-Fall(Addr-Cmd) ........................................................................................................... 161
Slew Rate-Hold-Rise(Addr-Cmd) ......................................................................................................... 161
Slew Rate-Setup-Fall(Addr-Cmd) ......................................................................................................... 161
Slew Rate-Setup-Rise(Addr-Cmd) ....................................................................................................... 161
tAH ....................................................................................................................................................... 161
tAPW .................................................................................................................................................... 161
tAS ........................................................................................................................................................ 162
tCIPW-High .......................................................................................................................................... 162
tCIPW-Low ........................................................................................................................................... 162
tCMDH .................................................................................................................................................. 162
DDR Analysis Printable Application Help vii
Table of Contents
tCMDPW .............................................................................................................................................. 162
tCMDS .................................................................................................................................................. 162
tIS(base) ............................................................................................................................................... 162
tIH(base) ............................................................................................................................................... 162
tIS(derated) .......................................................................................................................................... 163
tIH(derated) .......................................................................................................................................... 163
tIPW-High ............................................................................................................................................. 163
tIPW-Low .............................................................................................................................................. 163
Refresh ....................................................................................................................................................... 163
tCKSRE ................................................................................................................................................ 163
tCKSRX ................................................................................................................................................ 163
tRFC ..................................................................................................................................................... 164
tREFTR(Read) ..................................................................................................................................... 164
tREFTR(Write) ...................................................................................................................................... 164
tXSNRW ............................................................................................................................................... 164
Power down ............................................................................................................................................... 164
tPD ....................................................................................................................................................... 164
Active ......................................................................................................................................................... 164
tRAS ..................................................................................................................................................... 164
tRC ....................................................................................................................................................... 165
tRCDRD ............................................................................................................................................... 165
tRCDWR ............................................................................................................................................... 165
Precharge ................................................................................................................................................... 166
tPPD ..................................................................................................................................................... 166
tRP(ACT) .............................................................................................................................................. 166
tRP(MRS) ............................................................................................................................................. 166
tRP(REF) .............................................................................................................................................. 167
tRP(SRE) .............................................................................................................................................. 167
tRTPL ................................................................................................................................................... 167
GPIB commands
About the GPIB program ............................................................................................................................ 169
GPIB reference materials ........................................................................................................................... 169
Argument types .......................................................................................................................................... 169
Commands ................................................................................................................................................. 170
DDRA:APPLYBurstconfig ..................................................................................................................... 170
DDRA:ADDALLTerr .............................................................................................................................. 170
DDRA:ADDALLSLewdq ....................................................................................................................... 171
DDRA:ADDALLDiffdqs ......................................................................................................................... 171
viii DDR Analysis Printable Application Help
Table of Contents
DDRA:ADDCMDFLTFile ...................................................................................................................... 172
DDRA: ADVBURSTLevelmode ............................................................................................................ 172
DDRA:ADDALLSEdqs .......................................................................................................................... 173
DDRA:ADDMeas .................................................................................................................................. 173
DDRA:ALTernatethresholds ................................................................................................................. 175
DDRA:AMPBasedmargin ..................................................................................................................... 175
DDRA:BURSTIDMethod ...................................................................................................................... 176
DDRA:BURSTDETectmethod .............................................................................................................. 176
DDRA:BURSTLEngth ........................................................................................................................... 177
DDRA:BURSTLAtency ......................................................................................................................... 177
DDRA:BURSTLevelmode .................................................................................................................... 178
DDRA:BURSTTOlerance ..................................................................................................................... 178
DDRA:BUS ........................................................................................................................................... 179
DDRA:CLKFLTFile ............................................................................................................................... 179
DDRA:CSACTive ................................................................................................................................. 180
DDRA:CLEARALLMeas ....................................................................................................................... 180
DDRA:CSSOUrce ................................................................................................................................ 180
DDRA:CLKBARFLTFile ........................................................................................................................ 181
DDRA:CASMAX ................................................................................................................................... 181
DDRA:CASMIN .................................................................................................................................... 182
DDRA:CSLEvel .................................................................................................................................... 182
DDRA:CSMOde ................................................................................................................................... 182
DDRA:CUSTOMRate ........................................................................................................................... 183
DDRA:DATAHIGH ................................................................................................................................ 183
DDRA:DATALOW ................................................................................................................................ 184
DDRA:DQSBARFLTFile ....................................................................................................................... 184
DDRA:DQSFLTFile .............................................................................................................................. 185
DDRA:DQFLTFile ................................................................................................................................. 185
DDRA:DATAMID .................................................................................................................................. 186
DDRA:DATARate ................................................................................................................................. 186
DDRA:DQDQSLEVELSTAtus? ............................................................................................................ 187
DDRA:FLTtype ..................................................................................................................................... 187
DDRA:GENeration ............................................................................................................................... 187
DDRA:HYSTEREsis ............................................................................................................................. 188
DDRA:HORIzontalscaling .................................................................................................................... 188
DDRA:ISOLBurstlen ............................................................................................................................. 189
DDRA:LASTError? ............................................................................................................................... 189
DDRA:LOGICTrigger ............................................................................................................................ 189
DDRA:MEASType ................................................................................................................................ 190
DDR Analysis Printable Application Help ix
Table of Contents
DDRA:MARGIN .................................................................................................................................... 190
DDRA:POSTamble ............................................................................................................................... 190
DDRA:PREAmbletype .......................................................................................................................... 191
DDRA:PTPeak ..................................................................................................................................... 191
DDRA:RXMASKFile ............................................................................................................................. 191
DDRA:SOURCE:CLOCK ..................................................................................................................... 192
DDRA:SOURCE:STROBE ................................................................................................................... 192
DDRA:SOURCE:DATa ......................................................................................................................... 193
DDRA:SOURCE? ................................................................................................................................. 193
DDRA:SOURCE:CLOCKBar ................................................................................................................ 194
DDRA:SOURCE:STRObebar ............................................................................................................... 194
DDRA:STROBEHIGH .......................................................................................................................... 195
DDRA:STROBEMID ............................................................................................................................. 195
DDRA:STROBELOW ........................................................................................................................... 195
DDRA:SOURCE:WCKBar .................................................................................................................... 196
DDRA:SOURCE:WCK ......................................................................................................................... 196
DDRA:SYMBOLFile ............................................................................................................................. 197
DDRA:THREShold ............................................................................................................................... 197
DDRA:TDQS2DQMode ........................................................................................................................ 198
DDRA:TDQS2DQ ................................................................................................................................. 198
DDRA:TCKAVG ................................................................................................................................... 198
DDRA:TIMGMode ................................................................................................................................ 199
DDRA:TCKAVGMIN ............................................................................................................................. 199
DDRA:VCENTCA ................................................................................................................................. 199
DDRA:VCENTDQ ................................................................................................................................. 200
DDRA:VDD ........................................................................................................................................... 200
DDRA:VDDMode .................................................................................................................................. 201
DDRA:VERTicalscaling ........................................................................................................................ 201
DDRA:VERsion? .................................................................................................................................. 202
DDRA:VIHACMin? ............................................................................................................................... 202
DDRA:VIHDCMin? ............................................................................................................................... 202
DDRA:VILACMax? ............................................................................................................................... 203
DDRA:VILDCMax? ............................................................................................................................... 203
DDRA:VREF ......................................................................................................................................... 203
DDRA:VREFDC? ................................................................................................................................. 204
DDRA:VREFMode ................................................................................................................................ 204
DDRA:WRITEAmpgtread ..................................................................................................................... 204
DDRA:WCKBARFLTFile ...................................................................................................................... 205
DDRA:WCKFLTFile .............................................................................................................................. 205
x DDR Analysis Printable Application Help

Welcome

DDR (Dual Data Rate) is a dominant and fast-growing memory technology. It offers the high data transfer rates needed for virtually all computing applications, from consumer products to the most powerful servers. The high speeds of these signals require high performance measurement tools.
The DDRA application includes compliance measurements as part of our DDR Analysis solution. The DDR Analysis solution enables you to achieve new levels of productivity, efficiency, and measurement reliability. It requires the Jitter and Eye Diagram Analysis tool (Opt. DJA) and the Advanced Search and Mark capability (Opt. ASM).
Some of the DDRA features are:
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Provides debug, analysis, and compliance in one solution for multiple DDR standards such as DDR, DDR2, DDR3, DDR3L, DDR4. LPDDR, LPDDR2, LPDDR3,LPDDR4, GDDR3, and GDDR5.
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Enables analysis of compliance measurements either through the DDRA or DPOJET application for all bursts in an acquisition.
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Differentiates data reads from writes, or analyzes signal integrity on the clock or on a data (DQ) line during Read or Write cycles, or measures Data to Strobe setup and hold during Write cycles.
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Includes limit files to test measurement pass/fail status per standard, speed grades and speed bins. Supports non-standard speed grades.
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Provides both single-ended and differential measurements on Data, Strobe, Clock, Address and Command signals.
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Includes comprehensive measurement statistics.
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Includes sophisticated graphical analysis tools such as Histograms, Time Trends, Spectrums, Bathtub Plots, and Real-Time Eye® diagrams with superimposition of the strobe eye with the data eye.
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Produces consolidated reports automatically with pass/fail information, statistical measurement results, setup information, limits information, waveform path location, plots and user comments, if any.
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Automatically applies signal slew rate derating of measurement limits for Address/Command and data signals.
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Dynamically normalizes limits for clock measurements such as tERR based on the measured tCK(avg).
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Logic state configuration using the DDRA user interface.
DDR
DDR is the DRAM (Dynamic Random Access Memory) technology responsible for increasing data transfer rates to meet high­speed requirements and data capacity of computer systems.
DDR2
DDR2 is the Double Data Rate 2 SDRAM and is widely available in products with data rates up to 1066MT/s.
DDR3
DDR3 DRAM memory is widely available in products and extends data rates to 1600 MT/s and faster rates to come.
DDR3L
DDR3L (low voltage) DRAM memory is widely available in products and extends data rates to 1600 MT/s and faster rates to come.
DDR4
DDR4 DRAM memory is widely available in products and extends data rates to 3200 MT/s and faster rates to come.
DDR Analysis Printable Application Help xi
Welcome
Low Power DDR
LPDDR (Low Power DDR) is a technology for mobile phones and portable computing devices, driven by the need for faster operation with long battery life.
Low Power DDR2
LPDDR2 (Low Power DDR2) is a technology for mobile phones and portable computing devices as it supports advanced power management. Includes a reduced interface voltage of 1.2 V from the 1.8 V specification as compared to LPDDR memory technology. This results in a power consumption reduced by over 50%.
Low Power DDR3
LPDDR3 (Low Power DDR3) is a technology for mobile phones and portable computing devices as it supports advanced power management. Includes a reduced interface voltage of 1.2 V from the 1.8 V specification as compared to LPDDR memory technology. This results in a power consumption reduced by over 50%.
LPDDR4
LPDDR4 (Low Power DDR4) is an emerging technology for mobile phones and portable computing devices as it supports advanced power management. Includes a reduced interface voltage of 1.1 V from the 1.8 V specification as compared to LPDDR memory technology.
Graphic DDR3
GDDR3 (Graphic DDR) offers faster access and is used in graphics-intensive applications such as video cards and gaming systems.
GDDR5
GDDR5 (Graphic DDR) is a type of high performance dynamic random-access graphics card memory designed for applications requiring high bandwidth.
xii DDR Analysis Printable Application Help

Introduction to the application

Related documentation

Tektronix manuals are available at: www.tektronix.com/manuals and www.tektronix.com/software. Use the following table to determine the document that you need:
Table 1: List of reference documents
For information on Refer to
■
Operating the Oscilloscope
■
Software warranty
■
List of available applications
■
Compatible oscilloscopes
■
Relevant software and firmware version numbers
■
Applying a new option key label
■
Installing an application
■
Enabling an application
Oscilloscope user manual. Oscilloscope user online help.
Optional Applications Software on Windows-Based Oscilloscopes Installation Manual, which is provided on the
Optional Applications Software on Windows-Based Oscilloscopes DVD, in the Documents directory.
■
Downloading updates from the Tektronix Web site

Conventions

Online Help uses the following conventions:
■
When steps require a sequence of selections using the application interface, the “>” delimiter marks each transition between a menu and an option. For example, Analyze> DDR Analysis.
■
The terms “DDR application” and “application” refer to DDRA.
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The term “DPOJET application” or “DPOJET” refers to Jitter and Eye Diagram Analysis Tool.
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The term “oscilloscope” refers to any product on which this application runs.
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The term “DUT” is an abbreviation for Device Under Test.
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The term “select” is a generic term that applies to the methods of choosing an option: with a mouse or with the touch screen.
■
User interface screen graphics are taken from a DPO7000 series oscilloscope.
You can find a PDF (portable document format) file for this document in the Documents directory on the Optional Applications Software on Windows-Based Oscilloscopes DVD. The DVD booklet contains information on installing the application from the DVD and on how to apply a new label.
DDR Analysis Printable Application Help
1
Introduction to the application
Table 2: Icon descriptions
Icon Meaning
This icon identifies important information.
This icon identifies conditions or practices that could result in loss of data.
This icon identifies additional information that will help you use the application more efficiently.

Technical support

Tektronix welcomes your comments about products and services. Contact Tektronix through mail, telephone, or the Web site. Click Contacting Tektronix for more information. Tektronix also welcomes your feedback. Click Customer feedback for suggestions for providing feedback to Tektronix.

Customer feedback

Tektronix values your feedback on our products. To help us serve you better, please send us your suggestions, ideas, or other comments you may have regarding the application or oscilloscope.
Direct your feedback via e-mail to
techsupport@tektronix.com
Or FAX at (503) 627-5695, and include the following information:
General Information
■
Oscilloscope series (for example: DPO7000C or DSA/DPO/MSO70000C/D/DX series) and hardware options, if any.
■
Software version number.
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Probes used.
Application-specific Information
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Description of the problem such that technical support can duplicate the problem.
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If possible, save the oscilloscope and application setup files as .set and associated .xml files.
■
If possible, save the waveform on which you are performing the measurement as a .wfm file.
Once you have gathered this information, you can contact technical support by phone or through e-mail. In the subject field, please indicate “DDRA Problem” and attach the .set, .xml and .wfm files to your e-mail. If there is any query related to the actual measurement results, then you can generate a .mht report and send it. If you need to send very large files, technical support can assist you to transfer the files via ftp (file transfer protocol).
The following items are important, but optional:
■
Your name
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Your company
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Your mailing address
2 DDR Analysis Printable Application Help
Introduction to the application
■
Your phone number
■
Your FAX number
Enter your suggestion. Please be as specific as possible.
Please indicate if you would like to be contacted by Tektronix regarding your suggestion or comments.
DDR Analysis Printable Application Help 3
Introduction to the application
4 DDR Analysis Printable Application Help

Getting started

Product description

DDR Analysis is a standard specific solution tool for Tektronix Performance Digital Oscilloscopes (DPO7000C or DSA/DPO/ MSO70000C/D/DX series). DDR Analysis requires Jitter and Eye Diagram Analysis Tool (Opt.DJA) and the advanced Search and Mark capability (Opt. ASM).
The features of DDRA are:
■
Provides debug, analysis, and compliance in one solution for multiple DDR standards such as DDR, DDR2, DDR3, DDR3L, DDR4. LPDDR, LPDDR2, LPDDR3, LPDDR4,GDDR3, and GDDR5.
■
Identifies Read and/or Write operations automatically.
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Custom data rates and input levels to tailor DDRA Read and/or Write burst identification.
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Provides both single-ended and differential measurements on Data, Strobe, Clock, Address and Command signals.
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Analyze compliance measurements either through DDRA or Jitter and Eye Diagram Analysis Tool.
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Limit files to test measurement pass/fail status.
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Automatically applies signal slew rate derating of measurement limits for Address/Command and data signals.
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Preferences shortcut available for all DDRA steps. For more details, refer to the DPOJET online help.
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Logic state configuration using the DDRA user interface.
DDR
DDR is the DRAM (Dynamic Random Access Memory) technology responsible for increasing data transfer rates to meet high­speed requirements and data capacity of computer systems.
DDR2
DDR2 is the Double Data Rate 2 SDRAM and is widely available in products with data rates up to 1066MT/s.
DDR3
DDR3 DRAM memory is widely available in products and extends data rates to 1600 MT/s and faster rates to come.
DDR3L
DDR3L (low voltage) DRAM memory is widely available in products and extends data rates to 1600 MT/s and faster rates to come.
DDR4
DDR4 DRAM memory is widely available in products and extends data rates to 3200 MT/s and faster rates to come.
Low Power DDR
LPDDR (Low Power DDR) is an emerging technology for mobile phones and portable computing devices, driven by the need for faster operation with long battery life.
Low Power DDR2
LPDDR (Low Power DDR) is an emerging technology for mobile phones and portable computing devices, driven by the need for faster operation with long battery life.
DDR Analysis Printable Application Help 5
Getting started
Low Power DDR3
LPDDR3 (Low Power DDR3) is a technology for mobile phones and portable computing devices as it supports advanced power management. Includes a reduced interface voltage of 1.2 V from the 1.8 V specification as compared to LPDDR memory technology. This results in a power consumption reduced by over 50%.
Low Power DDR4
LPDDR4 (Low Power DDR4) is an emerging technology for mobile phones and portable computing devices as it supports advanced power management. Includes a reduced interface voltage of 1.1 V from 1.8 V specification as compared to LPDDR memory technology.
Graphic DDR3
GDDR3 (Graphic DDR) offers faster access and is used in graphics-intensive applications such as video cards and gaming systems.
GDDR5
GDDR5 (Graphic DDR) is a type of high performance dynamic random-access graphics card memory designed fro applications requiring high bandwidth.

DDRA prerequisites

To use the DDRA application on instruments using 64-bit operating systems, you need DPOJET Advanced (Opt. DJA) enabled.

Requirements and restrictions

DPOJET (DJA) is required to operate DDRA on your oscilloscope. Also refer to subsequent requirements for DPOJET.

Supported probes

The application supports the following probes:
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TAP2500
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TAP1500
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TCP0030
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P6158
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P6101B
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P6246
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P6247 (DPO7254 only)
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P6248 (DPO7254 only)
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P6249
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P6150
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P6158
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P7240
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P7260
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P7330
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P7340A
6 DDR Analysis Printable Application Help
Getting started
■
P7350
■
P7360A
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P7380A
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P7313A
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P7513
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P7520A
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P7520
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P7500 Series TriMode

Installing the application

Refer to the Optional Applications Software on Windows-Based Oscilloscopes Installation Manual for the following information:
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Software warranty.
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List of available applications, compatible oscilloscopes, and relevant software and firmware version numbers.
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Applying a new option installation key label.
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Installing an application.
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Enabling an application.
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Downloading updates from the Tektronix Web site.
You can find a PDF (portable document format) file for this document in the Documents directory on the Optional Applications Software on Windows-Based Oscilloscopes DVD. The DVD booklet contains information on how to install the application from the DVD and on how to apply a new option installation key label.
DDR Analysis Printable Application Help 7
Getting started

About DDRA

Click Help > About DPOJET to view DDRA application details such as the software released version number, application name and copyright.
NOTE. The version displayed above is indicative only, the version number displayed will vary depending upon the exact version of the application installed.
8 DDR Analysis Printable Application Help

Operating basics

About basic operations

Starting the application

On the oscilloscope menu bar, click Analyze > DDR Analysis to open the application.

Menu controls

Table 3: Application Menu Controls descriptions
Item Description
Tab Shortcut to a menu in the menu bar or a category of menu options; most tabs are short cuts.
Area Visual frame with a set of related options.
Option button Button that defines a particular command or task.
Field Box that you can use to type in text, or to enter a value with the Keypad or a Multipurpose knob.
Check Boxes Use to select configuration options or clear preferences.
Browse Displays a window where you can look through a list of directories and files.
Command button
Virtual Keypad icon
MP knob references (a or b)
Button that initiates an immediate action such as Run command button in the control panel.
Click to use on-screen keypad to enter alphanumeric values.
Identifiers that show which Multi Purpose Knob (MPK) may be used as an alternate means to control a parameter; turn the knob on the oscilloscope front panel to adjust the corresponding parameter. Also, the value can be entered directly on the MPK display component.

Virtual keypad

Select the
icon and use the virtual keypad to enter alphanumeric values, such as reference voltage levels.
DDR Analysis Printable Application Help 9
Operating basics

Tips on the DDRA user interface

Here are some tips to help you with the application user interface:
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Use the Single button to obtain a set of measurements from a single new waveform acquisition. Pushing the button again before process is completed will interrupt the processing cycle.
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Use the Run button
to continuously acquire and accumulate measurements. If prior measurements have been acquired and have not been cleared, the new measurement are added to the existing set. Push the button again to interrupt the current acquisition.
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Use the Recalc button to perform measurements on the waveform currently displayed on the oscilloscope without performing a new acquisition. This is useful if you wish to modify a configuration parameter and re-run the measurements on the current waveform.
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Use the Clear button to clear all existing measurement results. Note that adding or deleting a measurement, or changing a configuration parameter of an existing measurement, will also cause measurements to be cleared. This is to prevent the accumulation of measurement statistics or sets of statistics that are not coherent.
10 DDR Analysis Printable Application Help
Operating basics

Basic oscilloscope functions

Application directories

The installation directory for DDRA executable files is C:\TekApplications\DDRA for oscilloscope running with Windows and C:\Users\Public\Tektronix\TekApplications\DDRA for oscilloscopes running with Windows7 operating system. During installation, the application sets up a limits folder in the user directory. This folder contains limit files for various DDR standards and speed grades.
For 64-bit systems, the DDRA installer copies the symbol files into the following location: C:\Users\Public\Tektronix
\TekScope\BusDecodeTables\DDR. This is different from the default TekScope location at C:\Users\[Username] \Tektronix\Tekscope\BusDecodeTables.

File name extensions

Table 4: File name extensions
File Extension Description
.csv An ascii file containing Comma Separated Values. This file format may be read by any ascii text
editor (such as Notepad) or may be imported into spreadsheets such as Excel.
.xml An ascii file containing measurement setup information, limits or other data in Extensible
Markup Language.
.set A binary file containing oscilloscope setup information in a proprietary format.
.mht An HTML archive file, compatible with common Windows applications; contains the full report,
including text and graphics.
.wfm A binary file containing an oscilloscope waveform record in a recallable, proprietary format.
.tsf A symbol file containing various symbols for various logic trigger patterns.
.chm, .pdf Help manuals.

Returning to the application

When you access oscilloscope functions, the DDRA control windows may be replaced by the oscilloscope control windows or by the oscilloscope graticule. You can access oscilloscope functions in the following ways:
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From the menu bar on the oscilloscope, choose Analyze > DDR Analysis.
■
Alternatively, you can switch between recently used control panels using the forward or backward arrows corner of the control panel.
on the right

Control panel

The Control Panel appears on the right of the application window. Using this panel, you can start or stop the sequence of processes for the application and the oscilloscope to acquire information from the waveform. The controls are Clear, Recalc, Single, and Run. The following table describes each of these controls:
Item Description
Clear Clears the current result display and resets any statistical results and autoset ref levels. For any
input sources that have reference level autoset enabled, clears the current ref levels so that they will be recalculated during the next acquisition.
Recalc Runs the selected measurements on the currently displayed waveform(s), without first
performing a new acquisition.
DDR Analysis Printable Application Help 11
Operating basics
Item Description
Single Initiates a single new acquisition and runs the selected measurements.
Run Initiates new acquisitions and runs the selected measurements repeatedly until Stop is clicked.
For any non-live sources (Reference waveforms or Math waveforms not dependent on a live
channel), only a single processing cycle will occur.
Show Plots Displays the plot summary window when clicked. This button appears in the control panel only
when one or more plots have been defined.
Advanced Setup DPOJET
Transitions to the Jitter and Eye Diagram Analysis application when clicked, importing all
currently defined DDRA measurements. This button appears in the control panel when you
open the DDR analysis application. This is useful if you wish to add additional measurements
not defined in DDRA, or wish to change measurement configurations to intentionally deviate
from those recommended by DDRA.

Saving and recalling setups

Saving a setup

The DDRA application state is automatically saved along with the oscilloscope state. To save the oscilloscope settings and the application state, follow these steps:
1. Click File > Save As > Setup.
2. In the file browser, select the directory to save the setup file.
3. Select or enter a file name. The application appends *_DDRA.xml and *_DPOJET.xml to store the DDR setup, and
*.set to store the oscilloscope settings.
4. Click Save.
NOTE. After the oscilloscope application is started, DDRA needs to be launched at least once before any saved DDRA configuration can be recalled.

Recalling a saved setup

To recall a previously saved set of application and oscilloscope settings, do the following steps:
NOTE. While recalling setup files with both DDRA and DPOJET saved settings, DDRA setup values get a higher precedence over DPOJET setup values. For example: Select a DPOJET measurement and a DDRA measurement, change the ref levels of DPOJET measurement and save the setup file. On recalling the setup file, you will see that the DPOJET ref level settings are overwritten by the DDRA measurement ref levels.
1. Click File > Recall.
2. Click Setup in the left column if it is not already selected.
3. Select the directory in the file browser from which you wish to recall the setup file.
4. Select a .set file and click Recall.
NOTE. Only .set files can be selected for recall; any corresponding *_DDRA.xml and *_DPOJET.xml file in the same directory will be recalled as well, if DDRA has been launched at least once since the oscilloscope application was started. If DDRA has not been launched at least once, the oscilloscope settings will be recalled but the DDRA configuration will be ignored.
12 DDR Analysis Printable Application Help
Operating basics

Recalling the default setup

To recall the default application and oscilloscope settings, click File > Recall Default Setup.
NOTE. Recalling default setup sets the DDRA application to DDR3 generation and data rate, None.

Search and mark

The data rate, generation, and measurement type selected in DDRA are also set in Advanced Search and Mark (ASM). Marks are available only for Read and Write bursts measurement type. You can configure Search using Advance > Search > Configure. The identified bursts are shown as small inverted marks ( ) in the oscilloscope display area. Each pair of marks specifies the start and stop of a burst. You can traverse from one mark to the other using the Mark Control window.
NOTE. LPDDR4 burst cannot be configured from ASM window.
DDR Analysis Printable Application Help 13
Operating basics

Limits

A limits file allows you to configure the limits used to determine Pass or Fail status for tests. Each limits file includes a list of one or more measurements, and the ranges of acceptable values for any or all statistics for each measurement that include combinations of all measurements and statistical characteristics, and an appropriate range of values for each combination.
The application provides preconfigured limits files for many combinations of standards and speed grades. You can create one by specifying limits for any of the result parameters such as Mean, Std Dev, Max, Min, peak-to-peak, population, MaxPosDelta and MinPosDelta. For each of these result parameters, you can specify the Upper Limit Equality (ULE), Lower Limit Equality (LLE), or Both. The measurement names in the limits file must be entered as mentioned in About DDR Analysis.
To include Pass/Fail status in the result statistics, you can create a custom limits file in the following format using an XML editor or any other editor. If the file is created in any other editor such as Notepad, it should be saved in Unicode format.
The following is a sample of the limit file for DDR2 generation, the data rate being 667 MHz
<?xml version="1.0" encoding="utf-16" ?>
<Main>
<Measurement>
<NAME>DDR Hold–Diff</NAME>
<STATS>
<STATS_NAME>Min</STATS_NAME>
<LIMIT>BOTH</LIMIT>
<ULE>175e-12</ULE>
<LLE>0</LLE>
</STATS>
<Measurement>
<NAME>tDH-Diff(base)</NAME>
<STATS>
<STATS_NAME>Min</STATS_NAME>
<LIMIT>BOTH</LIMIT>
<ULE>175e-12</ULE>
<LLE>0</LLE>
</STATS>
</Measurement>
</Main>
You can find limit files for various data rates of different DDR standards and speed bins at C:\Users\Public\Tektronix
\TekApplications\DDRA\Limits.
NOTE. Base limit values change based on the selected AC configuration at Step6 . For DDR3 1333 MT/s and 1600 MT/s, AC 150 ref level are applied independent of the specified AC config.
14 DDR Analysis Printable Application Help
Operating basics

Dynamic limits

The application supports both static (predefined using limits file) and dynamic limits. Dynamic limits are available for DDRA clock and other measurement groups. They are calculated using the result of other measurement(s).
The concept of dynamic limits is explained taking an example of a measurement, tCH(avg):
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If the dynamic limits of a measurement depend on the result of other measurement(s) that has not yet been calculated, the limit text field in the results panel shows “Derived...”. A tool tip displays the message “This limit is calculated based on measurement tCK(avg)”.
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On clicking Run/Single, the results are shown in the following figure:
■
If there is an error in calculating dynamic limits, the limit text field displays “Error...” as shown. A tool tip displays the message “This limit is calculated based on measurement tCK(avg)”.
DDR Analysis Printable Application Help 15
Operating basics
References
Dynamic Limits for LPDDR Measurements
Dynamic Limits for LPDDR2 Measurements
Dynamic Limits for LPDDR4 Measurements
Dynamic Limits for DDR Measurements
Dynamic Limits for DDR2 Measurements
Dynamic Limits for DDR3 Measurements

Setting up DDR for analysis

DDR standards and their measurements

The following tables lists the measurements displayed for each DDR standard:
NOTE. For more details on the measurements, refer to the Algorithms section.
The clock measurements displayed for LPDDR and DDR standards are tCH, tCK, tHP, and tCL.
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
Write Bursts
Data Eye Width ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
Data Eye Height ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tWRSRE ✓
tWRPDE ✓
tDQS2DQ ✓
tWPRE ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tWPST ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
DDRARXMask ✓ ✓
Differential DQS
Input Slew-Diff­Fall(DQS)
Input Slew-Diff­Rise(DQS)
tDH-Diff(base) ✓ ✓ ✓ ✓ ✓
tDH-Diff(derated) ✓ ✓ ✓ ✓ ✓
tDH-Diff(Vref­based)
tDQSH ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tDQSL ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tDS-Diff(base) ✓ ✓ ✓ ✓ ✓
tDS-Diff(derated) ✓ ✓ ✓ ✓ ✓
tDS-Diff(Vref­based)
✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓
✓ ✓
✓ ✓
16 DDR Analysis Printable Application Help
Operating basics
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
tDSS-Diff ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tDQSS-Diff ✓ ✓ ✓ ✓
tDSH-Diff ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
TdIPW-High ✓ ✓ ✓
TdIPW-Low ✓ ✓ ✓
VIHL-AC ✓ ✓
SRIN_dIVW_Rise ✓ ✓
SRIN_dIVW_Fall ✓ ✓
tDVAC(DQS) ✓ ✓ ✓ ✓ ✓
Single Ended DQS
Slew Rate-Hold­SE-Fall(DQS)
Slew Rate-Hold­SE-Rise(DQS)
Slew Rate-Setup­SE-Fall(DQS)
Slew Rate-Setup­SE-Rise(DQS)
tDH-SE(base) ✓ ✓ ✓
tDH-SE(derated) ✓
tDS-SE(base) ✓ ✓ ✓
tDS-SE(derated) ✓
tDIPW-SE ✓ ✓ ✓ ✓ ✓ ✓
tDQSS-SE ✓ ✓ ✓
tDSH-SE ✓ ✓ ✓ ✓ ✓
tDSS-SE ✓ ✓ ✓ ✓ ✓
Slew Rate DQ
Slew Rate-Hold­Fall(DQ)
Slew Rate-Hold­Rise(DQ)
Slew Rate-Setup­Fall(DQ)
Slew Rate-Setup­Rise(DQ)
tDQSS
RX Mask ✓
Read Bursts
Data Eye Width ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
Date Eye Height ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tRDSRE ✓
✓
✓
✓
✓
✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓
DDR Analysis Printable Application Help 17
Operating basics
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
tRDPDE ✓
tDQSCK ✓ ✓ ✓ ✓
tQW_Total ✓
tQW_Total_DBI ✓
tRPRE ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tRPST ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
Differential DQS
tAC-Diff ✓ ✓ ✓
tDQSCK-Diff ✓ ✓ ✓ ✓ ✓
tDQSQ-Diff ✓ ✓ ✓ ✓ ✓ ✓ ✓
tDQSQ-DBI ✓
tDVAC(DQS) ✓ ✓ ✓ ✓ ✓
tQH ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tQH_DBI ✓
tQSL ✓ ✓ ✓ ✓ ✓ ✓
tQSL_DBI ✓
tLZ(DQ) ✓ ✓
tHZ(DQ) ✓ ✓
tQSH ✓ ✓ ✓ ✓ ✓ ✓
tQSH_DBI ✓
SRQdiff­Rise(DQS)
SRQdiff-Fall(DQS) ✓ ✓ ✓ ✓ ✓ ✓
Single Ended DQS
tDIPW-SE ✓
tDQSS-SE ✓
tDSH-SE ✓
tDSS-SE ✓
tDQSCK-SE ✓
tDQSQ-SE ✓ ✓ ✓
Vox(ac)DQS ✓
tLZ(DQS) ✓ ✓
tHZ(DQS) ✓ ✓
Slew Rate (DQ)
SRQse-Fall(DQ) ✓ ✓ ✓ ✓ ✓ ✓
SRQse-Rise(DQ) ✓ ✓ ✓ ✓ ✓ ✓
Clock (Diff)
Clock Eye Height ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
Clock Eye Width ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓
18 DDR Analysis Printable Application Help
Operating basics
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
tCH(abs) ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tCH(avg) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tCK(abs) ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tCK(avg) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tCL(abs) ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tCL(avg) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tDVAC(CK) ✓ ✓ ✓ ✓ ✓
tERR (Includes measurements from tERR2 to 49per)
tERR(11–50per) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tERR(2per) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tERR(3per) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tERR(4per) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tERR(5per) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tERR(6–10per) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tJIT(cc) ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tJIT(duty) ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
tJIT(per) ✓ ✓ ✓ ✓ ✓ ✓ ✓
tHP ✓ ✓ ✓ ✓ ✓
VID(ac) ✓ ✓ ✓
Input Slew-Diff­Rise(CK)
Input Slew-Diff­Fall(CK)
tDVAC(CK) ✓ ✓ ✓
tCK ✓
tCH ✓
tCL ✓
SSC Downspread (CK)
SSC Mod Freq (CK)
Clock (Single Ended)
AC­Overshoot(CK#)
AC­Overshoot(CK)
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓
✓
✓
DDR Analysis Printable Application Help 19
Operating basics
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
ACOvershootAre a(CK#)
ACOvershootAre a(CK)
AC­Undershoot(CK#)
AC­Undershoot(CK)
AC­UndershootArea(C K#)
AC­UndershootArea(C K)
VIXCA ✓
Vix(ac)CK ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
Vox(ac)CK ✓
VSWING(MAX)CK ✓
VSWING(MAX)CK #
VSEH(AC)CK ✓ ✓ ✓ ✓
VSEH(AC)CK# ✓ ✓ ✓ ✓
VSEH(CK#) ✓ ✓ ✓ ✓
VSEH(CK) ✓ ✓ ✓ ✓
VSEL(AC)CK ✓ ✓ ✓ ✓
VSEL(AC)CK# ✓ ✓ ✓ ✓
VSEL(CK#) ✓ ✓ ✓ ✓
VSEL(CK) ✓ ✓ ✓ ✓
VIN(CK) ✓
VIN(CK#) ✓
CKSlew-Rise(CK) ✓
CKSlew­Rise(CK#)
CKSlew-Fall(CK) ✓
CKSlew-Fall(CK#) ✓
DQS (Single Ended, Write)
AC­Overshoot(DQ)
AC­Undershoot(DQ)
AC­Overshoot(DQS#)
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓
✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
20 DDR Analysis Printable Application Help
Operating basics
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
AC­Overshoot(DQS)
AC­OvershootArea(D Q)
AC­UndershootArea(D Q)
AC­OvershootArea(D QS#)
AC­OvershootArea(D QS)
AC­Undershoot(DQS# )
AC­Undershoot(DQS)
AC­UndershootArea(D QS)
AC­UndershootArea(D QS#)
Vix(ac)DQS ✓ ✓ ✓ ✓ ✓
VIXDQ ✓
VSWING(MAX)D QS
VSWING(MAX)D QS#
VSEH(AC)DQS ✓ ✓ ✓ ✓ ✓
VSEH(AC)DQS# ✓ ✓ ✓ ✓ ✓
VSEH(DQS#) ✓ ✓ ✓
VSEH(DQS) ✓ ✓ ✓
VSEL(AC)DQS ✓ ✓ ✓ ✓ ✓
VSEL(AC)DQS# ✓ ✓ ✓ ✓ ✓
VSEL(DQS#) ✓ ✓ ✓
VSEL(DQS) ✓ ✓ ✓
DQS (Single Ended, Read)
AC­OvershootArea(D Q)
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓
✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
DDR Analysis Printable Application Help 21
Operating basics
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
AC­UndershootArea(D Q)
AC­Overshoot(DQ)
AC­Undershoot(DQ)
AC­OvershootArea(D QS)
AC­UndershootArea(D QS)
AC­Overshoot(DQS)
AC­Undershoot(DQS)
AC­OvershootArea(D QS#)
AC­UndershootArea(D QS#)
AC­Overshoot(DQS#)
AC­Undershoot(DQS# )
Vox(ac)DQS ✓
VESH(AC)DQS ✓
VESH(AC)DQS# ✓
VESH(DQS#) ✓
VSEH(DQS) ✓
VSEK(AC)DQS ✓
VSEL(AC)DQS# ✓
VSEL(DQS#) ✓
VSEL(DQS) ✓
Address/Command
AC-Overshoot ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
AC­OvershootArea
AC-Undershoot ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
22 DDR Analysis Printable Application Help
Operating basics
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
AC­UndershootArea
DDRARXMask ✓
SRIN_cIVW_Fall ✓
SRIN_cIVW_Rise ✓
VIHL_AC(CA) ✓
InputSlew-Diff­Fall(CK)
InputSlew-Diff­Rise(CK)
Slew Rate-Hold­Fall(Addr/Cmd)
Slew Rate-Hold­Rise(Addr/Cmd)
Slew Rate-Setup­Fall(Addr/Cmd)
Slew Rate-Setup­Rise(Addr/Cmd)
tIH(base) ✓ ✓ ✓ ✓ ✓ ✓
tIH(base)CA ✓
tIH(base)CS ✓
tIH(derated)CA ✓
tIH(derated)CS ✓
tIPW-High(CA) ✓
tIPW-High(CS) ✓
tIPW-Low(CA) ✓
tIPW-Low(CS) ✓
tIS(base)CA ✓
tIS(base)CS ✓
tIS(derated)CA ✓
tIS(derated)CS ✓
tIS(base) ✓ ✓ ✓ ✓ ✓ ✓
tIS(derated) ✓ ✓ ✓ ✓
tIS(Vref-based) ✓
tIH(Vref-based) ✓
tIH(derated) ✓ ✓ ✓ ✓
tIPW-High ✓ ✓ ✓ ✓ ✓ ✓ ✓
tIPW-Low ✓ ✓ ✓ ✓ ✓ ✓ ✓
tDIPW ✓
tCMDS ✓
✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓
✓ ✓ ✓ ✓ ✓
DDR Analysis Printable Application Help 23
Operating basics
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
tCMDH ✓
tCHDPW ✓
tAS ✓
tAH ✓
tAPW ✓
TCIPW-High ✓
TCIPW-Low ✓
WCK (Differential)
tWCK-Rise-Slew ✓
tWCK-Fall-Slew ✓
tWCK-TJ ✓
tWCK-DJ ✓
tWCK-RJ ✓
VWCK-Swing ✓
tDVAC(WCK) ✓
tJIT(cc) ✓
tJIT(per) ✓
tWCK ✓
tWCKH ✓
tWCKL ✓
tWCKHP ✓
SSC Downspread (WCK)
SSC Mod Freq (WCK)
SSC Profile(WCK) ✓
WCK (Single Ended)
VIN(WCK) ✓
VIN(WCK#) ✓
VIX(AC)WCK ✓
VOL(WCK) ✓
VOH(WCK) ✓
VOL(WCK#) ✓
VOH(WCK#) ✓
WCKSlew­Rise(WCK)
WCKSlew­Rise(WCK#)
WCKSlew­Fall(WCK)
✓
✓
✓
✓
✓
24 DDR Analysis Printable Application Help
Operating basics
Measurements DDR DDR2 DDR3 DDR3L DDR4 LPDDR LPDDR2 LPDDR3 LPDDR4 GDDR3 GDDR5
WCKSlew-
✓
Fall(WCK#)
Refresh
tCKSRE ✓
tCKSRX ✓
tRFC ✓
tXSNRW ✓
tREFTR(Write) ✓
tREFTR(Read) ✓
Power Down
tPD ✓
Active
tRC ✓
tRAS ✓
tRCDRD ✓
tRCDWR ✓
Precharge
tPPD ✓
tRP ✓
tRP(ACT) ✓ ✓ ✓
tRP(MRS) ✓ ✓ ✓
tRP(REF) ✓ ✓
tRP(SRE) ✓
tRTPL ✓
NOTE. The clock measurements displayed for LPDDR and DDR standards are tCH, tCH, tHP, and tCL.
When you select GDDR3 as the standard, the application displays a message: "GDDR3 not completely supported."

Derating

Signal slew rate derating is required to verify the setup and hold timing requirements on address/command and data signals. The base setup and hold limits are defined using input signals that have a 1.0 V/ns slew rate. To determine final pass/fail status, the limits must be adjusted based on the actual slew rates of the target signals, according to derating tables appearing in the DDR2 and DDR3 specifications.
DDR2 derated measurements for data signals are as follows:
■
tDS-SE(derated)
■
tDH-SE(derated)
■
tDS-Diff(derated)
■
tDH-Diff(derated)
DDR Analysis Printable Application Help 25
Operating basics
DDR3 derated measurements are as follows:
■
tDS-Diff(derated)
■
tDH-Diff(derated)
The DDR2/DDR3 Address/Command derated measurements are as follows:
■
tIH(derated)
■
tIS(derated)
The derated value (Δ) is calculated as per the JEDEC standard using either the DDR Method or Nominal Method, depending on the user configuration.
Derating is explained taking an example of Setup(tIS) measurement. The same concept is applicable for other derated measurements.
When the nominal method is set, Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V between the last crossing of V
and the first crossing of V
REF(dc)
REF(dc)
. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate
IH(ac)min
and the first crossing of V
IL(ac)
max.
+
If the DDR Method is set, the application takes the maximum slope. This method is applicable if the actual signal is earlier than the nominal slew rate line.
26 DDR Analysis Printable Application Help
Operating basics
According to the specified reference levels, rise slew rate is always positive whereas fall slew rate is negative. A single slew rate value is obtained by averaging the absolute values of rise and fall slew rate. Using this value and a similarly-derived slew rate for the clock signal, the total setup time (tIS) is calculated by adding ΔtIS to the tIS(base)limit from the following table:
Table 5: Address/Command Setup and Hold Values
Units(ps) DDR3–800 DDR3–1066 DDR3–1333 DDR3–1600 Units
tIS(base) AC 175 200 125 65 45 ps
tIS(base) AC150 350 275 190 170 ps
tIH(base) 275 200 140 120 ps
NOTE. For DDR3 speeds 1333 and 1600 MT/s, the AC 150 reference levels are applied, though the default selection in the Step
6 is AC175.
ΔtIS is determined using the derating table (AC 175), where the Y-axis represents the Address/Command slew rate and the X­axis, the clock differential value. By indexing the Address/Command value and Clock differential value, ΔtIS value is obtained from AC175 table.
The calculated slew rate is approximated to the derating table specified value (Example: 0.4 V/ns ≈ 1.0V/ns). For values greater than 4.0 V/ns, the table returns the base limit value.
For example: For a Clock differential value= 1.0 V/ns, Address/Command Slew Rate =1.0 V/ns, and AC 175 Threshold selected in Step 6, the resulting derated values are:
tIS
deratedlimit
tIS
deratedlimit
= tIS(base)
limit
+ΔtIS.
= 200+ 40= 240
The result statistics of the both tIS(base) and tIS(derated) are the same as shown in the following figure. In case of derating, the limit values get changed depending on the signal slew rate.
Reference. '
DDR3 Measurement Sources
DDR2 Measurement Sources
DDR Analysis Printable Application Help 27
Operating basics

About DDR analysis

The DDR Analysis window allows you to select various standards, set up and run a pre-configured measurement either through the DDRA or the DPOJET application.
Select Analyze > DDR Analysis to open the DDRA application.
The setup panel in the DDR Analysis application includes the following steps:
Generation, Rate and Levels
Interposer Filter
Measurements and Sources
Burst Detection Method
Burst Detection Settings
Thresholds and Scaling
NOTE. You can use the Next/Prev buttons or click directly on the step numbers to traverse through the steps in the DDR Analysis. The steps for which configuration is complete are denoted .
The setup panel displays hints to help you understand the configuration options wherever applicable.
You can run a set of measurement in either of the two ways:
■
Click Run to start the acquisition sequence using the selected settings and to view the results in the DDRA window. This is the normal way to generate results.
■
Click to move to the DPOJET application, where you can add or modify measurements before
sequencing. For more details, refer to the DPOJET Online Help. You need to click
in the DPOJET
application to return to the DDRA window. Alternatively, you can reselect Analyze >DDR Analysis from the menu bar.

Step 1: Generation rate and levels

Select the DDR generation, data rate and the voltage levels (if required). There are different speed bins for each standard data rate for specific DDR generations.
1. Select the DDR Generation from the drop-down list.
2. Select the Data Rate from the drop-down list. On selecting Custom, an edit box allows you to enter the value using the
virtual keypad. Limit files are not defined for custom data rates for Pass/Fail status and as a result, the application displays a hint at the bottom of the screen “Please provide a limits file under Jitter and Eye > Limits”. Note that selecting non-standard data rates in ASM (under Search > DDR Read or DDR Write), changes the data rate to “None” in DDRA.
28 DDR Analysis Printable Application Help
Operating basics
3. Set the voltage levels:
■
If you select JEDEC Defaults, the application uses the nominal voltage levels according to the JEDEC specification.The Vdd field is not editable.
■
If you select User Defined, enter the Vdd or Vref voltage values using the virtual keypad.
NOTE. The Vcent DQ and Vcent CA voltage values are only available for LPDDR4. For DDR4 and LPDDR4, the external Vref is not available. Vcent is similar to the traditional Vref parameter but takes into account the fact that the actual reference voltage used inside the DRAM is adjusted during write training and is not physically visible at the balls of the DRAM.
4. (Optional) Click View to view the Vih and Vil values calculated automatically based on the Vref value. To manually adjust the reference levels, go to Step6 of DDRA or use the DPOJET source configuration panel.
Vdd
Is the supply voltage for each DDR standard. Vdd is based on DDR generation.
Vref
Is the reference voltage for each DDR standard. Vref is calculated using Vdd, which in turn is based on DDR generation. In most cases, Vref=0.5Vdd.
VcentDQ
VcentDQ is the voltage at which the cumulative eye of the pin DQx is widest.
VcentCA
VcentCA is the voltage at which the cumulative eye of the pin CAx is widest.
The following table lists the minimum and maximum values of Vdd, Vref, VcentDQ, and VcentCA in the User Defined mode for all DDR generations:
DDR
Vdd Vref VcentDQ VcentCA
Generations
Default Min Max Default Min Max Default Min Max Default Min Max
1
DDR
2.5 V –6 V 6 V 1.25 V –6 V 6 V NA NA NA NA NA NA
DDR2 1.8 V –6 V 6 V 900 mV –6 V 6 V NA NA NA NA NA NA
DDR3 1.5 V –6 V 6 V 750 mV –6 V 6 V NA NA NA NA NA NA
DDR3L 1.35 V –6 V 6 V 675 mV –6 V 6 V NA NA NA NA NA NA
DDR4 1.2 V –6 V 6 V NA NA NA 850mV -2 V 2 V 600mV -2 V 2 V
LPDDR 1.8 V –6 V 6 V 900 mV –6 V 6 V NA NA NA NA NA NA
LPDDR2 1.2 V –6 V 6 V 600 mV –6 V 6 V NA NA NA NA NA NA
LPDDR3 1.2 V –6 V 6 V 600 mV –6 V 6 V NA NA NA NA NA NA
GDDR3 1.8 V –6 V 6 V 900 mV –6 V 6 V NA NA NA NA NA NA
GDDR5 1.5 V –6 V 6 V 750 mV –6 V 6 V NA NA NA NA NA NA
LPDDR4 1.1V -6 V 6 V NA NA NA 201.5 mV –1 V 1 V 191.5 mV –1 V 1 V
1
DDR 400 MT/s has Vdd value set to 2.6 V and Vref Value set to 1.3 V.
DDR Analysis Printable Application Help 29
Operating basics
Vdd and Vref. The configured values of Vdd and Vref are used to calculate V
IH(ac)
min, V
IH(dc)
min, V
IL(dc)
max and V
which are applied on the input signal. These levels are further used for calculating Setup and Hold measurements.
For DDR2, the relationship between Vdd and Vref is as shown in the following tables:
Table 6: Input DC logic Level
Symbol Parameter Min Max Units
V
V
IH(dc)
IL(dc)
DC input logic high Vref+0.125 NA V
DC input logic low –0.3 Vref–0.125 V
Table 7: Input AC logic Level
Symbol Parameter DDR2–400, DDR2–533 DDR2–667,DDR2–800 Units
Min Max Min Max
V
IH(ac)
V
IL(ac)
NOTE. Similar reference voltage levels are defined for DDR3 standard.
AC input logic high
AC input logic low
Vref+0.250 NA Vref+0.200 NA V
NA Vref–0.250 – Vref+0.200 V
IL(ac)
max,
30 DDR Analysis Printable Application Help
Operating basics
Speed Bins. For each DDR standard, the DDRA application automatically applies limits appropriate for the standard data rates without speed bins. Limit values are different for different speed bins. If you want to test according to a speed bin, you must manually configure the limit values from within DPOJET by manually overriding the limit file before running the measurements.
For more details, refer to Limits in the DPOJET help.
The following table lists the speed bins available for which pre-configured limit files are provided:
DDR Generation Speed bins
DDR-400 400A, 400B and 400C
DDR2
DDR2-667 800C and 800D
DDR2-800 800C, 800D and 800E
DDR3
DDR3-800 800D and 800E
DDR3-1066 1066E, 1066F and 1066G
DDR3-1333 1333F
DDR3-1600 1600G
2
, 1333G, 1333H and 1333J
3
, 1600H, 1600J and 1600K
2
3
NOTE. You can find limit files for various speed bins at . You need to manually select these limit files by clicking .
Vih
Is the input logic HIGH voltage.
Vil
Is the input logic LOW voltage.

Step 2: Interposer filter

Allows you to select and apply interposer type for each of the sources. Filter.xml file is available at C:\Users\Public\Filters. This file can be edited to add different interposer types. The absolute filter path for each source can be specified. You can specify filter files either for all the available sources or only to a subset of sources
When interposer filters are applied, MATH cannot be used as the measurement source in Step 3. The filter file will be applied when the scope acquisition sample rate is supported in the filter file..
NOTE. The fields and options on the Interposer filter panel will populate based on the type of generation selected.
2
1333F and 1333J are optional
3
1600G and 1600K are optional
DDR Analysis Printable Application Help 31
Operating basics
Filter types
■
None: Select if you do not to want to apply filter files. This option is selected by default.
■
Direct Attached: Select to attach pre-defined filter files.
■
User Defined: Select to define a pre-defined filter files. If you do not define at least one filter for a source, then, after clicking OK, the Interposer selection becomes to "None".
NOTE. Interposer types such as None, Direct Attached and User Defined are embedded in the application.
You can add additional filter files by adding the filter file name to the Filter.xml file. Once you update the XML file, restart the Tekscope to apply the changes. The names you added are now referenced in the Interposer filter type drop-down list.
NOTE. If filter files do not exist or there is any typo in entering the path, the application displays a message as " Filter File does not exist for <source name> in the path specified." The list of sources for which the filter files are not found will be listed.
Edit button: Opens the Filter.xml file for editing.
When you select “ User Defined ” from the drop-down list, the " User Defined Filter Path " dialog box is displayed, which allows you to select different filer files for each source.
32 DDR Analysis Printable Application Help
Operating basics
NOTE. The source displayed in User Defined Filter Path dialog box shall be enabled or disabled based on generation. For example, the source DQ, DQS shall remain disabled for GDDR5 and WCK shall be disabled for DDR3, DDR3L, DDR4, LPDDR3 and LPDDR4. You can select filter files either for all the available sources or only a subset of sources. The Filters.xml file is located at C:\Users\Public\Filters folder. The filter file can be modified outside the application as well.

Step 3: Measurements and sources

Select measurements and their corresponding sources in this step. Measurement availability depends on the selected DDR standard. Select the Measurement Type (Read Bursts, Write Bursts, Clock(Diff), Clock(Single Ended), Address/Command, Address/Command, DQS(Single Ended), WCK(Single Ended), WCK(Diff), Refresh, Power Down, Active, or Precharge) from the drop-down list. WCK(Single Ended), WCK(Diff), Refresh, Power Down, Active, or Precharge are only available for GDDR5. Power Down, Active, and Precharge are only available 64-bit instruments. A message prompts you to select one or more measurements before moving to the next step.
DDR Analysis Printable Application Help 33
Operating basics
Measurement Type Reference Levels. The voltage reference levels for each measurement are automatically set to be consistent with JEDEC guidelines unless they are manually overridden. In cases where none of the chosen measurements have any applicable guidelines or manually set levels, DDRA will automatically choose reference levels based on the signal's maximum and minimum levels. DDRA displays a hint if both Single Ended DQS and Differential DQS measurements are selected at the same time, and measurements made with this configuration may not be accurate due to conflicting ref level requirements. When two or more measurements are selected in different sub-node categories under a Measurement Type, the following precedence is set for measurement ref levels:
■
Slew Rate ref levels
■
Single Ended specific ref levels
■
Differential specific ref levels
For Example: When Eye Width measurement is selected along with Differential DQS or Single Ended DQS or Slew Rate measurements, Eye measurement may not produce the expected results. This is because the actual mid level needed by Eye Width gets overwritten with SE levels and hence produces no results.
34 DDR Analysis Printable Application Help
Operating basics
Tree Structure Flow. The measurement tree structure is as follows:
■
The tree structure displays only those measurements appropriate for the selected measurement type.
■
All generations except GDDR3 display both parent and nested elements under measurement type (such as tERR) as shown:
■
Click to expand and show the elements within the parent element.
■
Click to collapse and hide the elements within the parent element.
■
Selecting the parent check box, selects all the children elements. Selecting all the children elements, selects the parent element.
DDR Analysis Printable Application Help 35
Operating basics
■
Clearing the parent check box clears all the children elements.
■
When the children include both checked and unchecked elements, the parent element becomes highlighted as shown:
NOTE. If you move to the next step without selecting any measurements, the application displays the message “Please select measurements in Step3”.
Timing Mode. When you select any measurement from the Address/Command group, the Timing Mode drop-down field is populated. Select either 1T or 2T depending on memory mode in which they are operating. This field is applicable for DDR3, DDR3L, and DDR4 generations. Selecting 1T and 2T timing is mandatary for Address/Command setup and hold measurements.
36 DDR Analysis Printable Application Help
Operating basics
Mask Margin Measurement. You can specify a custom mask file using the Mask file control. The Mask file control allows you to change mask width, mask height, and mask position. When Mask margin measurement is selected, the application will update the default mask file depending on the data rate selected. You should not modify the default mask files.
Timing error (tERR) measurements. Timing error measurements such as tERR(2per), tERR(3per) until tERR(50per) are grouped together and included as a nested element (tERR) under the parent element, Clock(Diff)measurements. Selecting tERR selects all the timing error measurements.
Sources. Select a measurement to view the sources available for the measurement. The sources are mutually exclusive. For each required signal, select the appropriate source. A tool tip displays the required sources for the selected measurement at the nodes of the measurement tree. A maximum of four analog sources are available at a time.
NOTE. If the same channels are used for DQ/DQS/Clock sources (Example: DQ=Ch1, DQS=Ch1), the application displays a hint “Cannot use the same waveform for different sources”. If Live and Ref channels are used together (Example: Ch1 for DQS and Ref2 for DQ), the application displays a hint “Cannot use Live and Ref waveforms together”.
DDR Analysis Printable Application Help 37
Operating basics
Reference.
Hints
LPDDR Measurement Sources
LPDDR2 Measurement Sources
LPDDR3 Measurement Sources
LPDDR4 Measurement Sources
DDR Measurement Sources
DDR2 Measurement Sources
DDR3 Measurement Sources
DDR3L Measurement Sources
DDR4 Measurement Sources
GDDR5 Measurement Sources

Step 4: Burst detection method

Burst Detection is based on the measurement type and generation, and is applicable only for Write Bursts, Read Bursts, DQS(Single Ended, Read) and DQS(Single Ended) measurement types.
The application supports the following burst detection methods for DPO/DSA/MSO oscilloscopes:
■
DQ/DQS Phase Alignment
■
Chip Select, Latency + DQ/DQS Phase Alignment
■
Logic State + Burst Latency (Available only for MSO series of oscilloscopes)
■
Visual Search
■
Preamble Pattern Matching
■
Amplitude Based
NOTE. The Preamble Pattern Matching and Amplitude Based detection methods are applicable only to LPDDR4.
Config button
Click the Config button to select Preamble Pattern Matching and Amplitude Based burst identification method. The fields on the Configuration panel are populated based on the measurement type selected in Step 3.
NOTE. The Config button appears only for LPDDR4 generation.
38 DDR Analysis Printable Application Help
Operating basics
The Configuration panel dialog box is displayed.
Measurement Type=Writer Burst=Preamble Patter Matching
Measurement Type=Read Burst=Preamble Patter Matching
DDR Analysis Printable Application Help 39
Operating basics
Table 8: Burst Detection Parameter
Parameters Description
Preamble Pattern Matching This algorithm is based on finding the appropriate preamble
patterns over the entire acquisition. Each burst's association index (similarity coefficient) is compared with the user provided threshold to determine whether a burst is READ or WRITE.
Isolated Burst Length Specifies the isolated burst length. For LPDDR4 it could be
16 or 32.
Threshold Specifies the threshold with which the burst's association index
will be compared. This parameter measures the similarity between READ and WRITE burst preambles.
Preamble Type Specifies the READ burst preamble type as either Static or
Toggle.
NOTE. This option is applicable only for Read Bursts and DQS (Single Ended, Read) group measurements.
Postamble Length Specifies the READ burst postamble length. This could be
either 0.5 tCK or 1.5 tCK (extended postamble). This control is used only for Read Bursts and DQS (Single Ended, Read) group measurements.
Limitations
40 DDR Analysis Printable Application Help
Operating basics
Preamble Pattern Matching
■
Needs at least one isolated burst in the acquisition.
■
In some scenarios, the algorithm may not distinguish properly between WRITE bursts and READ bursts with toggle preamble and extended postamble.
Measurement Type=Write Burst=Amplitude Based
Table 9: Burst Detection Parameter
Parameters Description
Amplitude Based Select this measurement when there is a voltage difference
between READ and WRITE burst peak to peak level.
Peak-Peak Specifies the strobe (DQS) Pk-Pk voltage level of either READ
or WRITE bursts.
Margin Specifies the voltage variance allowed in terms of percentage
of peak-peak voltage.
WRITE amplitude greater than READ amplitude Check if WRITE burst amplitude is greater than READ burst
amplitude; otherwise, uncheck.
This option is available for both the DQ-DQS Phase Alignment and Chip Select Latency + DQ-DQS Phase Alignment methods. By default, the Preamble Pattern Matching option is selected. For Write Bursts and DQS (Single Ended, Write) group measurements, you can specify the tDQS2DQ by selecting User Defined. By default, this is set to Auto so that the ASM (Advanced Search and Mark Capability) algorithm will calculate the tDQS2DQ and use that in burst marking. When User Defined is selected, the value you specify is used for burst marking.
DDR Analysis Printable Application Help 41
Operating basics
NOTE. Current version of the application supports only write bursts having 2 clock cycle preamble.
Reference. Hints

Step 5: Burst detection settings

Displays the settings based on the burst detection method:
■
DQ/DQS Phase Alignment
■
Chip Select, Latency+ DQ/DQS Phase Alignment
■
Logic State + Burst Latency (Available only for MSO series of oscilloscopes)
■
Visual Search

Step 6:Thresholds and scaling

The left half of this panel controls selection of critical voltage thresholds used by the measurement algorithms. The right half determines whether scaling is automatically adjusted each time you sequence.
Measurement Thresholds. Select either Auto or Manual as the Measurement Threshold type.
■
If you select Auto, the application calculates these levels for you based on the DDR generation and speed grade. It is recommended that you use this option.
■
If you select Manual, set the measurements levels by clicking the Setup button.
For more details, refer to Ref Levels in the DPOJET help.
NOTE. For every measurement selected in DDRA, appropriate reference levels are set in the DPOJET application. You can change these levels, if needed, from the DPOJET application.
Vertical Scaling. Selecting Auto performs autoset on the oscilloscope vertical settings only.
For more details, refer to Source Autoset in the DPOJET help.
Horizontal Scaling. Selecting Auto performs autoset on the oscilloscope horizontal settings only.
For more details, refer to Source Autoset in the DPOJET help.
NOTE. If both Vertical and Horizontal are checked, the application performs autoset on both vertical and horizontal oscilloscope settings when Single/Run is selected.
42 DDR Analysis Printable Application Help
Operating basics
Alternate Thresholds. Alternate Thresholds only apply to the DDR3,DDR3L, and LPDDR2 Address and Command measurement type. It allows you to select derating values(Δ) from the derating tables– AC 175 and AC 150. The default is AC 175 (typical).
AC 175. The AC 175 Threshold derating table is as follows:
Table 10: Derating Values for DDR3 800/1066/1333/1600 MT/s tIS/tIH
ΔtIS, ΔtIH derating in ps AC/DC based AC 175 Threshold(VIH(ac))= VREF(dc)+175 mV, VIL(ac)=VREF(dc)–175 mV CK , CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
CMD/
2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100
ADD
1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84
R
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
Slew rate
0.9 –2 –4 –2 –4 –2 –4 6 4 14 12 22 20 30 30 38 46
(v/ns)
0.8 –6 –10 –6 –10 –6 –10 2 –2 10 6 18 14 26 24 34 40
0.7 –11 –16 –11 –16 –11 –16 –3 –8 5 0 13 8 21 18 29 34
0.6 –17 –26 –17 –26 –17 –26 –9 –18 –1 –10 7 –2 15 8 23 24
0.5 –35 –40 –35 –40 –35 –40 –27 –32 –19 –24 –11 –16 –2 –6 5 10
0.4 –62 –60 –62 –60 –62 –60 –54 –52 –46 –44 –38 –36 –30 –26 –22 –10
DDR Analysis Printable Application Help 43
Operating basics
AC 150. The AC 150 Threshold derating table is as follows:
Table 11: Derating Values for DDR3 800/1066/1333/1600 MT/s tIS/tIH
ΔtIS, ΔtIH derating in ps AC/DC based AC 150 Threshold(VIH(ac))= VREF(dc)+150 mV, VIL(ac)=VREF(dc)–150 mV CK , CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
CMD/
2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100
ADD
1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84
R
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
Slew rate
0.9 0 –4 0 –4 0 –4 8 4 16 12 24 20 32 30 40 46
(v/ns)
0.8 0 –10 0 –10 0 –10 8 –2 16 6 24 14 32 24 40 40
0.7 0 –16 0 –16 0 –16 8 –8 16 0 24 8 32 18 40 34
0.6 –1 –26 –1 –26 –1 –26 7 –18 15 –10 23 –2 31 8 39 24
0.5 –10 –40 –10 –40 –10 –40 –2 –32 6 –24 14 –16 22 –6 30 10
0.4 –25 –60 –25 –60 –25 –60 –17 –52 –9 –44 –1 –36 7 –26 15 –10
For DDR3 1866 and 2133 speeds, AC135 (typical) and AC125 are default settings.
Reference.
Hints

DQ-DQS phase alignment

Select the burst detection method as shown:
The DQ/DQS levels indicator shows "Auto" when both Strobe/Data and Edge detection hysteresis are set to Auto. If one of the options is Manual, then the DQ/DQS levels shows as Manual. Click Settings tab to set advanced burst detection parameters.
44 DDR Analysis Printable Application Help
Operating basics
The burst detection settings panel controls how data bursts are identified within a waveform that includes tri-state levels. For appropriately-probed signals with good signal fidelity, no adjustment to the default values should be required. For signals with poor fidelity or unusual properties, burst detection can be improved by switching to Manual control and adjusting the detection levels.
NOTE. The High/Mid/Low levels used for burst detection have no relationship to the reference levels used for measurement points. The measurement thresholds are defined in Step6 .
1. Select the type of burst detection level for the search.
■
If you select Auto, the application calculates these levels for you . It is recommended unless you find that manual levels are necessary for reliable detection.
■
If you select Manual, enter both the Strobe and Data reference levels for the signal (High, Mid, and Low). As you adjust the detection levels, observe the search-and-mark sprites that appear above the waveform. These sprites are dynamically updated as you adjust the levels, helping you to identify levels that properly delimit the selected burst type.
2. These settings need not be changed in most cases:
■
Edge Detection Hysteresis: This control configures the internal edge finder’s hysteresis band which is used to detect read or write bursts. In the event of noisy inputs, it can be increased to correct marks which may be larger than appropriate.
■
Termination Logic Margin: This control can be increased to help in terminating marks on back-to-back writes in cases where otherwise a continuous strobe would cause a write-mark to merge two back-to-back writes.
DDR Analysis Printable Application Help 45
Operating basics

Chip select latency + DQ-DQS phase alignment

1. If you wish to filter the data bursts based on a CS Source signal, select the CS Source using the CS Source drop-down.
Select CS Active and CS Mode as shown in the following figure. CS source is available only for Read and Write bursts measurements.
NOTE. Postamble length is applicable for LPDDR4 generation Read and DQS (Single Ended, Read) measurements. Set the postamble length to 0.5 tCK or 1.5 tCK, depending on the actual read postamble length.
NOTE. If a CS source is selected, CS-DQS(Strobe) is used for signal separation otherwise DQS(Strobe)-DQ(Data) is used. You must configure DQ source to enable Search and Mark.
CS Source
CS Source is used as a logic input to select read or write bursts corresponding to the chip select signal. When a chip-select signal source other than none is specified, reads or writes will only be shown when the chip-select source is active.
CS Active
Selects whether the chip-select source logic is considered active high or active low.
CS Mode
CS Mode consists of two modes – Auto and Manual. CS Auto mode calculates the level automatically for you (as half the peak­to-peak voltage), while manual mode allows you to specify a CS level. In cases where an entire acquisition could occur with no transitions on the chip-select line, you must select the manual mode to set the correct logic level.
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Operating basics

Logic state + burst latency

This burst detection method is available only on MSO series of oscilloscopes. You can configure the logic state, burst latency, tolerance, burst length, and DQ/DQS levels.
The DDRA application provides a shortcut, Bus Setup, to configure the bus in the oscilloscope bus setup window. Click Bus Setup in Step 5 to view the Bus setup screen as shown
NOTE. For more details, refer to Bus Setup Control Window (Select Tab) section in your oscilloscope online help.
DDRA application lists the buses defined in the bus setup menu. For DDRA to use the logic bus for read/write burst detection, it must have an associated symbol file.
NOTE. The Burst Length field is not used for LPDDR4 generation. The LPDDR4 burst detection algorithm will internally analyze the digital Bus to get the burst length.
By default, the DDRA application displays the symbol file that corresponds to the selected DDR generation in Step Step:1. Click Browse to select a symbol file of your choice. On selecting the symbol file, the Logic trigger lists the available patterns as shown. The symbol files per generation are located at C:\Users\Public\Tektronix\TekScope\busDecodeTables\DDR This is different from the default TekScope location at C:\Users\[Username]\Tektronix\Tekscope\BusDecodeTables.
Edit/customize the symbols based on your requirements and save it in *.tsf format. Place the created symbol files for access at C:\Users\Public\Tektronix\TekScope\busDecodeTables\DDR. Use Bus setup config menu or browse (Step
5) to access the created symbol file. A sample file for DDR3 is as shown:
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Operating basics
Symbol Pattern
MOD_REG 0000
REFRESH 0001
PRECHARGE 0010
ACTIVATE 0011
WRITE 0100
READ 0101
NOP 0111
DESELECT 1XXX
The DDRA application displays a hint “There may be a possible mismatch in the selected logic trigger and the measurement type. Please verify before continuing” when you select a logic state of READ and the measurement type selected is WRITE or vice versa.
NOTE. Any change in the symbol file in the DDRA application, is reflected in the oscilloscope bus configuration menu. The symbols of interest for DDRA are READ and WRITE patterns.
Symbol File
Symbol files are files of alphanumeric symbol names and associated data values, and are used to map a group value to a text string. The oscilloscope displays the symbol in place of the numeric value. For more details on symbol file format, refer to your oscilloscope online help .
Specify the Burst Latency, Tolerance, and burst length values.
CAS Min and Max
For READ commands, Read Latency (RL) is defined as the delay, in clock cycles, between the rising CLK edge that latches the READ command and the rising DQS edge signifying availability of the first data bit. The Read Latency is equal to the additive Latency and the CAS Latency (RL = AL + CL). CAS Min specifies the minimum time delay between the start of READ bus state and the initial rising DQS edge, for the first bit to be recognized. CAS Max specifies the maximum time delay between the end of the READ bus state and the initial rising DQS edge, for the first bit to be recognized. In the following figure, the actual READ latency is 2 and the CAS Min and CAS Max are set to 2. The green zone indicates where the initial rising DQS edge must be for burst recognition to occur.
For WRITE commands, Write Latency (WL) is defined as the delay, in clock cycles, between the rising CLK edge that latches the WRITE command and the rising DQS edge in the center of the first data bit. The Write Latency is equal to the Additive Latency and the CAS Write Latency (WL = AL + CWL). As with the READ case, the CAS Max and CAS Min parameters define a window following the WRITE bus state where the initial rising DQS edge must be for burst recognition to occur.
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Operating basics
Entering Read Latency(RL) and Write Latency(LW) in case of LPDDR4
Read Latency (RL): Enter the time delay between the mid of the first READ command to start of the data.
In the above diagram, RL* is the latency that you have to enter as Read Latency.
Writer Latency(WL): Enter the time delay between the mid of the first WRITE command and the center of the first data eye.
In the above diagram, WL* is the latency that you have to enter as Writer Latency.
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Operating basics
Burst Length
READ and WRITE operations are burst oriented, they start at a selected location, and continue for a burst length. Burst length, specified in cycles, determines where a read/write mark ends after the start of a read/write mark has been identified. Any change in DDR generation resets the burst length to 8.0.
Reference.
Salient Features of MSO-DDR Integration Using Digital Channels

Visual search

Capturing and analyzing the right part of the waveform can require hours of collecting and sorting through the many acquisitions. The Visual Trigger feature in the oscilloscope makes the identification of the desired waveform events quick and easy by scanning through acquired analog waveforms and graphically comparing them to geometric shapes on the display. By discarding acquired waveforms which do not meet the graphical definition, Visual Triggering extends the trigger capabilities of the oscilloscope beyond the traditional hardware trigger system.
In DDR, Visual Trigger can be used to separate Read bursts from Write Bursts and mark them. By selecting the Visual Search option in Step4: Burst Detection Method, these marked bursts can be used for further debugging and analysis.
Marking Read/Write bursts using visual trigger. Visual Trigger can also be used to mark all bursts which have a specific property (for example, marking a Read burst that has a spike just before it comes out of tri-state or marking a Write burst with a known data pattern). The figure below shows Visual Trigger that was used to mark (green marks) Write bursts with a known data pattern.
Along with the Visual search mark, Advanced search and mark (another feature in Tektronix oscilloscopes) has also been used to mark all the Write bursts (pink marks). Visual trigger has been used to isolate a burst with a specific data pattern, which allows the marked burst to be used for further debugging and analysis.
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Operating basics
Isolating Read and Write bursts on the DDR3 bus using Visual trigger. DDR3 SDRAM is a high speed, dynamic random access memory internally configured as an eight bank DRAM. It can Read (fetch) and Write data as a burst operation. The burst length can be 4 clock cycles, 8 clock cycles, and can go up to 32 clock cycles so that it can fetch the data byte 1 to 8 bytes in a burst.
DDR3 defines the polarity of the Preamble different for Read and Write. For a Read burst, the Preamble would be negative polarity. For a Write burst, the Preamble would be positive polarity. For DDR3, the Read and Write Preamble widths are defined by parameters tRPRE and tWPRE in the JEDEC specification, and whose minimum value has been defined as 0.9 times that of the clock period.
Additionally, the phase between the Strobe signal (DQS) and Data Signals (DQ) are different for Read and Write. DQS and DQ are aligned for Read bursts and shifted by 90 degrees for Write bursts.
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Operating basics
Isolating based on Preamble polarity and phase between DQS and DQ using Visual trigger. Figure 1 shows a screen capture of using Visual Trigger to isolate Read signals based on Preamble polarity and phase difference between the DQS and DQ signals. Channel 1 of the oscillocope is DQS and Channel 2 is DQ. Areas A1 and A2 are set so that when a signal is captured, there is no DQS signal in these regions. This ensures that the captured signal is coming out of tri-state. Area A3 is set to select the negative polarity of the Preamble. Areas A4 and A5 are set so that the DQ signal does not enter these regions, making sure that the DQS and DQ are aligned.
Figure 1: Read burst
Figure 2: Write burst
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Operating basics

Measurement levels

By definition, edges occur when a waveform crosses specified reference voltage levels. Reference voltage levels must be set so that the application can identify state transitions on a waveform. By default, the application automatically chooses reference voltage levels when necessary.
The DDRA application uses three basic reference levels: High, Mid and Low. In addition, a hysteresis value defines a voltage band that prevents a noisy waveform from producing spurious edges. The reference levels and hysteresis are independently set for each source waveform, and are specified separately for rising versus falling transitions.
Item Description
Measurement Reference Levels Setup (one level per source)
Rise High Sets the high threshold level for the rising edge of the source.
Rise Mid Sets the middle threshold level for the rising edge of the source.
Rise Low Sets the low threshold level for the rising edge of the source.
Fall High Sets the high threshold level for the falling edge of the source.
Fall Mid Sets the middle threshold level for the falling edge of the source.
Fall Low Sets the low threshold level for the falling edge of the source.
Hysteresis Sets the threshold margin to the reference level which the voltage must cross to be recognized
as changing; the margin is the relative reference level plus or minus half the hysteresis; use to filter out spurious events.
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Operating basics

Hints

The DDRA application displays the following hints at different steps:
Hint Step Description
Select a standard data rate in DDRA 1 Displayed when data rate is None. When you select a non standard data
rate in ASM, the data rate is set to None in DDRA.
GDDR3 not completely supported. Some features may not function.
Please provide a Limits file under Jitter and Eye > Limits
Cannot use Live and Ref waveforms together.
Cannot use the same waveform for different sources.
Cannot select Diff and SE measurements at the same time.
Use unique sources that are either Live or Ref.
1 Displayed on selecting GDDR3 standard, which does not have standard
data rates. Only Data Eye Width measurement is available for both Read and Write bursts.
1 Displayed for custom data rates for which limits are not defined. You need to
manually configure the limits.
3 Displayed on selecting both Live and Ref waveforms as source for DQ and
DQS. Example: Data Eye Width measurement with sources as Ch1 for DQ and Ref1 for DQS.
3 Displayed on selecting the same source for DQ and DQS. Example: Data
Eye Width using Ch3 for both DQ and DQS.
3 Displayed on selecting measurements with suffix SE and Diff. Example:
DDR2, Write bursts, tDH-Diff and tDH-SE measurements.
3 Displayed on selecting measurements which require DQ, DQS and Clock
sources. Example: DDR3, 800MT/s, select all Read burst measurements.

Results as statistics

Result statistics for most of the measurements show Population in terms of UI or transitions. According to the JEDEC specification, the analysis for most of the clock measurements is done for a 200-cycle moving window. However, for clock measurements such as tCL(avg) and tCH(avg), the population is shown as tCK(avg) units. For some measurements such as Data Eye Width, exactly one measurement occurs per acquisition. For such measurements, the population increases by one for each acquisition independent of the number of UI in the acquisition.
For more details, refer to Viewing Statistical Results in the DPOJET help.
Reference.
Dynamic Limits
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Operating basics

Plots

The only measurement for which a plot is automatically configured is Data Eye Width, which is available for both Read and Write bursts. However, plots may be added for other measurements through the plot panel. The plot selection and configuration methods are identical to those used for DPOJET. For more details, refer to the DPOJET help.
For acquisitions containing more than one read or write burst, time trend plots connect together all measurements within each burst with a continuous line, but do not draw lines between bursts. If a vertical cursor is placed where it does not intersect a line, the cursor annotation will read "NaN" (Not a Number).
For more details, refer to About Configuring Plots in the DPOJET help.

Reports

For more details, refer to About Reports in the DPOJET help.

Switching between the DDRA and DPOJET applications

For advanced analysis, click to switch to the DPOJET application. Likewise, click in the DPOJET application to revert to the DDRA application.
The transition behaves as follows:
■
The application name in the title bar switches between DDR Analysis and Jitter and Eye Diagram Analysis Tool.
■
Measurement name remains unchanged while traversing from DDRA to DPOJET.
■
Within DPOJET, more measurements may be added to those automatically configured in DDRA. These measurements must be configured manually.
■
Once in DPOJET, measurements automatically configured by DDRA may be reconfigured. (The measurements will generally no longer be JEDEC-compliant in this case.)
■
Upon returning to DDRA, new or non-standard measurements will be retained.
■
Measurement sequencing, results analysis and report generation can be done from either application.
■
Any change in generation and measurement type in the DDRA deselects all the currently selected measurements.
■
Switching back from DPOJET to DDRA, always resets focus to the Setup panel.
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Operating basics
■
DPOJET or DDRA application is always accessible from the oscilloscope menu bar, as an alternative to the quick navigation buttons.
■
If DPOJET application is opened from the oscilloscope menu (Analyze > Jitter and Eye Diagram Analysis), the shortcut button to DDR Analysis is not shown. This shortcut only appears if DPOJET is entered from the DDRA interface.
■
Any change in the reference voltage levels in DPOJET is reflected in DDRA Step 1, Vih and Vil. Vih and Vil specify the static voltage reference levels of the measurements. You can modify these levels either in Step 6 of DDRA or in the DPOJET source configuration screen.

Salient features of MSO-DDRA integration

The following are the salient features of MSO-DDR integration:
■
Use the DDRA user interface for the required settings without exiting from the DDRA setup panel for digital configuration.
■
Logic State burst detection method is more reliable than the conventional DQ/DQS Phase alignment.
■
Digital configurations are available at Step 4 and Step 5 of the DDRA application. The Logic pattern or Logic state triggering is used on the digital control signals such as RAS, CAS, CS and WE, which identify the desired burst type.
■
Symbol files per DDR generation are available.
■
Identify marks using the specified digital control signals and Burst Latency and Tolerance values. The Burst Latency and Tolerance values are important to precisely mark the bursts.
■
Change in DDR generation resets the burst length to 8.0.
56 DDR Analysis Printable Application Help

Tutorial

Introduction to the tutorial

This tutorial teaches how to set up the application, take measurements, and view results as plots or statistics.
Before you begin the tutorial, perform the following tasks:
■
Set up the oscilloscope.
■
Start the application.
■
Recall the tutorial waveform.

Setting up the oscilloscope

The steps to set up the oscilloscope are:
■
Click File > Recall Default Setup in the oscilloscope menu bar to recall the default settings.
■
Press the individual CH1, CH2, CH3, and CH4 buttons as needed to add or remove active waveforms from the display.

Starting the application

Click Analyze > DDR Analysis to open the application.

Waveform files

The DDRA application provides the following waveforms at C:\Users\Public\Tektronix\TekApplications\DDRA
\Waveforms for oscilloscopes running the Windows7 operating system:
■
DDR2_800_DQS_Write.wfm
■
DDR2_800_DQ_Write.wfm
■
DDR2_800_CLK.wfm
NOTE. These waveforms have to be used only for Write bursts and CLK.

Recalling a waveform file

To recall a waveform file, follow these steps:
1. Click File > Recall in the oscilloscope menu bar to display the Recall dialog box.
2. Click Waveform icon in the left of the Recall dialog box.
3. Select Ref1, Ref2, Ref3, or Ref4 as the Destination option.
4. Browse to select the waveform. Use the keypad to edit the waveform file name.
5. Click Recall. The oscilloscope recalls and activates the Reference Waveform control window.
6. Click On to display the waveform.
7.
Click to return to the application. Alternatively, DDRA can also be accessed from Analyze > DDR Analysis.
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Tutorial

Taking a measurement

This tutorial uses the following example
DDR2 800MT/s, Write bursts - Differential measurements
Waveforms Used: DDR2_800_DQS_Write.wfm and DDR2_800_DQ_Write.wfm
1. To set the application to default values, click File > Recall Default Setup. This is not necessary if you have just started the
application.
2. To view the DDRA application, select Analyze > DDR Analysis.
3. At Step 1, select the DDR2 standard and the data rate as 800 MT/s. The default voltage settings are retained as shown:
4. At Step 2, select the filter and the probing type.
5. At Step 3, select the measurements and the associated sources.
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Tutorial
6. At Step 4, select the burst detection method.
The selected data rate, generation, and measurement type are reflected in ASM on selection in DDRA. Marks are available only for Read and Write bursts measurement type. Configure Search using Advance > Search > Configure. The identified bursts are shown as small inverted marks ( ) in the oscilloscope display area. Each pair of marks specifies the start and stop of a burst. You can traverse from one mark to the other using the Mark Control window. For more details, refer to your oscilloscope online help.
NOTE. Logic state+ DQ/DQS Phase Alignment is available only for MSO series of oscilloscopes.
7. At Step 5, select the burst detection settings based on the selected burst detection method as shown:
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Tutorial
8. At Step 6, retain the settings as shown:
9. Click Single to run the application. When complete, the result statistics with limits are shown in the results tab.
The eye diagram plot is displayed as shown:
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Parameters

About parameters

This section describes the DDRA application parameters and includes the menu default settings. Refer to the user manual of your oscilloscope for operating details of other controls, such as front-panel buttons.
The parameter tables list the selections or range of values available for each option, the incremental unit of numeric values, and the default selection or value.

Step 1: Generation rate and levels parameters

Step1 includes the following parameters:
Table 12: Generation, rate and levels parameters
Option Parameters Default setting
DDR Generation DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR, LPDDR2, LPDDR3,
LPDDR4,GDDR3, and GDDR5
Data Rate
Vdd JEDEC Default, User Defined JEDEC Default
Vref JEDEC Default, User Defined JEDEC Default
Vcent DQ LPDDR4: JEDEC Default, User Defined 201.5 mv
1
DDR: 200 MT/s, 266 MT/s, 333 MT/s, 400 MT/s, Custom and None 200 MT/s for DDR
DDR2: 400 MT/s, 533 MT/s, 667 MT/s, 800 MT/s, 1066 MT/s, Custom
and None
DDR3: 800 MT/s, 1066 MT/s, 1333 MT/s, 1866 MT/s, 2133 MT/s, Custom and None
DDR3L: 800 MT/s, 1066 MT/s, 1333 MT/s, 1600 MT/s, 1866 MT/s, Custom and None
DDR4: 1600 MT/s, 1866 MT/s, 2133 MT/s, 2400 MT/s, 2466 MT/s, 3200 MT/s, Custom and None
LPDDR: 200 MT/s, 266 MT/s, Custom and None 200 MT/s for LPDDR
LPDDR2: 333 MT/s, 400 MT/s, 533 MT/s, 667 MT/s, 933 MT/s,
1066 MT/s, Custom and None
LPDDR3: 333 MT/s, 800 MT/s, 1066 MT/s, 1200 MT/s, 1333 MT/s, 1466 MT/s, 1600 MT/s, Custom and None
LPDDR4: 533 MT/s, 1066 MT/s, 1600 MT/s, 2133 MT/s, 2400 MT/s, 2667 MT/s, 3200 MT/s, 3733 MT/s, 4266 MT/s, Custom and None
GDDR3: 500 MT/s, 600 MT/s, 700 MT/s, 800 MT/s, 900 MT/s, 1000 MT/ s, Custom and None
GDDR5: 4000 MT/s, 4800 MT/s, 5000 MT/s, 5500 MT/s, Custom, and None
Custom 800 MT/s
DDR3
400 MT/s for DDR2
800 MT/s for DDR3
800 MT/s for DDR3L
1600 MT/s for DDR4
333 MT/s for LPDDR2
333 MT/s for LPDDR3
533 MT/s for LPDDR4
500 MT/s for GDDR3
4000 MT/s for GDDR5
1
Data rate varies for different DDR standards.
DDR Analysis Printable Application Help 61
Parameters
Option Parameters Default setting
DDR4 : JEDEC Default, User Defined 850 mv
Vcent CA LPDDR4:JEDEC Default, User Defined 191.5 mv
VrefCA DDR4:JEDEC Default, User Defined 600 mv

Step 2: Interposer filter parameters

Step2 includes the following parameters under Filter Type:
■
None
■
User Defined
■
Direct Attached

Step 3: Measurement and sources parameters

Step3 includes the following parameters under Measurement Type:
■
Read Bursts
■
Write Bursts
■
WCK(Single Ended)
■
WCK(Diff)
■
Clock(Diff)
■
Clock(Single Ended)
■
Address/Command
■
Refresh
■
Power Down
■
Active
■
Precharge
■
DQS(Single Ended)/DQS(Single Ended,Write)
2
2
2
2
2
2
■
DQS(Single Ended, Read)
The sources parameters are as shown in the following table:
2
These measurement types and parameters are available for GDDR5 generation.
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Parameters
Table 13: Sources parameters
Option Parameters Default setting
DQS(Strobe) Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch1
DQS#(Strobe) Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch3
DQ(Data) Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch2
Addr/Cmd Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch4
Clock Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch3
Clock# Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch4
WCK Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch1
WCK# Ch1-Ch4, Ref1-Ref4, Math1-Math4 Ch4
WE, CS, CAS, RAS, CKE D0-D15 None

Step 4: Burst detection method parameters

Step 4 has the following parameters:
■
DQ/DQS Phase Alignment
■
Chip Select, Latency + DQ/DQS Phase Alignment
■
Logic State + Burst Latency
■
Visual Search

Step 5: Burst detection settings parameters

Step5 has the following parameters:
NOTE. The DQ/DQS Phase Alignment settings are same for Chip Select and Logic State Burst Detection methods.
Table 14: Burst detection parameters
Option Parameters Default setting
Chip Select, Latency + DQ/DQS Phase Alignment
CS Source None, Ch1-Ch4, Ref1-Ref4, Math1-Math4 None
CS Mode
CAS Min(Cyc)
DDR Analysis Printable Application Help 63
3
3
Auto, Manual Auto
0–1k 2.0
Parameters
Option Parameters Default setting
CS Active
CS Level
CAS Max(Cyc)
DQ/DQS Levels
3
3
3
4
High, Low Low
-50V to +50V 0.0 V
0–1k 3.0
Auto, Manual Auto
DQ/DQS Phase Alignment
Strobe
High Auto, Manual Auto
Mid Auto, Manual Auto
Low Auto, Manual Auto
Data
High Auto, Manual Auto
Mid Auto, Manual Auto
Low Auto, Manual Auto
Edge Detection Hysteresis Auto, Manual Auto
Termination Logic Margin Auto, Manual Auto
LogicState + Burst Latency DQ/DQS Phase Alignment
5
Bus B1–B16 None
Tolerance
Burst Latency
4
4
0–50 G 1Cyc
0–50 G 2.5Cyc
Burst Length 0–50 G(ui) 8 UI
DQ/DQS Levels
Logic Trigger
3
Available only when you select CS source.
4
These measurement types and parameters are available for GDDR5 generation.
5
Available only for the MSO series of oscilloscopes.
4
4
Auto, Manual Auto
MODE_REG, REFRESH, PRECHARGE,
MODE_REG ACTIVATE, WRITE, READ, SRX, DESELECT, SRE, PDE
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Parameters

Step 6: Thresholds and scaling parameters

Step6 has the following parameters:
Table 15: Thresholds and scaling parameters
Option Parameters Default setting
Measurement Thresholds Auto, Manual Auto
Vertical Scaling Set, Clear Clear
Horizontal Scaling Set, Clear Clear
Alternate Thresholds
Measurement Levels
Rise High –20 V to 20 V Default varies depends upon DDR
Rise Mid –20 V to 20 V
Rise Low –20 V to 20 V
Fall High –20 V to 20 V
Fall Mid –20 V to 20 V
Fall Low –20 V to 20 V
Hysteresis 0 to 10 V 30 mV
1
AC160, AC130, AC135, AC175 , AC150,
AC175
AC125, AC220 , AC300,
generation
1
Available for DDR3,DDR3L,LPDDR2 generation.
DDR Analysis Printable Application Help 65
Parameters
66 DDR Analysis Printable Application Help

Reference

DDR measurement sources

The sources required for analysis may include DQS(Strobe), DQ(Data), DQS# (Strobe), Clock, Clock#, and Addr/Cmd. Clock and DQS can be either Single-Ended (SE) or Differential (Diff). CS Source is available, as appropriate, as an optional qualifier.
The following table lists the sources required for each DDR measurement:
Table 16: DDR measurement sources
DDR measurements DPOJET base measurement Performed on Additional required sources
Write Bursts
Data Eye Width Eye Width DQS and DQ NA
Data Eye Height Eye Height DQS and DQ NA
Differential DQS
tDQSH Pos Width DQS and DQ NA
tDQSL Neg Width DQS and DQ NA
tDSH-Diff Hold DQS and Clock DQ
tDSS-Diff Setup DQS and Clock DQ
Single Ended DQS
tDH-SE DDR Hold-SE DQS and DQ NA
tDIPW-SE Period DQ DQS
tDSH-SE Hold DQS and Clock DQ
tDS-SE DDR Setup–SE DQS and DQ NA
tDSS-SE Setup DQS and Clock DQ
tWPRE DDR tRPRE DQS DQ
tWPST DDR tPST DQS DQ
Read Bursts
Data Eye Width Eye Width DQS and DQ NA
Data Eye Height Eye Height DQS and DQ NA
Differential DQS
tAC-Diff DDR Setup-Diff DQ and Clock DQS
tDQSCK-Diff Skew DQS and Clock DQ
tQH Hold DQS and DQ NA
Single Ended DQS
tDQSQ-SE Setup DQS and DQ NA
tRPRE DDR tRPRE DQS DQ
tRPST DDR tRPST DQS DQ
Clock (Diff)
2
1
1
1
1
1
1
1
1
1
1
2
Required so that the Search-and-Mark feature can properly identify bursts
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Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
tCH Pos Width Clock NA
tCK Period Clock NA
tCL Neg Width Clock NA
tHP Period Clock NA
VID(ac) DDR VID(ac) Clock NA
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# NA
AC-Overshoot(CK) Overshoot Clock NA
AC-OvershootArea(CK#) DDR Over Area Clock# NA
AC-OvershootArea(CK) DDR Over Area Clock NA
AC-Undershoot(CK#) Undershoot Clock# NA
AC-Undershoot(CK) Undershoot Clock NA
AC-UndershootArea(CK#) DDR Under Area Clock# NA
AC-UndershootArea(CK) DDR Under Area Clock NA
Vix(ac)CK V–Diff–Xovr Clock and Clock# NA
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ
1
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
1
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ
1
AC-UndershootArea(DQS#) DDR Under Area DQS# DQ, DQS
AC-UndershootArea(DQS) DDR Under Area DQS DQ
Vix(ac)DQS V–Diff–Xovr DQS and DQS# DQ
1
1
DQS (Single Ended, Read)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
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Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-UndershootArea(DQS#) DDR Under Area DQS# DQ, DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
Address/Command
AC-Overshoot Overshoot Addr/Cmd NA
AC-OvershootArea DDR Over Area Addr/Cmd NA
AC-Undershoot Undershoot Addr/Cmd NA
AC-UndershootArea DDR Under Area Addr/Cmd NA
tIH(base) DDR Hold–Diff Clock and Addr/Cmd NA
tIPW-High Pos Width Clock and Addr/Cmd NA
tIPW-Low Neg Width Clock and Addr/Cmd NA
tIS(base) DDR Setup–Diff Clock and Addr/Cmd NA

DDR2 measurement sources

The sources required for analysis may include DQS(Strobe), DQ(Data), DQS# (Strobe), Clock, Clock#, CS Source, and Addr/ Cmd. Clock and DQS can be either Single-Ended (SE) or Differential (Diff). Read and Write bursts have CS as an optional source.
The following table lists the sources required for each DDR2 measurement:
Table 17: DDR2 measurement sources
DDR measurements DPOJET base measurement Performed on Additional required sources
Write Bursts
Data Eye Width Eye Width DQS and DQ NA
Data Eye Height Eye Height DQS and DQ NA
Differential DQS
InputSlew-Diff-Fall(DQS) Fall Slew Rate DQS DQ
InputSlew-Diff-Rise(DQS) Rise Slew Rate DQS DQ
tDH-Diff(base) DDR Hold–Diff DQS and DQ NA
tDH-Diff(derated) DDR Hold–Diff DQS NA
tDQSH Pos Width DQS DQ
tDQSL Neg Width DQS and DQ DQ
tDQSS-Diff Skew DQS and Clock DQ
tDS-Diff(base) DDR Setup–Diff DQS and DQ NA
tDS-Diff(derated) DDR Setup–Diff DQS and DQ NA
tDSH-Diff Hold DQS and Clock DQ
3
2
2
2
2
2
3
Required so that the Search-and-Mark feature can properly identify bursts
DDR Analysis Printable Application Help 69
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
tDSS-Diff Setup DQS and Clock DQ
2
tDVAC(DQS) Time Outside Level DQS DQ
Single Ended DQS
Slew Rate-Setup-SE-
Fall Slew Rate DQS DQ
2
Fall(DQS)
Slew Rate-Setup-SE-
Rise Slew Rate DQS DQ
2
Rise(DQS)
Slew Rate-Hold-SE-Fall(DQS) Fall Slew Rate DQS DQ
Slew Rate-Hold-SE-Rise(DQS) Rise Slew Rate DQS DQ
2
2
tDH-SE(base) DDR Hold–SE DQS and DQ NA
tDH-SE(derated) DDR Hold–SE DQS and DQ NA
tDIPW-SE Period DQ DQS
tDQSS-SE Skew DQS and Clock DQ
tDSH-SE Hold DQS and Clock DQ
2
2
tDS-SE(base) DDR Setup–SE DQS and DQ NA
tDS-SE(derated) DDR Setup–SE DQS and DQ NA
tDSS-SE Setup DQS and Clock DQ
2
Slew Rate DQ
Slew Rate-Setup-Fall(DQ) Fall Slew Rate DQ DQS
Slew Rate-Setup-Rise(DQ) Rise Slew Rate DQ DQS
Slew Rate-Hold-Fall(DQ) Fall Slew Rate DQ DQS
Slew Rate-Hold-Rise(DQ) Rise Slew Rate DQ DQS
tWPRE DDR tRPRE DQS DQ
tWPST DDR tPST DQS DQ
2
2
2
2
2
2
Read Bursts
Data Eye Width Eye Width DQS and DQ NA
Data Eye Height Eye Height DQS and DQ NA
Differential DQS
tAC-Diff DDR Setup-Diff DQ and Clock DQS
2
tDQSQ-Diff Setup DQS and DQ NA
tQH Hold DQS and DQ NA
tDVAC(DQS) Time Outside Level DQS DQ
Single Ended DQS
tDQSCK-SE Skew DQS and Clock NA
tDQSQ-SE Setup DQ and DQS NA
tRPRE DDR tRPRE DQS DQ
tWPRE DDR tPST DQS DQ
2
2
Vox(ac)DQS V-Diff-Xovr DQS, DQS# DQ
Clock (Diff)
70 DDR Analysis Printable Application Help
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
tCH(abs) Pos Width Clock NA
tCH(avg) DDR tCH(avg) Clock NA
tCK(abs) Period Clock NA
tCK(avg) DDR tCK(avg) Clock NA
tCL(abs) Neg Width Clock NA
tCL(avg) DDR tCL(avg) Clock NA
tDVAC(CK) Time Outside Level CK NA
tERR(11–50per) DDR tERR(m–n) Clock NA
tERR(2per) DDR tERR(n) Clock NA
tERR(3per) DDR tERR(n) Clock NA
tERR(4per) DDR tERR(n) Clock NA
tERR(5per) DDR tERR(n) Clock NA
tERR(6–10per) DDR tERR(m–n) Clock NA
tHP Period Clock NA
tJIT(cc) CC–Period Clock NA
tJIT(duty) DDR tJIT(duty) Clock NA
tJIT(per) DDR tJIT(per) Clock NA
VID(ac) DDR VID(ac) Clock NA
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# NA
AC-Overshoot(CK) Overshoot Clock NA
AC-OvershootArea(CK#) DDR Over Area Clock NA
AC-OvershootArea(CK) DDR Over Area Clock NA
AC-Undershoot(CK#) Undershoot Clock# NA
AC-Undershoot(CK) Undershoot Clock NA
AC-UndershootArea(CK#) DDR Under Area Clock NA
AC-UndershootArea(CK) DDR Under Area Clock NA
Vix(ac)CK V–Diff–Xovr Clock and Clock# NA
Vox(ac)CK V–Diff–Xovr Clock and Clock# NA
VSWING(MAX)CK Cycle Pk-Pk Clock NA
VSWING(MAX)CK# Cycle Pk-Pk Clock NA
DQS (Single Ended)
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
DDR Analysis Printable Application Help 71
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-UndershootArea(DQS#) DDR Under Area DQS# DQ, DQS
Vix(ac)DQS V–Diff–Xovr DQS and DQS# DQ
VSWING(MAX)DQS Cycle Pk-Pk DQS DQ
VSWING(MAX)DQS# Cycle Pk-Pk DQS# DQ
2
2
2
DQS (Single Ended, Read)
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ
2
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
2
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ
2
AC-UndershootArea(DQS#) DDR Under Area DQS# DQ, DQS
AC-UndershootArea(DQS) DDR Under Area DQS DQ
2
Vox(ac)DQS V-Diff-Xovr DQS, DQS# DQ
Precharge
tRP(MRS) tCMD-CMD Bus, CK NA
tRP(REF) tCMD-CMD Bus, CK NA
Address/Command Measurements
AC-Overshoot Overshoot Addr/Cmd NA
AC-OvershootArea DDR Over Area Addr/Cmd NA
AC-Undershoot Undershoot Addr/Cmd NA
AC-UndershootArea DDR Under Area Addr/Cmd NA
InputSlew-Diff-Fall(CK) Fall Slew Rate Clock NA
InputSlew-Diff-Rise(CK) Rise Slew Rate Clock NA
Slew Rate-Hold-Fall(Addr/
Fall Slew Rate Addr/Cmd NA
Cmd)
Slew Rate-Hold-Rise(Addr/
Rise Slew Rate Addr/Cmd NA
Cmd)
Slew Rate-Setup-Fall(Addr/
Fall Slew Rate Addr/Cmd NA
Cmd)
72 DDR Analysis Printable Application Help
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
Slew Rate-Setup-Rise(Addr/
Rise Slew Rate Addr/Cmd NA
Cmd)
tIH(base) DDR Hold–Diff Clock and Addr/Cmd NA
tIH(derated) DDR Hold–Diff Clock and Addr/Cmd NA
tIPW-High Pos Width Clock and Addr/Cmd NA
tIPW-Low Neg Width Clock and Addr/Cmd NA
tIS(base) DDR Setup–Diff Clock and Addr/Cmd NA
tIS(derated) DDR Setup–Diff Clock and Addr/Cmd NA

DDR3 measurement sources

The sources required for analysis may include DQS(Strobe), DQ(Data), DQS# (Strobe), Clock, Clock#, and Addr/Cmd. Clock and DQS can be either Single-Ended (SE) or Differential (Diff). CS Source is available, as appropriate, as an optional qualifier.
The following table lists the sources required for each DDR3 measurement:
Table 18: DDR3 measurement sources
DDR measurements DPOJET base measurement Performed on Additional required sources
Write Bursts
Data Eye Width Eye Width DQS and DQ NA
Data Eye Height Eye Height DQS and DQ NA
Differential DQS
InputSlew-Diff-Fall(DQS) Fall Slew Rate DQS DQ
InputSlew-Diff-Rise(DQS) Rise Slew Rate DQS DQ
tDH-Diff(base) DDR Hold-Diff DQS and DQ NA
tDH-Diff(derated) DDR Hold-Diff DQS and DQ NA
tDQSH Pos Width DQS DQ
tDQSL Neg Width DQS DQ
tDQSS-Diff Skew DQS and Clock DQ
tDS-Diff(base) DDR Setup–Diff DQS and DQ NA
tDS-Diff(derated) DDR Setup–Diff DQ and DQS NA
tDSH-Diff Hold DQS and Clock DQ
tDSS-Diff Setup DQS and Clock DQ
tDVAC(DQS) Time Outside Level DQS DQ
Single Ended DQS
tDIPW-SE Period DQ DQS
tDQSS-SE Skew DQS and Clock DQ
tDSH-SE Hold DQS and Clock DQ
4
3
3
3
3
3
3
3
3
3
4
Required so that the Search-and-Mark feature can properly identify bursts
DDR Analysis Printable Application Help 73
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
tDSS-SE Setup DQS and Clock DQ
3
Slew Rate DQ
Slew Rate-Hold-Rise(DQ) Rise Slew Rate DQ DQS
Slew Rate-Hold-Fall(DQ) Fall Slew Rate DQ DQS
Slew Rate-Setup-Rise(DQ) Rise Slew Rate DQ DQS
Slew Rate-Setup-Fall(DQ) Fall Slew Rate DQ DQS
tWPRE DDR tWPRE DQS DQ
tWPST DDR tPST DQS DQ
3
3
3
3
3
3
Read Bursts
Data Eye Width Eye Width DQS and DQ NA
Data Eye Height Eye Height DQS and DQ NA
Differential DQS
SRQdiff-Fall(DQS) Fall Slew Rate DQS DQ
SRQdiff-Rise(DQS) Rise Slew Rate DQS DQ
tDQSCK-Diff Skew DQS and Clock DQ
3
3
3
tDQSQ-Diff Setup DQS and DQ NA
tQH Hold DQ and DQS NA
tDVAC(DQS) Time Outside Level DQS DQ
tRPRE DDR tRPRE DQS DQ
tRPST DDR tPST DQS DQ
tQSH Pos Width DQS DQ
tQSL Neg Width DQS DQ
3
3
3
3
Clock (Diff)
tCH(abs) Pos Width Clock NA
tCH(avg) DDR tCH(avg) Clock NA
tCK(abs) Period Clock NA
tCK(avg) DDR tCK(avg) Clock NA
tCL(abs) Neg Width Clock NA
tCL(avg) DDR tCL(avg) Clock NA
tDVAC(CK) Time Outside Level CK NA
tERR DDR tERR Clock NA
tJIT(cc) CC–Period Clock NA
tJIT(duty) DDR tJIT(duty) Clock NA
tJIT(per) DDR tJIT(per) Clock NA
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# NA
AC-Overshoot(CK) Overshoot Clock NA
AC-OvershootArea(CK#) DDR Over Area Clock# NA
74 DDR Analysis Printable Application Help
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
AC-OvershootArea(CK) DDR Over Area Clock NA
AC-Undershoot(CK#) Undershoot Clock# NA
AC-Undershoot(CK) Undershoot Clock NA
AC-UndershootArea(CK#) DDR Under Area Clock# NA
AC-UndershootArea(CK) DDR Under Area Clock NA
Vix(ac)CK DDR3 Vix(ac) Clock and Clock# NA
VSEH(AC)CK# Cycle Max Clock# NA
VSEH(AC)CK Cycle Max Clock NA
VSEH(CK#) Cycle Max Clock# NA
VSEH(CK) Cycle Max Clock NA
VSEL(AC)CK# Cycle Min Clock# NA
VSEL(AC)CK Cycle Min Clock NA
VSEL(CK#) Cycle Min Clock# NA
VSEL(CK) Cycle Min Clock NA
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ NA
AC-UndershootArea(DQ) DDR Under Area DQ NA
AC-Overshoot(DQ) Overshoot DQ NA
AC-Undershoot(DQ) Undershoot DQ DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ
3
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
3
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ
3
AC-UndershootArea(DQS#) DDR Under Area DQS# DQ, DQS
AC-UndershootArea(DQS) DDR Under Area DQS DQ
Vix(ac)DQS DDR3 Vix(ac) DQS and DQS# DQ
VSEH(AC)DQS# Cycle Max DQS# DQ
VSEH(AC)DQS Cycle Max DQS DQ
VSEH(DQS#) Cycle Max DQS# DQ
VSEH(DQS) Cycle Max DQS DQ
VSEL(AC)DQS# Cycle Min DQS# DQ
VSEL(AC)DQS Cycle Min DQS DQ
VSEL(DQS#) Cycle Min DQS# DQ
VSEL(DQS) Cycle Min DQS DQ
3
3
3
3
3
3
3
3
3
3
DQS (Single Ended, Read)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
DDR Analysis Printable Application Help 75
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS) Overshoot DQS DQ
AC-Undershoot(DQS) Undershoot DQS DQ
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-UndershootArea(DQS#) DDR Under Area DQS# DQ, DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
Precharge
tRP(ACT) tCMD-CMD Bus, CK NA
tRP(MRS) tCMD-CMD Bus, CK NA
Address/Command Measurements
AC-Overshoot Overshoot Addr/Cmd NA
AC-OvershootArea DDR Over Area Addr/Cmd NA
AC-Undershoot Undershoot Addr/Cmd NA
AC-UndershootArea DDR Under Area Addr/Cmd NA
InputSlew-Diff-Fall(CK) Fall Slew Rate Clock NA
InputSlew-Diff-Rise(CK) Rise Slew Rate Clock NA
Slew Rate-Hold-Fall(Addr/ Cmd)
Slew Rate-Hold-Rise(Addr/ Cmd)
Slew Rate-Setup-Fall(Addr/ Cmd)
Slew Rate-Setup-Rise(Addr/ Cmd)
tIH(base) DDR Hold–Diff Clock and Addr/Cmd NA
tIH(derated) DDR Hold–Diff Clock and Addr/Cmd NA
tIPW-High Pos Width Addr/Cmd NA
tIPW-Low Neg Width Addr/Cmd NA
tIS(base) DDR Setup–Diff Clock and Addr/Cmd NA
tIS(derated) DDR Setup–Diff Clock and Addr/Cmd NA
Fall Slew Rate Addr/Cmd NA
Rise Slew Rate Addr/Cmd NA
Fall Slew Rate Addr/Cmd NA
Rise Slew Rate Addr/Cmd NA
76 DDR Analysis Printable Application Help
Reference

DDR3L measurement sources

The sources required for analysis may include DQS (Strobe), DQS# (Strobe), DQ (Data), Clock, Clock #, and Addr/Cmd. Clock and DQS can be either Single-Ended (SE) or Differential (Diff). Read and Write bursts have CS as an optional source.
The following table lists the sources required for each DDR3L measurement:
Table 19: DDR3L measurement sources
DDR measurements DPOJET base measurement Performed on Additional required sources
Write Bursts
Data Eye Width Eye Width DQS and DQ NA
Data Eye Height Eye Height DQS and DQ NA
tWPRE DDR tRPRE DQS DQ
tWPST DDR tPST DQS DQ
Differential DQS
InputSlew-Diff-Fall(DQS) Fall Slew Rate DQS DQ
InputSlew-Diff-Rise(DQS) Rise Slew Rate DQS DQ
tDH-Diff(base) DDR Hold-Diff DQS and DQ NA
tDH-Diff(derated) DDR Hold-Diff DQS and DQ NA
tDQSH Pos Width DQS and DQ NA
tDQSL Neg Width DQS and DQ NA
tDQSS-Diff Skew DQS and Clock DQ
tDS-Diff(base) DDR Setup–Diff DQS and DQ NA
tDS-Diff(derated) DDR Setup–Diff DQS and DQ NA
tDSH-Diff Hold DQS and Clock DQ
tDSS-Diff Setup DQS and Clock DQ
tDVAC(DQS) Time Outside Level DQS DQ
Single Ended DQS
tDIPW-SE Period DQ DQS
tDQSS-SE Skew DQS and Clock DQ
tDSH-SE Hold DQS and Clock DQ
tDSS-SE Setup DQS and Clock DQ
Slew Rate DQ
Slew Rate-Hold-Rise(DQ) Rise Slew Rate DQ DQS
Slew Rate-Hold-Fall(DQ) Fall Slew Rate DQ DQS
Slew Rate-Setup-Rise(DQ) Rise Slew Rate DQ DQS
Slew Rate-Setup-Fall(DQ) Fall Slew Rate DQ DQS
Read Bursts
Data Eye Width Eye Width DQS and DQ NA
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
Required so that the Search-and-Mark feature can properly identify bursts
DDR Analysis Printable Application Help 77
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
Data Eye Height Eye Height DQS and DQ NA
tRPRE DDR tRPRE DQS DQS
tRPST DDR tRPST DQS DQS
4
4
Differential DQS
SRQdiff-Fall(DQS) Fall Slew Rate DQS DQ
SRQdiff-Rise(DQS) Rise Slew Rate DQS DQ
tDQSCK-Diff Skew DQS and Clock DQ
4
4
4
tDQSQ-Diff Setup DQS and DQ NA
tQH Hold DQS and DQ NA
tDVAC(DQS) Time Outside Level DQS DQ
tAC-Diff DDR Setup-Diff DQ and Clock DQS
tQSH Pos Width DQS DQ
tQSL Neg Width DQS DQ
4
4
4
4
Slew Rate DQ
SRQse-Fall(DQ) Fall Slew Rate DQ DQS
SRQse-Rise(DQ) Rise Slew Rate DQ DQS
4
4
Clock (Diff)
tCH(abs) Pos Width Clock NA
tCH(avg) DDR tCH(avg) Clock NA
tCK(abs) Period Clock NA
tCK(avg) DDR tCK(avg) Clock NA
tCL(abs) Neg Width Clock NA
tCL(avg) DDR tCL(avg) Clock NA
tDVAC(CK) Time Outside Level Clock NA
tERR DDR tERR Clock NA
tJIT(cc) CC–Period Clock NA
tJIT(duty) DDR tJIT(duty) Clock NA
tJIT(per) DDR tJIT(per) Clock NA
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# NA
AC-Overshoot(CK) Overshoot Clock NA
AC-OvershootArea(CK#) DDR Over Area Clock# NA
AC-OvershootArea(CK) DDR Over Area Clock NA
AC-Undershoot(CK#) Undershoot Clock# NA
AC-Undershoot(CK) Undershoot Clock NA
AC-UndershootArea(CK#) DDR Under Area Clock# NA
AC-UndershootArea(CK) DDR Under Area Clock NA
Vix(ac)CK DDR3 Vix(ac) Clock and Clock# NA
78 DDR Analysis Printable Application Help
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
VSEH(AC)CK# Cycle Max Clock# NA
VSEH(AC)CK Cycle Max Clock NA
VSEH(CK#) Cycle Max Clock# NA
VSEH(CK) Cycle Max Clock NA
VSEL(AC)CK# Cycle Min Clock# NA
VSEL(AC)CK Cycle Min Clock NA
VSEL(CK#) Cycle Min Clock# NA
VSEL(CK) Cycle Min Clock NA
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ
4
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
4
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ
4
AC-UndershootArea(DQS#) DDR Under Area DQS# DQ, DQS
AC-UndershootArea(DQS) DDR Under Area DQS DQ
Vix(ac)DQS DDR3 Vix(ac) DQS and DQS# DQ
VSEH(AC)DQS# Cycle Max DQS# DQ
VSEH(AC)DQS Cycle Max DQS DQ
4
4
4
4
VSEH(DQS#) Cycle Max DQS# DQ, DQS
VSEH(DQS) Cycle Max DQS DQ
VSEL(AC)DQS# Cycle Min DQS# DQ
VSEL(AC)DQS Cycle Min DQS DQ
4
4
4
VSEL(DQS#) Cycle Min DQS# DQ, DQS
VSEL(DQS) Cycle Min DQS DQ
4
DQS (Single Ended, Read)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
AC-UndershootArea(DQS) DDR Under Area DQS DQ
AC-Overshoot(DQS) Overshoot DQS DQ
DDR Analysis Printable Application Help 79
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
AC-Undershoot(DQS) Undershoot DQS DQ
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-UndershootArea(DQS#) DDR Under Area DQS# DQ, DQS
Address/Command Measurements
AC-Overshoot Overshoot Addr/Cmd NA
AC-OvershootArea DDR Over Area Addr/Cmd NA
AC-Undershoot Undershoot Addr/Cmd NA
AC-UndershootArea DDR Under Area Addr/Cmd NA
Slew Rate-Hold-Fall(Addr/ Cmd)
Slew Rate-Hold-Rise(Addr/ Cmd)
Slew Rate-Setup-Fall(Addr/ Cmd)
Slew Rate-Setup-Rise(Addr/ Cmd)
tIH(base) DDR Hold–Diff Clock and Addr/Cmd NA
tIH(derated) DDR Hold–Diff Clock and Addr/Cmd NA
tIPW-High Pos Width Clock and Addr/Cmd NA
tIPW-Low Neg Width Clock and Addr/Cmd NA
tIS(base) DDR Setup–Diff Clock and Addr/Cmd NA
tIS(derated) DDR Setup–Diff Clock and Addr/Cmd NA
Fall Slew Rate Addr/Cmd NA
Rise Slew Rate Addr/Cmd NA
Fall Slew Rate Addr/Cmd NA
Rise Slew Rate Addr/Cmd NA
80 DDR Analysis Printable Application Help
Reference

DDR4 measurement sources

The sources required for analysis may include DQS (Strobe), DQS# (Strobe), DQ (Data) , Clock, Clock #, and Addr/Cmd. Clock and DQS can be either Single-Ended (SE) or Differential (Diff). Read and Write bursts have CS as an optional source.
The following table lists the sources required for each DDR4 measurement:
Table 20: DDR4 measurement sources
DDR measurements DPOJET base measurement Performed on Additional required sources
Write Bursts
Data Eye Width Eye Width DQS and DQ NA
Data Eye Height Eye Height DQS and DQ NA
DDRARX Mask Mask Hits DQS and DQ NA
tWPRE DDR tRPRE DQS DQ
tWPST DDR tPST DQS DQ
VIHL_AC Cycle Pk-Pk DQ DQS
Differential DQS
SRIN_dIVW_Fall Fall Slew Rate DQ DQS
SRIN_dIVW_Rise Rise Slew Rate DQ DQS
TdIPW-High Pos Width DQ DQS
TdIPW-Low Neg Width DQ DQS
tDQSH Pos Width DQS DQ
tDQSL Neg Width DQS DQ
tDQSS-Diff Skew Clock and DQS DQ
tDSH-Diff Hold Clock and DQS DQ
tDSS-Diff Setup Clock and DQS DQ
tDVAC(DQS) Time Outside Level DQS DQ
Read Bursts
Data Eye Width Eye Width DQS and DQ NA
Data Eye Height Eye Height DQS and DQ NA
tRPRE DDR tRPRE DQS DQ
tRPST DDR tRPST DQS DQ
Differential DQS
SRQdiff-Fall(DQS) Fall Slew Rate DQS DQ
SRQdiff-Rise(DQS) Rise Slew Rate DQS DQ
tDQSCK-Diff Skew DQS and Clock DQ
tDQSQ-Diff Setup DQS and DQ NA
tDVAC(DQS) Time Outside Level DQS DQ
tHZ(DQ) DDR tHZDQ Clock and DQ DQS
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
Required so that the Search-and-Mark feature can properly identify bursts
DDR Analysis Printable Application Help 81
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
tLZ(DQ) DDR tLZDQ Clock and DQ DQS
5
tQH Hold DQS and DQ NA
tQSH Pos Width DQS DQ
tQSL Neg Width DQS DQ
5
5
Single Ended DQS
tHZ(DQS) DDR tHZDQ DQS and Clock DQ
tLZ(DQS) DDR tLZDQ DQS and Clock DQ
5
5
Slew Rate DQ
SRQse-Fall(DQ) Fall Slew Rate DQ DQS
SRQse-Rise(DQ) Rise Slew Rate DQ DQS
5
5
Clock (Diff)
Clock Eye Height Eye Height Clock NA
Clock Eye Width Eye Width Clock NA
InputSlew-Diff-Fall(CK) Fall Slew Rate Clock NA
InputSlew-Diff-Rise(CK) Rise Slew Rate Clock NA
tCH(abs) Pos Width Clock NA
tCH(avg) DDR tCH(avg) Clock NA
tCK(abs) Period Clock NA
tCK(avg) DDR tCK(avg) Clock NA
tCL(abs) Neg Width Clock NA
tCL(avg) DDR tCL(avg) Clock NA
tDVAC(CK) Time Outside Level Clock NA
tERR DDR tERR(n) Clock NA
tJIT(cc) CC–Period Clock NA
tJIT(duty) DDR tJIT(duty) Clock NA
tJIT(per) DDR tJIT(per) Clock NA
Clock (Single Ended)
AC-Overshoot(CK#) Overshoot Clock# NA
AC-Overshoot(CK) Overshoot Clock NA
AC-OvershootArea(CK#) DDR Over Area Clock# NA
AC-OvershootArea(CK) DDR Over Area Clock NA
AC-Undershoot(CK#) Undershoot Clock# NA
AC-Undershoot(CK) Undershoot Clock NA
AC-UndershootArea(CK#) DDR Under Area Clock# NA
AC-UndershootArea(CK) DDR Under Area Clock NA
Vix(ac)CK DDR3 Vix(ac) Clock and Clock# NA
VSEH(CK#) Cycle Max Clock# NA
VSEH(CK) Cycle Max Clock NA
82 DDR Analysis Printable Application Help
Reference
DDR measurements DPOJET base measurement Performed on Additional required sources
VSEL(CK#) Cycle Min Clock# NA
VSEL(CK) Cycle Min Clock NA
DQS (Single Ended)
AC-OvershootArea(DQ) DDR Over Area DQ DQS
AC-UndershootArea(DQ) DDR Under Area DQ DQS
AC-Overshoot(DQ) Overshoot DQ DQS
AC-Undershoot(DQ) Undershoot DQ DQS
AC-Overshoot(DQS#) Overshoot DQS# DQ, DQS
AC-Overshoot(DQS) Overshoot DQS DQ
5
AC-OvershootArea(DQS#) DDR Over Area DQS# DQ, DQS
AC-OvershootArea(DQS) DDR Over Area DQS DQ
5
AC-Undershoot(DQS#) Undershoot DQS# DQ, DQS
AC-Undershoot(DQS) Undershoot DQS DQ
5
AC-UndershootArea(DQS#) DDR Under Area DQS# DQ, DQS
AC-UndershootArea(DQS) DDR Under Area DQS DQ
Vix(ac)DQS DDR3 Vix(ac) DQS and DQS# DQ
5
5
VSEH(DQS#) Cycle Max DQS# DQ, DQS
VSEH(DQS) Cycle Max DQS DQ
5
VSEL(DQS#) Cycle Min DQS# DQ, DQS
VSEL(DQS) Cycle Min DQS DQ
5
Address/Command Measurements
AC-Overshoot Overshoot Addr/Cmd NA
AC-Overshoot(AbsMax) Overshoot Addr/Cmd NA
AC-OvershootArea DDR Over Area Addr/Cmd NA
AC-OvershootArea(AbsMax) DDR Over Area Addr/Cmd NA
AC-Undershoot Undershoot Addr/Cmd NA
AC-UndershootArea DDR Under Area Addr/Cmd NA
SRIN_cIVW_Fall Fall Slew Rate Addr/Cmd NA
SRIN_clVW-Rise Rise Slew Rate Addr/Cmd NA
tIH(base)
tIH(Vref)
7
8
DDR Hold-Diff Clock and Addr/Cmd NA
DDR Hold-Diff(Vref) Clock and Addr/Cmd NA
tIPW-High Pos Width Addr/Cmd NA
tIPW-Low Neg Width Addr/Cmd NA
tIS(base)
tIS(Vref)
9
10
DDR Setup-Diff Clock and Addr/Cmd NA
DDR Setup-Diff(Vref) Clock and Addr/Cmd NA
7
tIH(base) : Command and Address hold time to CK_t, CK_c referenced to Vih(ac) / Vil(ac) levels. It uses the DPOJET measurement "DDR Hold-Diff".
8
tIH(Vref) : Command and Address hold time to CK_t, CK_c referenced to Vref levels. It uses the DPOJET measurement 'DDR Hold-Diff(Vref)'.
9
tIS(base) : Command and Address setup time to CK_t, CK_c referenced to Vih(ac) / Vil(ac) levels. It uses the DPOJET measurement 'DDR Setup-Diff'.
10
tIS(Vref) : Command and Address setup time to CK_t, CK_c referenced to Vref levels. It uses the DPOJET measurement 'DDR Setup-Diff(Vref)'.
DDR Analysis Printable Application Help 83
Reference

GDDR5 measurement sources

The sources required for analysis may include DQ, WCK, WCK#, CK, CK#,WE, CS, CAS, RAS, CKE, and Addr/Cmd.
The following table lists the sources required for each GDDR5 measurement:
Table 21: GDDR5 measurement sources
DDR measurements DPOJET base measurement Performed on Additional required sources
Write Bursts
Data Eye Width Eye Width DQ and WCK NA
Data Eye Height Eye Height DQ and WCK NA
tWRPDE tBurstToCMD Clock WE, CS, CAS, RAS, CKE
tWRSRE tBurstToCMD Clock WE, CS, CAS, RAS, CKE
Read Bursts
Data Eye Height Eye Height DQ and WCK NA
Data Eye Width Eye Width DQ and WCK NA
tRDPDE tBurstToCMD Clock WE, CS, CAS, RAS, CKE
tRDSRE tBurstToCMD Clock WE, CS, CAS, RAS, CKE
WCK (Single Ended)
Vin(WCK#) High-Low WCK# NA
VIN(WCK) High-Low WCK NA
Vix(ac)WCK V-Diff-Xovr WCK, WCK# NA
VOH(WCK#) High WCK# NA
VOH(WCK) High WCK NA
VOL(WCK#) Low WCK# NA
VOL(WCK) Low WCK NA
WCK Slew-Fall(WCK#) Fall Slew Rate WCK# NA
WCK Slew-Fall(WCK) Fall Slew Rate WCK NA
WCK Slew-Rise(WCK#) Rise Slew Rate WCK# NA
WCK Slew-Rise(WCK) Rise Slew Rate WCK NA
WCK (Diff)
SSC Downspread(WCK) SSC-Freq-DEV WCK NA
SSC Mod Freq(WCK) SSC-MOD-FREQ WCK NA
SSC Profile(WCK) SSC-PROFILE WCK NA
tDVAC(WCK) Time Outside Level WCK NA
tJIT(cc) CC-Period WCK NA
tJIT(per) DDR tJIT(per) WCK NA
tWCK Period WCK NA
tWCK-DJ TJ@BER WCK NA
tWCK-Fall-Slew Fall Slew Rate WCK NA
tWCKH Pos and Neg Width WCK NA
84 DDR Analysis Printable Application Help
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