Tektronix DC 503 INSTRUCTION MANUAL

Tektvonix, Inc. P.O. Box Beaverton, Oregon
500
97005
INSTRUCTION MANUAL
Serial Number
972
TABLE
OF
CONTENTS
SECTION 1 OPERATING INSTRUCTIONS
INTRODUCTION
Description Option
I
l
OPE RATIONAL CHECK
Controls and Connectors Display Tests Channels A and
INPUT CONSIDERATIONS
l lnput Coupling Attenuators and Maximum lnput Volts Sensitivity and Frequency Range Slope and LEVEL
FREQUENCY MEASUREMENTS
FREQ A Triggering Measurement Measurement Rate
PERIOD MEASUREMENTS
Gating Averaging Low Frequencies
RATIO MEASUREMENTS
Bandwidth Limitations Triggering
TIME INTERVAL MEASUREMENTS
Electronic Single-Shot Using HOLD GATE Output
MANUAL TIMING MEASUREMENTS
Starting and Stopping Clocking Rate
I'OTALIZING
Purpose
Operation REAR CONNECTOR ASSIGNMENTS
Customizing the Interface
Control Lines
Signal Lines 5;PECIFlCATlONS
FUNCTIONS
DISPLAY
CH A and
OUTPUT
-Time Base
nstallation
nput Sources
StartIStop
B
B
Intervals
I10
INPUTS
Page SECTION 1 OPERATING INSTRUCTIONS (cont)
INTERNAL TlME BASE OTHER
SECTION
SECTION
2
THEORY OF OPERATION INPUT CIRCUIT
Attenuators, Channels A and Signal Shaping and Slope Channels
A and DCU Signal Selection Gates Time
TlME BASE AND CONTROL CIRCUITS
1 Optional Decade Divider Units Gate Generator
COUNTER CIRCUITS
Decade Counter Units Storage Register Overflow Register and Drive
DECODE AND DISPLAY MULTIPLEX
Scan Clock
+8
Seven-Segment Decoder and Driver, Leading Zero Suppression
lnput and Output Data Lines
REGULATED POWER SUPPLIES
3
SERVICE INFORMATION
Symbols and Reference Designators Electrical Parts List Internal Adjustment Procedure Controls and Connectors Illustration Block Diagram Parts Location Grid Trigger Amplifier Diagram Counter Time Base and Control
Counters and Display Diagram Mechanical Parts List Fig. Accessories and Repackaging
(B)
A
B (A Start-B Stop)
MHz Clock
1
MHz Clock
Counter and Time-Slot Decoder
and Display and Parameter
Diagram
1
Exploded View
(B)
(DDU's)
(DCU)
LED'S
.
Page
Operating Instructions-DC
503
Slope and
A front-panel pushbutton for each channel determines whether the trigger circuits will respond to either positive- stable triggering. See Fig. or negative-going transitions of each input signal. over
(A)
LEVEL
Noise Impulses 200-millivolt
Erroneous count.
Fig.
1-2.
Triggeringcircuit responses to improper
hysteresis window
The LEVEL control for each channel allows the
operator to move the hysteresis window of the trigger circuit to an optimum level on the input
+,I
.5
V of the input signal in the
(6)
Correct count.
(A)
and proper
(B)
LEVEL settings.
FREQUENCY MEASUREMENTS
FREO
100
GATE TIMEs Make sure the LEVEL control
signal to the CH A INPUT. Set the DISPLAY TlME control
CCW.

Triggering

A
To measure and display the frequency of
MHz, set the FUNCTION switch to one
bracketed
under
the
heading
is
pushed in and connect the
a
signal up to
of
the shorter
of
FREO
A.
count varies from reading to reading, jitter in the signal source. If the count changes unreason­able~
the
DC
503
is
not being triggered prc)per'yr either because the controls are not set right or the signal the
For frequency measurements, all CH B trigger settings have no effect. "N" or "CLOCK RATE" settings are irrelevant.
capabilities.
signal to assure
1-2.
The LEVEL control adjusts
XI
ATBEN position.
it
is
probably due to
is
beyond
The CH A LEVEL, Slope, Coupling, and controls all affect the ability to make a measurement. In general, the trigger controls are similar to oscilloscope controls, except that the end result is not a stable waveform graphic display, but a stable digital frequency display.
Coupling and
quency
control for changing DC levels. The repetitive nature of frequency signals makes SLOPE selection insignificant.
5
amplitude signals, select an attenuation factor such that the attenuated signal peak-to-peak. The LEVEL control must be varied for a stable reading. amplitude and frequency are close to (or perhaps beyond) the specified limits.
show jitter when measured with 7-digit resolution. If the
measurements
Attenuators and
V, peak-to-peak, should not be attenuated. For higher
A signal which looks stable on an oscilloscope may still
SLOPE.
falls into the range of
It
will not be touchy unless the signal
Use AC-coupling
to
avoid re-adjusting the LEVEL
LEVEL.
Signals between
ATTENuator
for
most
300
500
mV to 5 V,
fie-
mV and

Measurement Intervals

To adjust the trigger controls, choose a short GATE TlME such as display as to whether the Counter is being triggered or not.
If
it
is, numbers will appear in the display. (If the frequency
is below shortest gate times. For such low frequencies, a PERIOD
measurement
Final selection of GATE TlME depends on the quency being measured, desired resolution, and willingness of the operator to wait for a measurement. Using short gate times, higher frequencies may be measured, but at the expense of the greater resolution capabilities of the longer gate times.
Resolution.
must wait displayed. and accuracy for signals below second count will display fewer than the available 7 digits.
.I
s
or
.O1
s.
This gives rapid feeldback via the
100
HZ, numbers may not appear during the
is
better
suited-)
A
10
s
GATE TlME means the operator
10
seconds for a measurement to be made and
It
is
the only way to get best possible resolution
1
MHz. Even then, a
fre-
10
-
Operating Instructions-DC
503
Overflow.
it
is
Choose
-
number of the measurement as far to the left Note the Move the decimal point to the left by choosing longer GATE TIME!; until the desired resolution display will flash when the most significant number over-
flows the
lution does
except for quick A-B comparisons. The relationship
GATE TIME, measured frequency, displayed digits, and
overflow
:EF
10
Through intentional use of "overflow" displays,
possible to improve the resolution of the counter.
a
GATE TlME which displays the most significant
numbers displayed to the right of the decimal.
is
achieved. The
last
storage register. Note that the increased reso-
not add to the accuracy of the measurement,
is
shown in Table 1-6.
TABLE
10
1
2100
MHz
100
;
1
7
digits
(3verflow
(3verflow Overflow
s
Overflow Overflow Overflow
1
MHz
MHz
6 digits
7
digits
1-6
1
MHz
to
,
10
MHz
1
5
digits
6
digits
7
digits 6 digits
to
as
possible.
betwen
hl
MHz
1
4
digits
5
digits
7
digits

Measurement Rate

Once a stable measurement which measurements are made can be controlled by the DISPLAY TlME control. Turning the control cw holds off the gate and stores the display for
a
before DISPLAY TlME and GATE TlME together complete measurement-display cycle.
The D
able from about 0.1
cw end. At the cw end, there HOLD. In HOLD, the displayed for an indefinite time. A new count and display may be initiated by pushing the RESET button, turning the
DISPLAY TlME control ccw, or changing to another GATE
TIME.
new measurement
ISPLAY TI ME control
s
at
the ccw end to about 10
last
is
obtained, the rate
a
longer time
is
made and displayed.
is
uncali brated and vari-
is
a
detent position called
count taken will be stored and
at
s
at
the
a

PERIOD MEASUREMENTS

-

Gating

is
Period measurement timers primarily to overcome a basic limitation of counters, i.e., the long time required to make a high resolution high accuracy measurement of low frequency signals. For example, a 1 kHz signal requires 1,000 seconds of GATE TlME to second, a 1 kHz signal can gate pulses from a 1 MHz clock.
functions of signal and clock as compared to the FREQ A mode. In FREQ A, the gate of clock pulses while signal events are counted, then waves can be measured accurately at the very low end if the displayed. In PERIOD B, the gate
number of signal events (N), while 1 ps clock pulses are
counted,

Averaging

signal value over
the selected number of N (AVG'D OVER N CYCLES OF B) increases the total time to take to selecting general, the product of the signal period and the selected N
acc~~mulate a million counts. However, in only one
Simply stated, the PERIOD B mode reverses the rather sensitive to wave shape and amplitude. Since
then displayed.
Resolutiori and accuracy
a
large number of signal events. Increasing
a1
longer GATE TlME in the F REQ A mode. In
provided in universal counter-
a
count of one million clock
is
held open for some number abruptly, square waves are preferred. Sine and triangle
is
held open for some
is
increased by averaging the
a
measurement, similar
factor should be 1 to < 10 seconds. The maximum period capacity
frequency
with
Low
ularly in the lowest decade from 0.1 Hz to 1.0 Hz, become
desirable for the signal to pass through the trigger hysteresis
input amplitude driven hard. For repetitive signals below 0.1 Hz, use the TIME A*B mode.
its
the higher frequencies, the frequency mode should be used. The CH B controls operate the same
Because PERIOD frequencies, the use of DC COUPLING will be more common than with CH A.
is
9,999,999
will
cause
practical
N=~.
Frequencies
Period measurements of signals below 10 Hz, and partic-
CH
B
is
the channel provided for period measurement;
bandwidth of 10 MHz
ps.
Therefore, a period X N product
an
overflow.
for
period
is
kept high so that the trigger input
B
measurements may involve very low
This
means
that
measurement
is
adequate for that purpose. For
is
O.l
as
the CH A controls.
the
lowest
Hz,
even
it
is
is
Operating Instructions-DC
503
REAR

Customizing the Interface

Input and output access to the DC 503 rear of the main circuit board. Fig. 1-4 identifies the contacts and their respective
A Power Module mainframe option (Option 2) available which provides to which Also possible are intra-compartment connections with other plug-in modules in multiple-compartment mainframes. The Reset, Time-Slot Zero

Control Lines

These lines allow the user to externally command the
DC
A Reset input line, which doubles line, clears the Counter to zero when a low An input line to disable the flashing overflow display also doubles as an output signal line during overflow. The the interface for possible synchronous applications.
If0 lines can be hard-wired for external access.
503
to certain operating conditions.
CONNECTOR I/O ASSIGNMENTS
.
internal scan clock can be shut off by the Internal Scan
is
available at the
I10 assignments.
a
rear-panel, multi-pin connector
as
an output signal
is
applied to
it.
Clock Disable line, while using an external scan clock.

Signal Lines

These lines provide for signal input to each channel,
is
status and clock signal outputs, BCD data outputs, and external scan clock inputs.
(TSO), Data Good, and Overflow lines report the status of the DC 503. BCD data lines report the count in an 8-4-2-1, serial-by-cligit method.
As long as the Internal Scan Clock Disable line remains high, the Internal Scan Clock output signal When the Disable line Clock line becomes an input line for an External Scan Clock signal.
The DC 503's internal
is
pulled down, the Internal Scan
1
MHz Clock signal
is
iis
available.
brought to
INTERNAL
OVERFLOW
SCAN
CLOCK
OUTIEXTERNAL
OUTIOVERFLOW
BCD
OUTPUT,
SERIAL-BY-DIGIT
CHANNEL B INPUT
FUNCTION
SCAN
DISPLAY
CHANNEL
Fig.
I
ASSIGNMENTS
CONTACT
I
I
1-
-
{
25B
24B
23
:::
19B
17B 16B
B
-1
CLOCK
IN
DISABLE
DATA
1-4.
IN
GOOD
B
INPUT
GROUND
InputIOutput contact assignments at rear connector.
4
+I
4
d
-
I
I
-
-
I
-
I
-
I
I
ASSIGNMENTS
FUNCTION
27A 26A 25A
20A 19A
17A
16A CHANNEL A INPUT
14A
INTERNAL
RESET,
TIME
SLOT
CHANNEL
1-MHz
CLOCK
SCAN
INIOUT
ZERO
BCD
OUTPUT, SERIAL-BY-DIGIT
A
INPUT
OUT
CLOCK
(TS,)
GROUNID
CllSABLE
Section
2-DC
503
INPUT
Attenuators, Channels A and (B)
Events to be counted are applied via front-panel INPUT connector are frequency-compensated voltage dividers consisting of resistors R 18-R25
(C118-C125). Switches S20A (S120A) and S20B (S120B) allow front-panel selection of XI, X10, or XI00 atten­uation of coupling.
J10 (J110) to the attenuators. The attenuators
(R 1 18-R 125) and capacitors C18
the input signal. C15 (C115) provides AC
SECTION
THEORY
OPERATION
CIRCUIT

DCU Signal Selection Gates

The two separate bistable multivibrators produce sharp signal edges for the decade counter units TOTALIZE A, RATIO positions,
and
MANUAL, or TlME bistable multivibrator for the DCU drive and by the DDU (decade divider unit) output. In PERIOD U200D-U226C
control signal from the 1 MHz clock.
U200A-U200C
is
switched
by the channel A input signal. In TlME
is
AIB, or one of the FREQ A
is
the active bistable multivibrator
A-tB, U200D-U226C
the active multivibrator.
OF
(DCU). In
is
the active
is
controlled
It
receives
2
B,
a
Signal Shaping and Slope, Channels A and (B)
Field effect transistor (FET) 035 (0135) presents a high impedance base of between the LEVEL control R45 050 (0150). Adjustment of the LEVEL control changes
the bias on the input signal will trigger the DC 503.
060 and 1050 in the Channel A signal shaping circuitry comprise in the Channel B signal shaping circuitry) acts follower.
070-080 (0160-0170) pair. slope by biasing the desired slope to R74 positive slope negative slope follower 095 and the slope-determined output signal to the appropriate
DCU signal selection gate and the A start portion of the
Time
to1 the input signal and a low impedance to the
050 (01 50). FET 040 (0140) provides isolation
(R145) and the base of
(150 (0150) and thus selects what portion of
a
hiigh frequency, high gain amplifier. 068 (0150
as
an emitter
is
a
signal switched differential
+
SLOlPE switch S75 (S170) selects the triggering
(R165). The
is
passed through 090 (0165), while the
is
passed through 074 (0180). Emitter
(0185) couples the signal level to a TTL level
A+B ciircuit.
The output signal from the active bistable multivibrator goes to NOR gate toggle the decade counter units.
U200B. The output of U200B
is
used to
Time A+B (A Start-B Stop)
The two separate bistable multivibrators (U220C-U220D
and U220A-U220B) produce sharp edges to toggle U224A
and B.
In TlME
at
pin 1 of U226A, making pin 3 of NAND gate U226B
high. Pin 4 of U226B starts low when
pin 4 of U224A. Pin 5 of U226B starts high due to a low pin 13 of U224B. An "A trigger" causes U224A to toggle, which makes pin 4 of
pin 14 of
of event to be counted).
"armed" by the high that occurs circuit now waits for a "B trigger" which will toggle and put a low on pin 5 of U226B. When the B trigger arrives, gate generator circuit closing the gate. When the gate closes, a CLEAR resets
A+B mode the FUNCTION switch puts a low
CLEAR
U226B high. This outputs a low to
U272B1 causing the gate to "open" (permits input
U224B simultaneously becomes
at
its
pins 12 and 13. The
U226B will output a high to pin 14 of U272B in the
U224A, which in turn resets U224B.
goes low
U224B
at
at
Loading...
+ 33 hidden pages