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DC 503
INSTRUCTION MANUAL
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Tektronix DC 503 INSTRUCTION MANUAL

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Tektvonix, Inc. P.O. Box Beaverton, Oregon
500
97005
INSTRUCTION MANUAL
Serial Number
972
TABLE
OF
CONTENTS
SECTION 1 OPERATING INSTRUCTIONS
INTRODUCTION
Description Option
I
l
OPE RATIONAL CHECK
Controls and Connectors Display Tests Channels A and
INPUT CONSIDERATIONS
l lnput Coupling Attenuators and Maximum lnput Volts Sensitivity and Frequency Range Slope and LEVEL
FREQUENCY MEASUREMENTS
FREQ A Triggering Measurement Measurement Rate
PERIOD MEASUREMENTS
Gating Averaging Low Frequencies
RATIO MEASUREMENTS
Bandwidth Limitations Triggering
TIME INTERVAL MEASUREMENTS
Electronic Single-Shot Using HOLD GATE Output
MANUAL TIMING MEASUREMENTS
Starting and Stopping Clocking Rate
I'OTALIZING
Purpose
Operation REAR CONNECTOR ASSIGNMENTS
Customizing the Interface
Control Lines
Signal Lines 5;PECIFlCATlONS
FUNCTIONS
DISPLAY
CH A and
OUTPUT
-Time Base
nstallation
nput Sources
StartIStop
B
B
Intervals
I10
INPUTS
Page SECTION 1 OPERATING INSTRUCTIONS (cont)
INTERNAL TlME BASE OTHER
SECTION
SECTION
2
THEORY OF OPERATION INPUT CIRCUIT
Attenuators, Channels A and Signal Shaping and Slope Channels
A and DCU Signal Selection Gates Time
TlME BASE AND CONTROL CIRCUITS
1 Optional Decade Divider Units Gate Generator
COUNTER CIRCUITS
Decade Counter Units Storage Register Overflow Register and Drive
DECODE AND DISPLAY MULTIPLEX
Scan Clock
+8
Seven-Segment Decoder and Driver, Leading Zero Suppression
lnput and Output Data Lines
REGULATED POWER SUPPLIES
3
SERVICE INFORMATION
Symbols and Reference Designators Electrical Parts List Internal Adjustment Procedure Controls and Connectors Illustration Block Diagram Parts Location Grid Trigger Amplifier Diagram Counter Time Base and Control
Counters and Display Diagram Mechanical Parts List Fig. Accessories and Repackaging
(B)
A
B (A Start-B Stop)
MHz Clock
1
MHz Clock
Counter and Time-Slot Decoder
and Display and Parameter
Diagram
1
Exploded View
(B)
(DDU's)
(DCU)
LED'S
.
Page
Operating Instructions-DC
503
Slope and
A front-panel pushbutton for each channel determines whether the trigger circuits will respond to either positive- stable triggering. See Fig. or negative-going transitions of each input signal. over
(A)
LEVEL
Noise Impulses 200-millivolt
Erroneous count.
Fig.
1-2.
Triggeringcircuit responses to improper
hysteresis window
The LEVEL control for each channel allows the
operator to move the hysteresis window of the trigger circuit to an optimum level on the input
+,I
.5
V of the input signal in the
(6)
Correct count.
(A)
and proper
(B)
LEVEL settings.
FREQUENCY MEASUREMENTS
FREO
100
GATE TIMEs Make sure the LEVEL control
signal to the CH A INPUT. Set the DISPLAY TlME control
CCW.

Triggering

A
To measure and display the frequency of
MHz, set the FUNCTION switch to one
bracketed
under
the
heading
is
pushed in and connect the
a
signal up to
of
the shorter
of
FREO
A.
count varies from reading to reading, jitter in the signal source. If the count changes unreason­able~
the
DC
503
is
not being triggered prc)per'yr either because the controls are not set right or the signal the
For frequency measurements, all CH B trigger settings have no effect. "N" or "CLOCK RATE" settings are irrelevant.
capabilities.
signal to assure
1-2.
The LEVEL control adjusts
XI
ATBEN position.
it
is
probably due to
is
beyond
The CH A LEVEL, Slope, Coupling, and controls all affect the ability to make a measurement. In general, the trigger controls are similar to oscilloscope controls, except that the end result is not a stable waveform graphic display, but a stable digital frequency display.
Coupling and
quency
control for changing DC levels. The repetitive nature of frequency signals makes SLOPE selection insignificant.
5
amplitude signals, select an attenuation factor such that the attenuated signal peak-to-peak. The LEVEL control must be varied for a stable reading. amplitude and frequency are close to (or perhaps beyond) the specified limits.
show jitter when measured with 7-digit resolution. If the
measurements
Attenuators and
V, peak-to-peak, should not be attenuated. For higher
A signal which looks stable on an oscilloscope may still
SLOPE.
falls into the range of
It
will not be touchy unless the signal
Use AC-coupling
to
avoid re-adjusting the LEVEL
LEVEL.
Signals between
ATTENuator
for
most
300
500
mV to 5 V,
fie-
mV and

Measurement Intervals

To adjust the trigger controls, choose a short GATE TlME such as display as to whether the Counter is being triggered or not.
If
it
is, numbers will appear in the display. (If the frequency
is below shortest gate times. For such low frequencies, a PERIOD
measurement
Final selection of GATE TlME depends on the quency being measured, desired resolution, and willingness of the operator to wait for a measurement. Using short gate times, higher frequencies may be measured, but at the expense of the greater resolution capabilities of the longer gate times.
Resolution.
must wait displayed. and accuracy for signals below second count will display fewer than the available 7 digits.
.I
s
or
.O1
s.
This gives rapid feeldback via the
100
HZ, numbers may not appear during the
is
better
suited-)
A
10
s
GATE TlME means the operator
10
seconds for a measurement to be made and
It
is
the only way to get best possible resolution
1
MHz. Even then, a
fre-
10
-
Operating Instructions-DC
503
Overflow.
it
is
Choose
-
number of the measurement as far to the left Note the Move the decimal point to the left by choosing longer GATE TIME!; until the desired resolution display will flash when the most significant number over-
flows the
lution does
except for quick A-B comparisons. The relationship
GATE TIME, measured frequency, displayed digits, and
overflow
:EF
10
Through intentional use of "overflow" displays,
possible to improve the resolution of the counter.
a
GATE TlME which displays the most significant
numbers displayed to the right of the decimal.
is
achieved. The
last
storage register. Note that the increased reso-
not add to the accuracy of the measurement,
is
shown in Table 1-6.
TABLE
10
1
2100
MHz
100
;
1
7
digits
(3verflow
(3verflow Overflow
s
Overflow Overflow Overflow
1
MHz
MHz
6 digits
7
digits
1-6
1
MHz
to
,
10
MHz
1
5
digits
6
digits
7
digits 6 digits
to
as
possible.
betwen
hl
MHz
1
4
digits
5
digits
7
digits

Measurement Rate

Once a stable measurement which measurements are made can be controlled by the DISPLAY TlME control. Turning the control cw holds off the gate and stores the display for
a
before DISPLAY TlME and GATE TlME together complete measurement-display cycle.
The D
able from about 0.1
cw end. At the cw end, there HOLD. In HOLD, the displayed for an indefinite time. A new count and display may be initiated by pushing the RESET button, turning the
DISPLAY TlME control ccw, or changing to another GATE
TIME.
new measurement
ISPLAY TI ME control
s
at
the ccw end to about 10
last
is
obtained, the rate
a
longer time
is
made and displayed.
is
uncali brated and vari-
is
a
detent position called
count taken will be stored and
at
s
at
the
a

PERIOD MEASUREMENTS

-

Gating

is
Period measurement timers primarily to overcome a basic limitation of counters, i.e., the long time required to make a high resolution high accuracy measurement of low frequency signals. For example, a 1 kHz signal requires 1,000 seconds of GATE TlME to second, a 1 kHz signal can gate pulses from a 1 MHz clock.
functions of signal and clock as compared to the FREQ A mode. In FREQ A, the gate of clock pulses while signal events are counted, then waves can be measured accurately at the very low end if the displayed. In PERIOD B, the gate
number of signal events (N), while 1 ps clock pulses are
counted,

Averaging

signal value over
the selected number of N (AVG'D OVER N CYCLES OF B) increases the total time to take to selecting general, the product of the signal period and the selected N
acc~~mulate a million counts. However, in only one
Simply stated, the PERIOD B mode reverses the rather sensitive to wave shape and amplitude. Since
then displayed.
Resolutiori and accuracy
a
large number of signal events. Increasing
a1
longer GATE TlME in the F REQ A mode. In
provided in universal counter-
a
count of one million clock
is
held open for some number abruptly, square waves are preferred. Sine and triangle
is
held open for some
is
increased by averaging the
a
measurement, similar
factor should be 1 to < 10 seconds. The maximum period capacity
frequency
with
Low
ularly in the lowest decade from 0.1 Hz to 1.0 Hz, become
desirable for the signal to pass through the trigger hysteresis
input amplitude driven hard. For repetitive signals below 0.1 Hz, use the TIME A*B mode.
its
the higher frequencies, the frequency mode should be used. The CH B controls operate the same
Because PERIOD frequencies, the use of DC COUPLING will be more common than with CH A.
is
9,999,999
will
cause
practical
N=~.
Frequencies
Period measurements of signals below 10 Hz, and partic-
CH
B
is
the channel provided for period measurement;
bandwidth of 10 MHz
ps.
Therefore, a period X N product
an
overflow.
for
period
is
kept high so that the trigger input
B
measurements may involve very low
This
means
that
measurement
is
adequate for that purpose. For
is
O.l
as
the CH A controls.
the
lowest
Hz,
even
it
is
is
Operating Instructions-DC
503
REAR

Customizing the Interface

Input and output access to the DC 503 rear of the main circuit board. Fig. 1-4 identifies the contacts and their respective
A Power Module mainframe option (Option 2) available which provides to which Also possible are intra-compartment connections with other plug-in modules in multiple-compartment mainframes. The Reset, Time-Slot Zero

Control Lines

These lines allow the user to externally command the
DC
A Reset input line, which doubles line, clears the Counter to zero when a low An input line to disable the flashing overflow display also doubles as an output signal line during overflow. The the interface for possible synchronous applications.
If0 lines can be hard-wired for external access.
503
to certain operating conditions.
CONNECTOR I/O ASSIGNMENTS
.
internal scan clock can be shut off by the Internal Scan
is
available at the
I10 assignments.
a
rear-panel, multi-pin connector
as
an output signal
is
applied to
it.
Clock Disable line, while using an external scan clock.

Signal Lines

These lines provide for signal input to each channel,
is
status and clock signal outputs, BCD data outputs, and external scan clock inputs.
(TSO), Data Good, and Overflow lines report the status of the DC 503. BCD data lines report the count in an 8-4-2-1, serial-by-cligit method.
As long as the Internal Scan Clock Disable line remains high, the Internal Scan Clock output signal When the Disable line Clock line becomes an input line for an External Scan Clock signal.
The DC 503's internal
is
pulled down, the Internal Scan
1
MHz Clock signal
is
iis
available.
brought to
INTERNAL
OVERFLOW
SCAN
CLOCK
OUTIEXTERNAL
OUTIOVERFLOW
BCD
OUTPUT,
SERIAL-BY-DIGIT
CHANNEL B INPUT
FUNCTION
SCAN
DISPLAY
CHANNEL
Fig.
I
ASSIGNMENTS
CONTACT
I
I
1-
-
{
25B
24B
23
:::
19B
17B 16B
B
-1
CLOCK
IN
DISABLE
DATA
1-4.
IN
GOOD
B
INPUT
GROUND
InputIOutput contact assignments at rear connector.
4
+I
4
d
-
I
I
-
-
I
-
I
-
I
I
ASSIGNMENTS
FUNCTION
27A 26A 25A
20A 19A
17A
16A CHANNEL A INPUT
14A
INTERNAL
RESET,
TIME
SLOT
CHANNEL
1-MHz
CLOCK
SCAN
INIOUT
ZERO
BCD
OUTPUT, SERIAL-BY-DIGIT
A
INPUT
OUT
CLOCK
(TS,)
GROUNID
CllSABLE
Section
2-DC
503
INPUT
Attenuators, Channels A and (B)
Events to be counted are applied via front-panel INPUT connector are frequency-compensated voltage dividers consisting of resistors R 18-R25
(C118-C125). Switches S20A (S120A) and S20B (S120B) allow front-panel selection of XI, X10, or XI00 atten­uation of coupling.
J10 (J110) to the attenuators. The attenuators
(R 1 18-R 125) and capacitors C18
the input signal. C15 (C115) provides AC
SECTION
THEORY
OPERATION
CIRCUIT

DCU Signal Selection Gates

The two separate bistable multivibrators produce sharp signal edges for the decade counter units TOTALIZE A, RATIO positions,
and
MANUAL, or TlME bistable multivibrator for the DCU drive and by the DDU (decade divider unit) output. In PERIOD U200D-U226C
control signal from the 1 MHz clock.
U200A-U200C
is
switched
by the channel A input signal. In TlME
is
AIB, or one of the FREQ A
is
the active bistable multivibrator
A-tB, U200D-U226C
the active multivibrator.
OF
(DCU). In
is
the active
is
controlled
It
receives
2
B,
a
Signal Shaping and Slope, Channels A and (B)
Field effect transistor (FET) 035 (0135) presents a high impedance base of between the LEVEL control R45 050 (0150). Adjustment of the LEVEL control changes
the bias on the input signal will trigger the DC 503.
060 and 1050 in the Channel A signal shaping circuitry comprise in the Channel B signal shaping circuitry) acts follower.
070-080 (0160-0170) pair. slope by biasing the desired slope to R74 positive slope negative slope follower 095 and the slope-determined output signal to the appropriate
DCU signal selection gate and the A start portion of the
Time
to1 the input signal and a low impedance to the
050 (01 50). FET 040 (0140) provides isolation
(R145) and the base of
(150 (0150) and thus selects what portion of
a
hiigh frequency, high gain amplifier. 068 (0150
as
an emitter
is
a
signal switched differential
+
SLOlPE switch S75 (S170) selects the triggering
(R165). The
is
passed through 090 (0165), while the
is
passed through 074 (0180). Emitter
(0185) couples the signal level to a TTL level
A+B ciircuit.
The output signal from the active bistable multivibrator goes to NOR gate toggle the decade counter units.
U200B. The output of U200B
is
used to
Time A+B (A Start-B Stop)
The two separate bistable multivibrators (U220C-U220D
and U220A-U220B) produce sharp edges to toggle U224A
and B.
In TlME
at
pin 1 of U226A, making pin 3 of NAND gate U226B
high. Pin 4 of U226B starts low when
pin 4 of U224A. Pin 5 of U226B starts high due to a low pin 13 of U224B. An "A trigger" causes U224A to toggle, which makes pin 4 of
pin 14 of
of event to be counted).
"armed" by the high that occurs circuit now waits for a "B trigger" which will toggle and put a low on pin 5 of U226B. When the B trigger arrives, gate generator circuit closing the gate. When the gate closes, a CLEAR resets
A+B mode the FUNCTION switch puts a low
CLEAR
U226B high. This outputs a low to
U272B1 causing the gate to "open" (permits input
U224B simultaneously becomes
at
its
pins 12 and 13. The
U226B will output a high to pin 14 of U272B in the
U224A, which in turn resets U224B.
goes low
U224B
at
at
Theory of Operation-DC
503
charges. At TI, 0288 reaches discharges the capacitor. This results in
pulse on the direct-set input (pin 2) of U270AI forcing
-
output high and
U280A, high, The next high-to-low transition from the 1 MHz clock toggles U27i!A, causing go low. With a low applied to one of reverts to and CLEAR pulses. The DDU's then start counting from their 09999919 reset condition.
DDU's to count the first digit, plus negative transition from the DDU's via either the FUNC­TION or mode) toggles 2-1. next negative transition from the 1 MHz clock U272B, causing
its
GATE indicator LED, is preventing
(GATE)
inverter and isolation transistor
.-
selected by either the FUNCTION or switch (depending on operating mode). At the end of this time, which corresponds to transition from the DDU's toggles
its
produciing the CLEAR and CLEAR control signals.
At the
N1C:LOCK RATE switch (depending on operating
U270B1s Q goes high and
a
output .to go low (supplying current to the front-panel
applied to the base of Q280, saturating the tran~stor and
is
The GATlE remains open (high) for the time duration
its
a
output low. With two high inputs on
output goes low and the output of U280D goes
its
Q output to go high and
its
original condition, terminating the CLEAR
end of a 10-microsecond delay (time for the
U270B. This event corresponds to T3 in Fig.
its
Q output to go high (GATE open) and
DS275). The U272B Q output (gate)
C:285 from charging. The U272B Q output
also supplied to a front-panel connector via
its
firing potential and
a
short-duration low
its
inputs, U280A
a
propagation delay),
output goes low. The
its
(2278.
NICLOCK RATE
T5 in Fig. 2-1, another negative
U270B. U270B1s Q
its
(T,)
its
Eto
(T4) toggles
output goes low and negative transition from the
Q
a
U272B1 causing Simultaneously, the Q output goes high, removing current from the GATE indicator LED.
When the
transition toggles
U280B has two high inputs, placing a low at the output of
U280B, terminating the LATCH signal.
The display time begins when the GATE signal ends (T6). When 0280 turns off, C285 begins to charge through R282-R285 toward the
TIME, provides an adjustable time constant to vary the display time form about 0.1 second to about 10 seconds. When the DISPLAY
(HOLD detent position), S285 opens, and C285 stops
charging. When S285 ciently to bring Q288 to display time ends and the next GATE-opening sequence
begins.
Q270 provides an automatic reset by grounding the
RESET line for FUNCTION and NICLOCK RATE switches also provide method of automatic reset. The two switches ground the
RESET line between switch matic reset insures that the readout has been cleared before
the next measurement. The automatic reset can be seen by noting that the display goes to all eights (all LED segments lit) in between switch detent positions.
U272B Q output goes low,
a
its
output goes high. The next
1 MHz clock (T6) toggles
its
Q-output to go low, closing the gate.
U270A, switching Q low and Q high. Now
Vcc
supply. R285, DISPLAY
TlME control
is
closed and C285 charges suffi-
its
firing potential (TI
short time after instrument turn-on. The
detent positions. The auto-
is
fully clockwise
the
negative
),
the
a

COUNTER CIRCUITS

Decade Counter Units (DCU)
The 100 through 106 DCU
ten counters. The first decade counter
J-E<
individual circuit board,, to accept the high-speed decade input (up to
100 MHz), U210B, U21:2, and U214 comprise the first (100) decade
counter, and U305 through
DCU1s.
six
When the J and K inputs of U210A are high (GATE open), the counter the toggle counted by goes low, providing
input for the second decade counter. Each subsequent decade divides by ten in output lines are connected from each DCU to storage-register latch. When the CLEAR (high) and CLEAR
flip-flops, located on the Trigger Amplifier
and each subsequent DCU
is
enabled. The input signal is applied to
input of U210A. On every tenth clock input
the first decade counter, the output of U214
a
carry signal which becomes the clock
is
seven cascaded divide-by-
is
made up of four
is a single IC. U210A,
U310 make up the remaining
a
similar manner. Four BCD
its
associated
(low) signals are activated, all of the decade counters are
reset to the zero-count
state.

Storage Register

The seven IC latches (U320 through U326) comprise
storage register which stores the corresponding decade counter BCD output. The BCD output number the data inputs bits respectively). The LATCH pulse data-strobe input
(negative transition) or when the FUNCTION switch placed in the TOTALIZE A, or TlME MANUAL positions. While the LATCH input inputs are transferred to the associated BCD bit output to
be scanned by the multiplexing circuit.
at
pins 1, 5, 7, and 3 (20, 21, 22, and 23
at
pin 2 of each latch
is
high, the logic levels
at
is
applied to
is
applied to the
the end of GATE
at
the data
is

Overflow Register and Drive

When the decade counters have counted to 9,999,999,
the counters are full. At the next count the
23 output of
a
Theory of Operation-DC
U310 goes low, providing a toggle input to U311A. When
this occurs,
U311 A. When the LATCH pulse ends (goes low), U311
toggled and the high
U311 B goes high, high now at the input of which causes the LED display to flash.
a
high
503
is
transferred from pin 14 to pin 12 of
B
is
transferred to pin 8. When pin 8 of
CR311 and CR314 are turned off. The
U328B starts a multivibrator
U311A goes low on the first overflow count, 0312 and
of
CR314 turn off. Since pin 8 of U311B
off) by the clear input (pin 6), this first overflow count
is
causes overflow circuit the display
high).
a
flashing LED display. This difference in the
is
necessary in the "manual" modes, since
is
continuously read from the DCIJrs (LATCH
is
held high (CR311
-
In the modes, overflow indication CR314. The emitter of 0312 closure
TIME MANUAL and TOTALIZE A counting U311A
is
achieved via 0312 and leading-zero suppression during the overflow condition, the
is
grounded by a switch display-controlling circuits are notified via U328A that the
as
is
the clear input (pin 6) of U311
B.
When pin 13 count
is
reset by the CLEAR pulse. To prevent
is
in excess of that displayed by the LED readout.

DECODE AND DISPLAY MULTIPLEX

Scan Clock

is
The scan rate of the multiplexing circuit
is
by the scan clock. The scan clock and U330C, which operate at an approximate 2-kilohertz rate. provided for internal scan-clock disable, internal scan clock output, and external scan clock input. The scan clock output drives an eight-state counter and for zero suppression.
+8
Counter and Time-Slot Decoder
The divide-by eight counter
U333A, and U333B. The output of this counter drives BCD output of the latches, then supplies current to the
as
composed of U330B
a
free-running multivibrator
Input/output lines are
is
made up of U332B,
determined
a
storage register
U335, a BCD-to-decimal decoder. U335 provides eight output lines (designated TSo through TS, in the schematic, and in Fig. 2-2) to simultaneously enable
its
each counter latch and sequentially. For example, when the 0360
is
turned on to supply anode voltage to DS360
same time inverter
U326, enabling allows the latches to share
U337A applies a high to pin 6 of latch
its
output. Operation in a time sequence
corresponding display LED
a
common
set
the output of
TS, line goes low,
at
the
of ou~:put lines.
Seven-Segment Decoder and Driver, and Display and Parameter LED'S
U340
is
a
BCD-to-seven-segment decoder.
It
accepts the
-
Scan clock
TS
Q
TS
7
-
RESET Dl D2 D3 04 D5
RBI, pin
5
U340
I
Fig.
r---
I
2-2.
Multiplexing circuit ladder diagram showing timing with an all-zero display.
r----
I
-
T-"--'---'T""
I
1 1
I
I
1
L
Forced
by
-
RESET
--
Theory of Operation-DC
503
appropriate cathodes of the enabled LED to display the correct number. The display
DS384. When looking DS360 controls the numerical digit displayed (1
06), DS364 controls the second (1 05), etc. Each LED has seven segments, arranged so that segments forms
"8"
lighted, an
is
at
a
number. When all of the segments are
formed.
LED'S are DS360 through
the front panel of the DC 503,
at
the far left
a
combination of lighted

Leading Zero Suppression

Decoder driver U340 also has which allows suppression of the zeros leading the most significant digit (MSD) in the display. At applied to the direct-clear input of U332A, the zero­suppression storage register. This zero-suppress
Blanking Input (RBI, pin 5) of U340 to be low. When the
output of U335 advances to the next time slot
of
RBI
propagation delays, which allows the first digit to arrive from the latches while RBI decoded
inhibited and the ~i~~l~ ~l~~ki~~
be
low. and RBO goes high. The RBO of U332A and scan-clock transition occurs. Thus if the first digit pin 5 of U340 is held low, inhibiting the output until the
first non-zero digit comes through the decoder. When the first non-zero digit arrives, the outputs of U340 are enabled
and the set high, removing the RBI from pin 5 and allowing all succeeding digits to be displayed through the
state
(high
at
U340 remains low for a few nanoseconds due to
is
a
zero, the output to the display LED will be
If the digit
digit
is
is
not a zero, the outputs are enabled
is
transferred to the output when the next
displayed. Also, the RBO output
a
zero-blanking feature
TSo, a low
sets
U332A to the plug-in
pin 6), allowing the Ripple-
(TS,
),
the
is
low. If this first digit being
output
is
applied to the pin 2 input
(RBO
pin
4) will
is
a
at
pin 4
TS7 sequence.
zero,
is
is
gates U350A and U350B, NOR gate U330A and inverter
U354B, setting U332A to the non-blank appropriate time. In the case where the counter overflows,
031 2
the high output from U311 B or setting U332A to the non-blank
When the front-panel RESET button goes low, overriding the output of non-blank and lamp-test functions to the decoder. This causes all seven segments in the display on.
Input
and
Output
The following inputs and outputs are available via the
connector
INT SCAN CLOCK DISABLE: A low applied to this line disables the internal scan clock.
INT-EXT SCAN CLOCK: This
output line, input of an external scan clock. provided the hternal scan
TSo: A low
state.
DATA GOOD: A high
when a new reading
register latches.
is
disabled.
it
Data
Lines
for
external
provides output for the internal scan clock or
is
present on this output line in the TSo
is
access.
is
present on this output line
being transferred into the storage
is
state.
U332A, applying the
is
a
dual-function input/
state
at
the
applied to U350B,
is
pushed, RESET
LED'S to be turned
When the scan gets past the decimal point in the display,
any
or
if
the
display
decoder are displayed. This is achieved inverted by U352A and applied through negative output OR gate
is
This holds pin 5 of U340 high, preventing zero-blanking during the TS,, time slot.
determined switches. The proper information
contacts of the switches to NAND gates U352B, U354C or U354A. Time slot lines TS2 through TS6 enable the PJAND gates to output to negative output OR
U350B, NOR gate U330A, and inverter U354B. It
then applied to the direct-set input of U332A
loca,tion of the decimal point in the display
The
by
the
zeroes
is
arriving
as
follows: TS7 is
Or
NICLoCK RATE
applied via the closed
U352C, U352D1
as
at
a
low.
the
is
IN-OUT OVERFLOW DISPLAY DISABLE: This output
alternates when the count overflows. It can also be forced low
at
any
time
to
disable the display.
RESET line. It provides
an external reset input.
BCD OUTPUTS: 1, 2, 4, 8 provide BCD output, serial by digit, from the currently enabled storage-register latch.
1 MHz CLOCK: Provides output for the internal 1 MHz
clock.
IN-OUT: This
a
low output during reset, or can be used
is a dual-function inputloutput

REGULATED POWER SUPPLIES

The DC 503 operating power
module mainframer then regulated to provide stable transistors Q540, 0545 and 0548 regulate the supplies of +15 volts, 4-5 volts, and -22 volts. The +15-volt
supply, whose active device for the remaining supplies. Its output volts by adjustment of R505.
is
obtained from the power
is
U500, provides the reference
is
set
to exactly +I5
Integrated circuit U520 regulates the +5-volt supply, and
upp ply.
located
proper
The series-pass transistors for these supplies are
in
the
mainframe,
heat dissipation.
where they
can
as
-22
volt
provide the
Al' B
BT C Cer
C
C
DL
D
Elect.
Ek\C
EMT
F
Ckt. No.
AS SEMBLIE3
3
A3 A3 A4 A5
CAPAC
ITORS
C10 C15
C18 R2 C28 S2 C32 T2 C35 S2 C38 C40 52 C52 S2 C54 C67
C76 '42 C80 C90 C115 s5
ELECTRICAL PARTS
Replacement parts should be ordered from the Tektronix Field Office or Representative in your area. Changes to Tektronix products give you the benefit of improved circuits and components. Please include the instrument type number and serial number with each order for parts or service.
ABBREVIATIONS AND REFERENCE DESIGNATORS
Assembly, separable or F repairable H Attenuator, fixed or variable Motor HR Battery Capacitor, fixed or variable Ceramic Diode, signal or rectifier
A!
cathode-ray tube M
R!T
Delay line Indicating device ( lamp)
5;
Electrolytic P electrolytic, metal cased PMC electrolytic, metal tubular PT Fuse
Filter
L
Heat dissipating device
(
heat sink, etc.
Heater
Connector, stationary portion
J
Relay
K
Inductor, fixed or variable
L
Inductor/resistor combination
L
R
Meter Transistor or silicon-
Q
controlled rectifier Connector, movable portion Paper, metal cased paper, tubular
.
)
LIST
paper or plastic, tubular
PTM
molded Resistor, fixed or variable Thermistor Switch Transformer Test point Assembly, inseparable or non-repairable Electron tube Variable Voltage regulator (zener diode, etc.
1
wire-wound Crystal
Tektronix Serial/Model No.
Part
No.
Eff
Disc
Description
DISPLAY Circuit Board Assembly MAIN Circuit Board Assembly
MAIN
Circuit Board Assembly TRIGGER TRIGGER
AMP.
Circuit Board Assembly
AMP.
Circuit Board Assembly
PROTECTION Circuit Board Assembly
S3
T1
S1
R2
Q1 42
i5 Circuit . ~oard
68 pF, Cer, 500
uF, Cer, 500
0.01 170 pF, Cer, 500
0.01 pF, Cer, 150
0.1
uF,
Cer,
0.1 pF, Cer, 50
0.01
uF,
0.1 pF, Cer, 50
0.1 pF,
Cer,
24 pF, Cer, 500
pF, Cer, 50
0.1
0.1 pF, Cer, 50
0.1 pF, Cer, 50
0.1 pF, Cer, 50
0.01 pF, Cer, 500
--
V,
50
V V
Cer, 150
V
50
V V, V V
V
V
Assembly.
.
--
10%
V
V,
5%
V,
+80%-20%
V,
+80%-20%
5%
V
'standard only. 2~ption 1 only.
20
pF, Cer, 500 100 pF, Cer, 350 10
pF, Cer, 500 1000 pF, Cer, 500
pF, Cer, 150
0.01
0.1 pF, Cer, 50
0.1 pF, Cer, 50
0.1
uF,
Cer, 50
V,
V,
V,
V, V,
V
V
V
10%
20%
10%
10% +80%-20%
Electrical Parts
List-DC
503
@rid Tektronix
Ckt. No.
boc Part
CAPACITORS
C138 C140 C141 C167 C170 C180 C187
No.
(cont)
R5 283-0003-00 S4 283-0111-00 R6 283-0111-00
P4
Q5 283-0111-00 44 283-0003-00 R3 283-0111-00
283-0003-00
ELECTRICAL PARTS LIST
SeriaVModel
Eff
No.
Disc
(cont)
.01 pF, Cer, 150 .1
pF, Cer, 50
.1
pF, Cer, 50
.O1
pF, Cer, 150
0.1
pF, Cer, 50
0.01 pF, Cer, 150
0.1 pF,
L
pF, Cer, 25
Cer,
10 pF, Cer, 500
pF, Cer, 500
18
1.9-15.7
1
pF, Elect., 35
10
pF, Elect., 25
510
33
pF, Elect., 10
0.001
pF, Var,
pF, Mica, 500
pF, Cer, 500
33 pF, Elect., 10
pF, Cer, 100
0.1
0.1 pF, Cer, 100
0.001 pF, Cer, 500
0.001 pF, Cer, 500
50
V
V
V
V
V,
V, V,
+80%-20%
V,
+80%-20%
V,
980%-20%
V,
+80%-20%
10% 5%
Air,
V,
20%
V,
20%
V,
2%
V,
20%
V,
V,
20%
V,
+80%-20%
V,
+80%-20%
V,
V,
250
V
+loo%-0%
+loo%-0% +fOO%-0%
DIODES
CK28 CR7
9
CR80 CB128 CRl79 CRl80 CU60 CR270 CR271
-\.
1
'standard only. 2~pcion 1 only.
0.001 pF, Cer, 500
0.001 pF,
Cer,
0.001 pF, Cer, 500
0.001
0.001 pF,
pF, Cer, 500
Cer,
0.001 pFy Cer, 500 47 pF, Elect., 20 100
pF,
Cer,
pP, Elect., 20
47 68
pFy
Elect., 6
pF, Cer, 200
650 100 pF, Cer, 350 100 pF,
Cer,
350
200
500
500
V,
V,
V,
V,
V,
V, V,
V,
V,
V,
V,
V,
V,
+loo%-0% +loo%-0% 9100%-0% +loo%-0% +loo%-0%
+loo%-0%
20%
5%
20%
20%
5%
20% 20%
4.7 pFy Elect., 50Vy 20%
0.001 15 pF, Elect., 50
6.8
pF,
Cer,
500
pF, Elect., 35
V,
V,
V,
20%
+loo%-OX
20%
Silic~n, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, replaceable by IN4152 SI~ICQB, replaceable by IN4152 Silicon, replaceable by IN4152
Electrical Parts List-DC
503
Ckt.
No.
DIODES
CK290
ELECTRICAL PARTS LIST
Grid Tektronix SerialIModel
Loc
(~0;:)
Part
No.
Eff
XB010131 Zener, selected from 1N753A, 0,,4
(cont)
No.
Disc Description
Silicon, Silicon, replaceable by IN4152 S ilicon, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, Silicon, Silicon, Silicon, Silicon, Silicon,
Silicon, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, replaceable by IN4152 Silicon, replaceable by IN4252 Silicon, replaceable by IN4152 Zener, selected from 1N751AY 0.4
'Zener, selected from
replaceable by
replaceable by replaceable by replaceable by replaceable by replaceable by replaceable by
IN4152
IN4152 IN4152 IN4152 IN4152 IN4152 IN4152
1N75lAY 0.4
W, W, W,
5.1
5.1
5.1
V, V, V,
5%
5%
5%
Lamp, LED, red Numeric display, seven-segment, LED Numeric display, seven-segment, LED Numeric display, seven-segment, LED Numeric display, seven-segment, LED Numeric display, seven-segment, LED Numeric display, seven-segment, LED Numeric Lamp, LED, red Lamp, LED, red Lamp, LED, red
display; seven-segment, LED
.
FUSE
F520 V5 159-0021-00 XB010131 Cartridge, 2A, 3AG, fast-blo
CONNECTORS
J10 131-0955-00 Receptacle, electrical,
JllO
5275 136-0491-00 Socket, banana jack
131-0955-00 Receptacle, electrical,
INDUCTORS
L18 R2 L523 N2 L549 02
Core, toroid ferrite
pH
2.7 5
c1H
TRANS ISTORS
435 T2
Silicon, FET, selected from 2N4392 Silicon, FET, selected from 2N4392 Silicon, NPN, selected From 2N3563 or replaceable
CS23366
by Silicon, PNP, replaceable by 2N4258 Silicon, NPN, selected from 2N3563 or replaceable
CS23366
by Silicon, NFN, selected from 2N3563 or replaceable
CS23366
by
BNC,
BNC,
female female
Electrical Parts List-DC
503
-
Ckt. No.
RESISTORS
R40 R4 R45 R50 R52 R54 R56
z1
ELECTRICAL PARTS LIST
Grid Tektronix Serial/Model No.
Loc Part No.
(cont)
TI 321-0222-00 S2 315-0823-00
311-1310-00 S1 315-0470-00 S1 315-0152-00 S1 315-0511-00 R1 315-0221-00
Eff
Disc Description
2
W2,
82 20 47
1.5 510 220
118
W2,
114
kQ,
Var
Q,
114
kS2,
Q,
114
n,
114
(cont)
W,
W,
W,
114
W,
W,
w,
1%
5%
5%
5% 5% 5%
R82
\
R84 R85 R90 R9 2 R94 R96 R97 RllO Rlll R115 R118 R122 R124 R125 R127
i~urnished
Furnished
as
as
a
a
unit with unit with
S10.
S110.
20 10 47 510 1
kQ,
2.4 10
W2,
W2,
Q,
a, k0,
W2,
Var
114
114
1/4
114
114
114
W,
W,
W,
W,
W,
W,
5%
5%
5%
5%
5%
5%
ELECTRICAL PARTS LIST (cont)
Electrical Parts List-DC
503
Ckt
No.
INTEGRATED CIRCUITS ( cont
U270 F3 156-0042-00
Grid
Tektronix
Loc Part No.
SerialIModel No.
Eff
)
BOlOlOO
B050000 Dual 15
BOlOlOO
B050000 Dual 15
Disc
Dual 15 replaceable by
20
Dual replaceable by Quad 2-input positive nand buffer, replaceable
by
SN7473N Single 10 replaceable by Single 10 replaceable by Single 10 replaceable by Single 10 replaceable by Single 10 replaceable by Single 10 replaceable by Dual 15
by
SN7473N Quad latch, replaceable by MC4035P Quad latch, replaceable by MC4035P Quad latch Quad latch, replaceable by MC4035P
Quad latch, replaceable by MC4035P Quad latch, replaceable by MC4035P Quad latch , replaceable by MC40 35P Quad 2-input positive nand gate, replaceable
SN7401N
by
Quad 2-input positive nand gate, replaceable
SN7401N
by
B049999 Dual 15
replaceable by
replaceable by
B049999 Dual 15
replaceable by
replaceable by Single BCD-to-decimal decoderldriver, replaceable
by
SN74145N
Hex. inverter, replaceable by SN7404N
Single BCD-to-seven segment decoderldriver, replaceable by SN7447N
Dual 4-input positive nor gate, replaceable by
SN7425N
Quad 2-input positive nor gate, replaceable by
SN7425N
Quad 2-input positive nor gate, replaceable by
SN7425N Voltage regulator, replaceable by UA723C
Voltage regulator, replaceable by UA723C
Description
MHz
J-K
mas ter-slave flip-flop,
MHz
MHz
SN7476N
J-K
master-slave flip-flop,
SN74111N
MHz
divide-by-2-&-5 ripple counter,
SN7490N
MHz
divide-by-2-&-5 ripple counter,
SN7490N
MHz
divide-by-2-&-5 ripple counter,
SN7490N
MHz
divide-by-2-&-5 ripple counter,
SN7490N
MHz
divide-by-2-&-5 ripple counter,
SN7490N
MHz
divide-by-2-&-5 ripple counter,
SN7490N
J-K
master-slave flip-flop, replaceable
replaceable by MC4035P
,
.
MHz
D-type pos-edge-trig flip-flop,
SN7474N
MHA
D-type pos-edge-trig flip-flop,
SN7474N
MHz
D-type pos-edge-trig flip-flop,
SN7474N
MHz
D-type pos-edge-trig flip-flop,
SN7474N
CRYSTALl
Y2502 C5 158-00 79-00 P251 C5 119-0262-00
:standard only.
Option
1
only.
Crystal,
Oscillator,
1'
MHz
RF
+0.001%

INTERNAL ADJUSTMENTS PROCEDURE

Services Available

I
Tektronix, adjustment at local Field Service Centers and at the Factory Service Center. Contact your local TEKTRON Office or representative for further information.
Test
Equipment
For measurement of the power supply voltages,
ohmslvolt
example, Triplett 630 NA multimeter.
A
lox
time base reference to the oscilloscope to prevent excessive
loading.
For
,
frequency standard or other frequency source having stability of
measuring optional 5 MHz crystal output) is recommended
nc. provides complete instrument repair and
VOM
will give satisfactory measurements. For
probe is required to connect the DC 503 I-MHz
1
-MHz frequency measurement,
at
least 5 parts on
lo7
a
secondary Power Supply Checks and Adjustment. Connect the
(5 parts in
lX Field
a
20,000
a
lo8
if
for accuracy. Also recommended is a test oscilloscope with
at
a bandwidth of for frequency-comparison measurement.
least 1 MHz and a stable triggering circuit

Procedure

NOTE
The performance of this instrument can be check at
0°C
to
any temperature within the Make any adjustment at a temperature between
+20"~
TM extender (TEKTRGN
voltmeter between the +15-volt test point and ground.
Adjust R505 for
+5 volt and -22-volt supplies to be within 5%.
and
+30"~ (+68"
The DC 503 can be operated either fully installed in a
500 Series Power Module
a
reading of +15-volts. Then check the
F
and
or
IX Part No. 067-0645-01).
+50°c
+86"
F).
connected
to
range.
a
plug-in
NOTE
If
the instrument is operated on the plug-in extender,
the +5-volt supply may not regulate.
Secondary
standard
Time-Base Frequency Check and Adjustment. Connect
the
DC
503 1-MHz time base reference and the secondary standard to the oscilloscope as shown. Adjust the oscillo­scope to display several complete cycles.
0
1
1
MHz
l nput
O
Ext
Trig
NOTE
I;
1
MHz
Option removing the slotted plug from the crystal oven to
gain access to interior adjusting slug.
To determine oscillator error, observe the rate of horizontal drift of the displayed waveform. Waveform moving to the right indicates that the time-base frequency is
<I
MHz; to the left, > 1 MHz. The period in seconds for the waveform to move the width of one cycle is equal to the frequency difference in parts in the waveform drifts to the right at a rate of one cycle's width every 10 seconds, the time-base frequency in
lo6
low. Maximum allowable frequency difference
part in
Adjust C255 for no drift.
lo5
(5 parts in
clock adjustment is made
lo6.
For example, if
lo7
for the optional 5 MHz crystal).
is
0.1 part
by
is
1
+5 V Test Point
R522
+I5 V Adjust
R505
+I5 V Test Point
R502
v
-22
Test Point
R542
/
Outline indicates area occupied by crystal oven when option 1 is installed. Components inside outline are removed when option is installed.
1
MHz
I
Clock
C255
1
MHz
Test Point
U272,
Pin 5
@
FRONT
Attenuation Pushbuttons
Two self-canceling buttons select XI, attenuation of the input signal.
LEVEL Control
Selects the amplitude point on the input
signal input source. Pulled out selects the rear connec­tor input. Pushed in the front-panel BNC con­nector input.
X10,
\ \
signal at
selects
PANEL
or XlOO
CONTROLS & CONNECTORS
Display Readout
LED readout, seven
segment
matically placed decimal point. The leading zeroes are overflow is indicate1
d~g~ts with auto-
~~DDresSed unless an
..
L
7-
Units Indicators
LED indicates that
played number is MHz
(106), or kHz (103) if in
CDCn
A
--_I--
(100) if in a time mode. In the RATIO TOTALIZE A modes, no units are indicated.
AIB and
/
FUNCTION Switch
Selects measurement or time counting modes for
counter. Also selects the gate (measurement) inter­val in the four FREQ A positions.
Gate Indicator
Lights
/
during the active
gating
interval.
dis-
-
Manual Gate Pushbutton
Push-push switch operable
TlME MANUAL or
when
Gate Output Connector
Provides a inciding with the measure­ment interval.
INPUT Connector
BNC connector for signal input.
Input Coupling Pushbutton A push-push switch which
selects whether the input Variable control concentric signal is AC or DC coupled with into the attenuators. switch sets the
Trigger
A push-push switch which selects the slope of the input signal on which trig­gering will occur.
+5-volt pulse co-
Slope Pushbutton
/
/
Selects the gate (measure-
ment) interval for the RATIO TlME A--PB and TlME MANUAL modes of the FUNCTION switch.
AIB, PERIOD
6,
:\,
:
which manually resets (acts as a master reset) and vides a segment check of the
I
Ground Connector
Provides a chassis return for signals.
TOTALIZE A is selected by the FUNCTION switch.
Button in starts the u re men
button out terminates the gate.
RESET Pushbutton
Monentary
7
readout digits.
.
t
pushbunon
DISPLAY
NICLOCK RATE
+;ma
+he
.llllr
displayed after the count is made and before the next measurement is taken. Dis­play time can be varied from 0.1 s
10 seconds position continuous display until re­set by pressing the RESET button.
i
nterval gate;
pro-
TIME Control
~a-rl;.-.~
I=aUltlg
(ccw) to about
(cw). HOLD
(detent) provides
meas-
'--m+'-
lelmyttm
will be
-*
MANUAL
RESET
CONTROL SIGNALS
U280A U280B U280C U280D
U328C
-
CLEAR
LATCH
-
RESET
A
A
w
A
-
1
19B
LATCH
f
8
BLOCK
DIAGRAM

PARTS LOCATION GRID

NOTE: COMPONENTS SHOWN WITH DASHED LINES ARE LOCATED ON BACK SIDE OF BOARD.
*Located
on
back
of
board
SN
8070000
and
up.
IUT
IN
P
5170
SEE PARTS LIST FOR EARLIER VALUES AND SERIAL NUMBER RANGES OF PARTS MARKED
WITH
BLUE OUTLINE.
-
Replacement parts should be ordered from the Tektronix Field Office or Representative in your area. Changes to Tektronix products give you the benefit of improved circuits and components. Please include the instrument type number and serial number with each order for parts or service.
ABBREVIATIONS
binding head brass
binding head steel cathode-ray tube countersunk
double end flat head brass
flat head steel
fillister head brass
fillister head steel
Fig.
BHB
BHS CRT csk
DE
FHB
FHS
Fil HB
Fil HS
&
lndex Tektronix SerialIModel No.
No. Part No.
ff
.
Disc
h
hex. HHB HHS HSB HSS
ID
lg OD
height or high hexagonal hex head brass hex head steel hex socket brass hex socket steel inside diameter length or long outside diameter
t
Y
1234s
OHB OHS
PHB
PHs RHS SE THB THS
W
Description
oval head brass oval head steel pan head brass
pan head steel round head steel single end truss head brass truss head steel wide or width
337-1399-00
BOlOlOO
337-'1399-00 B050000 337-1399-02 B050000 366-0494-00
------
213-0153-00 366-1190-00
------
2.13-0153-00 366-1031-05
------
2l3-0153-00
366-1170-01
------
2l3-0153-00 366-1422-00 366-1422-01 B010152 214-1840-00 XB010152 366-1257-87
366-1402-41 366-1257-27 366-1257-28
366-1402-64
366-1257-30 3'58-0029-00
-
- - -
2:LO-0590-00 2:LO-09 78-00
BOlOlOO
- -
B049999
B010151
SHIELD, electrical, side SHIELD, electrical, side SHIELD, electrical, side
KNOB,
gray--LEVEL (CHA & CHB) each knob includes: SETSCREW, 5-40 x 0.125 inch, HSS
KNOB,
gray--FUNCTION
knob includes
:
SETSCREW, 5-40 x 0.125 inch, HSS
KNOB
red--DISPLAY TIME
knob includes
:
SETSCREW, 5-40 x 0.125 inch, HSS
KNOB,
gray--CLOCK RATE
knob includes
:
SETSCREW, 5-40 x 0.125 inch, HSS
KNOB,
KNOB,
latch
latch PIN, knob, latch PUSHBUTTON--XI0 PUSHBUTTON--XI00 PUSHBUTTON--AC COUPL PUSHBUTTON--+ SLOPE PUSHBUTTON--IN START OUT STOP PUSHBUTTON--RESET BUSHING, 0.375-32 x 0.50 inch
mounting hardware for each NUT, hex., 0.375-32
WASHER, flat, 0.375
x
ID
:
0.438 inch
x
0.50 inch
(not included wlbushing)
OD
NUT, knurled, 0.25-28 x 0.375 inch
OD
STUD, binding post SOCKET, banana jack
mounting hardware: (not included NUT, hex., 0.25-32
x
0.312 inch
wlsocket)
LUG, terminal, SE WASHER, insulating, 0.375 inch diameter
Mechanical Parts List-DC
Fig.
&
503
FIGURE 1 EXPLODED (cont)
Index Tektronix SerialIModel No. t
No. Part
No.
Eff
Disc
Q
y
12345
1
CONNECTOR, receptacle,
1
CONNECTOR, receptacle,
-
mounting hardware: (not included w/connector)
1
TERMINAL, lug, 0.391 inch
2 RESISTOR, variable
-
mounting hardware for each: (not included wlresistor)
1
NUT, hex., O'i25-32 x 0.312 inch
1
WASHER, flat, 0.25
Description
BNC,
BNC,
ID,
ID
x 0.375 inch
wlhardware wlhardware
SE
OD
333-1610-00 426-0681-00 426-0916-00 331-0314-00 214-1513-00 214-1513-01 B010152
BOlOlOO
------
213-0254-00
376-0051-00 376-0051-01 B050000
BOlOlOO
------
213-0022-00 213-0178-00 B050000 354-0251-00 376-0049-00 384-1127-00 384-1099-00 386-2303-00
BOlOlOO
B010151
B049999
B049999
PANEL, front FRAME, pushbutton FRAME, readout window WINDOW, readout LATCH, plug-in securing LATCH, plug-in securing mounting hardware: (not included
SCREW, thread forming, 2-56 x 0.25 inch, 100" csk, FHS
COUPLING
COUPLING
coupling includes: SETSCREW, 4-40 x 0.188 inch, HSS SETSCREW, 4-40 x 0.125 inch, HSS
RING
COUPLING SHAFT, extension, 7.50 inches long SHAFT, extension, plastic, 1.54 inches long SUBPANEL, front
mounting hardware
SCREW, thread forming, 6-20 x 0.375 inch, 100" csk, FHS SCREW, thread forming,
SHIELD, electrical, subpanel CIRCUIT BOARD ASSEMBLY--DISPLAY (See
circuit board assembly includes:
SOCKET, pin connector CIRCUIT
circuit board assembly includes SWITCH, push SWITCH, push SPACER, switch, red SOCKET, integrated circuit,-16 pin
SOCKET, integrated circuit, 16 pin SOCKET, pin connector SOCKET, pin connector
-
CIRCUIT BOARD ASSEMBLY-- f5 (SEE EPL A5)
-
mounting hardware: (not included wlcircuit board assembly) SCREW,
ROD,
SCREW, SCREW, thread forming, TUBE, spacing, 0.189 SPACER, SLEEVE
1
SCREW, 4-40 x 1.25 inches, PHs 2 SCREW, 6-32 x 0.50 inch, PHs 2 SPRING, grounding, plug-in 2
TUBE,
2 NUT, keps, 6-32
BOARD
circuit board includes
TERMINAL PIN: 0.835 inch long
SOCKET, PIN
6-32 x 0.25 inch,
spacing, hex., - 6-32 x 0.25 x 0.562 inch long
6-32 x 0.25 inch,
spacer, 0.18
ASSEMBLY--TRIGGER (See A3 electrical list)
:
(not included
:
CONN:
x
0.188 inchlong
OD
ID
x
0.312 inch
6-32 x 0.50 inch, 100° csk,
:
PHs
PHs
6-32 x 1.25 inches,
x 0.986 long BRS
0.25
wllatch)
w/
subpanel)
A1
electrical list)
:
OD
x 0.25 inch long
PHs
FHS
@-
Mechanical Parts List-DC
FIGURE 1 EXPLODED (cont)
-
Fig.
&
Q
SHIELD, electrical
CIRCUIT BOARD ASSEMBLY--MAIN (See A2 electrical list)
circuit board assembly includes: CONTACT, SOCKET, pin connector SOCKET. integrated circuit. 16 pin SOCKET, integrated circuit, 14 pin SWITCH, push--RESET START SPACER, switch, brown SHIELD, electrical. cam switch
mounting hardware: (not included
SCREW. thread forming, 6-32 x 0.50 inch, FHS
WASHER, lock, internal, 0.092
WASHER, flat , 0.092 INSULATOR, circuit board
1
RESISTOR, variable
-
mounting hardware: (not included w/resistor)
1
NUT, hex., 0.25-32 x 0.312 inch
1
WASHER, lock, internal, 0.261
1
BRACKET, variable resistor mounting
electrical (See maintenance section for repair)
wlshield)
ID
ID x 0.140 inch
x 0.18 inch
OD
ID
x 0.40 inch
503
OD
OD
ACTUATOR ASSEMBLY--FUNCTION
actuator assembly includes: COVER
RING,
BEARING, front SPRING, flat, gold SPRING, flat, green SPRING, flat, red ROLLER, detent
DRUM
BEARING, rear
NUT, hex., 4-40 x 0.188 inch mounting hardware: (not included SCREW, sems, 4-40
ACTUATOR ASSEMBLY--CLOCK RATE
actuator assembly includes:
COVER
RING,
BEARING, front
SPRING. flat, gold SPRING, flat, green SPRING, flat, red ROLLER, d e
DRUM
BEARING, rear NUT, hex,, 4-40
mounting hardware: (not included
SCREW; sems, 4-40 x 0.25 inch
mounting hardware: (not included
SCREW, SCREW,
retaining
.
ASSEMBLY
x
0.312 inch, PHB
retaining
t
en
ASSEMBLY
thread forming, 6-20 x 0.312 inch,
thread forming, 6-20 x 0.312 inch,
t
x
0.188 inch
w/actuator assembly)
wlactuator assembly)
w/circuit board assembly)
PHs PHs
//
J
l~e~lace only with part bearing the same color code as the original part in your instrument.
Mechanical Parts List-DC
Fig.
&
Index Tektronix SerialIModel No.
No. Part No.
503
Eff
Disc
FIGURE 1 EXPLODED (cont)
Q
t
y
12345
/--,
Description
CIRCUIT BOARD ASSEMBLY--PROTECTION
(SEE
A4
EPL)
circuit board assembly includes: CLIP, fuse
mounting hardware
:
(not included wlcircuit board assembly) SCREW,'thread forming, 6-32 x 1.25 inches, PHs SPACER, sleeve,
FRAME
FRAME
SECTION, bottom, wlthreads SECTION, top
0.25
OD
x
0.750
inch long
SPRING, flat, ground (not shown)
4
WIRE, electrical, 3 wire ribbon, WIRE, electrical, WIRE, electrical, WIRE, electrical,
7
wire ribbon,
8
wire ribbon,
9
wire ribbon,
inches long
8.50
inches long
9.50
inches long
5.75
inches long
DC
503
UNIVERSAL
COUNTER
ACCESSORI ES
Fig.
&
Index Tektronix SerialIModel No.
No. Part No.
Eff
Disc
Q
t
y
1 2 3 4 5 Description
REPACKAGING
2-
070-141 1-00 1
MANUAL, instruction
DC
503
UNIVERSAL COUNTER
Fig.
&
lndex
No.
Tektronix
Part No.
SerialIModel No.
Eff
Disc
Q
t
y
12345 Description
CARTON ASSEMBLY
carton assembly includes:
FRAME END CAP, front END CAP, rear PAD
CARTON
DC
503
EFF
SN E060000-up
Page
1
of
2
I"--
\-/
REMOVE
ELECTRICAL PARTS
:
LIST
AND SCHEWTIC CORRECTION
Single 40
MHz
replaceable by
J-K
edge-triggered flip-flop,
SN74H102
r'
DC
503
DC
503 950A
EFF
SN B091650-up
EFF
SN B101730-up
ELECTRICAL PARTS LIST
CHANGE
TO:
DS275 150- 1001-00
Lamp,
CHANGE
LED,
2V
100
MA
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