Tektronix DAS-4100 Series Users Guide

D AS-4100 Series

USER’S GUIDE

DAS-4100 Series

User’s Guide

Revision A - October 1995

Part Number: 94540

New Contact Information

Keithley Instruments, Inc.

28775 Aurora Road

Cleveland, OH 44139

Technical Support: 1-888-KEITHLEY

Monday – Friday 8:00 a.m. to 5:00 p.m (EST)

Fax: [phone]

Visit our website at http://www.keithley.com

The information contained in this manual is believed to be accurate and reliable. However, Keithley
Instruments, Inc., assumes no responsibility for its use or for any infringements of patents or other rights
of third parties that may result from its use. No license is granted by implication or otherwise under any
patent rights of Keithley Instruments, Inc.

KEITHLEY INSTRUMENTS, INC., SHALL NO T BE LIABLE FOR ANY SPECIAL, INCIDENT AL,
OR CONSEQUENTIAL DAMAGES RELATED TO THE USE OF THIS PRODUCT. THIS
PRODUCT IS NOT DESIGNED WITH COMPONENTS OF A LEVEL OF RELIABILITY
SUITABLE FOR USE IN LIFE SUPPORT OR CRITICAL APPLICATIONS.

Refer to your Keithley Instruments license agreement for specific warranty and liability information.

MetraByte, Visual Test Extensions, and VTX are trademarks of Keithley Instruments, Inc. All other
brand and product names are trademarks or registered trademarks of their respective companies.

© Copyright Keithley Instruments, Inc., 1995.

All rights reserved. Reproduction or adaptation of any part of this documentation beyond that permitted
by Section 117 of the 1976 United States Copyright Act without permission of the Copyright owner is
unlawful.

Keithley MetraByte Division

Keithley Instruments, Inc.

440 Myles Standish Blvd. Taunton, MA 02780

FAX: [phone]

Telephone: [phone]

●

Preface

The DAS-4100 Series User’s Guide provides the information needed to
install and use DAS-4101 Series and D AS-4102 Series high-speed analog
input boards.

The manual is intended for data acquisition system designers, engineers,
technicians, scientists, and other users responsible for installing, setting
up, and connecting applications to DAS-4101 and D AS-4102 boards. It is
assumed that users are familiar with data acquisition principles, with their
computer, and with their particular application.

Throughout the manual, references to DAS-4100 Series boards apply to
all DAS-4101 and DAS-4102 boards. When a feature applies to a
particular board, that board’s name is used.

The DAS-4100 Series User’s Guide is organized as follows:

Chapter 1 provides an overview of the features of DAS-4100 Series

●

boards, including a description of supported software and accessories.
Chapter 2 provides a detailed technical description of the features of

●

DAS-4100 Series boards.
Chapter 3 describes how to unpack, install, set up, and connect

●

applications to DAS-4100 Series boards.
Chapter 4 describes how to use the scope and test program to test the

●

functions of DAS-4100 Series boards.

●

Chapter 5 provides troubleshooting information.

●

Appendix A lists the specifications for DAS-4100 Series boards.

●

Appendix B describes the Keithley Memory Manager.
Appendix C presents bandwidth charts for the supported input ranges.

●

vii

An index completes this manual.

Note:

Not all features of DAS-4100 Series boards are currently
supported by all software packages. Refer to the documentation provided
with your software package to determine which features are supported.

viii

Table of Contents

Preface

1

Overview

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

Supporting Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2

Accessories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3

Technical Reference

2

Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .2-3

Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3

Reference Voltage Range and Vernier Gain . . . . . . . . . . . . . .2-3

Static Conversion Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3

Noise Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

Dynamic Conversion Errors . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

Onboard Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

Buffer Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

Nonvolatile Memory (EEPROM). . . . . . . . . . . . . . . . . . .2-10

Host Computer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

I/O Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12

Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12

Pacer Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13

Internal Pacer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13

External Pacer Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14

Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14

Trigger Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-14

Software Trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15

Analog Trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15

Digital Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-16

iii

Trigger Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-16

Post-Trigger Acquisition . . . . . . . . . . . . . . . . . . . . . . . . .2-16

About-Trigger Acquisition . . . . . . . . . . . . . . . . . . . . . . . .2-20

Trigger Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23

Equivalent Time Sampling (ETS) Option . . . . . . . . . . . . . . . . .2-24

Peak Detector Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-27

3

Setup and Installation

Unpacking the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

Installing the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2

Installing the DAS-4100 Series Standard Software Package .3-2

Installing the ASO-4100 Software Package . . . . . . . . . . . . . .3-3

DOS Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3

Windows Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4

Configuring the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5

Creating a Configuration File . . . . . . . . . . . . . . . . . . . . . . . . .3-6

Setting Jumpers on the Board . . . . . . . . . . . . . . . . . . . . . . . . .3-9

Setting the Base I/O Address . . . . . . . . . . . . . . . . . . . . . . .3-9

Setting the Memory Address . . . . . . . . . . . . . . . . . . . . . .3-10

Setting the Interrupt Level . . . . . . . . . . . . . . . . . . . . . . . .3-12

Setting the Input Impedance for Analog Input Channels.3-12

Trigger and Clock Input Termination . . . . . . . . . . . . . . . . . .3-16

Analog Trigger Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19

Factory-Set Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20

Memory Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21

Adding a Ground Connection . . . . . . . . . . . . . . . . . . . . . . . .3-21

Installing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22

Attaching Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23

Scope and Test Program

4

Control Keys for D4100.EXE . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

Scope and Test Program Menus. . . . . . . . . . . . . . . . . . . . . . . . . .4-3

A/D Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

Display Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6

Gates Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8

Calibrating the DAS-4100 Series Board . . . . . . . . . . . . . . . . . . .4-9

Using Parameter Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10

iv

v

Troubleshooting

5

Identifying Symptoms and Possible Causes . . . . . . . . . . . . . . . .5-1

Testing Board and Host Computer. . . . . . . . . . . . . . . . . . . . . . . .5-3

Testing Accessory Slot and I/O Connections. . . . . . . . . . . . . . . .5-3

Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4

A

Specifications

B

Keithley Memory Manager

Installing and Setting Up the KMM. . . . . . . . . . . . . . . . . . . . . . B-2

Using KMMSETUP.EXE . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

Using a Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

Removing the KMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

Bandwidth Charts for Input Voltage Ranges

C

Index

List of Figures

Figure 2-1. DAS-4100 Series Functional Block Diagram . . . .2-1

Figure 2-2. Ideal Transfer Function of a 3-Bit ADC . . . . . . . .2-4

Figure 2-3. Non-Ideal Transfer Function of a 3-Bit ADC . . . .2-5

Figure 2-4. Host Computer Memory Address Space . . . . . . .2-11

Figure 2-5. Analog Trigger Modes. . . . . . . . . . . . . . . . . . . . .2-17

Figure 2-6. Post-Trigger Acquisition . . . . . . . . . . . . . . . . . . .2-18

Figure 2-7. Memory Usage in Post-Trigger Acquisition . . . .2-19

Figure 2-8. About-Trigger Acquisition . . . . . . . . . . . . . . . . .2-21

Figure 2-9. Memory Usage in About-Trigger Acquisition. . .2-22

Figure 2-10. Possible Trigger Position. . . . . . . . . . . . . . . . . . .2-23

Figure 2-11. Trigger Jitter with Synchronized Divider . . . . . .2-23

Figure 2-12. Equivalent Time Sampling (ETS) . . . . . . . . . . . .2-24

Figure 2-13. ETS Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26

Figure 3-1. Jumper Locations. . . . . . . . . . . . . . . . . . . . . . . . . .3-9

Figure 3-2. Analog Input Circuitry. . . . . . . . . . . . . . . . . . . . .3-13

Figure 3-3. Clock I/O Connector Circuitry . . . . . . . . . . . . . .3-17

Figure 3-4. Trigger I/O Connector Circuitry . . . . . . . . . . . . .3-18

Figure 3-5. Analog Trigger In Connector Circuitry . . . . . . . .3-19

Figure C-1. ±0.5 V Input Range (Gain Code 0) . . . . . . . . . . . C-1

Figure C-2. ±2 V Input Range (Gain Code 1). . . . . . . . . . . . . C-2

Figure C-3. ±2.5 V Input Range (Gain Code 2) . . . . . . . . . . . C-2

Figure C-4. ±4 V Input Range (Gain Code 3). . . . . . . . . . . . . C-3

Figure C-5. ±0.25 V Input Range (Gain Code 4) . . . . . . . . . . C-3

Figure C-6. ±1 V Input Range (Gain Code 5). . . . . . . . . . . . . C-4

Figure C-7. ±1.25 V Input Range (Gain Code 6) . . . . . . . . . . C-4

Figure C-8. ±2 V Input Range (Gain Code 7). . . . . . . . . . . . . C-5

Figure C-9. ±0.125 V Input Range (Gain Code 8) . . . . . . . . . C-5

Figure C-10. ±0.5 V Input Range (Gain Code 9) . . . . . . . . . . . C-6

Figure C-11. ±0.625 V Input Range (Gain Code 10) . . . . . . . . C-6

Figure C-12. ±1 V Input Range (Gain Code 11). . . . . . . . . . . . C-7

Figure C-13. ±0.1 V Input Range (Gain Code 12) . . . . . . . . . . C-7

Figure C-14. ±0.4 V Input Range (Gain Code 13) . . . . . . . . . . C-8

Figure C-15. ±0.5 V Input Range (Gain Code 14) . . . . . . . . . . C-8

Figure C-16. ±0.8 V Input Range (Gain Code 15) . . . . . . . . . . C-9

List of Tables

Table 2-1. Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . .2-8

Table 2-2. Available Conversion Rates Using

Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13

Table 3-1. Configuring DAS-4100 Series Boards . . . . . . . . .3-6

Table 3-2. Base I/O Address . . . . . . . . . . . . . . . . . . . . . . . . .3-10

Table 3-3. Memory Address . . . . . . . . . . . . . . . . . . . . . . . . .3-11

Table 3-4. Interrupt Level Selection . . . . . . . . . . . . . . . . . . .3-12

Table 3-5. Input Impedance for Analog Input Channels. . . .3-14

Table 3-6. Input Resistor Selection Chart. . . . . . . . . . . . . . .3-15

Table 3-7. TTL Clock In/Out Settings, J710. . . . . . . . . . . . .3-17

Table 3-8. TTL Trigger In/Out Settings, J711 . . . . . . . . . . .3-18

Table 3-9. Analog Trigger Input . . . . . . . . . . . . . . . . . . . . . .3-20

Table 3-10. Factory-Set Jumper Locations . . . . . . . . . . . . . . .3-20

Table 3-11. Factory-Set Memory Jumpers . . . . . . . . . . . . . . .3-21

Table 4-1. Control Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

Table 4-2. A/D Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

Table 4-3. Display Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

Table 4-4. Gates Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8

Table 5-1. Troubleshooting Information. . . . . . . . . . . . . . . . .5-1

Table A-1. DAS-4100 Series Specifications . . . . . . . . . . . . . A-1

vi

Table 2-1. Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . .2-8

Table 2-2. Available Conversion Rates Using

Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13

Table 3-1. Configuring DAS-4100 Series Boards . . . . . . . . .3-6

Table 3-2. Base I/O Address . . . . . . . . . . . . . . . . . . . . . . . . .3-10

Table 3-3. Memory Address . . . . . . . . . . . . . . . . . . . . . . . . .3-11

Table 3-4. Interrupt Level Selection . . . . . . . . . . . . . . . . . . .3-12

Table 3-5. Input Resistor Selection Chart. . . . . . . . . . . . . . .3-14

Table 3-6. TTL Clock In/Out Settings, J710. . . . . . . . . . . . .3-16

Table 3-7. TTL Trigger In/Out Settings, J711 . . . . . . . . . . .3-17

Table 3-8. Analog Trigger Input . . . . . . . . . . . . . . . . . . . . . .3-17

Table 3-9. Factory-Set Jumper Locations . . . . . . . . . . . . . . .3-18

Table 3-10. Factory-Set Memory Jumpers . . . . . . . . . . . . . . .3-19

Table 4-1. Control Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

Table 4-2. A/D Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

Table 4-3. Display Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

Table 4-4. Gates Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8

Table 5-1. Troubleshooting Information. . . . . . . . . . . . . . . . .5-1

Table A-1. DAS-4100 Series Specifications . . . . . . . . . . . . . A-1

Figure 2-1. DAS-4100 Series Functional Block Diagram . . . .2-1

Figure 2-2. Ideal Transfer Function of a 3-Bit ADC . . . . . . . .2-4

Figure 2-3. Non-Ideal Transfer Function of a 3-Bit ADC . . . .2-5

Figure 2-4. Host Computer Memory Address Space . . . . . . .2-11

Figure 2-5. Analog Trigger Modes. . . . . . . . . . . . . . . . . . . . .2-17

Figure 2-6. Post-Trigger Acquisition . . . . . . . . . . . . . . . . . . .2-18

Figure 2-7. Memory Usage in Post-Trigger Acquisition . . . .2-19

Figure 2-8. About-Trigger Acquisition . . . . . . . . . . . . . . . . .2-21

Figure 2-9. Memory Usage in About-Trigger Acquisition. . .2-22

Figure 2-10. Possible Trigger Position. . . . . . . . . . . . . . . . . . .2-23

Figure 2-11. Trigger Jitter with Synchronized Divider . . . . . .2-23

Figure 2-12. Equivalent Time Sampling (ETS) . . . . . . . . . . . .2-24

Figure 2-13. ETS Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26

Figure 3-1. Jumper Locations. . . . . . . . . . . . . . . . . . . . . . . . . .3-9

1

Overview

Features

DAS-4100 Series boards are analog input boards for IBM
compatible computers. This chapter describes the features of the
DAS-4100 Series boards, the software that supports them, and available
accessories.

Note:

supported by all software packages. Refer to the documentation provided
with your software package to determine which features are supported.

The major features of DAS-4100 Series boards are as follows:

●

●

●

Not all features of DAS-4100 Series boards are currently

The boards support high-speed data acquisition on one or two analog
input channels; two-channel operation is simultaneous.

The analog-to-digital converter (ADC) can digitize an analog input
signal at a rate of 64 Msamples/second with a resolution of 8 bits.

Digitized data is stored in an onboard, high-speed memory buffer to
ensure continuous acquisition of data. The host computer can
download data for further processing, display, and storage.



PC AT



or

A wide variety of trigger options allows you to tailor operation of the

●

board to the specific requirements of your application.
The boards can support, as an option, Equivalent Time Sampling

●

(ETS) for repetitive waveforms; ETS provides conversion rates of up
to 2.048 Gsamples/second.

Features 1-1

The boards are suitable for the following applications:

●

– Digital oscilloscopes
– Spectrum analysis
– Automated Test Equipment (ATE)
– Capturing transient data
– Ultrasonic inspection systems
– Measuring acoustic emissions
– Nondestructive testing
– Mass spectrometry
– Radar systems
– Time-domain reflectometry
– Pattern recognition
– Video digitization
– Acquisition of optical and laser signals

Supporting Software

The following software is available for operating DAS-4100 Series
boards:

DAS-4100 Series standard software package - This package, which

●

comes with the board, is provided on 3.5-inch high-density disks. The
package includes utility programs that allow you to configure, test,
and calibrate DAS-4100 Series boards.

●

ASO-4100 software package - The optional Advanced Software

Option for DAS-4100 Series boards is provided on 3.5-inch
high-density disks. The package includes function libraries for
writing application programs using Microsoft C/C++, Borland
C/C++, or Microsoft Visual Basic™ for Windows. The package also
includes support files, utility programs, and language-specific
example programs. Refer to the DAS-4100 Series Function Call

Driver User’s Guide for more information.

®

1-2 Overview

)

DAS-4100 Series configuration utility - The configuration utility

●

(CFG4100.EXE), provided as part of both the DAS-4100 Series
standard software package and the ASO-4100 software package, runs
under DOS and allows you to create or modify a configuration file.
The configuration file provides information about the board; this
information is used by the DAS-4100 Series Function Call Dri ver and
other software packages to perform the board’s operations. Refer to
page 3-6 for more information.

●

DAS-4100 Series scope and test program - The scope and test

program (D4100.EXE), provided as part of both the DAS-4100 Series
standard software package and the ASO-4100 software package, runs
under DOS and allows you to test the hardware features of a
DAS-4100 Series board, calibrate the analog input circuitry of the
board, and perform basic oscilloscope functions on the board. Refer
to Chapter 4 for more information.

Accessories

●

Visual Test Extensions



(VTX



- These optional custom controls
for Visual Basic for W indo ws help you write application programs for
DAS-4100 Series boards. Refer to the V isual T est Extensions

User’s



Guide and the VTX online help for more information.

VisualSCOPE - This optional software package runs under Windows

●

and emulates a stand-alone oscilloscope on your host computer. Refer
to the VisualSCOPE documentation for more information.

The following accessories are av ailable for use with the DAS-4100 Series
boards:

●

SDC-5600 Digital Signal Processing board - Uses the optional DSP

port on the DAS-4100 Series board to transfer data for digital signal
processing; available from Sonix Inc., 8700 Morrissette Drive,
Springfield, VA 22152 (703-440-0222).

●

Memory expansion accessories - Provide up to 128M bytes of

additional buffer memory for storing data; refer to the Keithley
MetraByte catalog or contact your local sales office for information
on obtaining these accessories.

Accessories 1-3

2

Technical Reference

A functional block diagram of the DAS-4100 Series board is shown in
Figure 2-1.

Figure 2-1. DAS-4100 Series Functional Block Diagram

2-1

The analog signal is applied to one of the two input connectors (Channel
A or Channel B). You can use software-selectable AC or DC coupling,
and 50

Ω

or 1M

Ω

input impedances. The input signal is buf fered and then
fed into a programmable attenuator stage, followed by a programmable
gain stage, which drives the input of the analog-to-digital (A/D)
converter.

A programmable offset supplied by a digital-to-analog con verter (DAC1)
is added to the signal to shift it into the correct input voltage range of the
ADC. The overall gain and attenuation of the analog signal path are
programmable in coarse, discrete steps. To provide a final input
sensitivity programmable in very small increments, a second DAC
(DAC2) feeds a finely programmable voltage into the ADC as a reference
signal. The ADC compares the analog signal at its input to the applied
reference voltage and generates an 8-bit number proportional to the ratio
of these two voltages at the rate of the input clock.

The two DACs used together provide an accurate compensation for all
device tolerances in the analog input circuitry . The settings of these D A Cs
are stored as calibration data for various input voltage ranges in
nonvolatile memory.

The clock signal at the Clock I/O connector can be generated either
externally or internally. The internal clock signal is routed through a
programmable divider to the ADC and the counter logic.

The trigger signal at the Trigger I/O connector is an input signal when an
externally generated digital trigger signal is applied or an output signal
when a software or analog trigger event occurs.

An analog signal in the range of

16 to +16 V may be applied to the

−

Analog Trigger In connector. Operating under software control, the board
can be programmed to respond to either the rising or falling edge of the
trigger signal.

The remainder of this chapter describes the analog input features of
DAS-4100 Series boards in more detail.

2-2 Technical Reference

Analog-to-Digital Converter (ADC)

The ADC on DAS-4100 Series boards is a 64 Msamples/second, 8-bit
flash converter. This section describes the data format, reference voltage
range and vernier gain, static conversion errors, noise gain, and dynamic
conversion errors of the ADC.

Data Format

The ADC outputs data in a twos complement data format (
where
positive full scale.

128 corresponds to negative full scale and +127 corresponds to

−

Reference Voltage Range and Vernier Gain

The reference voltage range of the ADC is typically
nominal value of
input voltage range of the ADC. You specify a reference v oltage from 0 V
to

2.1 V by programming the gain DAC (DAC2). Decreasing the

−

magnitude of the reference voltage increases the overall gain, since the
full-scale input voltage range of the ADC becomes smaller. This allows
you to moderately increase the overall gain without any degradation in
input bandwidth; however, note that the existing nonlinearities of the
ADC have more impact on the accuracy of the digitized waveform.

−

2.0 V. The reference voltage determines the full-scale

Static Conversion Errors

The ADC produces one of 256 discrete output codes for an analog input
voltage, resulting in a stair-step shaped transfer function. Ideally, all steps
of this transfer function have the same width (the full-scale input voltage
V

divided by the number of steps 2

fs

ADC in bits). For DAS-4100 Series boards, the resolution is eight bits
and the ADC full-scale input voltage range is ±4 V; therefore, the
resulting step width is 31.25 mV. Figure 2-2 illustrates a 3-bit ADC
example.

N

1, where N is the resolution of the

−

−

128 to +127)

−

2.0 V to 0 V with a

Analog-to-Digital Converter (ADC) 2-3

Output
codes,
binary

Input voltage

Figure 2-2. Ideal Transfer Function of a 3-Bit ADC

Full scale

The transfer curve of a device with no conversion error at all would be a
straight line. Since the ADC transforms a continuous input voltage into
discrete codes, as expressed by the stair-step function, it has an inherent
conversion error. The magnitude of this error depends on the size of the
steps and on the number of bits of the ADC. The theoretical
signal-to-noise ratio (SNR) in dB of an ideal ADC with a full-scale input
signal is equal to (6.02 * N + 1.76) dB, where N is the resolution of the
ADC in bits. For DAS-4100 Series boards (8-bit ADC), the SNR is

49.92 dB. If a smaller input signal V
theoretical SNR is decreased by 20 * log(V

is applied to the ADC, the

in

/V

) dB.

fs

in

The transfer function of a real ADC deviates somewhat from the ideal
curve in Figure 2-2. The deviation of a transfer function from the ideal
curve is specified by integral nonlinearity and differential nonlinearity, as
shown in Figure 2-3.

2-4 Technical Reference

Output
codes,
binary

Input voltage

Figure 2-3. Non-Ideal Transfer Function of a 3-Bit ADC

Full scale

The width of the two steps producing output codes 2 and 3 is one-half the
ideal value, and the width of the next two steps is 1.5 times the ideal
width. In this case, the differential nonlinearity is ±0.5 LSB and the
maximum deviation from the ideal straight line (integral nonlinearity) is
±1.5 LSB. By shifting the straight reference line (adjusting the input
offset), the "best fit" integral nonlinearity would be ±0.75 LSB.

The ADC of DAS-4100 Series boards is specified with an integral and
differential nonlinearity of ±0.6 LSB (no missing codes). This is a
guaranteed worst-case value; the actual nonlinearity is lower. Assuming
the worst distribution of step widths still satisfying the guaranteed
nonlinearity (all even steps 0.4 LSBs wide and all odd steps 1.6 LSBs
wide), the SNR is reduced to approximately 46.3 dB. The actual value is
closer to the theoretical 49.9 dB, typically 48 dB. This value is relative to
a full-scale input signal. The noise voltage due to the conversion into
discrete amplitude values has a constant rms amplitude of 0.29 LSB.

Analog-to-Digital Converter (ADC) 2-5

Noise Gain

The small-signal gain of the ADC can be directly deri v ed from its transfer
curve: the steeper the slope, the higher the gain. Since the transfer
function is a stair-step function, most of the input voltage range has a
small-signal gain of zero (horizontal section of the curve) interspersed
with small parts of very high small-signal gain at the transition between
two output codes. This leads to an offset-dependent amplification or
attenuation of very small input signals like noise.

The offset voltage at the ADC input can be programmed in very fine
steps; in most ranges, each step can be less than one LSB. The input noise
is less than one LSB in the less sensitive input voltage ranges, but can be
made to appear with a full one LSB amplitude or to completely disappear
by finely shifting the offset voltage. This phenomenon directly results
from the noise voltage, which in this case is comparable to the actual
input noise voltage.

Dynamic Conversion Errors

The ADC samples the analog input v oltage at regular interv als, con verting
the time-continuous input signal into a time-discrete output signal. This
introduces errors in the conversion process if the input signal varies over
time. The pacer clock causes the ADC to sample its input signal at regular
intervals; however, small deviations from this regular schedule introduce
an amplitude error if the input signal changes between the correct time
and the actual time the sample is taken. This timing uncertainty is called
aperture jitter.

Other sources of dynamic distortion are unequal frequency responses and
delay times of the individual comparators inside the flash con verter . Noise
on the clock lines also contributes to the dynamic errors.

The error introduced by these types of distortion depends on the slew rate
of the input signal at the ADC input. The effective number of bits of
resolution (ENOB) specifies the resolution of an ideal converter
producing the observed output signal with the same input signal. With a
full-scale input signal of 1.23 MHz, DAS-4100 Series boards have an
ENOB of 7.5 bits.

2-6 Technical Reference

Channels

The slew rate dependency of the sampling accuracy has the effect that the
peak of a high-frequency input signal is sampled much more accurately
than the regions with the largest slew rates. This makes over-sampling
with very high effective sampling rates a useful tool for accurate peak
amplitude measurement. For these types of applications, the specification
of dynamic performance in ENOBs is not applicable.

DAS-4101 Series boards have a single analog input. DAS-4102 Series
boards can acquire data from either analog input (Channel A or B), or
from both channels simultaneously. The software is used to specify the
channel(s).

The analog input channels are terminated with a 50

Ω

socketed resistor.
You can use the configuration file to disconnect this resistor by operating
a relay; in this case, the input resistance is 1M
resistor to select any input impedance between 50

. You can also replace the

Ω

and 1 M

Ω

. Refer to

Ω

page 3-12 for more information.

Note:

To use a 10:1 oscilloscope probe, you must select the 1 M

Ω

input

resistance under software control.

Exceeding the maximum input voltage causes distortion of the sampled
waveform. If you select an input impedance of 50

Ω

, the input voltage

should not exceed 11.3 V peak-to-peak.

Channels 2-7

Input Ranges

DAS-4100 Series boards currently support 16 bipolar factory-calibrated
analog input ranges. Through software, you specify the analog input
range and the gain of the analog input channel.

Table 2-1 lists the analog input ranges supported by DAS-4100 Series
boards and their corresponding gain codes. The gain code is used in
software to determine the range. The choice of gain code affects the
bandwidth; refer to Appendix C for more information.

Table 2-1. Analog Input Ranges

Input Range Gain Code Bandwidth ( − 3dB) DC to:

±100 mV 12 100 MHz
±125 mV 8 110 MHz
±250 mV 4 100 MHz
±400 mV 13 140 MHz
±0.5 V 0 100 MHz
±0.5 V 9 160 MHz
±0.5 V 14 150 MHz
±0.625 V 10 160 MHz
±0.8 V 15 160 MHz
±1 V 5 210 MHz
±1 V 11 170 MHz
±1.25 V 6 220 MHz
±2 V 1 250 MHz
±2 V 7 230 MHz
±2.5 V 2 250 MHz
±4 V 3 280 MHz

2-8 Technical Reference

Memory

This section describes memory on the DAS-4100 Series board and
memory on the host computer.

Onboard Memory

DAS-4100 Series boards contain buffer memory for storing data and
nonvolatile memory for storing calibration values.

Buffer Memory

Since the conversion rate of DAS-4100 Series boards is too high to be
directly processed by the host computer, the digitized data is stored in an
onboard memory buffer. Groups of two samples from the ADC are
packed together and written to the memory buffer as one block.

The DAS-4101 contains 64K, 256K, 1M, or 2Mbytes of onboard
memory; the DAS-4102 contains 64K, 256K, or 1Mbytes. If you require
larger memory sizes, you can use up to eight memory expansion
accessories with up to 16M bytes of memory each to provide a maximum
of 128M bytes of memory. Since only one expansion accessory can be
active at any given time, the maximum length of a single data acquisition
is 16,777,216 samples. Intervention by the host computer is necessary to
switch between expansion accessories. You must specify that you are
using a memory expansion accessory by setting a jumper on the board;
jumper information is supplied with the memory expansion accessory.

Whenever a DAS-4100 Series board is idle, the host computer can access
the buffer memory. The computer reads the data to download it into its
own main memory and process it. For diagnostic purposes, the host
computer can also write to the buffer memory; this allows testing of the
hardware and easier debugging of application algorithms.

Memory 2-9

Nonvolatile Memory (EEPROM)

DAS-4100 Series boards contains 128 16-bit registers of Electrically
Erasable and Programmable Read-Only Memory (EEPROM). Unlike the
onboard buffer memory, the EEPROM does not lose its contents when
power to the board is removed. Most of the EEPROM holds calibration
settings for the four DACs used for fine control of analog offset and gain.

The EEPROM also holds a linearization table for the ETS delay, a copy of
the board's serial number, a CRC check code, and some housekeeping
information.

Host Computer Memory

DAS-4100 Series boards require part of both the host computer I/O
address space and the host computer memory address space.

I/O Address Space

DAS-4100 Series boards require sixteen bytes in the I/O address space of
the host computer.

You select the base address for the I/O address space by setting jumpers
on the board; refer to page 3-9 for information.

Memory Address Space

The memory address space of the host computer is used for reading the
acquired data from the DAS-4100 Series onboard buffer memory or
expansion accessory memory and for loading the counters. The host
computer accesses the onboard memory using the decoding logic on the
DAS-4100; onboard buf fer memory is mapped to the host computer upper
memory. The host computer accesses the memory of an expansion
accessory using the bus interface of the memory expansion accessory;
refer to the documentation provided with the expansion accessory for
more information.

Figure 2-4 illustrates the memory address space of a host computer.

2-10 Technical Reference

Figure 2-4. Host Computer Memory Address Space

The host computer reads from or writes to the onboard memory by using
banks of 16K bytes. The 16K byte area acts as a window through which
part of the memory on the DAS-4100 Series board is accessed. One of
these banks at a time is selected to appear in this window.

You select the base address for the memory address space by setting
jumpers on the board; refer to page 3-11 for information.

Memory 2-11

Bus Interface

The bus interface allows the host computer to initialize all onboard
parameters, read from and write to onboard memory, set the counters,
trigger the board, and obtain status information.

The bus interface uses two distinct address spaces of the host computer: a
16 byte segment in the I/O address space for control information and a
16K byte segment in the memory address space for data exchange. Refer
to page 2-10 for more information.

An interrupt can be generated to signal the host computer at the end of a
data acquisition or peak detection. You select the interrupt lev el by setting
jumpers on the board. Refer to page 3-12 for more information.

Counters

During power-up and whenever the RESET button is pressed, the host
computer activates its RESET signal, and the internal logic of the board is
forced into a known, inactive state. Since the settings of the DACs are
unknown, all reference voltages in the analog input circuitry are held at a
value close to 0 V. The first write to the board in the I/O address space
releases these voltages to their normal levels.

DAS-4100 Series boards use the following counters:

●

Start counter - Determines the location in buffer memory where the

currently sampled data is stored; it is preset by the host computer with
the starting address of the next data acquisition.

●

Length counter - Determines the total number of samples acquired.

When the length counter counts down to zero, the data acquisition
ends.

●

Post-trigger counter - Determines the number of samples to delay

the start of a data acquisition after a valid trigger has been accepted.
The post-trigger delay is programmable from 0 to 16,777,216
samples in 2-byte increments.

2-12 Technical Reference

The host computer loads the counters before the start of a data acquisition
operation or the start of the peak detector.

Pacer Clocks

Through software, you select either an internal or an external pacer clock
to determine when each A/D conversion is initiated.

Internal Pacer Clock

The internal pacer clock is the onboard 64 MHz crystal oscillator. The
clock signal is fed through a driver to the Clock I/O connector.

You can divide the frequency of the internal pacer clock by 1, 2, 4, 8, 16,
32, 64, or 128, as shown in Table 2-2.

Table 2-2. Available Conversion Rates Using Internal Clock

Sample

Divider Conversion Rate

256 64.0 Msamples/second 15.625 ns
512 32.0 Msamples/second 31.25 ns
1,024 16.0 Msamples/second 62.5 ns
2,048 8.0 Msamples/second 125 ns
4,096 4.0 Msamples/second 250 ns
8,192 2.0 Msamples/second 500 ns
16,384 1.0 Msamples/second 1000 ns
32,768 0.5 Msamples/second 2000 ns

Period

Pacer Clocks 2-13

You can also use the Clock I/O connector as an output. When used as an
output, the Clock I/O connector can provide a TTL-level output signal
(0 to 5 V) of the undi vided clock frequenc y to a doubly terminated (25
load.

External Pacer Clock

An external pacer clock is an externally generated clock signal of any
frequency up to 64 MHz applied to the Clock I/O connector. When you
start an analog input operation, the board is armed. At the ne xt rising edge
(and at every subsequent rising edge of the external pacer clock), a
conversion is initiated.

Note:

T o a v oid reflections on the connecting cable, you can terminate the
Clock I/O connector input by inserting a jumper into jumper block J700;
refer to page 3-16 for information.

Ω

)

Triggers

A trigger is an event that determines when a DAS-4100 Series board can
respond to either an internal or an external pacer clock. Depending on the
type of acquisition and setup parameters, the trigger event can occur
before, during, or after the actual sampling of data. The trigger signal can
originate from a variety of sources.

This section describes trigger sources, types of trigger acquisition, and
trigger synchronization on DAS-4100 Series boards.

Trigger Sources

DAS-4100 Series boards support software triggers, analog triggers, and
digital triggers. These trigger sources are described in the following
sections.

2-14 Technical Reference

Software T rigger

Analog T rigger

A software trigger event occurs when a particular instruction is executed
by the host computer.

When you use a software trigger, the Trigger I/O connector acts as an
output. When the trigger event occurs, either a rising or a falling edge is
output on the Trigger I/O connector. The edge polarity depends on the
internal pacer clock and can be used to start an external process, such as
pulsing an ultrasonic transducer. At the end of the data acquisition, the
signal on the Trigger I/O connector returns to its inactive state.

An analog trigger (or threshold trigger) event occurs when one of the
following conditions is met by an analog input signal:

●

The analog input signal changes from a voltage that is less than the
trigger level (threshold) to a voltage that is greater than the trigger
level (positive-edge trigger).

●

The analog input signal changes from a voltage that is greater than
the trigger level (threshold) to a voltage that is less than the trigger
level (negative-edge trigger).

●

The analog input signal is already above the trigger level at the time
the board becomes ready to accept a trigger (positive-level trigger).

The analog input signal is already below the trigger level at the time

●

the board becomes ready to accept a trigger (negative-level trigger).

DAS-4100 Series boards can be triggered by the analog input signal on
Channel A, on Channel B (DAS-4102 Series boards), or by a signal
applied to the Analog Trigger Input. To trigger on Channel A (or B), you
can use software to program the threshold in 256 steps covering the
software-selected input range. To trigger using the Analog Trigger Input,
you can program the threshold in 256 steps from

16 to +15.875 V.

−

When you use an analog trigger, the Trigger I/O connector acts as an
output. When the trigger event occurs, either a rising or a falling edge is
output on the Trigger I/O connector. A rising edge signal is output if the
trigger polarity is positive; a falling edge signal is output if the trigger
polarity is negative. At the end of the data acquisition, the signal on the
Trigger I/O connector returns to its inactive state.

Triggers 2-15