Tektronix AMM2 User manual

AMM2

Master Analog Measurement Module

The AMM2 Analog Measurement Module combines three important Series 500 func­tions into a single module. First, the AMM2 functions as a standard analog input
module, and wiu accept up to 16 single-ended or eight differential analog input signals.
It contains signal conditioning and switching circuitry for these channels. Second, the
AMM2 selects and conditions analog signals from other analog input modules in a
Series 500. Last, the AMM2 serves as a 16-bit A/D converter for its own analog input
channels, as well as any other analog signals which have been processed by the global
select/conditioning circuitry. After analog conditioning, signals are routed to the A/D
converter section of the module for the analog-to-digital conversion process.

Input signals are applied to the AMM2’s analog input channels through on-card quick­connect screw terminals. The AMM2 has a total of 16 local single-ended, or eight dif­ferential inputs. The input configuration is controlled through software, rather than
with hardware switches. These analog input channels can be conditioned with pro­grammable local gains of either xl or x10.

Global conditioning consists of a high-speed software-controlled gain amplifier with
programmable xl, x2, x5 and x10 gain values. All analog inputs connected to the Series

500 pass through the global circuitry, whether the signals originate on the AMM2 or

some other analog input module. Therefore, these gain values can be applied to any
analog input in the system.

For A/D conversion, the AMM2 uses a l&bit successive approximation converter. A
maximum conversion time of only 20psec allows sampling rates as high as 5OkHz. To
maximize resolution, the AMM2 has O-XIV and &lOV A/D converter ranges which are
software selectable.

CAUTION: Always tum off the system power before installing or removing modules.
To minimize the possibility of EM1 radiation, always operate the system with the top
cover in place and properly secured.

The Ah4M2 is designed to be used only in slot 1 of the 500-series system baseboard. To
install the module, first remove the baseboard top cover and install the module in slot 1
with the component side facing the power supply.

Document Number: 501-912-01 Rev. C

AMM2-1

AMM2-2

Figure 1. AMM2 Component Layout

High-speed Acquisition Mode with AMMP and ANINQ
(SOFT500 and QUICK500)

The ANINQ command can operate the AMM2 module in a high-speed “auto-acquire”
mode at an aggregate throughput rate of up to 5OkHz. Auto-acquire applies to single or
multiple channels. For multiple channels, the per-channel scan rate equals 5OkHz divid­ed by the number of channels.

The analog input modules AIM2 and AIM3 can also provide up to 5OkHz throughput
when these modules are used in a system containing an AMM2.

To operate the AMM2 in auto-acquire mode, you must satisfy the following
requirements:

1. The analog input channels sampled by ANINQ may be on an AMM2, AIM2, or
AIM3.

2. All the channels sampled by the specific ANINQ command must be on one module.

3. If the input channels are on an AlM3, the AIM3 must be set to xl gain.

4. The AMM2’s input filter must be set to lOOkI&.

If any of these conditions cannot be met, the speed of the ANINQ command will revert
to the speed of an ANIN command. Under these circumstances, it is better to use
ANIN in order to take advantage of foreground/background operating mode.

NOTE: The ANINQ command in Soft500 and Quick500 has been optimized for auto­acquire (5OkHz) operation with the AMM2. If you attempt auto-acquire mode with
BASIC’s PEEK/POKE, or the memory READ&VRlTE commands of other languages, you
may receive incorrect data. If you do not use Soft500 or Quick500, Keithley suggests
that you run the AMM2 only in “regular acquisition mode”. This mode is described
under the heading “SELECT ACQUISITION MODE” later in this manual.

Self-calibration During “CALL INIT” (SOFT500 and QUICK500)

The AMM2 module performs a self-calibration each time a CALL INIT is issued.

Soft500 executes a CALL INIT each time it is run in the non-resident mode, or just
once when it is loaded into memory in resident mode. Quick500 executes a CALL INIT.
each time it is loaded under the QuickBASIC environment or with the “QRUN” option,
or just once when it is made resident with the “QLOAD” option. Therefore, you need
not issue a separate CALL INIT specifically to calibrate the Ah&I2.

Soft500 and Quick500 will expect an AMM2 in the system if the configuration file

(CONFIGTBL) shows an AMM2 in slot 1. If the software cannot complete the calibra­tion, it will issue an error message such as “Unable to calibrate A/D module”. If this oc­curs, check that:

1. The Series 500 is turned on.

2. The cable between Series 500 and IBIN interface is connected.

3. An AMM2 is mounted in slot 1 of the Series 500.

AMM2-3

Connection and Operation

Signal Connection
The AMM2 can be programmed for either differential or single-ended local input con-

figurations. These local input signals are applied to screw terminals located toward the
rear portion of the AMM2. Single-ended and differential inputs use the same screw
terminals.

The channel numbers are shown in Figure 1. Figure 2 shows typical connections for
channels 0 through 7 in differential mode. For differential mode, connect the high (+)

side of an input signal to the (+) terminal, and the low (-) side of the signal to the
corresponding (-) terminal. When the AMM2 is configured for single-ended input,
connect the high (+) side of the input signal to one of the terminals 0 through 15, and
the low (-) side to the module ground at either end of the terminal strip. In Figure
the numbers listed in parentheses above the lower connector are the single-ended local
channels 9 through 15.

.’ ’ ’ ’ ‘Jl” ’ ’ ’ ’

eeeeeeeee@

GND 7+ 6+ 5+ 4+ 3+ 2+ l+ Cj+GND

2,

Measured

Voltage

” Shield

(Optional)

Series 500

Chassis Ground

t

I

1

Figure 2. Typical Differential Connection (Channel 0 Shown)

CAUTION: The AMM2 inputs are non-isolated. In single-ended mode, one side of the
input is connected to power line ground. Any signal connected to the AMM2 must
also be referenced to power line ground, or module or system damage may occur Also
note that inaccuracies on other channels may result. When used in differential mode,
the AMM2 local inputs must both be within flOV of module ground for proper
operation. If either signal exceeds k3OV module damage may result.

I

In many situations, shielded cable may be required to minimize EMI radiation, or to
keep noise to a minimum. If shielded cable is used, connect the shield to ground only,
and do not use the shield as a signal-carrying lead. Usually, a module ground terminal
should be used, but in some cases better results may be obtained by using one of the

baseboard ground posts. Use the configuration that results in the lowest noise.

For shielding to be effective, the shield must contain both high and low signal wires,
and must not carry any other signals. If a number of AMM2 signal input lines are
shielded, all shields should be connected to the same ground terminal.

Signal Conditioning

Figure 3 shows a simplified block diagram of the AMM2. The module is divided into
six general sections: a local multiplexer, a local programmable gain amplifier, a global
multiplexer, a global programmable gain amplifier, a programmable low-pass filter, and
a 16-bit A/D converter.

Local input signals from channels 0 to 15 are applied to the local multiplexer for selec­tion. At any given time, only one channel will be selected, as determined by the
SELECT CHANN-S L command (covered later in this section). The signal from the
selected channel is then routed through a local programmable gain amplifier to the

global multiplexer for further signal selection and conditioning.

The globalmultiplexer se!ects a sing!e signal from among the 10 s!ots in the system. In
this manner, signals from any of the 10 slots can be selected by software. The global
multiplexer is controlled by the SELECT SLOT command, discussed later in this
section.

After the signal is selected, the Global PGA applies software-selectable gains of xl, x2,
x5, or x10. The signal finally passes through a one-pole filter with software selectable

-3db frequencies of either lOOkHz or 2kHz. When this signal conditioning process is
complete, the signal is routed to the 16-bit A/D converter for digitization. After the con­version process, digital data representing the applied signal travels via the baseboard
and interface card to the host computer.

Local
Programmable
Gain Amplifer

16 Single-ended or

8 Differential

inputs

(input Mode

Programmably

Selected)

Programmable

Locd

Channel

(Xl orX10)

-7

\L

Analog hyd.S

From Other

Slots e-

Global

Programmable

Gain Amplifier

(Xl .XZ,X6,OR

16Bl-r E

AlDAND =

SM-

f

Programmable

Filter

(1OOkHz OR

2kHz)

Figure 3. AMM2 Signal Conditioning

Input Filtering
Noise introduced into the input signal can corrupt the accuracy of the measurement.

Such noise will usually be seen as an unsteady reading, or, in some cases, as a con­stant offset. In the former case, the effects of noise will usually be quite obvious, but
may not be noticeable in the steady-state offset situation.

Frequently, noise is introduced into the signal from 50 to 6OHz power sources. In many
cases, noise can be attenuated by shielding or relocating the input signal lines, as
discussed earlier. It may also be possible to reject unwanted 60Hz noise by using the

AMM2-5

AMM2 in differential mode. Since the 6OHz noise may also be present on the low side
of the signal, the differential amplifier will reject the common signal. In more difficult
situations, however, it may be necessary to filter the input signal to achieve the
necessary noise reduction. This is especially important to make good use of 16-bit A/D
resolution.

When noise is a problem, a single-pole low-pass filter like the one shown in Figure 4
can be connected between the input signal and the corresponding AMM2 channel.
Note that the filter is made up of a single capacitor and resistor with the capacitor con­nected between the AMM2 channel input terminal and the module ground terminal.
The resistor is then placed in series with the high input signal lead.

From Signal

To AMM2 Input

Figure 4. Input Filtering

A common reference point for a simple filter like the one in Figure 4 is the -3dB or
half-power point, which is given as follows:

f-m =

where f is in Hz, C is in farads, R is in ohms. Above this frequency, filter response will
roll off (decrease) at a rate of -20dB per decade. Thus, each time the frequency in­creases by a factor of 10, filter output voltage decreases by a factor of 10 (-20dB).

Although such filtering can quiet down a noisy signal, there is a trade-off in the form
of slower response. This response time may be important in the case of a rapidly
changing input signal. For the filter in Figure 4, the response time to 1% of final value
is 4.6RC, while the response times to 0.1% and 0.01% of fmal value are 6.9RC and

9.2RC, respectively.

1/(27rRC)

AMM2-6

As an example, assume that 10 counts of 6OHz noise is present in the input signal. To
reduce the noise to one count, an attenuation factor of 10 (-20dB) at 6OHz will be
necessary. Thus, the filter should have a -3dB point of 6Hz.

To determine the relative RC values, the above equations can be rearranged to solve for
either R or C. If we wish to choose a nominal capacitor value and then solve for the
resistance, we have:

R = 1/(2&f-,,,)

Choosing a nominal value of 2pF for C, the necessary resistance is:

R = 1427r x (2 x 10”) x 6Hz)

R = 13.263k

The resulting response times with these R and C values would be:

t(l%) =
t(O.l%) = 6.9RC = 183ms
t(O.Ol%) = 9.2RC = 244ms

4.6RC = 122ms

Current-to-Voltage Conversion
AMM2 local inputs are designed to accept voltages in the range of &lOV. Thus, the

AMM2 can be directly connected to many signal sources. Some transducers and in­strumentation, however, provide current outputs that must be converted into voltages in
order to be measured through an AMM2 input channel.

When connecting current inputs to the AMM2, a resistor should be installed across the
input to make the necessary current-to-voltage conversion. J4, J5, and J6 provide loca­tions for installing these resistors on the AMh42. Refer to the circuit schematic and

board layout diagrams for header information.

The value of the resistor can be determined from Ohms law as follows:

R = E/I

Where R is the resistance in ohms, E is the maximum desired voltage in volts (usually

the upper range limit of the AID converter), and I is the maximum anticipated current

in amps.

As an example, assume the AID converter range is zero to +lOV and that the expected
current lies in the range of four to 401~~4. The required resistance is:

R

= 10/0.04

R = 250

Thus, a 25OQ resistor should be installed across the input of the channel in question
(note that a 2508 value is required when using Soft500 engineering units conversion).
Since current measurement accuracy is directly related to the accuracy of the resistor,
use the smallest tolerance resistor available (typically 0.1%). Suitable 25OQ precision
resistors can be purchased from Dale Resistors, (PIN RN55E2500B), or from Keithley
(PIN 500-RES-250).

AMh42-7

Analog-to-Digital Converter Timing
When programming high-speed sampling sequences, certain timing constraints concern-

ing the AID conversion cycle should be observed. Depending on the AMM2’s acquire
mode, the scenario for receiving converted values from the A/D is very different. Refer
to the discussion of the acquire modes below for specific instruction on how to process
analog signals.

To increase system throughput, data latches have been provided on the AMM2, making
data from the last conversion available while the converter is busy processing another
reading. The data is refreshed (updated) every time a conversion has been completed.

External Trigger Operation

The AMM2 has the capability of triggering an acquisition from an external TTLlevel
source. The jumper on the Ah4M2 (J3) dictates the triggering source. The external trig­ger can only be used in 5OkHz auto acquire mode which is explained below in the SET
ACQUISITION MODE command discussion.

When the AMM2 is in 5OkHz auto acquire mode, the trigger source can be set to either
external or internal by the J3 jumper. When set for internal triggering, the AMh42 con­tinuously converts analog signals as described below in the SET ACQUISITION MODE
command discussion. When the J3 jumper is removed, a TI’Llevel signal can be attach­ed to pin 2 of the jumper header. A low level applied to pin 2 will enable the con­tinuous conversion process, a high level applied to pin 2 will suspend the continuous
conversion process. In either case, the application program must synchronize itself to
the conversion process by polling the conversion status as explained in the SELECT AC­QUISITION MODE command discussion.

The pin configuration of the jumper header is as follows:
pin 1 +5v

pin 2
pin 3

The J3 jumper should be across pins 2 and 3 for internal trigger operation. The jumper
should be removed and the external trigger source should be connected to pin 2 for ex­ternal trigger operation

Commands

Table 1 summarizes the commands used with the AMM2. Note that several commands

share the CMDA and CMDB locations. Some commands use only selected bits in the
command byte, others are differentiated by whether a read or write operation is
performed.

trigger input
OV (ground)

Table 1. Commands Used with the AMM2
Command

SELECT CHANNEL
SELECT LOCAL CHANNEL MODE
SELECT LOCAL GAIN
SELECT ACQUISITION MODE
SELECT FILTER

Address Signal Line
xxx80

xxx80
xxx80
x=80

xxx80
SELECT SLOT xxx81
SELECT CMDA READ MODE

xxx81
SELECT RANGE xxx81
SELECT GLOBAL GAIN

XXX81

RESET AND RECAL XXX9A
A/D LOW DATA! xxx80
A/D STATUS* xxx80
A/D HIGH DATA xxx81
A/D START xxx9B
EOC (end-of-conversion) STATUS

XXX9B

CMDA (Write)
CMDA (Write)
CMDA (Write)
CMDA (Write)
CMDA (Write)
CMDB (Write)
CMDB (Write)
CMDB (Write)
CMDB (Write)
CMDC (Write)
CMDA (Read)
CMDA (Read)
CMDB (Read)
CMDD (Write)
CMDD (Read)

Bits Used
DO-D3

D4
D5
D6
D7
DO-D3
D4
D5
D6-D7
ALL
ALL
ALL
ALL
ALL
ALL

* The information read from CMDA is selected by the SELECT CMDA READ MODE

command. Refer to the sections below for the full description of their operations.

The “xxx” in the address column signifies the three hexidecimal digits that make up the
base hardware address which is either switch selected or programmed on the interface
card. The suggested address is &HCFFBO, so “xxx” = “&HCFF”.

Select Channel, Local Gain, Filter, Acquisition Mode, and Channel Mode.

D5 D4 D3 D21 Dl DO

I

Channel Select: SE (O-15), DIFF (O-7)
Channel Mode: Single-ended (l), DIFF (0)
Local Gain: Xl (0), X10 (1)
ACQ Mode: 50kHz Auto Acquire (l), Regular Acquire (0)
Filter Mode: 1 OOkHz (0), 2kHz (1)

Figure 5. CMDA Write Format (Address xxx80)

AMM2-9

Select Slot, Range, Global Gain, and CMDA Read Mode.

D71D6 1 D5 1 D4jD3 D2( Di ID0

Byte Format

Select Slot: (O-15)

CMDA Read Mode: A/D Status

Select

Range: -1 OV +l OV

Select Global Gain: Xl (0), X2 (l), X5 (2), X10 (3)

(0),

Low Data

(l), 0 Cl OV (0)

(1)

Figure 6. CMDB Write Format (Address xxx81)

SELECT CHANNEL
Location: xxx80
The SELECT. CHANNEL command is used to control the local signal multiplexer on the

AMM2, thus determinin

g which of the local input channels
sion. This command affects only those signals connected to the AMM2 local inputs,
and does not affect input channels connected to modules located in other slots.
SELECT CHANNEL must be used in conjunction with the SELECT SLOT command to
select the channels on slot one of the chassis.

is selected

for A/D conver-

Note that the channel number occupies the least significant four bits of Ch4DA. Make
sure that the channel number is combined with the appropriate upper four bits, as
shown in Figure 5, before it is sent.

SELECT LOCAL CHANNEL MODE
Location: xxx80
The SELECT LOCAL CHANNEL MODE command controls the configuration of the

local input

channels on the

AMM2. The AMM2 input channels can be configured as
either 16 single-ended or eight differential input channels. This command is selected by
assigning a value to the D4 bit position of CMDA as shown in Figure 5. A value of 1
will set the inputs to single-ended, a value of 0 will set them to differential.

Make sure that the other bits in the CMDA byte represent the desired selections before
it is sent.

SELECT LOCAL GAIN
Location: xxx80

The gain applied to the local channels of the Ah&I2 is programmable and can be set by
assigning a value to bit position D5 in CMDA. As shown in Figure 5, a value of 0 will
apply a local gain of Xl and a value of 1 will apply a local gain of X10 to the AMM2 in­put channels.

AMM2-10

The local gain can be changed at any time as long as the channel settling time is
satisfied before the conversion is started.

Make sure that the other bits in the CMDA byte represent the desired selections before
it is sent.

SELECT ACQUISITION MODE

The AMM2 has the capability of operating in either of two modes; the regular acquisi­tion mode, and the 5OkHz auto acquisition mode. As shown in Figure 5, the acquisition
mode is set by assigning a value to bit position D6 in CMDA. Assigning a value of 0
enables regular acquisition mode, a value of 1 enables 5OkHz auto acquisition mode.

To acquire an analog reading when in the regular acquisition mode, the slot, channel,
and gain must be selected. Then, after the appropriate settling time, the AMM2 is
issued a START CONVERSION command. At this time, the AMM2 latches the signal
and starts the digitization process. The EOC STATUS command can be polled for end­of-conversion (EOC) after which the digitized value can be read. The conversion process
will consume approximately 20psec.

Since the incoming signal is latched when the START CONVERSION command is
issued, the slot, channel, and gain selections can be changed immediately after the

command is issued. This will allow the settling time for the new selections to be

satisfied concurrently with the conversion of the previous selection. This type of opera­tion is not required but will increase the throughput capability of regular acquisition
mode.

The 5OkHz auto acquisition mode allows full 50kHz acquisition speed on analog signals.
Upon placing the AMM2 in this mode, the A/D enters a free-running 5OkHz conversion
process. Do not attempt to issue the START CONVERSION command in this mode.

Some microcomputers may not be capable of keeping up with the AMM2 in auto ac-

quire mode. If the AMM2 out-paces your microcomputer, the data points will be
unreliable.

After the completion of a conversion, the AMM2 begins the next conversion immediate­ly. The EOC STATUS command can be used to synchonize your program with the con-

versions. The conversions will take place on the slot and channel that are presently

selected at a rate of 5OkHz. The conversion status bit will be reset by the reading of
either the high or low AID data bytes. Figure 7 shows the timing for single channel
auto acquire operation.

While in auto acquire mode, the EOC status bit will become true (low) after the first
A/D conversion. Even though the next conversion begins immediately, the status bit re­mains true until the AID data is read. If the data is not read, it is over-written.

AM.M2-ll

EOC Status

Bit (CMDD)

Poll EOC

Bit Status (CMDD)

Read Low

Byte

Completed

Figure 7. Single Channel Auto Acquire Timing

Fiie 8 shows an example of the EOC status being polled only after one or more con-

versions have taken place. Even though the EOC status bit indicates that the conversion
is complete, there is no way of telling if another conversion is about to be completed.
Trying to read the data while the latches are being updated will cause unreliable
results. To guarantee reliable readings, your program should synchronize itself with the
AMM2 by taking a dummy reading to clear the conversion status bit. The next time the
status bit indicates the end of a conversion, the data at the AID latch will be valid for
the full 20psec.

EOC Status

Bit (CMDD)

Poll EOC

Bit Status (CMDD)

Although the converter status indicates

a completed conversion here, reading the data

might be coicident with an update of the

1 st

Conversion

-H
It­I

:
,
I

data from the converter.

2nd 3rd

Conversion

k

t
I
L

\
t
I

Data in the ND

Latch is Updated Here.

The EOC zatus bit

remains low until the

High or Low data are read.

Conversion

J

\-

Figure 8. Polling the Status Bit After One or More Conversions

For multichannel auto acquisition operation, all of the settling times for the new chan­nel must be satisfied 4psec before the EOC takes place. If it is not settled, it may be
necessary to throw away a reading or two until it has settled. To maximize the available
settling time, it is recommended that slot selection, gain selection, and channel selec­tion take place directly after the EOC becomes true.

For optimum operation follow these steps:

1. Monitor the EOC status bit until an end-of-conversion is sensed.

2. Select a new gain, a new slot, and a new channel, as needed.

3. Read the latched data from the last conversion.

AMM2-12

A timing diagram for multichannel operation is shown in Figure 9.

EOC Status

Bit (CMDD)

Poll EOC

Bit Status (CMDD)

Gain

Select

Slot

Select

Channel

Select

Read Low

Byte

Read High

Byte

Channel

A Data Ready

+ -I

- *,f-+

Set up

for Channel

B

I

lot mux

settling time : T

Read

Channel

4lq4-

I

Channel

I3 Data Ready

A

\

i I

C

Figure 9. Multichannel Operation in Auto Acquire Mode

I

Read

Channel

B

Even though the AMM2 is capable of digitizing analog signals at 50kHz, some modules
in the Series 500 module library are not capable of settling at these speeds. When do­ing multichannel acquisition, consult the individual module’s hardware manual for ap­propriate settling times.

SELECT FILTER
Location: xxx80
Two filters are available in the AMM2; a 1OOkHz filter, and a 2kHz filter. These filters

restrict the bandwidth of the incoming signal, rejecting either noise or unwanted high
frequency components that may create aliasing.

It is desirable to reject all signal frequency components that are greater than l/2 the
sampling frequency. These frequency components cause aliasing which produces inac­curate waveform representation. The filters are designed to reject frequencies above
1oOkHz or above 2kHz, depending on the filter used. The 1OOkHz filter, while not pro­viding complete protection against aliasing, does reduce the system noise with a
minimal effect on settling time.

Assign a value of 0 to bit position D7 in CMDA to select the 1OOkHz filter, assign a
value of 1 to select the 2kHz filter.

Make sure that the other bits in the CMDA byte represent the desired selection before
it is sent.

AMM2-13

SELECT SLOT
Location: xxx81
The SELECT SLOT command controls the global multiplexer on the AMM2, selecting

the appropriate slot on the Series 500 baseboard from which to read the input channel.

The value to be written to the SELECT SLOT location occupies the four least significant
binary digits of the command. Make sure that the channel number is combined with
the appropriate upper four bits as shown in Figure 6 before it is sent.

As indicated in Table 2, there are other values besides slot numbers that can be written
to this location. These values select ground, +5V, and +%JV sources and are intended
primarily for diagnostic purposes.

Table 2. Values Written to the SELECT SUrr Location
Function

Ground (0 volts)
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9

Slot 10
Reserved
Reserved

+lOV Reference
Ground (0 volts)

+5V Digital Power Supply

SELECT CMDA READ MODE

Location: xxx81
This command selects the usage of the CMDA read. Two types of information can be

read from CMDA (note that this affects only the read operation of CMDA), these are,
the low data byte of the AID or the AID status. In the low data byte mode, CMDA sup­plies the low data byte of the AID readings. In the AID status mode, CMDA supplies
status directly from the AID. The AID status is described further in the sections below.

Binary
bbbbOOO0

bbbbOOO1
bbbbOOl0
bbbbOOl1
bbbbOlO0
bbbbOlO1
bbbbOll0

bbbbOll1
bbbblOO0
bbbblOO1
bbbblOl0
bbbblOl1
bbbbllO0
bbbbllO1
bbbblll0
bbbbllll

AMM2-14

NOTE: When the CMDA read mode is set to AID status, a reset and recal sequence
will be initiated by any start conversion command. The start conversion command can
come either from a write to CMDD, or from the auto acquire mode hardware if this
mode has been enabled by a value of 1 in bit position D6 of CMDA. To avoid acciden­tally initiating a reset and recal sequence, be sure bit position D6 of CMDA is set to a
value of 0 before changing the CMDA read mode to A/D status. Do not write to CMDD
or change D6 of CMDA to a value of 1 as long as the CMDA read mode is set to A/D
status.

Assign a value of 0 to bit position D4 in CMDB to read A/D status from CMDA, assign

it a value of 1 to read the A/D low data byte.

Make sure that this bit is combined with the other appropriate bits as shown in Figure

6 before it is sent.

SELECT RANGE

Location: xxx81

The AMM2 has two programmable ranges; flOV (bipolar lOV) and zero to +lOV

(unipolar 1OV). Assigning a value of 0 to bit position D5 in CMDB will select the
AMM2 unipolar 1OV range, assigning a value of 1 will select the bipolar lOV range.

Make sure that this bit is combined with the other appropriate bits as shown in Figure

6 before it is sent.

SELECT GLOBAL GAIN
Location: xxx81
The GLOBAL GAIN command controls the PGA (Programmable Gain Amplifier)

located on the AMM2 module. Since all analog inputs are processed by the PGA, the
GLOBAL GAIN command affects every analog input connected to the Series 500. This
command is issued in combination with other commands on CMDB. The GLOBAL
GAIN value occupies the two most significant bits of CMDB and must be combined
with the other bits of the CMDB byte before it is issued.

Four programmable gain values, xl, x2, x5, and x10, are available with the PGA. These
gains are selected by setting the appropriate bits in CMDB before it is issued.

Table 3. Values Written to the GLOBAL GAIN Location

PGA Gain Binary

xl
x2 Olbbbbbb
x5 lobbbbbb

Xl0

RESET AND RECAL
Location: xxx9A

The RESET AND RECAL command starts the internal A/D calibration process. The pro-

cess takes approximately 360msec and should be completed once every time the system
is powered up.

After issuing this command, wait at

ted. To make sure that the calibration has taken place, set the CMDA read-mode to AID

OObbbbbb

llbbbbbb

least 36Omsec before any conversions are attemp-

AMhO-

status, as described above. The bit configuration of the calibration status is described
below. This bit can be polled to make sure calibration has been completed.

This command has no specific data associated with it, any value sent will start the
calibration process.

AID LOW DATA - AID STATUS

Location: xxx80
The contents of CMDA depends on the state of the AMM2 set by the SELECT CMDA

READ MODE command. If D4 of CMDB has been set to 0, CMDA returns the A/D
status of the AMM2. If D4 has been set to 1, the low byte of the AID counts is return­ed in CMDA.

When AMM2 is in the A/D status mode, the bit configuration of the CMDA byte is as
follows:

DO none
Dl none
D2 none
D3 none
D4 none
D5 TRACKING (lstracking in process, O=tracking stopped)
D6 CONVERTING (l=conversion in process, O=no conversion in process)
D7 CALIBRATING (l=calibration in process, O=calibration not in process)

After the A/D completes a digitization of an analog signal, it begins a process called
tracking. The A/D consumes 4,usec for the analog signal at its input to be tracked to the
specified accuracy. The time relationship between the TRACKING bit and the EOC bit
in CMDD is shown in Figure 10.

The converting bit indicates the actual A/D conversion status. The time relationship bet­ween the CONVERTING bit and the EOC bit in CMDD is shown in Figure 10.

Won’t Reset Until

bata

is Read

EOC Bit

in CMDD

Tracking Bit

in CMDA

Converting Bit

in CMDA

i

c-- 16~s

47

K

Conversion

Begins

Figure 10. Time Relationship of Status Bits

AMM2-16

The CALIBRATING bit returns the status of a RESET AND RECAL command as
described above.

If the M2 is in the low data mode, the byte received is the low byte of the 16 bit
A/D conversion. Since the module incorporates data latches, one conversion may be
read while another conversion is in progress. To find out when data from one conver­sion is available, use the A/D STARTlEOC S’IXI’US command, discussed below.

Reading this location resets the EOC status.

AID HIGH DATA
Location: xxx81

The A/D HIGH DATA command performs essentially the same function as the A/D

LOW DATA command, except that the high data byte is returned. Since the Alvilvl2 has
a 16 bit A/D, all of the bits in the high data byte are significant.

Once both the low and the high data bytes have been obtained, the total number of
counts representing A/D converter data can be determined with the following BASIC
formula:

= DL + 256*DH

co

CO represents the number of counts, and DL and DH are the low and high bytes
respectively. Since the AMM2 uses a 16-bit converter, the number of counts will lie in
the range of zero to 65,535.

Reading this location resets the EOC status.

A/D START
Location: xxx9B
The A/D START COMMAND

starts the A/D conversion process. Writing to the A/D
START location will trigger (start) the A/D conversion cycle. Although any value (O-255)
can be written to trigger a conversion, a value of 255 should be used to minimize noise.
Do not issue an A/D start command while in auto acquisition mode or the internal tim­ing of the A/D will be skewed.

The A/D conversion cycle takes approximately 16psec. During this period, the converter
should not be re-triggered. Status of the conversion process can be checked by access­ing the EOC STATUS command.

EOC STATUS
The EOC S’MTUS command returns a byte of data which indicates the state of the con-

version process. The returned value will depend on whether a conversion has been
completed (see Table 4).

AMM2-17

Table 4. Values Read from the A/D START/STATUS I-ocation

Calibmtion

This section contains calibration procedures for the AMM2 module. Note that these
procedures are intended for the field and may not be as accurate as those used in the
factory. Calibration accuracy depends both on the accuracy of the equipment used in
the procedure as well as the skill of the individual. If you are not familiar with calibra­tion equipment, do not attempt AMM2 calibration.

This procedure presumes that the unit is in working condition and at least one factory
calibration has been done in the past. An additional procedure is necessary to select
R25, R26, R27 and R28 if the voltage reference Ul3 has been replaced. The procedure
for replacing Ul3 is described after the section on troubleshooting.

Environmental Conditions

Calibration should be performed at an ambient temperature of 23°C (k5”). Turn on the
system power and allow it to warm up for at least 10 minutes before beginning the
calibration procedure.

EOC Status
Conversion in process

Binary

l.XXXXXXX

End-of-conversion OXXXXXXX

Recommended Calibration Equipment
The following equipment is recommended for AMM2 calibration. Other equipment may

be used as long as the corresponding specifications are at least as good as those given
below.

1. Keithley Model 196 DMM (0.005% basic DC accuracy).
Key specs needed on DMM:

DC accuracy of 60 ppm on a 1OV reading.
Sufficient resolution to read one microvolt offsets.

2. EDC Model ElOOC Millivolt Reference Source (0.005% accuracy).
Key specs needed on source:

Provides an output between 0.5 and 0.99 volts.
Maintains its output stable to 10 ppm for five minutes.

Overview of Adjustment Sequence

1. Adjust 1OV reference.

2. Adjust 4V reference.

3. Adjust Global Amp offset.

4. Adjust attenuator offset.

5. Adjust both Local amp offsets.

6. Adjust Local amp Xl.0 gain.

7. Tweak AID gain with 4V reference adjustment.

AMAO-B

Calibration Procedure
The test points, potentiometers, and connectors referenced in the procedure are shown

in Figure 1.

Adjust 1OV reference

1. Connect the DMM high lead to TP7 (WV). Connect the DMM low lead to TP4
(AGND). Select DCV and autoranging.

2. Adjust pot R7 for 10.0000 volts f100kV.

Adjust 4V reference
The following procedure will bring the 4V reference within range so that it can be

calibrated accurately later.

1. Connect the DMM high lead to TP8 (4V). Connect the DMM low lead to TP4
(AGND). Select DCV and autoranging.

2. Adjust pot R8 for 4.000 volts *lmV. This adjustment will be tweaked later.

Adjust Global Amp offset

1. Connect the DMM high lead to TP9. Connect the DMM low lead to TIP4 (AGND).
Select DCV and autoranging.

2. Select the PGA gain of Xl.0 and the zero voltage reference input by POKEing a value

of 192 to CMDB of slot 1 and a value of 0 to CMDA of slot 1.

3. Adjust pot R9 for zero volts *lOpV.

Adjust attenuator offset

1. Select the Xl global gain and the zero voltage reference input by POKEing a value of

zero to both CMBA and CMDB of slot 1.

2. Connect the DMM high lead to TPlO. Connect the DMM low lead to TP9. Select

DCV autoranging.

3. Adjust pot RlO for zero volts *lO$I.

Adjust both Local amp offsets

1. Connect a short jumper wire between differential channel 0 high input and signal
common (terminals 9 and 10 on Jl). Connect a short jumper wire between differen­tial channel 0 low input and signal common (terminals 1 and 2 on J2).

2. Connect the DMM high lead to TP3. Connect the DMM low lead to TP4. Select
DCV and autoranging.

3. Select differential input and Xl gain by POKEing a value of 0 to CMDA of slot 1.

4. Record the DMM reading as Vout(1) for use later.

5. Select a gain of X10 by POKEing a value of 32 to CMDA of slot 1.

6. Record the DMM reading as Vout(2).

7. Compute the offset contribution of U6 as follows: V, = (lO*VOur(l) - V0,A2))/9.

8. Adjust pot R5 so that the DMM reads the voltage computed for V,,

9. Select the Xl gain again by POKEing a value of zero to CMDA of slot 1.

10. Adjust pot R6 for a DMM reading of zero volts *lOpV. If desired, the adjustment
can be checked by once again outputting data: CMDA = 32. The DMM should read
zero volts *lOOflV.

AMM2-19

Adjust Local amp Xl0 gain

1. Remove the jumper between terminals 9 and 10 of Jl that was installed in previous
step. Connect voltage source (+) output to terminal 9 of Jl, and the voltage source
(-) output to terminal 10 of Jl. Leave the jumper installed between terminals 1 and 2

of J2.

2. Connect the high lead of the DMM to TP3. Connect the low lead of the DMM to
TP4. Select DCV and autoranging.

3. Set the voltage source to a value of 0.99 volts.

4. Select the X10 gain by POKEing a value of 32 to CMDA of slot 1.

5. Adjust pot R4 for a reading of 9.9 volts.

Tweak A/D gain with 4V reference adjustment

1. Use the test setup from the previous step. The DMM should be reading a voltage of
approximately 9.9 volts on TP3.

2. Select channel 0, local gain of XlO, differential input, filter on (2kHz), slot 1, unipolar
lOV range, and global gain of Xl by POKEing values of 224 and 17 to CMDA and

CMDB respectively.

3. Run the following BASIC program. This program assumes that the hardware address

in CFFO, if this is not the case, adjust line 10 for the proper address.

10 DEF SEG = &hCFFO ‘hardware segment*
20 CMDA = &h80: CMDB = &h81
30 CMDC = &h9A: CMDD = &h9B
40 POKE CMDA, 160 ‘set up from step 2 above
50 POKE CMDB, 17 ‘set up from step 2 above
60 POKE CMDD, 255 ‘start conversion
70 WHILE PEEK(CMDD) > 127 :WEND ‘wait until conversion is complete
80 TOTAL = PEEK(CMDA) + PEEK ‘get high and low data and combine

(CMDB)*256

90 VOLTS = TOTAL * 0.00015258

100 LOCATE l,l?RINT VOLlS,

110 GOTO 60

*Presumes interface is set to address CFF8O(h).

‘print value in volts

4. Adjust pot R8 so that the displayed voltage equals the DMM reading.

Theory of Operation

For the following discussion, please refer to the schematic diagram, drawing number
501-186.

AMM2 circuitry is divided into the following sections: local input multiplexer, program­mable gain, global input multiplexer, global gain amplifier, filter, A/D converter, A/D

voltage reference amplifier, and the lo-volt global reference.

Local Input Multiplexer
The local input multiplexer is made up of two 8 to 1 analog multiplexers Ul and U2, a

dual analog switch U3, and input protection resistor networks Rl and R2. The digital
control signals for the input multiplexer are latched by U19, and additional digital logic
to control the differential/single-ended mode selection is in the PAL, U18. When the

AMM2-20

single-ended mode is programmed, U3 grounds the inverting input of the differential
instrumentation amplifier (pin 3 of U7), and connects the output of both Ul and U2 to
the non-inverting input of the differential instrumentation amplifier (pin 3 of U5). The
selected input is switched through the appropriate 8 to 1 multiplexer to the differential
amplifier input while the output of the other 8 to 1 multiplexer is open circuited. When
the differential input mode is selected, U3 connects the output of U2 to the inverting
input of the differential instrumentation amplifier (pin 3 of U7). The output of Ul is
always connected to the non-inverting input of the differential instrumentation amplifier
(pin 3 of U5). The selected input channel

the +CH terminal is connected through Ul to the local amplifier inputs.

Local Programmable Gain Amplifier

U4, US, U6 and U7 make up the local programmable gain amplifier. U5 and U7 provide
the high input impedance, and also provide the voltage gain when the X10 gain is
selected. When Xl gain is selected, U4 (a dual analog switch) connects both U5 and U7
in the voltage follower configuration. When Xl0 gain is selected, U4 connects the inver­ting inputs of U5 and U7 to the taps on a voltage divider connected across the outputs
of U5 and U7. The voltage difference between the inverting inputs of U5 and U7 is 1110

the voltage difference between the outputs of U5 and U7. This arrangement gives a
voltage gain of 10 for differential input signals and a voltage gain of 1 for common
mode input signals. The common mode input signal is defined as the average of the

+CH and -CH input signals. The voltage gain in the X10 mode is adjusted with R4,
which adjusts the voltage divider ratio. The voltage gain in the Xl mode is not ad­justable. The outputs of U5 and U7 are connected to the precision resistor network Rll
and amplifier U6. Rll and U6 make up a unity gain differential amplifier, which
amplifies the differential signal and rejects the common mode signal. The output of U6
is the overall amplifier output, and consists only of the differential signal between U5
pin 3 and U7 pin 3.

-CH terminal is connected through U2 and

Global Input Multiplexer
The global multiplexer selects which signal is measured by the A/D converter. U8 is a

16 to 1 analog signal multiplexer. Inputs 0 and 14 of U8 are connected to ground. Input
1 is connected to the output of the local amplifier. Inputs 2 through 10 go to pins on

Pl4, and by external connections, are connectd to slots 2 through 10 of a Series 500

mainframe. These connections will carry the output signals of other signal processing
cards to the global multiplexer, where they can be routed to the A/D converter for
measurement. Inputs 11 and 12 also go to J14, but are typically not used. Input 13 is

connected to the lo-volt reference, and input 15 is connected to the +5-volt digital
power supply. The output of the multiplexer is connected to the Global Amplifier
input.

Global Programmable Gain Amplifier and Filter

The global programmable gain amplifier is made up of US, UlO, and Ull. The voltage
gain of U9 is determined by which tap on the precision resistor network R14 is selected
by the analog multiplexer Ull. The available gains are Xl, X2, X5, and X10. R14 is a
voltage divider connected to the output of US, and the tap determined by Ull is con­nected to the inverting input of U9. The non-inverting input of U9 is the overall input
of the circuit. At the output of US, 10 volts represents a full scale input. The A/D con­verter used cannot convert an input above 4 volts, so the output of U9 is reduced to
40% of its full scale output by a divider made up of Rl5, Rl.6, and Rl7. The analog filter
is applied after this divider, and is made up of C7 and Rl8 along with the combined
resistances of the divider. For the 2kHz pole, all resistors are in the circuit, but when
the 1OOkHz pole is programmed, RET Q3 is turned on and bypasses Rl8. The lOOkHz

AMM2-21

pole is determined by the equivalent output resistance of the 40% divider and C7. UlO
buffers the filter output and provides the low drive impedance required by the AID
converter. At the output of UlO, 4 volts represents a full scale input. CR& CR2, CR3,
and CR4 make up a clipping circuit to prevent overscale inputs from saturating the AID,
thus allowing immediate overload recovery.

A/D Converter
The A/D converter, UT& is a &bit successive approximation converter with an internal

sample and hold. Ul2 operates on +5 volts and -5 volts. These supplies are derived
from the +l5 and -15 volt analog supplies by U21 and U22 respectively. The A/D
determines the ratio of the analog input to the voltage reference input. The voltage
reference used is 4 volts. The digital outputs of the A/D are buffered by U16 and Ul.7.
The logic control for the A/D is in the PAL, Ul8.

A/D Voltage Reference Amplifier
The A/D converter requires a voltage reference source with a low output impedance

from dc up to several megahertz. Ul5, Ql, R8 and the associated components comprise
an amplifier with the needed characteristics. The reference voltage is derived from the
heated zener reference Ul3 and divided down to 4 volts by the divider made up of R8,

R21, R22, and R24. Resistors R27 and R28 are used to restrict the adjustment range of

R8, and are either installed or not used based upon the zener voltage of Yl3 at the time
of factory calibration. If Ul3 is replaced, it may be necessary to either install or remove
either one or both of these resistors. R31 and C6 frequency compensate the amplifier
loop, and C9 is a filter for zener noise.

10

Volt Global Reference

Ul3, U14 and the associated components form the 10 volt reference circuit. The zener
voltage of approximately 7 volts is amplified by U14 to 10 volts. R7, R19, R20, and R23

determine the output voltage by adjusting the gain of U14. R25 and R26 serve a func­tion similar to R27 and R28 in the A/D reference circuit. R30 and C8 filter the zener
noise, and D7 assures that the circuit will start properly when power is first applied.

AMM2 Troubleshooting Information

Diagnosing trouble with the AMM2 is best done in several steps. If the AMM2 is not
functioning at all, the following tests should be performed in the sequence indicated. It
may be possible to skip some of the tests if the AMM2 is partially functional.

A BASICA test program is listed at the end of this section which is used to setup the
hardware for these tests. Change line 10, if necessary, to the address segment used by
your system. Each test is independent, and can be run by itself if needed, as long as
the first 3 lines of the program are also entered.

AMIVQ-22

The overall test sequence is:

1. Check power supplies

2. Check reference voltages

3. Test digital control circuitry

4. Test local mu

5. VWify operation of local amplifier

6. Check operation of global amp

7.

Test global mux

8. Verify operation of A/D converter

The only additional equipment needed for these tests is a digital multimeter (DMM),
and two jumper leads. When performing these tests, refer to schematic diagram 501-186,
component layout 501-180, and the following instructions for the connections to use
while running the test program.

Test Sequence:

1. Check power supplies
Using a DMM on the 20-volt range, connect the minus lead to TP4 (AGND). The

positive lead should be used to test for the following voltages within ltO.5 volts:
U7pin7

U7pin4
TP6 (DIG GND)
Ul8 pin 24
ul2pirL25
UC! pin 11
ul2pin30
Ul.2 pin 36

+l5

-15

0

+5
+5
+5

-5

-5

2. Check reference voltages
With the DMM minus lead connected to TP4 (AGND), use the 20-volt range to read

the following voltages:
TM4 w

TP7 (lOVref)
Tl?8 (4V)

7 io.25 volts
lo.00 volts

4.0 rto.2 volts

zener reference voltage
u14 output
Ul5 output, A/D reference voltage

3. Test digital control circuitry
Use the test program lines 300-395 to verify that the control registers are capturing

the correct data. Connect the minus lead of the DMM to TP6 (DGND) and touch the
DMM plus lead to the pins indicated by the program.

If this test is completely unsucessful, first verify that the rest of the system is func­tioning properly before proceeding. The computer, IBIN interface card, 500 main­frame, and hardware address segment should be checked. If the rest of the system is
functioning properly, or if only some of the pins on U19 or U20 are not functional,
check U18, U19, U20 and the K’s connected to the nonfunctional pins.

AMlm-23

4. Test local mux
The local mux can be checked by putting a signal through each of its channels. A

convenient signal is the 4volt reference tested in step 2. The test program lines
400-490 will help perform the test. Connect a test lead to TP8 (4V) and connect the
other end of this test lead to the input on Jl or J2 as indicated by the program. Con­nect the DMM - lead to TP4 (AGND), and the + lead to Tl?l or TP2 as indicated by
the program. Run the program. The DMM should show the 4-volt signal on the in­dicated test point when the input pin indicated by the program is touched with,the
4V test signal.

5. Verify operation of local amplifier
Proper operation of the local amplifier can be tested by applying a voltage difference of

one volt to its input and looking for an output of one volt on the Xl gain range and 10
volts on the X10 gain range. A one volt signal can be obtained by connecting +4V reference
Tl?8 (4V) to -CHO on J2 pin 2, and +5V supply Tl?l2 (+5V) to +CHO on Jl pin 9. Connect
the DMM + lead to TP3 and the - lead to TP5 (SGND). Lines 500-580 provide the setup

for this test.

6. Check operation of global amp
The global amp can be tested by using the one volt signal generated in step 5 above,

and checking that the correct output at TP9 occurs for each gain setting. The global
mux channel 1 of U8 must be functional for this test to work, so it is checked first.
Connect a test lead from TP8 (4V) to J2 pin 2 and a second test lead from TIP12
(+5V) to Jl pin 9. The DMM -

TP indicated as the output in the test program. Lines 600-690 of the test program are

used.

lead connects to TP4 (AGND), and the + lead to the

7.

Test global mux
The global mux is tested by applying a signal to each input and verifying that the

signal appears at the output. Since the global amp was tested in the previous step,
any signal applied to the global mux should show up at TP9. The slot inputs can be
tested by applying the 4volt reference signal to the input under test. Other inputs to
the global mux are hardwired to various signals as indicated by the program. Setup
the test as follows: Connect a test lead from TIP8 (4V) to J2 pin 2 and a second test
lead from TPl2 (+5V) to Jl pin 9. The DMM - lead connects to TP4 (AGND), and
the + lead to TP9. At the point in the program where a signal is required as an in­put to a pin on US, disconnect the end of the test lead on J2 pin 2 and use this end
to touch the pin indicated by the program on U8. Lines 700-790 of the test program
are used.

8. Verify operation of A/D converter
The A/D converter is tested by inputting a signal from the local amp and displaying

the reading. The test setup uses the one volt test signal derived in step 5. The
displayed voltage should be about one volt. Connect a test lead from TIP8 (4V) to J2
pin 2 and a second test lead from TPE (+5V) to Jl pin 9. Lines 800-890 of the test
program are used.

Replacement Procedure for Ui3

The heated zener voltage reference Ul3 requires a special calibration procedure if it is
replaced. The LM399 used for Ul3 has a wide tolerance for its initial zener voltage, but

AMM2-24

drifts very little with time or temperature. Resistors R25, R26, R27 and R28 are used to
trim out a large portion of the initial zener voltage tolerance, with the balance of the
adjustment done by potentiometers R7 and R8. The adjustment range of R7 and R8 is
large enough to compensate for any drift in U13 over the life of the module, but has
been purposely restricted to improve the stability and adjustability of the voltage
reference. When U13 is replaced, the following procedure must be used to determine
which two of the four resistors (R25,26,27,28) must be installed.

The procedure is to measure the zener voltage, + lead to TPl4, - lead to TP4 (AGND),
find the range on the following table that includes this voltage, then install or remove
the resistors indicated in the table as required.

Zener Voltage R25

6.78 to 6.90

6.90 to 7.01

7.01 to 7.11

7.11 to 7.23

open 61.9 K 383 K open

49.9 K 61.9 K open open
open open 383 K

49.9 K open open 267 K

Troubleshooting Test Program

NOTE: This troubleshooting test program can be used with the 5OOA, 5OOP, or 575
Mainframes. When the program is testing the global multiplexer in a 500A or 5OOP
mainframe, random voltage values will be measured if no modules are plugged into
any of the remaining slots of the chassis. You will read a floating voltage.

When the program is testing the global multiplexer in a 575 mainframe, random voltage
values will be measured since slots 2,4,5, and 6 in the 575 are considered virtual slots.
Virtual slot 6 of the 575 functions as 8 single-ended inputs. Depending on the software
you plan to use, these analog inputs in configuration tables are shown as being slot 6.
This is for convenience only. The external function actually uses the AMM global analog
inputs 3-10 which feed the A/D converter of the AMM module in slot 1. If an analog
input module is used in slot 3 of the 575, only 7 external inputs will be available.

10
20

30
300
310
320
330
335
340
350
355
360
370
375
380
390
395
400
405

410

DEF SEG = &HCFFO HARDWARE SEGMENT
CMDA = &H80: CMDB= &H81
CMDC = &H9A CMDD = &H9B

PRINT “3. TEST DIGITAL CONTROL CIRCUITRY”
POKE CMDA, 255
PRINT “MEASURE > 3 VOLTS ON PINS 2,5,6,9,12,15,19 OF U19”

INRJT ‘TRESS RETURN TO CONTINUE”, A$
POKE CMDA,O
PRINT “MEASURE < 1 VOLT ON PINS 2,5,6,9,12,15,19 OF U19”
INPUT ‘TRESS RE’ITJKN TO CONTINUE”, A$
POKE CMDB,255
PRINT ‘MEASURE > 3 VOLTS ON PINS 2,5,6,9,12,15,19 OF U20”
INPUT ‘TRESS RETURN TO CONTINUI?, A$
POKE CMDB,O
PRINT ‘MEASURE < 1 VOLT ON PINS 2,5,6,9,12,15,19 OF U20”
INPUT ‘TRESS RETURN TO CO-, A$
CLS
PRINT “4a. TEST LOCAL MUX SINGLE ENDED MODE”
FORN=OTO15

R27

267K

AMM2-25

415
420
425
430

345
440
445
450
455
460
465
470
475
480
485

490
500
510

520
530
540
550
560
570
580
600
605
610
620
630
635
640
650
655
660
670
680
685
690
700
710
715
720
730
740
750
760
765
770
775
780
785
790

IFNc8THENl’IN=9-NELSEl’IN=N-6
IFN<8THENJ=lELSEJ=2
POKE CMDA, 16 + N
LOCATE 6,1
PRINT “INl?UT”;N;“ON PIN”;l’IN;“OF J”;J;“IS CONNECTED TO TPl”
INPUT ‘TRESS RETURN TO CONTINUE”, A$
NEXT-N

CLS
PRINT “4b. TEST LOCAL MUX DIFFE
FORN=OTO7
POKE CMDA, N
LOCATE 6,l
PRINT “+INFUT”;N;“ON MN”;9-N;“OF Jl IS CONNECTED TO Tpl”
PRINT “- lNl?UT’;N;“ON PLN”;N+2;“0F J2 IS CONNECTED TO TP2”
INPUT ‘TRESS RETURN TO CONTINUE”, A$

NEXTN

CLS

PRINT “5. TEST LOCAL AMP”
POKE CMDA, 0
PRINT “LOCAL GAIN = Xl, 1 VOLT INPUT GIVES 1 VOLT OUTPUT AT Tp3”
INPUT ‘TRESS RETURN TO CONTINUE”, A$
CLS
POKE CMDA, 32
PRINT “LOCAL GAIN=XlO, 1 VOLT INPUT GIVES 10 VOLT OUT!?UT AT TP3”
INPUT ‘TRESS RETURN TO CONTINUE”, A$
CLS
PRINT. “6a. SETUP LOCAL AND GLOBAL AMP”
POKE CMDA, 0
POKE CMDB, 1
PRINT “READ 1 VOLT AT PIN 28 OF U8”
INPUT ‘TRESS RETURN TO CONTINUE”, A$
FORN=OTO3
CLS
PRINT “6b. TEST GLOBAL AMP”
J?OKECMDB,l+(64*N) ‘SELECT GLOBAL GAIN
IF N < 2 THEN V=N+l ELSE V=(N-1)*5 ‘DETERMINE VOLTAGE GAIN
PRINT “READ”;V;“VOLTS AT Tl?9”
INPUT “PRESS RETURN TO CONTINUE”, A!$
NEXTN
POKE CMDA, 0
FORN=OTO15
CLS
PRINT “7. TEST GLOBAL MUX”
LOCATE 6,1
IFN<8THENMN=N+19ELSEPIN=19-N
POKE CMDB, N
IF N=O OR N=14 THEN PRINT “0 VOLTS AT TW’
IF N=l THEN PRINT “1 VOLT FROM LOCAL AMP AT TW’
IF N=13 THEN PRINT “10 VOLT REFERENCE AT TW’
IF N=15 TH.EN PRINT “5 VOLT DIGlTAL SUPPLY AT Tl?9”
IF N>l AND N<13 THEN PRINT “SIGNAL AT PIN”;l?IN;“OF U8 AT TP9”
INPUT ‘TRESS RETURN TO CONTINW?‘, A$
NEXTN

RENTIAL MODE”

‘SET LOCAL GAIN TO Xl0

‘SETUP LOCAL AMP TO Xl
‘SETUP GLOBAL INPUT AND AMP

‘SELECT LOCAL AMl’ FOR IV OUT

AMM2-26

AMM2-26

800
810
820
830
840
850
860

870
875
880
890
895
900
910

CLS
PRINT “8. TEST A/D CONVERTER”
POKE CMDA, 0
POKE CMDB, 17
POKE Ch4.DD, 255
WHILE PEEK(CMDD) > 127: WEND

‘SETUP LOCAL AMP
‘SETUP GLOBAL CHANNEL
‘START CONVERSION
WAIT FOR CONVERSION DONE

TOTAL=PEEK(CMDA) + PEEK(CMDB)*256 ‘GET READING, COMBINE

BYTES

VOLTS = TOTAL * 1.5259E-04

‘CONVERT READING TO VOLTS
LOCATE 6,l
PRINT VOLTS
A$=lNKEY$
IF A$ = NN THEN GOT0 840
PRINT “TEST DONE”

AMM2-26A

AMM2 Specifications

INPUT CHANNELS
Local: 8 differential inputs or 16 single

ended inputs.

Global: 9 inputs from slots 2-10.
LOCAL PGA

Programmable Gains: xl, x10.
Gain Accuracy: &O-016%, xl gain;

fo.O25%, x10 gain.

Gain TC: M.OOl%/oC, xl gain;

~.0017%/oc, XI0 gain.
Nonlinearity: &0.01X.
Input Offset: tiOi.tV initial, adjustable to

XXO.

Offset TC: tiOpV/OC.
Input Resistance: >lOOMR.
Input Bias Current: <InA.
Input Noise: c5OuV rms, O.lHz to

1OOkHz.
CMRR: >80dB, DC to 6OHz.
Input Protection (any terminal to

chassis): BOV max. (powered); *15V

max. (unpowered).

10.000 VOLT REFERENCE
Accuracy: fi.O2%.
AccuracyTC: #.0012%/“C.
Noise: 2OpV p-p, O.lHz to 10Hz.

POWER CONSUMPTION:
+5 Volt Supply: 125mA typical.
+15 Volt Supply: 65mA typical.

-15 Volt Supply: 65mA typical.

GLOBAL AMP AND
AfD CONVERTER

A/D Converter. Self-calibrating, succes-

sive approximation.
Resolution: 16 bits (1 part in 65,536).
A/D Ranges: Software selectable, 0 to

+lOV unipolar, and -lOV to +lOV

bipolar.
Conversion Tie: 2Oi.tsec (induding

acquisition time).
Software Trigger:

Oneshot Mode: A single reading is

available 2Opsec after trigger
location in memory is addressed.

Continuous Mode: Conversions are

continuously triggered every
2Ojrsec by internal crystal
controlled clock.

External Trigger: Continuous conver-

sions begin with falling edge of EXT
TRIG input and stop when input is
high. TTL compatible.

Noise: 40.005%

ranges and gains, s3dB signal to
noise ratio (sinewave rms signal to

rms noise).
Programmable Gains: xl, x2, x5, x10.
Gain Accuracy*:

f(0.02% + 1 LSB), xl gain;

tiO.O3% + 1 LSB), x2, x5, x10 gain.
Gain TC*: ~.ooZ%/°C.
Nonlinearity? M.O057%.
Input Offset+: if54tV + 1 LSB) initial,

adjustable to fl LSB.
Offset TC*: ti@V/“c.

Filter: Software selectable, 1oOkHz or

2kHz single pole filter.

Settling Time (to 0.003% of final

reading): 16,usec with 1oOkHz filter,
800~~ with 2kHz filter.

*Includes input MUX, amplifiers, and

A/D errors.

of

full scale) rms on all

AMM2-27

SYSTEM SPECIFICATIONS

500A MAINFRAME WITH AMM2 INSTALLED

AMML DIRECT INPUTS (AID in bipolar mode*)

ACCURACY (1 Year)** TEMPERATURE

RANGE
fl0 v 305 pv 0.065 + 0.7 mV 0.0026 + 0.03 mV

f5 v
f2 v

fl v
f5OOmV
*200mV
f1OQmV

CMRR: (DC to 6OHz): >gOdB.
Wideband Noise: c(5OpV + 0.005% of full scale) rms.

*For &polar A/D mode, divide resolution by 2. Other specifications are unchanged.

**Exclusive of noise.

RESOLUTION tifxrdg + mV)

153 pv

61 PV
31 pv
15pv

f51*V

3pV

w-28T COEFFICIENT

0.065 + 0.57 mV 0.0029 + 0.03 mV

0.065 + 0.52 mV 0.0029 + 0.03 mV

0.065 + 0.32 mV 0.0023 + 0.02 mV

0.065+03 mV 0.0026 + 0.016 mV
O&5+0.3 mV 0.0026 + 0.016 mV

0.065+0.3 mV 0.0026 + 0.016 mV

i(%rdg + mV)/“C

AMM2-28

AMM2, PARTS LIST

CIRCUIT
DESIG.

Cl,C2,C36
ClO,Cll

c12..c15
C16..C35
C3,c4
c5
c6

&3
CRl..CR9

Jl,J2
J3
J4..56

M6

DESCRIPTION

CAP,22pF,lO%,lOOOV,CERAMIC
CAP,luF,20%,50V,CERAMIC
CAP, 1 OuF,20%,20V,TANTALUM
CAP,.luF,20%,50V,CERAMIC
CAP,10pF,10%,1000V,CERAMIC
CAP,100pF,10%,1000V,CERAMIC
CAP,470pF,10%,1000V,CERAMIC
CAP,1000pF,10%,100V,POLYPROPYLENE
CAP,luF,20%,5OV,POLYESTER

DIODE,SILICON,IN4148 (DO-35)
SOCKET, 16-PIN (FOR J4..56, U18)

SOCKET, 8-PIN (FOR U18)

CONN,STRIP,lO PIN

CONNP-PIN
RESISTOR CARRIERS

CLAMP ASS’Y

KEITHLEY
PART NO.

C-64-22P
C-237- 1
c-179-10
C-365-. 1
C-64- 1OP
C-64-1OOP
C-64-470P
C-306-.00 1
c-350- 1

RF-28
SO-65

SO-72
CS-521-2

cs-339-4

CS-480

500-323

Ql

:
Rl,R2

Rll
R13
R14
R15

R16

R17

R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R3

TRANS,NPN SILICON,2N3904 (TO-92)
TRANS,PNP SILICON,2N3906 (TO-92)

FET, TO-92 CASE

RES NET,lK,2%,2.25W

RES NET,lOK,.Ol%,.lW

RES,2.274K,.l%,l/lOW,METAL FILM

RES NET,2K,6K,lOK,.l%,.lW

RES,2.87K,.l%,l/lOW,METAL FILM

RES,130,1%,1/8W,METAL FILM

RES,2K,.l%,l/lOW,METAL FILM

RES,75K,1%,1/8W,METAL FILM

RES,2.74K,.l%,l/lOW,METAL FILM

RES,6.65K,.l%,l/lOW,METAL FILM

RES,14.7K,.l%,l/lOW,METAL FILM
RES,20K,. 1 %,l/lOW,METAL FILM

RES,121,1%,1/8W,METAL FILM

RES,499,1%,1/8W,METAL FILM
RES,49.9K 1%,1/8W,METAL FILM
RES,61.9K,1%,1/8W,METAL FILM

RES,383K,l%,l/8W,METAL FILM
RES,267K,1%,1/8W,METAL FILM
RES,3.OlK,1%,1/8W,METAL FILM

RES,86.6K,.1%,1/8W,METAL FILM

TG-47
TG-84
TG-167

TF-177-1

TF-175
R-263-2.274K
TF- 174
R-263-2.87K
R-88-130
R-263-2K
R-88-75K
R-263-2.74K
R-263-6.65K
R-263-14.7K
R-263-20K
R-88-121
R-88-499
R-88-49.9K
R-88-61.9K
R-88-383K
R-88-267K
R-88-3.01K
R-88-86.6K

AMM2-29

R30
R31
R32
R33
R34,R35
R36
R37

R38
R39
R4

R40
R41 ,R42
R5,R6,R9,RlO

R7,R8

RES,2K,1%,1/8W,METAL FILM

RES,8.2K,5%,1/4W,COMPOSITION OR FILM
RES,100,5%,1/4W,COMPOSITION OR FILM

RES,390,5%,1/4W,COMPOSITION OR FILM

RES,1O,5%,1/4W,COMPOSITION OR FILM
RES,47K,5%,1/4W,COMPOSITION OR FILM
RES,lOOK,1%,1/8W,METAL FILM
RES,22K,5%,l/4W,COMPOSITION OR FILM
RES,5.6K,5%,1/4W,COMPOSITION OR FILM
POT,20K,10%,.75W,NON-WIREWOUND
RES,976,.1%,1/8W,FIXED
RES,lOK,.l%,l/lOW,METAL FILM
POT,20K,10%,.75W,NON-WIREWOUND
POT,ILK,lO%,.75W,NON-WIREWOUND

R-88-2K
R-76-8.2K
R-76-100
R-76-390
R-76-10
R-76-47K
R-88-100K

R-76-22K
R-76-5.6K
RP-89-20K

R-176-976

R-263-10K

RP-89-20K

RP-89-2K

TPl..TP14
Ul ,U2,Ull

u12
u13
u14,u15
U16,U17
U18
U18
u19,u20
u21
u22
u3 ,u4
U5..U7,U9,UlO
U8

Yl

SOCKET,40-PIN (FOR U12)
PIN,TEST POINT
IC,8 CH CMOS ANALOG MULTI,6108

IC, 16-BIT,16uS A/D CONV,CS5016-JC16

IC, VOLTAGE REFERENCE, LM399

IC,22V OP-AMP,OP-07

IC,OCTAL BUS DRIVER,74HCI’541

JUMPER

IC, PGMABLE LOGIC ARRAY,PAL20LlOACNS

IC, OCTAL EDGE TRIG FLIP FLOP,74HCT374

IC, 5V VOLTAGE REGULATOR, 78L05

IC, -5V VOLTAGE REGULATOR, 79L05

IC, DUAL SPST CMOS ANALOG SWITCH

IC, HIGH SPEED OP AMP, OP-42

IC,16 CHAN CMOS MULTIPLEXER,6116

OSCILLATOR, 4 MHz

SO-84-40
cs-553
IC-267

IC-606

IC-2 17
IC-207
IC-607
J-14
IC-605
IC-397
IC-603
IC-604
IC-455
IC-600
IC-365

CR-28-2

AMM2-30

/: Lug

*“x . . . . . . . . . . . . . . . . . . . . :.

.I

Il/llllllllll/lllllI

lllillllllllll

AMM2 COMPONENT LAYOUT

AMM2-311AMhG32

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