AMMIA
Master Analog Measurement Module
The AMMl A Analog Measurement Module combines three important Series 500 functions into a sin&e
module. First, the AMMlA functions
gle-ended or eight differential analog input signals. It contains signal conditioning and switching circuitry for these channels. Second, the Ah&ilA selects and conditions analog signals from other analog
input modules in a Series 500 system. Last, the AMMlA serves as a IZbit A/D converter for its own
analog input channels, as well as any other analog signals which have been processed by the global select/conditioning circuitry. After analog conditioning, signals are routed to the A/D converter section
of the module for the analog-to-digital conversion process.
Input signals are applied to the AMMl A’s analog input channels through on-card quick-connect screw
terminals. The AMMlA has a total of 16 local single-ended, or eight differential inputs. The input configuration is controlled through software, rather than with hardware switches. These analog input
channels can be conditioned with programmable local gains of either xl or x10.
Global conditioning consists of a high-speed software-controlled gain amplifier with programmable xl,
x2, x5 and x10 gain values. All analog inputs connected to the Series 500 pass through the global circuitry, whether the signals originate on the AMMlA or some other analog input module. Therefore, these
gain values can be applied to any analog input in the system.
as
a standard analog input module, and will accept up to 16 sin-
For A/D conversion, the AMMlA uses a E-bit successive approximation converter. A maximum conversion time of only l@ec allows sampling rates as high as 62.5kI-L~. to maximize resolution, the
AMMlA has 0-IOV and +lOV A/D converter ranges which are software selectable.
CAUTION: Always turn off the system power before installing or removing modules. To minimize
the possibility of EMI radiation, always operate the system with the top cover in place and properly
secured.
The AMMlA is designed to be used only in slot 1 of the 500-series chassis, Model 575, or Model 576. To
install the module in a series 500 chassis, first remove the baseboard top cover and install the module
in slot 1 with the component side facing the power supply. For Model 575 or 576, please refer to the Setup section of its hardware manual.
Document Number: 501-913-01 Rev. B
AMMl A-l
TPB TPl3 TPl2TP4 TPlO '61
go 0
*O
0
q
0
0
0
0
0
0
0
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0
0
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i
SOFTWARE CONSIDERATIONS THE AMMlA ANALOG MODULE
The AhJMlA module, when used in a 575 or 500 series chassis, operates with KDAC500 and a variety
of 3rd party software packages. For programmers who are writing their own register level driver, the
following data format explanation is provided:
BASIC PEEK/POKE operations and equivalent commands in other programming languages must access the AMMIA as a 16-bit A/D module, rather than a 12-bit module. The AMMlA’s 12-bit resolution
results from padding the last four of the 16 bits with zeros. The least significant bit position where
change will be observed in the fifth least significant bit, and the low byte will increment by 1000 binary.
The high and low bytes carry information as follows:
high byte
1i
HHHHHHHH LLLL 0000
where: H = high-order bit (8)
L = low-order bit (4)
0 = bit permanently wired low (4)
Thus, a complete read of the AMMlA requires that a high and low byte be read. Converting the high
and low bytes to a full A/D count can be performed as follows:
RES = (256 * HIBYTE) + LOWBYTE
The equivalent voltage can be calculated by multiplying RES by the bit value for a 16-bit conversion
referenced to the A/D converter range. Consult the following examples:
Assume a decimal value for HIBYTE of 170, and 48 for LOWBYTE. RES can be calculated as:
low byte
RES = 170956 i- 48
RES = 43568
1. For an A/D range of +lO volts, calculate the corresponding voltage reading as:
V = (RES X. 20/65536) - 10
V = (43568 + 20/65536) -10
V = 3.296V
2. For an A/D range of O-10 volts, calculate the corresponding voltage reading as:
v = (RES + 10/65536)
V = (43568 * 10/65536)
V=6.648
AM-MA-3
AMMI A High-speed Acquisition Mode with the ANINQ Command (KDACXOO)
The ANINQ command can operate the Ah4hJlA module in a high-speed “auto-acquire” mode at an aggregated throughput rate of up to 62.5kI-I~. Auto-acquire applies to single or multiple channels. For
multiple channels, the per-channel scan rate equals 62.5lcJ& divided by the number of channels.
The analog input modules AIM2 and AlM3A can also provide up to 62.5kHz throughput when these
modules are used in a system containing an AMMIA.
To operate the AMMlA in auto-acquire mode, you must satisfy the following requirements:
1. The analog input channels sampled by ANINQ must be on an AMMlA, AIM& or AIM3A.
2. All channels sampled by the specific ANINQ command must be on one module.
3. The AMMlA’s input filter must be set to 1001612.
If any of these conditions cannot be met, the speed of an ANINQ command will revert to the speed of
a BGREAD command. Under these circumstances, it is better to use BGREAD in order to take advantage of foreground/background operating mode.
NOTE: The ANlNQ command in KDAC500 has been optimized for auto-acquire operation with the
AMMIA. If you attempt auto-acquire mode with BASIC’s PEEK/POKE, or the memory READ/WRITE
commands of other languages, you may receive incorrect data. If you do not use KDAC500, Keithley
suggests that you run the AMMlA only in “regular acquisition mode”. This mode is described under
the heading “SELECT ACQUISlTION MODE” later in this manual.
Self-calibrating During “CALL KDINIT” (KDACSOO)
The AMMlA module performs a calibration of the A/D gain and range each time KDINlT is called.
KDAC500 executes the KDlNlT function automatically each time it is loaded. KDAC500 will expect an
Ah4MlA module in the system if the configuration file (CONFIG.TBL) shows an AMMlA in slot 1. If
the software cannot complete the calibration, it will issue an error message such as “Unable to calibrate
A/D module”. If this occurs, check that:
1. The data acquisition hardware is turned on.
2. The cable between the hardware and the host computer is connected.
3. An AMMlA module is mounted in slot 1 of the data acquisition system
AMMlA-4
Connection and Operation
Signal Connection
The Ah4MlA can be programmed for either differential or single-ended local input configurations.
These local input signals are applied to screw terminals located toward the rear portion of the AMMIA.
Single-ended and differential inputs use the same screw terminals.
The channel numbers are shown in Figure 1. Figure 2 shows typical connections for channels 0 through
7 in differential mode. For differential mode, connect the high (-I-) side of an input signal to the (+> terminal, and the low (-> side of the signal to the corresponding (-) terminal. When the AMMlA is configured for single-ended input,
through 15, and the low (-1 side to the module ground at either end of the terminal strip. In Figure 2, the
numbers listed in parentheses above the lower connector are the single-ended local channels 9 through
15.
conzlect
the high (+) side of the input signal to one of the terminals 0
Series 500
Chassis Ground
Figure 2 Typical Differential Connection (Channel 0 Shown)
Measured
Voltage
AMMlA-5
CAUTION: The AMMlA inputs are non-isolated. In single-ended mode, one side of the input is
connected to power line ground. Any signal connected to the AMMlA must also be referenced to
power line ground, or module or system damage may occur Also note that inaccuracies on other
channels may result. When used in differential mode, the AMMlA local inputs must both be within
HOV of module ground for proper operation. If either signal exceeds k3OV module damage may result.
In many situations, shielded cable may be required to
minimum. If shielded cable is used, connect the shield to ground only, and do not use the shield as a
signal-carrying lead. Usually, a module ground terminal should be used, but in some cases better results may be obtained by using one of the baseboard ground posts. Use the configuration that results in
the lowest noise.
For shielding to be effective, the shield must contain both high and low signal wires, and must not carry
any other signals. If a number of AMMlA signal input lines are shielded, all shields should be connected to the same ground terminal.
minimize EMI radiation, or to keep noise to a
Signal Conditioning
Figure 3 shows a simplified block diagram of the MIA. The module is divided into six general sections: a local multiplexer, a local programmable gain amplifier, a global multiplexer, a global programmable gain amplifier, a programmable low-pass filter, and a 12-hit A/D converter.
Local input signals from channels 0 to 15 are applied to the local multiplexer for selection. At any given
time, only one channel will be selected, as determined by the SELECT CHANNEL command (covered
later in this section). The signal from the selected channel is then routed through a local programmable
gain amplifier to the global multiplexer for further signal selection and conditioning.
AMMlA-6
The global multiplexer selects a single signal from among the 10 slots in the 500 series chassis. In this
manner, signals from any of the 10 slots can be selected by software. The global multiplexer is controlled
by
the SELECT
its hardware manual for information on how the global multiplexer selects signals from slot 3 and from
the 3B channel connector.
After the signal is selected, the Global PGA applies softwareselectable gains of xl, x2, x5, or x10. The
signal finally passes through a one-pole filter with software selectable -3db frequencies of either lOOkI&
or 2kH.z. When this signal conditioning process is complete, the signal is routed to the 12-bit A/D converter for digitization. After the conversion process, digital data representing the applied signal travels
via the baseboard and interface card to the host computer.
SLOT command, discussed later in this section. Users of the 575 or 576 should consult
Local
Prcgrammable
Gain Amplifiir
16 Single-ended or
8 Differential
Inputs
(input Mode
Programmably
Selected)
Programmable
Lccal
Channel
Selection
Gr--l
LOCAL
MUX
LQ
ti
Analog Inputs
From Other
Slots
DC1 orX10)
~
GLOW
MUX
iL
J
Global
Programmable
Gain Amplifier
(Xl .X2.X5.OR
-
12BlT =
AID AND =
S/H Z
f
Programnable
Filter
(1ookHz OR
2kHz)
Figure 3. AMMlA Signal Conditioning
Input Filtering
Noise introduced into the input signal can corrupt the accuracy of the measurement. Such noise will
usually be seen as an unsteady reading, or, in some cases, as a constant offset. In the former case, the
effects of noise will usually be quite obvious, but may not be noticeable in
tion.
the
steady-state offset situa-
Frequently, noise is introduced into the signal from 50 to 6OHz power sources. In many cases, noise can
be attenuated by shielding or relocating the input signal lines, as discussed earlier. It may also be possible to reject unwanted 6OHz noise by using the AMMlA in differential mode. Since the 60Hz noise
may also be present on the low side of the signal, the differential amplifier will reject the common signal. In more difficult situations, however, it may be necessary to filter the input signal to achieve the
necessary noise reduction.
When noise is a problem, a single-pole low-pass filter like the one shown in Figure 4 can be connected
between the input signal and the corresponding AMMlA channel. Note that the filter is made up of a
single capacitor and resistor with the capacitor connected between the AMMlA channel input termi-
nals
and the module ground terminal. The resistor is then placed in series with the high input signal
lead.
From Signal
l
C-
--r
I
To AMMIA Input
Figure 4. Input Filtering
AMMlA-7
A common reference point for a simple filter like the one in Figure 4 is the -3dB or half-power point,
which is given
where f is in Hz, C is in farads, R is in ohms. Above this frequency filter response will roll off (decrease)
at a rate of -2OdB per decade. Thus, each time the frequency increases by a factor of 10, filter output voltage decreases by a factor of 10 (-20dB).
Although such filtering can quiet down a noisy signal, there is a tradeoff in the form of slower response. This response time may be important in the case of a rapidly changing input signal. For the filter
in Figure 4, the response time to 1% of fmal value is 4.6RC, while the response times to 0.1% and 0.01%
of final value are 6.9RC and 9.2RC, respectively.
As a example, assume that 10 counts of 6OHz noise is present in the input signal. To reduce the noise to
one count, an attenuation factor of 10 (-20dB) at 6OHz wiIl be necessary. Thus, the filter should have a 3dB point of 6OHz.
To determine the relative RC values, the above equations can be rearranged to solve for either R or C.
If we wish to choose a nominal capacitor value and then solve for the resistance, we have:
as
follows:
fsMB = 1/(27cRC)
R = 1/(2rrCf,,)
Choosing a nominal value of 2@ for C, the necessary resistance is:
R=1/(2xx(2xW)x6Hz)
R = 13.263k
The resulting response times with these R and C values would be:
t(l%) = 4.6RC = 122ms
t(O.l%) = 6.9RC = 183ms
t(O.O1 %) = 9.2RC = 244ms
Note that there are a number of RC values that can be used in a given situation. To minimize the effects
of the series resistance, however, it s recommended that the value of R be kept under 2OwZ.
Current-to-Voltage Conversion
AMMlA local inputs are designed to accept voltages in the range of +lOV. Thus, the AMh41A can be
directly connected to many signal sources. Some transducers and instrumentation, however, provide
current outputs that must be converted into voltages in order to be measured through an AMMl Ainput
channel.
AMMA-
When connecting current inputs to the AM&$1 A, a resistor should be installed across the input to make
the necessary current-to-voltage conversion. J4, J5, and J6 provide locations for installing these resistors
on the AMMlA. Refer to the circuit schematic and board layout diagrams for header information.
The value of the resistor can be determined from Ohm’s Law as follows:
R=E/I
Where R is the resistance in ohms, E is the maximum desired voltage in volts (usually the upper range
limit of the A/D converter), and I is the maximum anticipated current in amps.
As an example, assume the A/D converter range is zero to +lOV and that the expected current lies in
the range of four to 4OmA. The required resistance is:
R = 10/0.04
R=250
Thus, a 25OQ resistor should be installed across the input of the channel in question (note that a 25OQ
value is required when using KDAC500 engineering units conversion). Since current measurement accuracy is directly related to the accuracy of the resistor, use the smallest tolerance resistor available (typically 0.1%). Suitable 25OQ precision resistors can be purchased from Dale Resistors, (P/N
RN55E2500B), or from Keithley (P/N 500~RES-250).
Analog-to-Digital Converter Timing
When programmin g high-speed sampling sequences, certain timing constraints concerning the A/D
conversion cycle should be observed. Depending on the AMMlA’s acquire mode, the scenario for receiving converted values from the A/D is very different. Refer to the discussion of the acquire modes
below for specific instruction on how to process analog signals.
To increase system throughput, data latches have been provided on the AMMl A, making data from the
last conversion available while the converter is busy processing another reading. The data is refreshed
(updated) every time a conversion has been completed.
External Trigger Operation.
The AMMlA has the capability of triggering an acquisition from an external TI’L-level source. The
jumper on the AMMlA 03) dictates the triggering source. The external trigger can only be used in
62.5kHz auto acquire mode which is explained below in the SET ACQUISITION MODE command discussion.
When the AMMlA is in 62.5161~ auto acquire mode, the trigger source can be set to either external or
internal by the J3 jumper. When set for internal triggering, the AMMlA continuously converts analog
signals as described below in the SET ACQUISITION MODE command discussion. When the J3 jumper
is removed, a TTL-level gating signal can be attached to pin 2 of the jumper header. A low level applied
to pin 2 will enable the continuous conversion process, a high level applied to pin 2 will suspend the
AMMlA-9
continuous conversion process. In either case, the application program must synchronize itself to the
conversion process by polling the conversion status
command discussion.
The pm configuration of the jumper header is as follows:
pill1 Special trigger output - valid only when using TRGl
pm2
pm3 OV (ground) - for internal triggering
The J3 jumper should be across pins 2 and 3 for internal trigger operation. The jumper should be re
moved and the external gating source should be connected to pin 2 for external gate operation. The J3
jumper should be across pins 1 and 2 if a TRGl analog trigger module is being utilized.
Commands
Table 1 summa rizes the commands used with the AMMlA. Note that several commands share the
CMDA and CMDB locations. Some commands use only selected bits in the command byte, others are
differentiated by whether a read or write operation is performed.
as explained in the SELECT ACQUISlTION MODE
trigger input
Table 1. Commands Used with the A.&M&l
5001575
Command
SELECT CHANNEL
SELECT LOCAL CHANNEL MODE
SELECT LOCAL GAIN
SELECT ACQUISITION MODE
SELECT HLTER
SELECT SLOT
SELECT CMDA READ MODE
SELECT RANGE
SELECT GLOBAL GAIN
RESET AND RECAL
A/D LOW DATA*
A/D STATUS
A/D HIGH DATA
A/D START
EOC (end-of-conversion) STATUS
The information read from CMDA is selected by the SELECT Ch4DA READ MODE command. Refer to the sections
below for the full description of their operations.
Address Signal Line
xxx80
XX&O
XXX80
xxx80
xxx81
xxx81
xxx81
xxx81
xxx9A
XXX80
XXX80
xxx81
xxx9B
xX&B
CMDA (Write)
CMDA (Write)
CMDA (Write)
CMDA (Write)
CMDA (Write)
CMDB (Write)
CMDB (Write)
CMDB (Write)
CMDB (Write)
CMDC (Write)
CMDA (Read)
CMDA (Read)
CMDB (Read)
CMDD (Write)
CMDD (Read)
Bits Used
DO-D3
D4
D5
D6
D7
DO-D3
lx
D5
D6-D7
ALL
ALL
ALL
ALL
ALL
ALL
AMMIA-10
The “xxx” in the 500/575 address column sign&s the three hexadecimal digits that make up the base
hardware
card. The suggested address is &HCFF80, so “xxx” = “&HCFl?‘.
address
which is either switch selected or programmed on the IBIN-A or IBIN-F’S/2 interface
Select Channel, Local Gain, Filter, Acquisition Mode, and Channel Mode.
D71D6ID5lD4031D2IDlIDO
) 4 4 4-
/
Select Slot, Range, Global Gain, and CMDA Read Mode.
D71D6 ID51 D41D3 1021 DllDO
V
t-
Channel Select: SE (O-15), DIFF (O-7)
Channel Mode: Single-ended (l), DIFF (0)
Local Gain: Xl (0), Xl 0 (1)
ACQ Mode: 62.5kHz Auto Acquire (I), Regular Acquire (0)
Filter Mode: 1 OOkHz (0), 2kHz (1)
Figure 5. CMDA Write Format
Byte Format
CMDA Read Mode: A/D Status (0), Low Data (1)
Select Range: -1 OV fl OV (l), 0 fl OV (0)
Select Global Gain: Xl (0), X2 (l), X5 (2), X10 (3)
I
Figure 6. CMDB Write Format
SELECT CHANNEL
Location: xxx80
The SELECT CHANNE L command is used to control the local signal multiplexer on the AMMl A, thus
determining which of the local input channels is selected for A/D conversion. This command affects
only those signals connected to the AMMlA local inputs, and does not affect input channels connected
to modules located in other slots. SELECT CHANNE
SLOT command to select the channels on the AMMlA to be measured.
Note that the channel number occupies the least significant four bits of CMDA. Make sure that the channel number is combined with the appropriate upper four bits, as shown in Figure 5, before it is sent.
L must be used in conjunction with the SELECT
AMMIA-11
SELECT LOCAL
Location: xxx80
The SELECT LOCAL CHAbINE L MODE command controls the configuration of the local input chan-
nels on the AMMl A. The AMMlA input channels can be configured as either 16 singleended or eight
differential input channels. This command is selected by assigning a value to the D4 position of CMDA
as shown in Figure 5. A value of 1 will set the inputs to singleended, a value of 0 will set them to differential.
Make sure that the other bits in the CMDA byte represent the desired selections before it is sent.
CHANNEL MODE
SELECT LOCAL GAIN
Location: xxx80
The gain applied to the local channels of the AMMlA is programmable and can be set by assigning a
value to bit position D5 in CMDA. As shown in Figure 5, a value of 0 will apply a local gain of Xl and
a value of 1 will apply a local gain of Xl0 to the AMMlA input channels.
The local gain can be changed at any time as long as the channel settling time is satisfied before the conversion is started.
Make sure that the other bits in the CMDA byte represent the desired selections before it is sent.
SELECT ACQUISITION MODE
Location: xxx80
The AMMlA has the capability of operating in either of two modes; the regular acquisition mode, and
the 62.5kHz auto acquisition mode. As shown in Figure 5, the acquisition mode is set by assigning a
value to bit position D6 in CMDA. Assigning a value of 0 enables regular acquisition mode, a value of
1 enables 62.5kHz auto acquisition mode.
To acquire an analog reading when in the regular acquisition mode, the slot, channel, and gain must be
selected. Then, after the appropriate settling time, the AMMlA is issued a START CONVERSION command. At this time, the AMMlA latches the signal and starts the digitization process. The EOC STATUS
command can be polled for end-of-conversion (EOC) after which the digitized value can be read. The
conversion process will consume approximately 16usec.
Since the incoming signal is latched when the START CONVERSION command is issued, the slot, channel, and gain selections can be changed immediately after the command is issued. This will allow the
settling time for the new selections to be satisfied concurrently with the conversion of the previous selection. This type of operation is not required but will increase the throughput capability of regular acquisition mode.
Ah4MlA-12
The auto acquisition mode allows full 62.5kHz’acquisition speed on analog signals. Upon placing the
AMMlA in this mode, the A/D enters a freerunnin
g 62.5kHz conversion process. Do not attempt to
issue the START CONVERSION command in this mode.
Some microcomputers may not be capable of keeping up with the AMMlA in auto acquire mode. If the
AMMlA outpaces your microcomputer, the data points will be unreliable.
After the completion of a conversion, the AMMlA begins the next conversion immediately The EOC
STATUS command can be used to synchronize your program with the conversions. The conversions
will take place on the slot and channel that are presently selected at a rate of 62.5kHz. The conversion
status bit will be reset by the reading of either the high or low A/D data bytes. Figure 7 shows the timing
for single channel auto acquire operation.
Read High
Byte
I
Completed
1
Figure 7. Single Channel Auto Acquire Timing
While in auto acquire mode, the EOC status bit will become true (low) after the first A/D conversion.
Even though the next conversion begins immediately, the status bit remains true until the A/D data is
read. If the data is not read, it is overwritten.
Figure 8 shows a example of the EOC status being polled only after one or more conversions have taken
place. Even though the EOC status bit indicates that the conversion is complete, there is no way of telling if another conversion is about to be completed. Trying to read the data while the latches are being
updated will cause unreliable results- To guarantee reliable readings, your program should synchronize
itself with the AMMlA by taking a dummy reading to clear the conversion status bit. The next time the
status bit indicates the end of a conversion, the data at the A/D latch will be valid for the full 16usec.
For multichannel auto acquisition operation, all of the settling times for the new channel must be satisfied 4pec before the EOC takes place. If it is not settled, it may be necessary to throw away a reading
or two until it has settled. To
maxim&z
gain selection, and channel selection take place directly after the EOC becomes true.
e the available settling time, it is recommended that slot selection,
AMMlA-13
EOC Status
Bit (CMDD)
Poll EOC :
Bit Status (CMDD)
Although the converter status indicates
a
completed conversion here, reading the data
might be coicident with an update of the
1 St
Conversion
-f
I
, I
I
data from the converter.
2nd 3rd
Conversion
k
I
I
b
\
I
Data in the ND
Latch is Updated Here.
Figure 8. PoIling the Status Bit After One or More Conversions
For optimum operation follow these steps:
1. Monitor the EOC status bit until an end-of-conversion is sensed.
2. Select a new gain, a new slot, and a new channel, as needed.
3.
Read
the latched data
from the last conversion.
Conversion
,/
I
t
,
b
\
The EOC status bit
remains low until the
High or Low data are read.
A timing
diagram for multichannel operation is shown in
EOC Status
Bit (CMDD)
Poll EOC
BitStetus(CMDD) . ,
Gain
Select
Slot
Select
Channel
Select
Read Low
Byte
Read High
Byte
A Date Ready
I
Chdnel
for Chekel
settling time] ! 7
B
f 1
Read
Channel
A
\
cilarlnel
B Date Ready
Figure 9.
J
for Chektel
\
C
I
1
I
1
1
f-f
1
\’
Read
CflZl~l
B
AMMlA-14
Figure 9. Multichannel Operation in Auto Acquire Mode
Even though the AMMlA is capable of digitizing analog signals at 62.5kHz, some modules in the Series
500 module library are not capable of settling at these speeds. When doing multichannel acquisition,
consult the individual module’s hardware manual for appropriate settling times.
SELECT FILTER
Location: ~xx80
Two filters are available in the AMMIA; a 1OOkHz filter, and a 2kHz filter. These filters restrict the band-
width of the incoming signal, rejecting either noise or unwanted high frequency components that may
create aliasing.
It is desirable to reject all signal frequency components that are greater than l/2 the sampling frequency.
These frequency components cause aliasing which produces inaccurate waveform representation. The
filters are designed to reject frequencies above 1OOkHz or above 2kHz, depending on the filter used. The
1OOkHz filter, while not providing complete protection against aliasing, does reduce the system noise
with a minimal effect on settling time.
Assign a value of 0 to bit position D7 in CMDA to select the 1OOkHz filter, assign a value of 1 to select
the 2kHz filter.
Make sure that the other bits in the CMDA byte represent the desired selection before it is sent.
SELECT SLOT
Location: xxx81
The SELECT SLOT command controls the global multiplexer on the AMMl A, selecting the appropriate
slot on the Series 500 baseboard from which to read the input.
The value to be written to the SELECT SLOT location occupies the four least significant binary digits of
the command. Make sure that the slot number is combined with the appropriate upper four bits as
shown in Figure 6 before it is sent.
As indicated in Table 2, there are other values besides slot numbers that can be written to this location.
These values select ground, +5V, and +lOV sources and are intended primarily for diagnostic purposes.
AMMlA-15
Table 2. Values Written to the SELECT SLOT Location
Function
Ground (0 volts)
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9
Slot 10
Reserved
Reserved
+lOV Reference
Ground (0 volts)
+5V Digital Power Supply
SELECT CMTIA READ MODE
Location: xxx81
Binary
bbbbOOO0
bbbwoO1
bbbbOOl0
bbbbOOl1
bbbbOlO0
bbbbOlO1
bbbbO110
bbbbOll1
bbbblOO0
bbbblOO1
bbbblOl0
bbbbloll
bbbbllO0
bbbbllol
bbbblll0
bbbbllll
This command selects the usage of the CMDA read. Two types of information can be read from CMDA
(note that this affects only the read operation of CMDA), these are, the low data byte of the A/D or the
A/D status. In the low data byte mode, CMDA supplies the low byte of the A/D readings. In the A/D
status mode, CMDA supplies status directly from the A/D. The A/D status is described further in the
sections below.
NOTE: When the CMDA read mode is set to A/D status, a reset and recal sequence will be initiated by
any start conversion comman d. The start conversion command can come either from a write to CMDD,
or from the auto acquire mode hardware if this mode has been enabled by a value of 1 in bit position
D6 of CMDA. To avoid accidentally initiating a reset and recal sequence, be sure bit position D6 of
CMDA is set to a value of 0 before changing the CMDA read mode to A/D status. Do not write to
CMDD or change D6 of CMDA to a value of 1 as long as the CMDA read mode is set to A/D status.
Assign a value of 0 to bit position D4 in CMDB to read A/D status from CMDA, assign it a value of 1
to read the A/D low data byte.
Make sure that the bit is combined with the other appropriate bits as shown in Figure 6 before it is sent.
AMMlA-16
SELECT RANGE
Location: xxx81
The AMMIA has two programmable ranges; +lOV (bipolar 1OV) and zero to +lOV (unipolar 1OV). As-
signing a value of 0 to bit position D5 in CMDB will select the AMMlA unipolar 1OV range, assigning
a value of 1 will select the bipolar 1OV range.
Make sure that this bit is combined with the other appropriate bits as shown in Figure 6 before it is sent.
SELECT GLOBAL GAIN
Location: xxx81
The GLOBAL GAIN command controls the PGA Wrogrammable Gain Amplifier) located on the
AMMIA module. Since all analog inputs are processed by the PGA, the GLOBAL GAIN command affects every analog input connected to the Series 500. This command is issued in combination with other
commands on CMDB. The GLOBAL GAIN value occupies the two most significant bits of CMDB and
must be combined with the other bits of the CMDB byte before it is issued.
Four programmable gain values, xl, x2, x5, and x10, are available with the PGA. These gains are selected by setting the appropriate bits in CMDB before it is issued.
Table 3. Values Written to the GLOBAL GAIN Location
PGA Gain
Xl
x2
x5
x10
BiIla.ly
OObbbbbb
01 bbbbbb
1Obbbbbb
llbbbbbb
RESET AND RECAL
Location: xxx9A
The RESET AND RECAL command starts the internal A/D calibration process. The process takes ap-
proximately 36Omsec and should be completed once every time the system is powered up.
After issuing this command, wait at least 360msec before any conversions are attempted. To make sure
that the calibration has taken place, set the CMDA read-mode to A/D status, as described above. The
bit configuration of the calibration status is described below. This bit can be polled to make sure calibration has been completed.
This command has no specific data associated with it, any value sent will start the calibration process.
AMMlA-17
AfD LOW DATA-A/D STATUS
Location: xxx80
The contents of CMDA depends on the state of the AMMlA set by the SELECT CMDA READ MODE
command. If D4 of CMDB has been set to 0, CMDA returns the A/D status of the AMMIA. If D4 has
been set to 1, the low byte of the A/D counts is returned in CMDA.
When AMMlA is in the A/D status mode, the bit configuration of the CMDA byte is as follows:
Do
Dl
D2
D3
D4
D5
D6
D7
none
none
none
none
none
TRACKING (1 =tracking in process, O=tracking stopped)
CONVERTING (l=conversion in process, O=no conversion in process)
CALIBRATING (l=calibration in process, O=calibration not in process)
After the A/D completes a digitization of an analog signal, it begins a process called tracking. The
A/D consumes 4l.~x for the analog signal at its input to be tracked to the specified accuracy. The time
relationship between the TRACKlNG bit and the EOC bit in CMDD is shown in Figure 10.
The converting bit indicates the actual A/D conversion status. The time relationship between the
CONVERTING bit and the EOC bit in CMDD is shown in Figure 10.
Won1 Reset Until
Data is Read
EOC Bit
in CMDD
Tracking Bit
in CMDA
Converting Bit
in CMDA
F
I
I
I
I
t
‘U
16~s
Conversion
Begins
AMMIA-18
Figure 10. Time
Relationship of Status Bits
The CALIBRATING bit returns the status of a RESET AND RECAL command as described above.
If the AMMlA is in the low data mode, the byte received is the low byte of a 16 bit A/D conversion.
However, the 4 least significant bits will be set to 0, thereby providing 12-bit resolution effectively Since
the module incorporates data latches, one conversion may be read while another conversion is in
progress. To find out when data from one conversion is available, use the A/D START/EOC STATUS
command, discussed below.
Reading this location resets the EOC status.
ND HIGH DATA
Location: xxx81
The A/D HIGH DATA command performs essentially the same function as the A/D LOW DATA com-
mand, except that the high data byte is returned. Since the AMMlA’s 12-bit resolution is actually the
resuh of setting the four least significant bits of a l&bit conversion to 0, all of the bits in the high data
byte of an AMMlA are sign&ant.
Once both the low and the high data bytes have been obtained, the total number of counts representing
A/D converter data can be determined using the following formula:
CO = DL + 256*DH
CO represents the number of counts, and DL and DH are the low and high bytes respectively. With the
AMMlA, the number of counts will lie in the range of 0 to 65,535 minus 4 least significant bit’s worth,
or 0 to 65520.
Reading this location resets the EOC status.
A/D START
Location: xxx9B
The A/D START COMMAND starts the A/D conversion process. Writing to the A/D START location
will trigger (start) the A/D conversion cycle. Although any value (O-255) can be written to trigger a conversion, a value of 255 should be used to minimize noise. Do not issue an A/D start command while in
auto acquisition mode or the internal tuning of the A/D will be skewed.
The A/D conversion cycle takes approximately 16pec. During this period, the converter should not be
m-triggered. Status of the conversion process can be checked by accessing the EOC STATUS command.
EOC STATUS
Location: xxx9B
The EOC STATUS command returns a byte of data which indicates the state of the conversion process.
The returned value will depend on whether a conversion has been completed (see Table 4).
AMMlA-19
Table 4. Values Read from the AID START/STATUS Location
EOC Status Bi.tlaly
Calibration
Conversion in process
End-of-conversion OXXXXXXX
This section contains calibration procedures for the AMMlA module. The procedures include programs which have been written with BASIC’s PEEK and POKE commands for use on a Series 500 or
575. Note that these procedures are intended for the field and may not be as accurate as those used in
the factory. If you are not familiar with calibration equipment, do not attempt AMMlA calibration.
This procedure presumes that the unit is in working condition and at least one factory calibration has
been done in the past. An additional procedure is necessary to select R2.5, R26, R27 and R28 if the volt-
age reference U13 has been replaced. The procedure for replacing U13 is described after the section on
troubleshooting.
lxxxxxxx
Environmental Conditions
Calibration should be performed at an ambient temperature of 23’C (f5”). Turn on the system power
and allow it to warm up for at least 10 minutes before beginning the calibration procedure.
Recommended Calibration Equipment
The following equipment is recommended for AMMlA calibration. Other equipment may be used as
long as the corresponding specifications are at least as good as those given below.
1. Keithley Model 196 DMM (0.005% basic DC accuracy).
Key specs needed on DMM:
DC accuracy of 60 ppm on a 1OV reading.
Sufficient resolution to read one microvolt offsets.
2. EDC Model ElOOC Millivolt Reference Source (0.005% accuracy).
Key specs needed on source:
Provides an output between 0.5 and 0.99 vohs.
Maintains its output stable to 10 ppm for five minutes.
Ovetiew of Adjustment Sequence
1. Adjust IOV reference.
2. Adjust 4V reference.
3. Adjust Global Amp offset.
4. Adjust attenuator offset.
5. Adjust both Local amp offsets.
6. Adjust Local amp Xl0 gain.
7. Tweak A/D gain with 4V reference adjustment.
AMMI A-20
Calibration Procedure
The test points, potentiometers, and connectors referenced in the procedure are shown in Figure 1.
Adjust 1OV reference
Connect the DMM high lead to TP7 (1OV). Connect the DMM low lead to TP4 (AGND). Select DCV
1.
and autoranging.
2. Adjust pot R7 for lO.OCQO volts +lOOj.tV.
Adjust 4V reference
The following procedure will bring the 4V reference within range so that it can be calibrated accurately
later.
Connect the DMM high lead to TP8 (4V). Connect the DMM low lead to TP4 (AGND). Select DCV
1.
and autoranging.
2. Adjust pot R8 for 4.000 volts +lmV. This adjustment will be tweaked later.
Adjust Global Amp offset
1. Connect the DMM high lead to TP9. Connect the DMM low lead to TP4 (AGND). Select DCV and
autoranging.
2. Select the PGA gain of X10 and the zero voltage reference input by POKEing a value of 192 to
CMDB of slot 1 and a value of 0 to CMDA of slot 1.
3. Adjust pot R9 for zero volts +10j~V.
Adjust attenuator offset
1. Select the Xl global gain and the zero voltage reference input by POKEing a value of zero to both
CMBA and Ch4DB of slot 1.
Connect the DMM high lead to TPlO. Connect the DMM low level to TP9. Select DCV autoranging.
2.
3. Adjust pot RlO for zero volts +10j.~V.
Adjust both Local amp offsets
Connect a short jumper wire between differential channel 0 high input and signal common (termi-
1.
nals 9 and 10 on Jl). Connect a short jumper wire between differential channel 0 low input and signal common (terminals 1 and 2 on J2).
Connect the DMM high lead to TP3. Connect the DMM low lead to TP4. Select DCV and autorang-
2.
ing.
3. Select differential input and Xl gain by POKEing a value of 0 to CODA of slot 1.
Record the DMM reading as Vout(l) for use later.
4.
Select a gain of X10 by POKEing a value of 32 to CMDA of slot 1.
5.
6. Record the DMM reading as Vout(2).
7. Compute the offset contribution of U6 as follows: V, = (lO*Vo,(l) - V,(2))/9.
8. Adjust pot R5 so that the DMM reads the voltage computed for V,.
AMMl A-21
9. Select the Xl gain again by POKEing a value of zero to CMDA of slot 1.
10. Adjust pot R6 for a DMM reading of zero volts +lOpV If desired, the adjustment can be
checked by once again outputting data: CMDA = 32. The DMM should read zero volts
k1OO~V
Adjust Local amp X10 gain
1. Remove the jumper between terminals 9 and 10 of Jl that was installed in previous step.
Connect voltage source (+) output to terminal 9 of Jl, and the voltage source (-) output to
terminal 10 of Jl. Leave the jumper installed between terminals 1 and 2 of J2.
2. Connect the high lead of the DMM to TP3. Connect the low lead of the DMM to TP4. Select
DCV and autoranging.
3. Set the voltage source to a value of 0.99 volts.
4. Select the X10 gain by POKEing a value of 32 to CMDA of slot 1.
5. Adjust pot R4 for a reading of 9.9 volts.
Tweak A/D gain with 4V reference adjustment
1. Use the test setup from the previous step. The DMM should be reading a voltage of approx-
imately 9.9 volts on TP3.
2. Select channel 0, local gain of X10, differential input, filter on QkHz), slot 1, unipolar 1OV
range, and global gain of Xl by POKEing values of 160 and 17 to CMDA and CMDB respectively.
3. Run the following BASIC program. This program assumes that the hardware address in
CFFO, if this is not the case, adjust line 10 for the proper address.
10 DEF SEG = tiCFF0
20 CMDA = &h80: CMDB = &h81
30 CMDC=ti9A:CMDD=&h9B
40 POKE CMDA, 160
50 POKECMDB, 17
60 POKE CMDD, 255
70 WHILE PEEK(CMDD) > 127 :WEND
80 TOTAL = PEEKCCMDA) + PEEK
CMDB)*256
90 VOLTS = TOTAL * 0.00015258
100 LOCATION 1,l:PRINT VOLTS,
110 GOT060
*Presumes interface is set to address CFFSO(h).
4. Adjust pot R8 so that the displayed voltage equals the DMh4 reading.
hardware segment*
‘set up from step 2 above
‘set up from step 2 above
‘start conversion
‘wait until conversion is complete
‘get high and low data and combine
‘print value in volts
AMMlA-22
Theory of Operation
For the following discussion, please refer to the schematic diagram, drawing number 501-196.
AMMlA circuitry is divided into the following sections: local input multiplexer, programmable gain,
global input multiplexer, global gain amplifier, filter, A/D converter, A/D voltage reference amplifier,
and the IO-volt global reference.
Local Input Multiplexer
The local input multiplexer is made up of two 8 to 1 analog multiplexer Ul and U2, a dual analog switch
U3, and input protection resistor networks Rl and R2. The digital control signals for the input multiplexer are latched by U19, and additional digital logic to control the differential/single-ended mode selection is in the PAL, U18. When the single-ended mode is programmed, U3 grounds the inverting input
of the differential instrumentation amplifier (pin 3 of U7), and connects the output of both Ul and U2
to the non-inverting input of the differential instrumentation amplifier (pin 3 of U5). The selected input
is switched through the appropriate 8 to 1 multiplexer to the differential amplifier input while the output of the other 8 to 1 multiplexer is open circuited. When the differential input mode is selected, U3
connects the output of U2 to the inverting input of the differential instrumentation amplifier (pin 3 of
U7). The output of Ul is always connected to the non-inverting input of the differential instrumentation
amplifier (pin 3 of U5). The selected input channel -CH
terminals is connected through Ul to the local amplifier inputs.
erminal is connected through U2 and the +CH
t
Local Programmable Gain Amplifier
U4, U5, U6 and U7 make up the local programmable gain amplifier. U5 and U7 provide the high input
impedance, and also provide the voltage gain when the X10 gain is selected. When Xl gain is selected,
U4 (a dual analog switch) connects both U5 and U7 in the voltage follower configuration. When Xl0
gain is selected, U4 connects the inverting inputs of U5 and U7 to the taps on a voltage divider connect-
ed across the outputs of U5 and U7. The voltage difference between the inverting inputs of U5 and U7
is 1 /lO the voltage difference between the outputs of U5 and U7. This arrangement gives a voltage gain
of 10 for differential input signals and a voltage gain of 1 for common mode input signals. The common
mode input signal is defined as the average of the +CH and -CH input signals. The voltage gain in the
X10 mode is adjusted with R4, which adjusts the voltage divider ratio. The voltage gain in the Xl mode
is not adjustable. The outputs of U5 and U7 are connected to the precision resistor network Rll and am-
plifier U6. Rll and U6 make up a unity gain differential amplifier, which amplifies the differential signal
and rejects the common mode signal. The output of U6 is the overall amplifier output, and consists only
of the differential signal between U5 pin 3 and U7 pin 3.
Global Input Multiplexer
The global multiplexer selects which signal is measured by the A/D converter. U8 is a 16 to 1 analog
signal multiplexer. Inputs 0 and 14 of U8 are connected to ground. Input 1 is connected to the output of
the local amplifier. Inputs 2 through 10 go to pins on P14, and by external connections, are connected to
slots 2 through 10 of a Series 500 mainframe. These connections will carry the output signals of other
signal processing cards to the global multiplexer, where they can be routed to the A/D converter for
measurement. Inputs 11 and 12 also go to J14, but are typically not used. Input 13 is connected to the
IO-volt reference, and input 15 is connected to the +5-volt digital power supply The output of the mul-
tiplexer is connected to the Global Amplifier input.
Ah4MlA-23
Global Programmable Gain Amplifier and Filter
The global programmable gain amplifier is made up of U9, UlO, and Ull. The voltage gain of U9 is de-
termined by which tap on the precision resistor network R14 is selected by the analog multiplexer Ull.
The available gains are Xl, X2, X5, and X10. R14 is a voltage divider connected to the output of U9, and
the tap determined by Ull is connected to the inverting input of U9. The non-inverting input of U9 is
the overall input of the circuit. At the output of U9,lO volts represents a fuh scale input. The A/D converter used cannot convert an input above 4 volts, so that output of U9 is reduced to 40% of its full scale
output by a divider made up of R15, R16, and R17. The analog filter is applied after this divider, and is
made up of C7 and R18 along with the combined resistance of the divider. For the 21612 pole, all resistors are in the circuit, but when the 1OOkHz pole is programmed, FET Q3 is turned on and bypasses R18.
The 1OOkHz pole is determined by the equivalent output resistance of the 40% divider and C7. UlO buffers the filter output and provides the low driver impedance required by the A/D converter. At the output of UlO, 4 volts represents a full scale input. CRl, CR2, CR3, and CR4 make up a clipping circuit to
prevent overscale inputs from saturating the A/D, thus allowing immediate overload recovery.
A/D Converter
The A/D converter, U12, is a 12-bit successive approximation converter with an internal sample and
hold. This converter is similar to the A/D converter on the 16-bit AMM2 module in that both converters
read as 16bit converters. Like the AMM2, the AMMlA returns a high and low byte. However, the four
lowest order bits from the AMMlA are zeros, thus providing 12 effective bits of resolution. U12 oper-
ates on +5 volts and -5 volts. These supplies are derived from the +15 and -15 volt analog supplies by
U21 and U22 respectively. The A/D determines the ratio of the analog input to the voltage reference
input. The voltage reference used is 4 volts. The digital outputs of the A/D reference input. The voltage
reference used is 4 volts. The digital outputs of the A/D are buffered by U16 and U17. The logic control
for the A/D is in the PAL, U18.
A/D Voltage Reference Amplifier
The A/D converter requires a voltage reference source with a low output impedance from dc up to several megahertz. U15, Ql, R8 and the associated components comprise an amplifier with the needed
characteristics. The reference voltage is derived from the heated zener reference U13 and divided down
to 4 volts by the divider made up of R8, R21, R22, and R24. Resistors R27 and R28 are used to restrict
the adjustment range of R8, and are either installed or not used based upon the zener voltage of Y13 at
the time of factory calibration. If U13 is replaced, it may be necessary to either install or remove either
one or both of these resistors. R31 and C6 frequency compensate the amplifier loop, and C9 is a titer
for zener noise.
10 Volt Global Reference
U13, U14 and the associated components form the 10 volt reference circuit. The zener voltage of approx-
imately 7 volts is ampli&cl by U14 to 10 volts. R7, R19, R20, and R23 determine the output voltage by
adjusting the gain of U14. R25 and R26 serve a function similar to R27 and R28 in the A/D reference
circuit. R30 and C8 filter the zener noise, and D7 assures that the circuit will start properly when power
is first applied.
AMhBA-24
AMMl A Troubleshooting Information
Diagnosing trouble with the AMMlA is best done in several steps. If the AMMlA is not functioning at
all, the following tests should be performed in the sequence indicated. It may be possible to skip some
of the tests if the AMMlA is partially functional.
A BASICA test program is listed at the end of this section which is used to setup the hardware for these
tests. Change line 10, if necessary, to the address segment used by your system. Each test is indepen-
dent, and can be run by itself if needed, as long as the first 3 lines of the program are also entered.
The overall test sequence is:
1. Check power supplies
2. Check reference voltages
3. Test digital control circuitry
4. Test local mux
5. Verify operation of local amplifier
6. Check operation of global amp
7. Test global mux
8. Verify operation of A/D converter
The only additional equipment needed for these tests is a digital multimeter (DMM), and two jumper
leads. When performing these tests, refer to schematic diagram 501-196, component layout 501-190, and
the following instructions for the connections to use while running the test program.
Test Sequence:
1. Check power supplies
Using a DMM on the 20-volt range, connect the minus lead to TP4 (AGND). The positive lead
should be used to test for the following voltages within ti.5 volts:
U7pin7
U7pin4
TP6 (DIG GND)
U18 pin 24
u12 pin 25
u12 pin II
u12 pin 30
U12 pin 36
2. Check reference voltages
With the DMhJ minus lead connected to TP4 (AGND), use the 20-volt range to read the following
voltages:
+15
-15
0
+5
+5
+5
-5
-5
Tr14 (Vz) 7 H.25 volts
zener reference voltage
AMMlA-25
TP7 (1OVref)
TP8 (4V)
10.00 volts
4.0 M.2 volts
u14 output
U15 output, A/D reference voltage
3. Test digital control circuitry
Use the test program lines 300-395 to verify that the control registers are capturing the correct data.
Connect the minus lead of the DMM to TP6 (DGND) and touch the DMM plus lead to the pins indicated by the program.
If this test is completely unsuccessful, first verify that the rest of the system is functioning properly
before proceeding. The computer, IBIN interface card, 500 mainframe, and hardware address segment should be checked. If the rest of the system is functioning properly, or if only some of the pins
on U19 or U20 are not functional, check Ul8, U19, U20 and the K’s connected to the nonfunctional
pins.
4. Test local mux
The local mux can be checked by putting a signal through each of its channels. A convenient signal
is the 4-volt reference tested in step 2. The test program lines 400-490 will help perform the test.
Connect a test lead to TP8 (4V) and connect the other end of this test lead to the input on Jl or J2 as
indicated by the program. Connect the DMh4 - lead to TP4 (AGND), and the + lead to TPl or TP2
as indicated by the program. Run the program. The DMM should show the 4-volt signal on the indicated test point when the input indicated by the program is touched with the 4V test signal.
5. Verify operation of local amplifier
Proper operation of the local amplifier can be tested by applying a voltage difference of one volt to
its input and looking for an output of one volt on the Xl gain range and 10 volts on the X10 gain
range. A one volt signal can be obtained by connecting +4V reference TP8 (4V) to -CHO on J2 pin 2,
and 15V supply TP12 (+5V) to +CHO on Jl pin 9. Connect the Dh4M + lead to TP3 and the - lead to
TP5 (SGND). Lines 500-580 provide the setup for this test.
6. Check operation of global amp
The global amp can be tested by using the one volt signal generated in step 5 above, and checking
that the correct output at TP9 occurs for each gain setting. The global mux channel 1 of U8 must be
functional for this test to work, so it is checked first. Connect a test lead from TP8 (4V) to J2 pin 2
and a second test lead from TP12 (+5V) to Jl pin 9. The DMM - lead co~ects to TP4 (AGND), and
the + lead to the TP indicated as the output in the test program. Lines 600-690 of the test program
are used.
7. Test global mux
The global mux is tested by applying a signal to each input and verifying that the signal appears at
the output. Since the global amp was tested in the previous step, any signal applied to the global
mux should show up at TP9. The slot inputs can be tested by applying the 4-volt reference signal
to the input under test. Other inputs to the global mux are hardwired to various signals as indicated
by the program. Setup the test as follows: Connect a test lead from TP8 (4V) to J2 pin 2 and a second
test lead from ‘IT?12 (+5V) to Jl pin 9. The DMM - lead connects to TP4 (AGND), and the + lead to
TP9. At the point in the program where a signal is required as an input to a pin on U8, disconnect
the end of the test lead on J2 pin 2 and use this end to touch the pin indicated by the program on
U8. Lines 700-790 of the test program are used.
AMMlA-26
8. Verify operation of A/D converter
The A/D converter is tested by inputting a signal from the local amp and displaying the reading. The
test setup uses the one volt test signal derived in step 5. The displayed voltage should be about one volt.
Connect a test lead from TP8 (4V) to J2 pin 2 and a second test lead from TP12 (+5V) to Jl pin 9. Lines
800-890 of the test program are used.
Replacement Procedure for U13
The heated zener voltage reference U13 requires a special calibration procedure if it is replaced. The
LM399 used for U13 has a wide tolerance for its initial zener voltage, but drifts very little with time or
temperature. Resistors R25, R26, R27 and R28 are used to trim out a large portion of the initial zener
voltage tolerance, with the balance of the adjustment done by potentiometers R7 and R8. The adjustment range of R7 and R8 is large enough to compensate for any drift in U13 over the life of the module,
but has been purposely restricted to improve the stability and adjustability of the voltage reference.
When U13 is replaced, the following procedure must be used to determine which two of the four resistors (R25,26,27,28) must be installed.
The procedure is to measure the zener voltage, c lead to TP14, - lead to TP4 (AGND), find the range on
the following table that includes this voltage, then install or remove the resistors indicated in the table
as required. Zener Voltage
6.78 to 6.90
6.90 to 7.01
7.01 to 7.11
7.11 to 7.23
-
-.open
49.9 K 61.9 K
open
49.9 K
Troubleshooting Test Program
10
20
30
300
310
320
330
335
DEF SEG = &HCFFO
CMDA = &H80: CMDB= &H81
CM-DC = &H9A: CMDD = &I-I9B
CLS
PRINT “3. TEST DIGlTAL CONTROL CIRCUITRY”
POKE CMDA, 255
PRINT “MEASURE > 3 VOLTS ON PINS 2,5,6,9,12,15,19 OF U19”
INPUT ‘TRESS RETURN TO CONTINUE”, A$
R26
61.9 K
open
open
R27 R28
383 K
open
383 K
open
open
open
267 K
267 K
‘HARDWARE SEGMENT
Ah4Ml A-27
340
350
355
360
370
375
380
390
395
400
405
410
415
420
425
430
345
440
445
450
455
460
465
470
475
480
485
490
500
510
520
530
54!0
550
560
570
580
600
605
610
620
630
635
640
650
655
660
670
680
685
690
700
710
POKE CMDA,O
PRINT “MEASURE < 1 VOLT ON PINS 2,5,6,9,12,15,19 OF U19”
INPUT ‘TRESS RETURN TO CONTINTJY, A$
POKE CMDB,255
PRINT %EA!XRE > 3 VOLTS ON PINS 2,5,6,9,12,15,19 OF U20”
INPUT ‘TRESS RETURN TO CONTINUE”, A$
POKE CMDB,O
PRINT ‘MEASURE < 1 VOLT ON PINS 2,5,6,9,12,15,19 OF U20”
INXJT ‘TRESS FETURN TO CONTINUE”, A$
PRINT “4a. TEST LOCAL MUX SINGLE ENDED MODE”
FORN=OTO15
lFN<8THENPIN=9-NELSEPIN=N-6
IFN<8THJZNJ=lELSEJ=2
POKECMDA,16+N
LOCATE 6,1
PRINT “INPUT”;N;“ON PIN”;PlN;“OF J”;J;“IS CONNECTED TO TPI”
INPUT ‘TRESS I7ETURN TO CONTINUE”, A!$
IWXTN
PRINT “4b. TEST LOCAL MUX DIFFERENTL4L MODE”
FORN=OTO7
POKE CMDA, N
LOCATE 6,l
PRINT “+INMJT”;N;“ON PIN”;9-N;“OF Jl IS CONNECTED TO TPI”
PRINT “- INMJT”;N;“ON PIN”;N+2;“OF J2 IS CONNECTED TO Tl?”
INPTJT ‘TRESS RETURN TO CONTINUE”, A$
NEXTN
PRINT “5. TEST LOCAL AMP”
POKE CMDA, 0
PRINT “LOCAL GAIN = Xl, 1 VOLT INFUT GIVES 1 VOLT OUTPUT AT TP3”
INPUT ‘TRESS RETURN TO CO-, A$
POKE CMDA, 32
PRTNT “LOCAL GAIN=XlO, 1 VOLT INPUT GIVES 10 VOLT OUTPUT AT TP3”
INF’UT ‘TRESS RETURN TO CO-, A!$
PRINT “6a. SETUP LOCAL AND GLOBAL AMP”
POKE CMDA, 0 ‘SETurLOcALAMP
POKE CMDB, 1 ‘SETUP GLOBAL INPUT AND AMP
PRINT “READ 1 VOLT AT PIN 28 OF U8”
INPUT ‘TRESS RETURN TO CONTINUE’, A!$
FORN=OTO3
PRINT “6b. TEST GLOBAL AMP”
POKECMDB,1+(64*N)
‘SELECT GLOBAL GAIN
IF N < 2 THEN V=N+l ELSE V=(N-114 ‘DETERMINE VOLTAGE GAIN
PRINT “READ”;V;“VOLTS AT TP9”
INPUT ‘TRESS RETURN TO CONTINUE”, A!$
NEXTN
POKE CMDA, 0
‘SELECT LOCAL AMP FOR 1V OUT
FORN=OTO15
AMMlA-28
715
720
730
740
750
760
765
770
775
780
785
790
800
810
820
830
840
850
860
870
875
880
890
895
900
910
CLS
PRINT “7. TEST GLOBAL MUX”
LOCATE 6,l
IFN<8THENPIN=N+19ELSEPIN=19-N
POKE CMDB, N
IF N=O OR N=14 THEN PRINT “0 VOLTS AT TP9”
IF N=I THEN PRINT “1 VOLT FROM LOCAL AMP AT TP9”
IF N=l3 THEN PRINT “10 VOLT REFERENCE AT TP9”
IF N=15 THEN PRINT “5 VOLT DIGITAL SUPPLY AT TP9”
IF N>l AND N<13 THEN PRII’JT “SIGNAL AT PlN”;PlN;“OF U8 AT TP9”
INPUT ‘TRESS RETURN TO CO-, A$
NEXTN
CLS
PRINT “8. TEST A/D CONVERTER”
POKE CMDA, 0
POKE CMDB, 17
‘SETUP LOCAL AMI?
‘SETUP GLOBAL CHANNEL
POKE CMDD, 255 ‘START CONVERSION
WHILE PEEK(CMDD) > 127: WEND
WAIT FOR CONVERSION DONE
TOTAL=PEEK(CMDA) + PEEK(CMDB)?56 ‘GET READING, COMBINE
BYTES
VOLTS = TOTAL * 1.5259E-04
‘CONVERT READING TO VOLTS
LOCATE 6,l
PRINT VOLTS
A$ = INKEY$
IF A$ = mu THEN GOT0 840
PRINT ‘TEST DONE”
AMMl A-29
AMMl A SPECIFICATIONS
INPUT CHANNELS
Local:
8 differential or 16 single-ended inputs.
Global: 9
inputs from slots 2-10.
LOCAL PROG IUMMABLE
Programmable Gains: xl,
Gain Accuracy: 9.045% @
GAIN AMPLIFIER
x10.
xl gain; M-OS% @ x10 gain.
Nonlinearity &O-05%
Temperature Coeffz zHl.OOl%/“C @ xl gain; rtO.O017%/“C @x10 gain.
Input Resistance: >lOOMQ.
Input Bias Current: <InA.
Input Noise:
CMRR: >70dB, DC to 6oH.z.
Input
Protection: k3OV maximum (powered), +15V maximum (unpowered).
10.000
<lOOpV p-p, O.lHz to 1OOkHz.
VOLT REPERENCE
Accuracy: M-025%.
Temperature Coeffz rto.O017%/“C.
Noise:
GLOBAL
A-to-D
Resolution:
A-to-D Range:
Conversion Time: 16p.sec.
Software Trigger:
External Gate:
Noise: <l/2
pr6gmsble Gma*tiscxl,~ ti; &.; and~xloe
251~-V p-p, O.lHz to 1OHz.
AMPLIFIER AND A-to-D CONVERTER
Converter:
Oneshot Mode:
Continuous Mode:
tilled clock.
is high. TTL compatible.
Self-calibrating, successive approximation.
12-b& (1 part in 4,096).
Software selectable, 0 to +lOV (unipolar) and -1OV to +lOV (bipolar).
A single reading is available 16pec. after trigger location in memory is addressed.
Conversions are continuously triggered every 16pec. by internal crystal con-
Continuous conversions begin with falling edge of input to J3 pin 2 and stop when input
LSB on all ranges and gains.
(including acquisition time).
AMMlA-30
Gain Accuracy? +(0.04% +
1 LSB) @ xl gain; +(0.15% + 1 LSB) @ x2, x5, and x10 gain.
Gain Nonlinearity*: &O-033%.
Gain Temp. Coeff? kWO3%/“C.
Filter:
Software selectable, 1OOkHz or 2kHz single pole.
Settling Tie**: 12l.r~~.
*Includes input MUX, amplifiers, and A-to-D Errors.
‘“(to 0.05% of final reading)
with 1OOkHz filter, 6OO~ec. with 2kHz filter.
AMMl A PARTS LIST
PART
NUMBER TITLE REMARKS
c-179-10
c-237-1
c-306-.001
c-350-1
c-365-.1
c-64-22P
c-64-1 or
c-64-1 OOP
c-64-47OP
CR-28-2
a-339-4
CS-553
CS-521-2
IC-607
IC-267
IC-365
IC-397
IC-603
IC-604
IC-674
IC-455
IC-217
IC-176
IC-605
J-14
CAP, 1 OuF, 20%, 2OV, TANTALUM
CAP, luF, 202, SOV, CERAMIC
CAP, lOOOpF, lo%, lOOV, POLYPROPYLENE
CAP, luF, 20%, 5OV, POLYESTER
CAP,. luF, 20%, 50V CERAMIC
CAP, 22pF, lo%, lOOOV, CERAMIC
CAP, IOpF, lo%, loOOV, CERAMIC
CAP, lOOpF, lo%, IOOOV, CERAMIC
CAP, 47OpF, lo%, IOOOV, CERAMIC
OSCILLATOR, 4 MHz
CONN, CPIN
PIN, TEST POINT
CONN, STRIP, 10 PIN
IC, OCTAL BUS DRIVER, 74HCT541
IC, 8 CH CMOS ANALOG MULTI, 6108
IC, 16 CHAN CMOS MULTIPLEXER, 6116
IC. OCTAL EDGE TRIG FLIP FLOP, 74HCT374
IC, 5V VOLTAGE REGULATOR, 78LO5
IC, -5V VOLTAGE REGULATOR, 79LO5
IC, 12-BIT, A/D CONV, C55012
IC, DUAL PST CMOS ANALOG SWITCH
IC, VOLTAGE REFERENCE, LM399
IC, lSV, OP-AMP, LF351
IC, PGMABLE LOGIC ARRAY, PAL20LlOACNS
JUMPER
C12..C15
(210, Cl 1
c7
03, c9
Cl6..C35
Cl, CL, C36
c3, c4
c5
C6
Yl
J3
Trl..Tr14
JL J2
U16, U17
Ul, u2, Ull
U8
u19, u20
u21
U22
u12
u3, u4
u13
u5..u7,u9,u10,u14,u15
U18
U18
SO-72
so-84-40
SO-65
CS-480
R-263-10K
R-263-14.7K
R-263-2.274K
R-263-2.74K
R-263-2.87K
R-263-20K
R-263-2K
R-263-6.65K
R-l 76-976
R-76-10
R-76-100
R-76-22K
R-76-390
R-76-47K
R-765.6K
R-76-8.2K
R-263-6K
R-88-IOOK
R-88-121
SOCKET, g-PIN
SOCKET, 40-PIN
SOCKET, 16-PIN
RESISTOR CARRIERS
RES, lOK, .l%, l/lOW, METAL FILM
RES, 14.7K, .l%, l/lOW, METAL FILM
RES, 2.274K, .l%, 1 /lOW, METAL FILM
RES, 2.74K, .l%, 1 /lOW, METAL FILM
RES, 2.87K, .l%, 1 /lOW, METAL FILM
RES, 2OK, .I%, l/lOW, METAL FILM
RES, 2K, .l%, 1 /lOW, METAL FILM
RES, 6.653 .l %, 1 /lOW, METAL EILM
RJ3,976, .l%, 1/8W, FIXED
RES, 10,5%, 1/4W, COMPOSITION OR FILM
RES, 100,5%, 1/4W, COMPOSITION OR FILM
RES, 22K, 5%, 1/4W, COMPOSITION OR FILM
RES, 390,5%, 1/4W, COMPOSITION OR FILM
RES, 47K, 5%, 1/4W, COMPOSITION OR FILM
RES, 5.6K, 5%, 1/4W, COMPOSITION OR FILM
RES, 8.2K, 5%, 1/4W, COMPOSITION OR FILM
RES, 6K, .l%, l/lOW, METAL FILM
RES, lOOK, l%, 1/8W, METAL EILM
RES, 121,1%, 1/8W, METAL FILM
FOR U18
FOR U12
FOR J4..J6,Ul8
J4..J6
R41, R42,Rl4A
iv1
R13
R19
R15
R22
R17, R14C,R14D
R20
R40
R34, R35
R32
R38
R33
R36
R39
R31
R14B
R37
R23
AMMlA-31
R-88-130
R-88-267K
R-88-2K
R-88-3.01 K
R-88383K
R-88-49.9K
R-88-499
R-88-61.9K
R-88-75K
R-88-86.6K
RES, 130,1%, 1 /SW, METAL FILM
RES, 267K, 1 %, 1 /SW, METAL FILM
RES, 2K, l%, 1 /SW, METAL FILM
RES, 3.01K, l%, 1 /SW, METAL FILM
RES, 383K, l%, 1 /SW, METAL FILM
RES, 49.9K, l%, 1 /SW, METAL FILM
RES, 449,1%, 1 /SW, METAL FILM
RES, 61.9K, l%, 1 /SW, METAL FILM
RES, 75K, l%, 1 /SW, METAL FILM
RES, 86.6K, .l%, 1 /SW, METAL FILM
R16
I728
R30
R29
R27
R2.5
Et
R18
R3
RF-28
RP-89-20K
RI’-89-2K
RP-89-20K
TF-175
TF-177-1
TG-167
TG-47
TG-84
DIODE, SILICON, IN4148 (DO-35)
POT, 20K, lo%, .75W, NON-WIREWOUND
POT, 2K, lo%, .75W, NON-WIREWOUND
POT, 20K, lo%, .75W, NON-WIREWOUND
RES NET, lOK, .Ol%, .lW
RES NET, IK, 2%, 2.25W
FET, TO-92 CASE
TRANS, NPN SILICON, 2N3904 (TO-92)
TRANS, PNP SILICON, 2N3906 (TO-92)
CR1 ..CR9
R5, R6, R9,RlO
R7, R8
R4
RI1
RI, R2
::
Q2
AMMIA-32
I I I -
8
I
7
I
6
I
S
I
4
I
3
I
2
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