Tektronix 576 schematic

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CONTENTS

Section
Section

n

Sectio
Section

Section

Section

Section
Section

1
2

3

4

5

6

7

8

Specification
Operating
Circuit

M

aintenance

P

erformanceCheck
Abbreviations
P

arts

E

lectricalPartsList

M

echanical
MechanicalPartsList
Diagrams

M

echanicalPartsList
Accessories

Instructions

Description

Ordering

PartsList

/Cal

and

Symbols

Information

η P

ibratio

Information

Illustrations

rocedure

Abbreviations
basedon
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value

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inFig.2-11,theappr

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theCRT.

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Collector-Emittervoltage

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ematicsoft h
.

Also

internal logicdiagrams
logic
in

blue

. t

wavespro

sch

and

and b

lockdiagramsinthismanual

in terms

he

m

ore

m

ore p

minals

e r elated

in the

currentor voltage

circuit

steps

converter

ort

consists

operation

cloc

with

respect tothecollector

output.Thecounter

andtransforms

igital-to-analog

transformsthe d

stepamplifier.T

α

variatio

durationpulsedsteps

the

counter

circuit

tegratedcircuits

convenient

circuitryisthroug
etaile

d

und

true

an d

false,has

symbols(NAND

willhelp

tables

ese

circuits

inclu

de

d

in t h

level

information

onthe Step

symbols

will

greatly

duced

at

timing source

ematic).Transformer

D10-D11,

erate

ofU22A

ofnegative

negativeofthetwo

ositive

.The

f

o

th

StandardΥ32

small

logic

symbols

e

negation

deviceisin

resent

αdiscrete

(orequiva-

test

for

eachsweep,

collector

formofascen

d

k p

are d

metho

circuit

erstandablebyα wid

Generatorsch

and

aidin

line

andtrigger

together to produce

.UsingU3A-U3Basan

symbolonit

.14

supply.

separation

of fourmajorsec-

igital-to-analog

section.The

ulseswhich d

each

n

ofthe

circuit

igital

circuitswhich

d of d

description.In

been

gates,

inund

aresh

ese

figures

forthe

forthese

relatedtruthtables

understandingthe

frequency

forthe clock

Τ

logic.In negative

logic

circlesonsome

indicateαlogic

its

activated

1962

.

These

ing

d

.

circuit

count

into

converter

igital

summing

he p
StepGen-

ratherthan

an d α

indigital

escribing

h α

using

utilized.

NOR

gates,

erstanding

own

inFigs

are

logic

devices

logicde-

ematic

by

trans-

701,

steering

generators

whichinvolve

levels

and

o

willbeat a

state

ste

cloc

code

ulsed

trut

logic,

.Fo

or

p

con-

eter-

sup

por-

logic

er

hig

Α

(see

low

t

he

fthe

nega-

example,

D1

turnon.When
in

put of

in

put

voltage d

s

theoutput ofU3A

F

ig.3-4).Thishighis

is

prod

ch

k

R4-R5.Whenthe voltageatD1
positive,D1turnsonandD2turns off.With

­in

puts to

ofU3B goes

α

generator.Trigger

.

U3

allowsthe
app

t h e
two

i

n

t h

eir
Supply
generatorsatthe
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ΝΡΝ

allows adj

h

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to

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ormallyhel

p

roducesαlowatits

w

.

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.

h ic h

counter
rate

generator
frequency)wh ic histhenormal

t

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theinput toth
pulsesatt
start

h alf t
d

elay

output

on

d

own
continues
to again turn

p

ro
andR33

inputofinverterU33A.The
ofU33A
laye

r

t

he h

each

time

the

transformer

crosses

applie

arges

B-U3Aexcept thatthe additional

liedtoit

Since

voltages at

o

Withth

normpulse gateU22B.The pin5

H

t h e

duced

d

zero

going

negative,

D2isconducting,

U

3A

isheldatα

3A,pin2,isheldat

to

U

ividerR4-R5,thislow

d to

t

he pin1

ucedbythetrigger

to α high voltage

U3A

are high,t h e

h ig

h.This isthe quiescent

generatorU3D-

triggergenerator to beinh

.

TransformerΤ701

its

outputs

trigger

generators

pp

ositephase,

out

puts

.

SinceΤ701

outp

ut, αpulseisgeneratedby

startofeachcollector

ΡΝΡ

or

ustment

p

-

eNORMRAT

generator

d h

olarity)

of

igh.

produces α h

circuit.Withthe

of production of clock p

rate)is120pulses/secon

ighlevel

of each

he

circuit

p

alf-step

out

put

edelay

normal

he

normal

duration

time

is

triggere

ofU22A.This

base of

on

ulse atthe pin13

Q30,

si

d

one

e of

to charge

on

at

its

collector,which

into α

is

α highatits

elay

d

Q30.WhenQ30

negative-going

low

(see

truthtable

invertedbyU3B

in

are

are

triggeredbyΤ701,they

pro

d

ucing

.ZEROCR

trigger

E bu

are

inverted

Αhighat

output.This

ighlevel

N

O

ulses

p

own

onthe Step

circuit.This

rate,

but d

cloc

kpulse)byα d

between

d each

ighturnsonQ23,

h

t u

rningitoff.Si

C26,theotherside

until

αhig h

output,

in

circuitiscontrolledbyDELAYadj

put of

generation

level

output

(seeFig.3-4)iscenter

is in

cloc

RMRAT

fromU22A

put of

voltageatthe

D1

will

turn

off

andD2

t hevoltageatthepin

voltage

equal

alternate

level

tton

ulses

time

resultofthis

level.Sincethe

αhig

h voltage

causes

αhig

h to

appear

forNORgatesh

andtheresulting

U

22A.This

continues

asdeterminedbydivider

crosses

t h

goes

low

U3Coperates

in

putatp

ibite

and

o

low

phase with

OSS

of

trigger

pressed,

toU22A

its

oth

er input,th

lowisapp

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ulsetobe

E

butto

(andth

d (assumi n

collector

are

Generatorschematic),

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elayed(withrespecttot

normal

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nce

enoug

h voltageisreac

turns

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spi

k

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a

andthus

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22D.T

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w

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pp

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levelpulses

theCollector

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sweep(assuming

d

j

ustmentR8

a

gen

erators

lowpulses

and

transmitted

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put to

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appliedtothe

n

p

resse

erefore

gα60Hz

supply

rate

also

applie

generates cloc

elay

timeequal

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k p

ulses.This

isproducedatthe

an

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Q23ispulling

begins ch

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lie

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α high

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will

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put

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22Bis

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22C,

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3-

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





Circuit

Description-Type

Clock
Pulses

576

STEP

FAMILY

Buttons

Lowonat least
of

each of

of

inputs

reset

pulseatoutput

of

U75

Fig.3-5.Block

one

these

pairs

causes

low

.

diagramofcounter

and

reset logic

NUMBER

To

Switch

.

OF

STEPS

3-7

Circuit

Descriptio

mentR24,

a

d

j

ustedfor

normal
fore,

pp

Su
cuitto5000μsw

frequency

The

output
various

some
summedby

cloc

of

Norm

Whent

ishel

also

a

fromU22A
applied to pin12

p

ulse.Whenthe.5

operates

inputs
low

an dinh

step

generator

(assumingα60Hz

b utton
highisapp

clockpulses
generator

th

e2Χ
normal
and

t h edelayed

this

casethe
occur
ofth

e

Counter.Wh

itiscountedby

counts

resets

counts,

digital-to-analog

t

he

U

70isα d

four of
tivepulse at
recorde

s

flo

p

binary

1,

2,4or

12,9,8 and11of U

By

connecting
inverters,
toα1-2-4-4

state
countedby

t

hezero

to

whichcontrols

αdelay

step(about

occur

coincident

ly

out

put

.

circuit

cloc

k

ofU22A

stepgenerator

the

clockpulses

of

U22C

kpulsesth

Pulse

Gate

heNO

h

igh,

d

enabling

lie

d to pin

pp

tobetransmittedto p

asdescribedfor

of

U20C

ibits

causes

normal

lie

d to p

to be app

rate

RAT

E an

cloc

kpulses

Step

out

ofphase

elay

circuit

d

cloc

kpulses

and begins

itch

angesαfour-bit

its

internal

the pin14

bythe

d

assumehig

de

.

Αhighstate

co

8.Α

t

he1-2-4-8

code.Thetrut

of each

modifie

U70up

count

.SW27lengt

U

RMRATEbutton

are

trigger

rateofhalf

in t hiscaseis240

d t h e .5

clock p

en

ivide-by-16 counter

flip-flops.In

low

in

p

-Ty

p

n

e

576

h

arge

t

hec

time

equal

tohalf

4167μs).

henΤ701isop

has

andthe

.Th

reedevices

roug

hthe

22Band

trigger

5

ofU22B,

ofU22D,

ΧRATEbutton

hel

d

line

frequency).Pressing

operationoft hecircuit,

in

12 ofU22D,

lie

areinh

Generator

withthenormal

.

t

heclockcircuit

t h e

counter

untilitreaches

counting

converter

flip-flops

h or

state

70rep

d

8

an

codeoft

counter

d

to 11.Wh

state

withlowsonallthe

Delayedcloc

withthepeakofth

hensth

edelay

erate

two

sourcesofcloc

output ofthe delay

rates

are

producedbyinh

fromth

generatorU3C-

in

low

ese

two

controlthe

circuit:Trig

DelayedPulse

ispressed,pin9of

generatorU3D-U3C.Α

allowingthe

in

in h

ibitingth

normal

h ig h

t h e

d to p

Χ

ibitedbyαlow

ulses

put of

representsth

representsα0.Out

resent1,2,4and8

p

eration

o

p

,

whic

normal

in

10 of

steps/second.Whenbot

RATEbuttons

are transmitted

rate

is

stepsbyt h e

generates α cloc

(seeFig.3-5)

again

.Each

binary

codewhichisapplie

.

withtheout

utilized(see

U70

record

states

according

in

11 of

heU70

h tableinTable

put

out

enever

tirneofC26

e

t

h

timeofthis

d with

sources

Gen

GateU22D

.R24

d

uration

k p

ulses,th
e Collector

α

50Hzli

k p

ulses,the

circuit.The

from

transmission

GateU20C,

ibiting

being

.

U3C

h ig h

clockp

9 of

U22C

delayed cloc

e

ispressed,the

exce

h h

spin

ol

d

U3D.The

rate,60ste

t h e2ΧRAT

except that

allowingthe delayed

U22C

arepressed,the

atpin5of

to

normal,

αpreset

butthe

T

.

number,th

timethe

.Αlow

circuit

tthatbot

p

9 ofU3C

resultisα

s/secon

p

.Th e

22C

U

delay

kpulse,

h

e

counter

counter

ulses

U22B

steps

time

puts of

Fig.3-5).Α

causes α

ingαcount,the

to α

epresentsofeit

put

U70toU

for

U

72Dth

out

puts

3-1

successive

70isreset,itreturns

outputs

nega-

counttobe

1-2-4-8

her

terminals

respectively

roug

is

modifie

s h

owsthe

counts

.

of

ere-

cir-

ste

.

en

d to

all

flip-

is

α

N

ormal

andModified

e

n

Count

N

P

12

0 L L L L

1

Η

2 L
3

Η

4 L
5

Η

6

L

7

is

is

k

h

d

been

E

minesonwhichcloc

α

p

resetsthe

countedthedesirednumber

p

ated

h

is
torU75

p

In

α

.

h

uts are
eachOR gateisconnectedthroug
ofthe
sectionoftheNUMBER
appears
inputstotheU75NAND

p

ulse

least

by
NUMBER
lows

OR

app
eleventhstep(1+

counter
p

ulse

cloc

BEROFSTEP

atwhichthisextra cloc
t

he p

stepnever

d

t

he Step

d

ucingαresethighatpin2and

stretchtheresethig
thatthe

Η

8 L
9

Η

10

L

11

Η Η

The

counter

prod

uced.The

in

putstoU

atpins2an

obtainedfrom

.

U75

connected

modifiedcounter.T

on

one

is

prod

ucedatthe

one

low

first

setting

OFSTEP

are

prod

ucedbythe

gates

with

lie

d to

U

75,the

outputs are

whic

h causesthe

k

Thehighattheoutput of

morethant h e n

Pulse

ointwhenthe

appears

GeneratorSch

counterisreset

TA

BLE

3-1

Cou

ormalCode
ins

onU70

9 8

L L L

Η
Η

L
L

Η Η
Η Η

L

L

Η

may

d 3 of

α highatthe

consistsoffour

in

eac

on

lows

outpreset

S switch.Thetime

at t h e

11

L L
L L

Η

L L L

Η

L
L L
L

Η

L
L

Η
Η

L
L

Η

be

reset

after

NUMBER

k p

ulsethe

75, sothatw

of clockpulses,

U

70,

resettingthe

output of

to α

4-inputNA

he oth

OFSTEP

put

of

eachOR gate ofU75,

gate

out

put

hOR

gate of

onsome

S switch.The

modifiedcounter

lows.Wh

counterisresetwhenit

2 + 4 +

low.Itshould be

counter

umber

kpu lseiscountedbythecounter

counterisresetissosh

StepGenerator

U75

ematic)

h to α

long-enoughdurationtoassure

.

n

terOutput

12

L L L L

Η

L

Η

Η

Η

L L

Η

L

Η Η Η

from

OFSTEPS

counterisreset.This

2-inputOR

h an

er in

willbelow
.

This

U75

oftheOR

counter

4 =

11)whenα11

toberesetisalways

duration

isinverted

and
3 ofU70

Codes

M

odifiedCode

P

ins

U

70

on

11 11

9

L L L

Η

L L

Η

L L

Η

L

Η

Η

Η

Η

Η
Η Η

L

Η

Η

Η

1

to10stepshave

switc

henthe

ND

invertertoan

put

S switch.Whenα

condition

is

en

notedthatthe cloc

selectedby

again

counterhas

αhighis

counter.Thishig

reset

trigger

gateswhose out-

gate.One

is

connecte

an

d α h

of h

typically
gatesth

t h

en cou

output atthe

nopreset

reachest

fromthe point

ortthatt

outpu

t-

byU33B(see

byU69C,

71Dand

.

U

U

72D

L
L
L
L

Η
Η
Η

hdeter-

switc

gener-

genera-

in

put of

out

d to α

all

ighreset

aving

obtaine

rought

nts

lows

modifie

t h e

NUM-

he extra

h

h

put

low

four

at

d

he

until

are

he

d

k

one

to

pro­C81

3-

8

Circ

uit

Description-Type

576

T

hestate
mineswhetherclock p
ofU70.Whenthe

lowisapplie
behel

p

ulses

counter
ispresse

w

hich
ablesU69A
theresethighcausespin

p

roducedatthepin2in

clockpulses

Digital-to-Analog
fiedcounter
ter.T

hepurpose
counter
thestepamplifier
consistsofα
sets

of current

ofpin2of

STEPFAMILY

in

d to p

d

p

ermanentlyhigh.

applie

d to

its

triggers.Whent h e

d

,αmomentary

goeshighas

untilone

being

from

connecte

are

of

out

putcod

e

setofcurre

steeringdiodes

ulses

5 of

in 1 in

p

C78ch

stepfamilyhas

Converter

this

intoanalog

in

put

Fi

g.3-6.Sim

cloc

kpulse

are

p

ap

REP

U69B

,

causing pin2

this

state

In

put

are

EPFAMILYSINGLE

ST

lowisapp

arges.This

4 ofU69

put of

transmitte

d to

circuitisto

.

n t

U

d

.The

thedigital-to-analog

currentwh

T

he d

igital-to-analog

setting

.

plif

ied

enableU69Adeter-

liedtothe pin14

button

ispressed,
of

U

ofU69A,

inverted,

lie

d to p

momentary

generated.When

been

B to

gohigh,αlow

69A.This

p

astU69A

outputsoft

convertthe

resistorpairs

all

and

in5ofU69

lowinh

.

hemo

modified

ic hisapp

converter

and four

schematic

input

69A

to

cloc

k

become

button

B

low

en-

is

ibits

i-

d

conver-

lie

d to

ofDigital-To-Analog

T

h

e

amount

α

setting

R

63-1964

crete

amount

counter

R 54-1955,

andfourbyR
causes

one

p

ut

.

Thesteeringdiodes

rent

fromth

D71,

D72

ifiedcounter

ducte

d

by

ifiedcounter

Anothersetofcurrentpaths

D57,

D60

betweenthe

Converter

d

igital-to-analog

of

current,

resistorpairsR54-1955,

(see

of currentwh ic hisα

code:one

two

63-1964.E achsuccessive

steptobegenerate

ese

and

outputs

oneoft

outputislow

andD63.Thesediodesprovide

current

.

converter

amount

the

F

ig.3-6)

.Eachresistorpair

increment

increments

resistorpairsiscon

D73provi

hese d

byR57- R58,

d

eterminewh

de cu

and

t heresistorpairs.Currentiscon-

iodeswh

.

summing

ofwhichissetbycurrent

1957-1958,R60-R61 and

multipleoft h e

of current

atthe

d

rrentpaths

enever

isprovi

node(atthe

conductsαconstant

con

ductsαd

modifie

con

ducted

fourbyR

incrementofcurrent

StepGe

ere

in thecircuit

ducted

betweenthe

its

associatedmod-

dedbydiod

cathodeof

60-R61

nerator out-

cur-

.

Dio

des

D70,

mod-

es

D54,

currentpaths

D83)

3-

is-

d

by

9

Circuit

Description-Type

and

thecurrent

hich

pat

h s

amp

lifier
ifiedcounter
and

t

he current

appliedtot

Theamount

put

isαfunctionof
bedeterminedby
resistorpair
whichishigh.For
cordedbyt
andD72.T
t h

erefore,

by

R60-R61,

cordedbythe
cu

rrent

modifiedco
applie

ment

for
counter
levelofthe

q

uiescent

Steeringdiodes

path

s

R64,

res

p

ressed.(

D58,

path

s

be

ap

p

result is
tor

outputisreducedto

The

D44isused

p

ulsedmode.

an

t

heyh

d

amplifier

T

he current

wellast
may

be

ing

or
mined
t

he d

button

t

h

to

e

whichraises
to

be conducted

button

Q90

using
rent to be
tion.OPPOS
adjustment
theOPPOS

p

ressed,

cause

w

input

.Whenever

outputs,

con

e

h

stepamplifier

of currentapp

associate

he counter, high

he currentapp

one

increment

totalling5increments.T

counter

appliedto

unter

d toth

e

stepamplifier

eachcloc

resets).ZERO ST

zero

current

for

t

hecu

ectively,

p

WiththeSTEP

D61

andD64

reduce

theamount

lie

d tothe

that

thenormal

fourth

setofsteering

only

w

In

all

avenoeffectont

i

npu

t

.

summing

he d

igital-to-analog

offset

either in

in

theop

bythe

irectio

DC

n ofthe

ispressed.

base of

the

ispressed,

theOFFSET

con

ducte

emitter

EOFFSE

R86

EOFFSE

respectively

576

settingresistorpairs.Itist

stepcurrent tobeapplie

α h

ig

happ

earsatoneofthemod-

its

associatedsteeringdiode turns

d

u

ctedbyits

themo

ing

add

d wit

example,iffive

liedto

by R54-R55plus

associatedresistorpair

input

.

the

liedto

ifiedcounter

d

he currentscond ucte

t

h

α

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