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Tektronix 318, 338 Technical Manual

TECHNICAL MANUAL
OPERATOR’S, ORGANIZATIONAL, DIRECT SUPPORT,
AND GENERAL SUPPORT MAINTENANCE MANUAL
LOGIC ANALYZER
TEKTRONIX MODELS 318/338
TM 11-6625-3145-14
HEADQUARTERS, DEPARTMENT OF THE ARMY
12 SEPTEMBER 1985
5
1
2
3
4
SAFETY STEPS TO FOLLOW IF SOMEONE IS THE VICTIM OF ELECTRICAL SHOCK
DO NOT TRY TO PULL OR GRAB THE INDIVIDUAL
IF POSSIBLE, TURN OFF THE ELECTRICAL POWER
IF YOU CANNOT TURN OFF THE ELECTRICAL POWER, PULL, PUSH, OR LIFT THE PERSON TO SAFETY USING A DRY WOODEN POLE OR A DRY ROPE OR SOME OT HER INSULATING MATERIAL
SEND FOR HELP AS SOON AS POSSIBLE
AFTER THE INJURED PERSON IS FREE OF CONTACT WITH THE SOURCE OF ELECTRICAL SHOCK, MOVE THE PERSON A SHORT DISTANCE AWAY AND
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IMMEDIATELY START ARTIFICIAL RESUSCITATION
A
THE FOLLOWING SERVICING INSTRUCTIONS ARE FOR USE BY QUALIFIED PERSONNEL ONLY. TO AVOID PERSONAL INJURY, DO NOT PERFORM ANY SERVICING OTHER THAN THAT CONTAINED IN OPERATING INSTRUCTIONS UNLESS YOU ARE QUALIFIED TO DO SO.
Copyright c 1984 Tektronix, Inc. All rights reserved. Contents of this publication may not be reproduced in any form without the written permission of Tektronix, Inc.
Products of Tektronix, Inc. and its subsidiaries are covered by U.S. and foreign patents and/or pending patents.
TEKTRONIX, TEK, SCOPE-MOBILE, and are registered trademarks of Tektronix, Inc. TELEQUIPMENT is a registered trademark of Tektronix U.K. Limited.
Printed in U.S.A. Specification and price change privileges are reserved.
Tektronix, Inc. Walker Road Industrial Park P.O. Box 4600 Beaverton, Or. 97075

WARNING

WARNING
B
The comm ercial manuals cited in paragraph la c ontain copyright material reproduced by perm ission of the T EKTRONIX, INC., BEAVERTON, OR 97075
TM 11-6625-3145-14
TECHNICAL MANUAL ) HEADQUARTERS
) DEPARTMENT OF THE ARMY
No. 11-6625-3145-14 ) Washington, DC, 12 September 1985
OPERATOR’S, ORGANIZATIONAL,
DIRECT SUPPORT, AND GENERAL SUPPORT
MAINTENANCE MANUAL
LOGIC ANALYZER
TEKTRONIX MODELS 318/338
REPORTING ERRORS AND RECOMMENDING IMPROVEMENTS
You can help improve this manual. If you find any mistakes, or if you know of a way to improve the procedures, please let us know. Mail your letter, DA Form 2028 (Recommended Change to Publications and Blank Forms), or DA Form 2028-2 located in the back of this manual direct to: Commander, US Army Communications-Electronics Command and Fort Monmouth, ATTN: AMSEL-ME­MP, Fort Monmouth, NJ 07703-5007.
In either case, a reply will be furnished direct to you.
i
TABLE OF CONTENTS
Section Page
0 INTRODUCTION
0-1 Scope....................................................................................................................................0-1
0-2 Consolidated Index of Army Publications and Blank Forms .................................................0-1
0-3 Maintenance Forms, Records and Reports ..........................................................................0-1
0-4 Reporting Equipment Improvement Recommendations (EIR)..............................................0-1
0-5 Administrative Storage..........................................................................................................0-1
0-6 Destruction of Army Electronics Material..............................................................................0-1
ii
MANUAL REVISION STATUS
PRODUCT: 318/338 Logic Analyzer Service Manual
This manual supports the following versions of this product: All
REV DATE DESCRIPTION
JAN 1984 Original Issue NOV 1984 Revised Printing: Pages-X1, 1-3, 5-2,-15,-49,-50 and -51, Tab-Fig. 4 Accessories page, Fig. 9-11,
Electrical Parts List, Diagrams < 5>and <6>
iii/(iv blank)
TABLE OF CONTENTS
Page
LIST OF ILLUSTRATIONS........................................................................................................................................... xv
LIST OF TABLES.........................................................................................................................................................xix
OPERATOR’S SAFETY SUMMARY............................................................................................................................ xxi
SERVICE SAFETY SUMMARY...................................................................................................................................xxiii
Section 1 INTRODUCTION AND SPECIFICATIONS
INTRODUCTION...................................................................................................................................1-1
DESCRIPTION......................................................................................................................................1-1
MODES OF OPERATION.....................................................................................................................1-1
CONFIGURATIONS..............................................................................................................................1-2
RELATED DOCUMENTS......................................................................................................................1-2
STANDARD AND OPTIONAL ACCESSORIES....................................................................................1-3
Standard Accessories ...................................................................................................................1-3
Options..........................................................................................................................................1-3
Optional Accessories.....................................................................................................................1-3
SPECIFICATIONS................................................................................................................................. 1-4
Section 2 OPTIONS Section 3 OPERATING INSTRUCTIONS
INTRODUCTION...................................................................................................................................3-1
INSTALLATION.....................................................................................................................................3-1
Power Requirements.....................................................................................................................3-1
Power Cord....................................................................................................................................3-1
MENU CHARACTERISTICS.................................................................................................................3-2
Power-Up Configuration Display...................................................................................................3-2
Menus and Submenus ..................................................................................................................3-2
Menu Default Displays...................................................................................................................3-2
Menu Fields and the Edit Cursor...................................................................................................3-2
Error Message and Acquisition Status Readout............................................................................3-3
Major Mode Selection Field...........................................................................................................3-3
Inputs During Acquisition...............................................................................................................3-3
MENU FUNCTIONS..............................................................................................................................3-3
Setup Menu...................................................................................................................................3-3
Threshold Menu ............................................................................................................................3-3
Trigger Menu.................................................................................................................................3-4
State Table Menu..........................................................................................................................3-4
Timing Diagram Menu (Parallel Only)...........................................................................................3-4
Character Menu (Serial Only) (318S1/338S1)...............................................................................3-4
Remote (RMT) Menu (318S1/338S1) ........................................................................................... 3-4
Non-Volatile (NVM) Menu (318S1/338S1)....................................................................................3-4
v
TABLE OF CONTENTS (cont.)
Section 3 OPERATING INSTRUCTIONS (cont.)
DIAGNOSTICS....................................................................................................................................... 3-5
Power-Up Self Test ........................................................................................................................ 3-5
Diagnostics Menu........................................................................................................................... 3-6
User-Changeable Fields for Each Test’s Display........................................................................... 3-6
Diagnostic Test Descriptions.......................................................................................................... 3-8
KBD Test................................................................................................................................ 3-8
CRT Test................................................................................................................................ 3-8
CLK Test .............................................................................................................................. 3-10
WR Test ............................................................................................................................... 3-10
ACQ Test.............................................................................................................................. 3-11
SQRAM Test........................................................................................................................ 3-11
N&DLY Test ......................................................................................................................... 3-12
SEQ Test.............................................................................................................................. 3-12
THRSH Test......................................................................................................................... 3-13
External Clock Probe Compensation................................................................................... 3-13
P6107 Probe Assignment and Compensation for the
318S1 and 338S1 ........................................................................................................ 3-14
SER Test.............................................................................................................................. 3-15
RMT Test ............................................................................................................................. 3-16
NVM Test ............................................................................................................................. 3-17
Section 4 THEORY OF OPERATION
SECTION ORGANIZATION................................................................................................................... 4-1
DIGITAL LOGIC CONVENTIONS.......................................................................................................... 4-1
GENERAL SYSTEM DESCRIPTION..................................................................................................... 4-1
Acquisition Module.................................................................................................................................. 4-2
Parallel Data Inputs (A01 AND A02).............................................................................................. 4-2
P6451 Parallel Data Probe..................................................................................................... 4-2
P6107 External Clock Probe.................................................................................................. 4-2
Data Buffers, Delay Lines, and First Lactches.......................................................................4-3
External Clock Circuit............................................................................................................. 4-3
Clock Selector........................................................................................................................ 4-3
Word Recognizer ................................................................................................................... 4-3
Threshold Circuit.................................................................................................................... 4-3
Acquisition Control Board (A03)............................................................................................................. 4-3
Qualifier Selector.................................................................................................................... 4-3
Strobe Generator.................................................................................................................... 4-3
Trigger Sequencer.................................................................................................................. 4-3
Event/Delay Counter.............................................................................................................. 4-3
Acquisition Memory Board (A04).................................................................................................... 4-3
100 MHz Oscillator................................................................................................................. 4-3
Sampled Data RAM and Glitch RAM ..................................................................................... 4-3
Acquisition Address Counter and Carry Flag F-F................................................................... 4-3
Output Multiplexer.................................................................................................................. 4-3
v
TABLE OF CONTENTS (cont.)
Section 4 THEORY OF OPERATION (cont.)
Mainframe............................................................................................................................................... 4-4
ROM/Threshold Board (A05).......................................................................................................... 4-4
ROM....................................................................................................................................... 4-4
Threshold Circuit.................................................................................................................... 4-4
MPU/Display Board (A06).............................................................................................................. 4-4
Microprocessor....................................................................................................................... 4-4
RAMs...................................................................................................................................... 4-4
Display Controller and Character ROM.................................................................................. 4-4
Bus Buffer............................................................................................................................... 4-4
Key Control Logic................................................................................................................... 4-4
Mother Board (A08)........................................................................................................................ 4-4
Keyboard (A09) .............................................................................................................................. 4-4
CRT Board (A10)............................................................................................................................ 4-4
CRT ....................................................................................................................................... 4-4
CRT Circuit............................................................................................................................. 4-4
Power Supply (A11 AND A12)........................................................................................................ 4-5
Left-Side Panel............................................................................................................................... 4-5
318S1/338S1 (A07)........................................................................................................................ 4-5
Serial Input Comparator......................................................................................................... 4-5
Serial I/O Controller................................................................................................................ 4-5
DETAILED CIRCUIT DESCRIPTIONS FOR THE 318 .......................................................................... 4-5
318 A01 Input A Board <1> <2> A02 Input B Board <3> <4>............................................................... 4-5
Overview ....................................................................................................................................... 4-5
Address Decoder <2> .................................................................................................................... 4-6
External Clock Input <4>................................................................................................................ 4-6
External Clock Comparator <4>..................................................................................................... 4-6
Clock Selector <4>......................................................................................................................... 4-6
Glitch Control <2> <3> <4>............................................................................................................ 4-7
Pipeline Register <1> <3>.............................................................................................................. 4-7
Word Recognizer <1> <2> <3>...................................................................................................... 4-7
Data Threshold Buffer <4>............................................................................................................. 4-7
Probe Compensation <4> .............................................................................................................. 4-8
318 A03 ACQ Control Board <5> <6> <7>............................................................................................. 4-8
I/O Address Decoder <6>............................................................................................................. 4-10
Qualify/SQRAM Data Register <5>.............................................................................................. 4-11
Qualify Logic <5> <6>.................................................................................................................. 4-12
START/STOP Logic <6>.............................................................................................................. 4-12
Trigger Qualify Flip-Flop <6>........................................................................................................ 4-12
Retiming Clock <6>...................................................................................................................... 4-12
Clock Qualify Flip-Flop <6>.......................................................................................................... 4-12
Strobe Generator <6>................................................................................................................... 4-12
External or Glitch Trigger Circuit <7>........................................................................................... 4-13
Retiming Flip-Flop <6>................................................................................................................. 4-13
Address Buffer <7> ...................................................................................................................... 4-14
Trigger Sequencer RAM <7> ....................................................................................................... 4-14
vii
TABLE OF CONTENTS (cont.)
Section 4 THEORY OF OPERATION (cont.)
Trigger Sequencer Flag <7> ........................................................................................................ 4-14
N Flag Circuit........................................................................................................................ 4-14
TRIG’D Flag Circuit.............................................................................................................. 4-15
SUCCEED Flag Circuit......................................................................................................... 4-15
STOP Flag Circuit ................................................................................................................ 4-15
SQRAM Data/Word Recognizer Data Multiplexer <7>................................................................. 4-15
LSI-A A03U158 <7>..................................................................................................................... 4-15
Address Decoder.................................................................................................................. 4-15
N Register ............................................................................................................................ 4-16
DL Register .......................................................................................................................... 4-16
Mask Register ...................................................................................................................... 4-16
Event/Delay Counter............................................................................................................ 4-16
ACQ Status Logic................................................................................................................. 4-16
318 A04 ACQ Memory Board <8> <9>................................................................................................. 4-17
Acquisition Memory and ACQ Address Counter <8>................................................................... 4-17
Chip Select Latch................................................................................................................. 4-17
Acquisition Memory.............................................................................................................. 4-18
ACQ Address Counter and Carry Latch............................................................................... 4-18
Timebase and MPU Bus Interface <9>........................................................................................ 4-19
TTL-to-ECL Translator ......................................................................................................... 4-19
Address Decoder.................................................................................................................. 4-19
Oscillator .............................................................................................................................. 4-19
Divider, Timer, and Slow Clock Detector ............................................................................. 4-19
INTCLK Buffer...................................................................................................................... 4-19
Data Selector........................................................................................................................ 4-19
ECL-to-TTL Translator and TTL Bus Buffer.........................................................................4-19
Full Valid Flag Latch............................................................................................................. 4-20
LSI-B (A04U 140)................................................................................................................. 4-20
318/338 A05 ROM/Threshold Board --<10>......................................................................................... 4-24
ROM Circuitry............................................................................................................................... 4-24
Threshold Circuit .......................................................................................................................... 4-25
D/A Converter....................................................................................................................... 4-25
Analog Switches................................................................................................................... 4-25
318/338 A06 MPU/Display Board <11>................................................................................................ 4-27
MPU .....................................................................................................................................4-27
RAM .....................................................................................................................................4-27
Bus Drivers................................................................................................................................... 4-27
Keyboard and Keyboard Controller.............................................................................................. 4-27
Interrupt Gates ............................................................................................................................. 4-27
Display Controller......................................................................................................................... 4-27
318/338 A07 Serial, Non-Volatile Memory, RS-232C <17> <18>........................................................4-30
Serial Input <17>.......................................................................................................................... 4-30
Input Comparator ................................................................................................................. 4-30
Offset Adjust......................................................................................................................... 4-30
Clock-Level Translator . ....................................................................................................... 4-30
viii
TABLE OF CONTENTS (cont.)
Section 4 THEORY OF OPERATION (cont.)
Non-Volatile Memory <17>........................................................................................................... 4-30
Threshold Voltage Detector.................................................................................................. 4-30
Chip Select Controller .......................................................................................................... 4-30
Battery Switch....................................................................................................................... 4-31
Battery Voltage Checker ...................................................................................................... 4-31
Random Access Memory..................................................................................................... 4-31
Serial Data Acquisition <18>........................................................................................................ 4-32
Data Bus Buffer.................................................................................................................... 4-32
I/O Selector .......................................................................................................................... 4-32
Baud-Rate Selector.............................................................................................................. 4-32
External Trigger Latch and Data Polarity............................................................................. 4-33
Serial I/O Controller.............................................................................................................. 4-33
RS-232 Control <18>.................................................................................................................... 4-34
Baud-Rate Selector.............................................................................................................. 4-34
Level Converter.................................................................................................................... 4-34
Serial I/O Controller.............................................................................................................. 4-34
318/338 A10 CRT Board <14>............................................................................................................. 4-35
Z-Axis Amplifier ............................................................................................................................ 4-35
Horizontal Sweep Generator........................................................................................................ 4-36
Vertical Sweep Generator............................................................................................................ 4-37
318/338 A11 Power Supply <15> <16>................................................................................................ 4-37
Line Input <15>............................................................................................................................. 4-37
Inverter Start Network <15>......................................................................................................... 4-38
Inverter Control <16>.................................................................................................................... 4-39
Regulator.............................................................................................................................. 4-39
Dead Time Controller........................................................................................................... 4-39
Over/Under Voltage Protection <16>........................................................................................... 4-39
Low Voltage Rectifiers and Regulators <16>............................................................................... 4-39
+12 Volt and -12 Volt Supplies............................................................................................. 4-39
-3.3 Volt Supply.................................................................................................................... 4-39
+5 Volt Supply...................................................................................................................... 4-40
Fan Circuit and Fan <16>............................................................................................................. 4-40
DETAILED CIRCUIT DESCRIPTIONS FOR THE 338 ........................................................................ 4-40
338A01 Input A Board <19> <20> A02lnputBBoard <21> <22>......................................................... 4-40
Overview ..................................................................................................................................... 4-40
Address Decoder <20> ................................................................................................................ 4-40
Glitch Control (CH 0-7) <21>........................................................................................................ 4-41
Word Recognizer <19> <21>...................................................................................................... 4-42
Threshold Buffer <22>.................................................................................................................. 4-42
Probe Compensation <21> <22>................................................................................................. 4-42
338 A03 ACQ Control Board <5> <6> <7>........................................................................................... 4-42
I/O Address Decoder <6>............................................................................................................. 4-44
Qualify/SQRAM Data Register <5>.............................................................................................. 4-45
Qualify Logic <5>.......................................................................................................................... 4-46
ix
TABLE OF CONTENTS (cont.)
Section 4 THEORY OF OPERATION (cont.)
START/STOP Logic <6>.............................................................................................................. 4-46
Trigger Qualify Flip-Flop <6>........................................................................................................ 4-46
Retiming Clock <6>...................................................................................................................... 4-46
Clock Qualify Flip-Flop <6>.......................................................................................................... 4-46
Strobe Generator <6>................................................................................................................... 4-47
External or Glitch Trigger Circuit <7>........................................................................................... 4-47
Retiming Flip-Flop <6>................................................................................................................. 4-47
Address Buffer <7> ...................................................................................................................... 4-48
Trigger Sequencer RAM <7> ....................................................................................................... 4-48
Trigger Sequencer Flag <7> ........................................................................................................ 4-48
N Flag Circuit........................................................................................................................ 4-49
TRIG’D Flag Circuit.............................................................................................................. 4-49
SUCCEED Flag Circuit......................................................................................................... 4-49
STOP Flag Circuit ................................................................................................................ 4-49
SQRAM, Data/Word Recognizer, Data Multiplexer <7>............................................................... 4-49
LSI A A03U158 <7>...................................................................................................................... 4-49
Address Decoder.................................................................................................................. 4-50
N Register ............................................................................................................................ 4-50
DL Register .......................................................................................................................... 4-50
Mask Register ...................................................................................................................... 4-50
Event/Delay Counter............................................................................................................ 4-50
ACQ Status Logic................................................................................................................. 4-50
338 A04 ACQ Memory Board <8> <9>................................................................................................. 4-52
Acquisition Memory and ACQ Address Counter <8>................................................................... 4-52
Chip Select Latch................................................................................................................. 4-52
Acquisition Memory.............................................................................................................. 4-52
ACQ Address Counter and Carry Latch............................................................................... 4-53
Timebase and MPU Bus Interface <9>........................................................................................ 4-53
TTL-to-ECL Translator ......................................................................................................... 4-53
Address Decoder.................................................................................................................. 4-53
Oscillator .............................................................................................................................. 4-53
Divider, Timer, and Slow Clock Detector ............................................................................. 4-53
INTCLK Buffer...................................................................................................................... 4-53
Data Selector........................................................................................................................ 4-53
ECL-to-TTL Translator and TTL Bus Buffer.........................................................................4-55
Full Valid Flag Latch............................................................................................................. 4-55
LSI-B A04U140 .................................................................................................................... 4-55
x
TABLE OF CONTENTS (cont.)
Section 5 VERIFICATION AND ADJUSTMENT PROCEDURES
INTRODUCTION.................................................................................................................................... 5-1
318/338 MULTI-PROBE TEST FIXTURE .............................................................................................. 5-1
TEST SETUP INFORMATION............................................................................................................... 5-4
Suggested Test Instruments .......................................................................................................... 5-4
FUNCTIONAL CHECK PROCEDURES FOR THE 318......................................................................... 5-6
Index of Functional Checks............................................................................................................ 5-7
Mainframe and Parallel Analyzer.................................................................................................... 5-7
Check 1. Power-up Diagnostics............................................................................................ 5-7
Check 2. Keyboard................................................................................................................ 5-7
Check 3. CRT........................................................................................................................ 5-8
Check 4. Threshold Voltage.................................................................................................. 5-9
Check 5. Parallel Data Acquisition with Test Output........................................................... 5-11
Check 6. Glitch Data Acquisition with Test Output.............................................................. 5-18
Check 7. Serial State Analyzer Check for the 318.............................................................. 5-19
ADJUSTMENT PROCEDURES FOR THE 318................................................................................... 5-22
Introduction................................................................................................................................... 5-22
Index of Adjustment Steps ........................................................................................................... 5-23
Mainframe .................................................................................................................................... 5-23
Parallel Analyzer........................................................................................................................... 5-27
Serial State Analyzer.................................................................................................................... 5-39
PERFORMANCE CHECK FOR THE 318............................................................................................ 5-43
Index of Performance Checks...................................................................................................... 5-43
The Performance Checks ............................................................................................................ 5-43
Test 1. Threshold Voltages ................................................................................................. 5-43
Test 2. Parallel Data Acquisition Word Recognition and Trigger
Sequencer Check with External Clock Minimum Period...................................................... 5-47
Test 3. Glitch Data Acquisition and Glitch Trigger .............................................................. 5-55
Test 4. Start Output and Trigger Output Test...................................................................... 5-58
Test 5. External Trigger Input Test...................................................................................... 5-59
Test 6. Serial State Analyzer (318S1)................................................................................. 5-60
FUNCTIONAL CHECK PROCEDURES FOR THE 318....................................................................... 5-63
Index of Functional Checks.......................................................................................................... 5-63
Mainframe and Parallel Analyzer.................................................................................................. 5-64
Check 1. Power-up Diagnostics.......................................................................................... 5-64
Check 2. Keyboard.............................................................................................................. 5-64
Check 3. Crt ........................................................................................................................ 5-64
Check 4. Threshold Voltage................................................................................................ 5-66
Check 5. Parallel Analyzer Check with Test Output............................................................ 5-67
Check 6. Glitch Data Acquisition Using Test Output........................................................... 5-74
Check 7. Serial State Analyzer Check for the 338S1.......................................................... 5-75
ADJUSTMENT PROCEDURES FOR THE 338................................................................................... 5-77
Introduction................................................................................................................................... 5-77
Index of Adjustment Steps ........................................................................................................... 5-78
xi
TABLE OF CONTENTS (cont.)
Section 5 VERIFICATION AND ADJUSTMENT PROCEDURES (cont.)
Mainframe .................................................................................................................................... 5-79
1. Adjust Power Supplies .................................................................................................... 5-79
2. Adjust CRT Circuit........................................................................................................... 5-81
3. Adjust Threshold Voltages on the A05 ROM Board....................................................... 5-82
Parallel Analyzer........................................................................................................................... 5-84
4. Adjust Threshold Voltages on the A02 Input-B Board.................................................... 5-84
5. Probe Compensation for the P6107 External Clock Probe............................................. 5-86
6. Adjust Ext Clk ↑ and Ext Clk ↓ Delay............................................................................. 5-87
7. Adjust delay of RET CLK, WE, ADRS CLK and TRIG CLK............................................ 5-89
Serial State Analyzer.................................................................................................................... 5-93
8. Adjust Threshold Voltages on the A07 Board................................................................. 5-93
9. Adjust Input Capacitance and Serial Data Probe Compensation.................................... 5-95
10. Adjust Non-Volatile Memory Battery Backup Threshold............................................... 5-98
PERFORMANCE CHECK FOR THE 338........................................................................................... 5-98
Index of Performance Checks...................................................................................................... 5-98
Test 1 - Threshold Voltages......................................................................................................... 5-99
Setup.................................................................................................................................... 5-99
Threshold Level TTL .......................................................................................................... 5-101
Threshold Levels V1, V2, and V3....................................................................................... 5-101
Test 2 - Parallel Data Acquisition, Word Recognition, and Trigger
Sequencer Checks with External Clock Minimum Period .......................................................... 5-102
Test 3 - Glitch Data Acquisition and Glitch Trigger .................................................................... 5-111
Setup.................................................................................................................................. 5-112
Negative Glitch................................................................................................................... 5-114
Test 4 - Start Output and Trigger Output.................................................................................... 5-114
Test 5 - External Trigger Input.................................................................................................... 5-116
Test 6 - Serial State Analyzer (338S1)....................................................................................... 5-117
Section 6 MAINTENANCE: GENERAL INFORMATION
TROUBLESHOOTING TREES .............................................................................................................. 6-1
TEST EQUIPMENT REQUIRED FOR MAINTENANCE........................................................................ 6-1
TOOLS REQUIRED FOR MAINTENANCE ........................................................................................... 6-1
MAINTENANCE PRECAUTIONS .......................................................................................................... 6-1
Soldering ........................................................................................................................................ 6-1
Light-Emitting Diodes (LEDs)......................................................................................................... 6-2
Static Precautions........................................................................................................................... 6-2
Lithium Battery Replacement......................................................................................................... 6-3
PREVENTIVE MAINTENANCE.............................................................................................................. 6-3
Exterior Cleaning............................................................................................................................ 6-3
Interior Cleaning............................................................................................................................. 6-4
Cleaning Guidelines....................................................................................................................... 6-4
Inspection....................................................................................................................................... 6-4
xii
TABLE OF CONTENTS (cont.)
Section 6 MAINTENANCE: GENERAL INFORMATION (cont.)
CORRECTIVE MAINTENANCE............................................................................................................. 6-5
Obtaining Replacements................................................................................................................ 6-5
Acquisition Boards and Probes...................................................................................................... 6-5
Repairing Multi-Conductor Connectors.......................................................................................... 6-5
Circuit Board Pin Replacement...................................................................................................... 6-6
DISASSEMBLY/INSTALLATION PROCEDURES................................................................................. 6-7
General Disassembly Precautions................................................................................................. 6-7
Circuit Board Locations.................................................................................................................. 6-7
Component Locations .................................................................................................................... 6-7
Removing and Replacement Instructions....................................................................................... 6-8
Removing the Cabinet............................................................................................................ 6-9
Removing the Front Panel...................................................................................................... 6-9
Removing the Keyboard....................................................................................................... 6-10
Removing the Power Supply Circuit Boards........................................................................ 6-10
Removing the CRT Circuit Board......................................................................................... 6-12
Removing the Cathode-Ray Tube (CRT)............................................................................. 6-12
Section 7 MAINTENANCE: TROUBLESHOOTING
318 DIAGNOSTIC TEST DESCRIPTIONS............................................................................................ 7-1
Index of 318 Diagnostic Test Descriptions..................................................................................... 7-1
318 Diagnostic Test Common Signal Paths................................................................................... 7-1
Mainframe ...................................................................................................................................... 7-3
1. Keyboard Test................................................................................................................... 7-3
2. CRT Test........................................................................................................................... 7-4
3. Jump Table ROM Test...................................................................................................... 7-6
4. Display RAM Test.............................................................................................................. 7-7
5. System RAM Test ............................................................................................................. 7-8
6. ROM Test.......................................................................................................................... 7-9
Parallel Analyzer........................................................................................................................... 7-11
7. Clock Test ....................................................................................................................... 7-11
8. Word Recognizer Test .................................................................................................... 7-13
9. Acquisition RAM Test...................................................................................................... 7-17
10. Sequence RAM Test..................................................................................................... 7-20
11. N & Delay Test.............................................................................................................. 7-23
12. Threshold Test .............................................................................................................. 7-26
13. SEQ Test....................................................................................................................... 7-28
318S1 Serial Analysis/RS232C/NVM........................................................................................... 7-29
14. Battery Test................................................................................................................... 7-29
15. Non-Volatile Memory Test............................................................................................. 7-30
16. RS-232 Test.................................................................................................................. 7-30
17. Serial Test..................................................................................................................... 7-32
Option I/O Function List................................................................................................................ 7-33
318 TROUBLESHOOTING TREES ..................................................................................................... 7-39
xiii
TABLE OF CONTENTS (cont.)
Section 7 MAINTENANCE: TROUBLESHOOTING (cont.)
338 DIAGNOSTIC TEST DESCRIPTIONS.......................................................................................... 7-93
Index of 338 Diagnostic Test Descriptions................................................................................... 7-93
338 Diagnostic Test Common Signal Paths................................................................................. 7-93
Mainframe .................................................................................................................................... 7-95
1. Keyboard Test................................................................................................................. 7-95
2. CRT Test......................................................................................................................... 7-96
3. Jump Table ROM Test.................................................................................................... 7-98
4. Display RAM Test............................................................................................................ 7-99
5. System RAM Test ......................................................................................................... 7-100
6. ROM Test...................................................................................................................... 7-100
Parallel Analyzer................................................................................................................................. 7-104
7. Clock Test ..................................................................................................................... 7-104
8. Word Recognizer Test .................................................................................................. 7-106
9. ACQ RAM Test.............................................................................................................. 7-110
10. SQRAM Test............................................................................................................... 7-113
11. N & DELAY Test.......................................................................................................... 7-116
12. Threshold Test ............................................................................................................ 7-119
13. SEQ Test..................................................................................................................... 7-121
338S1 Serial Analysis/RS232C/NVM......................................................................................... 7-122
14. Battery Test................................................................................................................. 7-122
15. Non-Volatile Memory Test........................................................................................... 7-122
16. RS-232 Test................................................................................................................ 7-123
17. Serial Test................................................................................................................... 7-124
Option I/O Function List.............................................................................................................. 7-126
338 TROUBLESHOOTING TREES ................................................................................................... 7-133
Section 8 REPLACEABLE ELECTRICAL PARTS................................................................................................ 8-1
Section 9 DIAGRAMS............................................................................................................................................ 9-1
Section 10 REPLACEABLE MECHANICAL PARTS............................................................................................. 10-1
Appendix A REFERENCES.......................................................................................................................................A-1
Appendix B INTRODUCTION....................................................................................................................................B-1
Appendix C ERROR AND ACQUISITION STATUS MESSAGES.............................................................................C-1
Appendix D MAINTENANCE ALLOCATION.............................................................................................................D-1
Appendix E ERROR CODES.....................................................................................................................................E-1
xiv
LIST OF ILLUSTRATIONS
Figure Page
3-1 Failure in the power-up Self Test .................................................................................................................. 3-6
3-2 Successful completion of the power-up Self Test ......................................................................................... 3-6
3-3 Diagnostics menu: first display...................................................................................................................... 3-7
3-4 Display sample with ALL/SINGLE and data entry fields................................................................................ 3-7
3-5 Display sample with LOOP and DISP fields.................................................................................................. 3-7
3-6 Display for KBD tests..................................................................................................................................... 3-8
3-7 CRT test: first display.................................................................................................................................... 3-8
3-8 CRT test: second display .............................................................................................................................. 3-9
3-9 CRT test: third display................................................................................................................................... 3-9
3-10 CRT test: fourth display................................................................................................................................. 3-9
3-11 Display for CLK tests..................................................................................................................................... 3-10
3-12 Display for word recognizer’s RAM tests....................................................................................................... 3-10
3-13 Display for acquisition’s RAM tests............................................................................................................... 3-11
3-14 Display for trigger sequencer’s RAM tests.................................................................................................... 3-11
3-15 Display for N counter or DLY counter tests................................................................................................... 3-12
3-16 Display for overall tests on parallel acquisition.............................................................................................. 3-12
3-17 Display for threshold tests............................................................................................................................. 3-13
3-18 Setup of probe compensation....................................................................................................................... 3-13
3-19 Display for probe compensation.................................................................................................................... 3-14
3-20 Setup for serial tests...................................................................................................................................... 3-15
3-21 Display for serial tests................................................................................................................................... 3-15
3-22 Setup for remote tests................................................................................................................................... 3-16
3-23 Display for remote tests................................................................................................................................. 3-16
3-24 Display for non-volatile memory tests........................................................................................................... 3-17
4-1 318 Input A and Input B block diagram......................................................................................................... 4-8
4-2 318 Simplified diagram of the ACQ control circuitry on schematics <5> and <6>........................................ 4-9
4-3 318 Simplified diagram of the ACQ control circuitry on schematic <7>........................................................ 4-10
4-4 318 SQRAM data register format.................................................................................................................. 4-11
4-5 318 Qualify register format............................................................................................................................ 4-11
4-6 318 Simplified diagram of the acquisition memory and ACQ address counter circuit .................................. 4-18
4-7 318 Simplified diagram of the timebase and MPU bus interface circuit........................................................ 4-23
4-8 318 Timing diagram of the slow-clock detector and timer circuit ..................................................................4-24
4-9 318/338 Simplified diagram of the ROM and threshold circuits.................................................................... 4-26
4-10 318/338 Simplified diagram of the MPU/Display board................................................................................. 4-29
4-11 318/338 Simplified diagram of the serial acquisition and RS-232C circuit.................................................... 4-31
4-12 318/338 Simplified diagram of the CRT circuit.............................................................................................. 4-35
4-13 318/338 Simplified diagram and waveform of the horizontal sweep generator............................................. 4-36
4-14 318/338 Simplified diagram of the power supply circuit................................................................................ 4-38
4-15 338 Input A and Input B block diagram......................................................................................................... 4-41
4-16 338 Simplified diagram of the ACQ control circuitry on schematics <5> and <6>........................................ 4-43
4-17 338 Simplified diagram of the ACQ control circuity on schematic <7>......................................................... 4-44
4-18 338 SQRAM data register format.................................................................................................................. 4-45
xv
LIST OF ILLUSTRATIONS (cont.)
Figure Page
4-19 338 Qualify register format............................................................................................................................ 4-45
4-20 338 Simplified diagram of the acquisition memory and ACQ address counter circuit .................................. 4-52
4-21 338 Simplified diagram of the timebase and MPU interface circuit............................................................... 4-54
4-22 338 Timing diagram of the slow-clock detector and timer circuit .................................................................. 4-55
5-1 Test fixture construction diagram.................................................................................................................. 5-2
5-2 Assembled test fixture................................................................................................................................... 5-3
5-3 318 Successful power-on diagnostic display................................................................................................. 5-7
5-4 318 Keyboard test display............................................................................................................................. 5-7
5-5 318 CRT test cross-hatch pattern ................................................................................................................. 5-8
5-6 318 CRT test white pattern............................................................................................................................ 5-8
5-7 318 CRT test parallel acquisition character fonts.......................................................................................... 5-8
5-8 318 CRT test serial acquisition character fonts............................................................................................. 5-8
5-9 318 Parallel data acquisition check setup..................................................................................................... 5-11
5-10 318 External trigger check setup................................................................................................................... 5-13
5-11 318 Trigger qualifier check setup.................................................................................................................. 5-16
5-12 318 Setup for serial data analysis................................................................................................................. 5-20
5-13 318 Setup for RS-232C control..................................................................................................................... 5-21
5-14 318 Power supply adjustment....................................................................................................................... 5-24
5-15 318 CRT adjustment..................................................................................................................................... 5-25
5-16 318 Threshold voltage adjustment on the ROM board (A05)....................................................................... 5-27
5-17 318 Threshold voltage adjustments on the Input B board (A02)................................................................... 5-29
5-18 318 Test equipment setup for the clock delay adjustment............................................................................ 5-32
5-19 318 EXT CLK and DLD CLK signal adjustment locations............................................................................. 5-33
5-20 318 RET CLK, WE, ADRS CLK, and TRIG CLK adjustments..................................................................... 5-38
5-21 318 Capacitor adjustment oscilloscope setup waveform.............................................................................. 5-38
5-22 318 Capacitor adjustment waveform............................................................................................................. 5-38
5-23 318 Serial analysis/RS-232C/NVM test points and adjustment locations..................................................... 5-39
5-24 318 Side view of A07, Serial analysis’RS-232C/,’NVM board....................................................................... 5-40
5-25 318 Input capacitance adjustment setup....................................................................................................... 5-42
5-26 318 Input capacitance waveform................................................................................................................... 5-42
5-27 318 Threshold voltage check setup............................................................................................................... 5-44
5-28 318 Parallel data acquisition test setup......................................................................................................... 5-48
5-29 318 Parallel data acquisition test waveform #1............................................................................................. 5-50
5-30 318 Parallel data acquisition test waveform #2............................................................................................. 5-50
5-31 318 Glitch data acquisition test setup............................................................................................................ 5-56
5-32 318 Glitch data acquisition test waveform #1................................................................................................ 5-57
5-33 318 Glitch data acquisition test waveform #2................................................................................................ 5-57
5-34 318 Serial state analyzer performance test setup......................................................................................... 5-61
5-35 338 Successful power-on diagnostic display................................................................................................. 5-64
5-36 338 Keyboard test display............................................................................................................................. 5-64
5-37 338 CRT test cross hatch display.................................................................................................................. 5-65
5-38 338 CRT test white pattern............................................................................................................................ 5-65
5-39 338 CRT test parallel acquisition character fonts.......................................................................................... 5-65
5-40 338 CRT test serial acquisition character fonts............................................................................................. 5-65
5-41 338 Parallel data acquisition check setup..................................................................................................... 5-69
xvi
LIST OF ILLUSTRATIONS (cont.)
Figure Page
5-42 338 External trigger check setup................................................................................................................... 5-71
5-43 338 Trigger qualifier check setup.................................................................................................................. 5-73
5-44 338 Setup for serial data analysis................................................................................................................. 5-76
5-45 338 Setup for RS-232C control..................................................................................................................... 5-77
5-46 338 Power supply adjustment....................................................................................................................... 5-80
5-47 338 CRT adjustment..................................................................................................................................... 5-81
5-48 338 Threshold voltage adjustment on the ROM board ................................................................................. 5-83
5-49 338 Threshold voltage adjustment on the (A02) Input B board..................................................................... 5-85
5-50 338 Test equipment setup for the clock delay adjustment............................................................................ 5-89
5-51 338 RET CLK, WE, ADRS CLK, and TRIG CLK adjustments...................................................................... 5-91
5-52 338 Capacitor adjustment oscilloscope setup waveform.............................................................................. 5-93
5-53 338 Capacitor adjustment waveform............................................................................................................. 5-93
5-54 338 Serial analysis/RS-232C/NVM test points and adjustment locations..................................................... 5-94
5-55 338 Side view of A07, Serial analysis/RS-232C/NVM board......................................................................... 5-95
5-56 338 Input capacitance adjustment................................................................................................................. 5-97
5-57 338 Input capacitance waveform................................................................................................................... 5-97
5-58 338 Threshold voltage check setup............................................................................................................... 5-100
5-59 338 Parallel data acquisition test setup......................................................................................................... 5-106
5-60 338 Parallel data acquisition test waveform #1............................................................................................. 5-106
5-61 338 Parallel data acquisition test waveform #2............................................................................................. 5-106
5-62 338 Glitch data acquisition test setup............................................................................................................ 5-112
5-63 338 Glitch data acquisition test waveform #1................................................................................................ 5-113
5-64 338 Glitch data acquisition test waveform #2................................................................................................ 5-114
5-65 338 Serial state analyzer performance test setup......................................................................................... 5-117
6-1 Multi-conductor terminal connectors ............................................................................................................. 6-6
6-2 Circuit board pin replacement ....................................................................................................................... 6-6
6-3 318/338 circuit board locations...................................................................................................................... 6-8
6-4 Cabinet removal............................................................................................................................................ 6-9
6-5 Power supply removal................................................................................................................................... 6-11
7-1 318 Keyboard test schematic........................................................................................................................ 7-4
7-2 318 CRT calibration and check..................................................................................................................... 7-5
7-3 318 Memory map .......................................................................................................................................... 7-6
7-4 318 MPU memory address assignment........................................................................................................ 7-7
7-5 318 A03 and A04 partial ACQ address assignment...................................................................................... 7-10
7-6 318 Clock test................................................................................................................................................ 7-13
7-7 318 Word recognizer test.............................................................................................................................. 7-16
7-8 318 ACQ memory test................................................................................................................................... 7-19
7-9 318 SQRAM test ........................................................................................................................................... 7-22
7-10 318 N and Delay counter test........................................................................................................................ 7-25
7-11 318 Threshold test......................................................................................................................................... 7-28
7-12 Troubleshooting Tree 1: Power On............................................................................................................... 7-39
7-13 Troubleshooting Tree 2: Startup Self Test.................................................................................................... 7-40
7-14 Troubleshooting Tree 3: Power Supplies A11, A12...................................................................................... 7-41
7-15 Troubleshooting Tree 4: CRT A10................................................................................................................ 7-43
7-16 Troubleshooting Tree 5: MPU A06................................................................................................................ 7-47
xvii
LIST OF ILLUSTRATIONS (cont.)
Figure Page
7-17 Troubleshooting Tree 6: Clock A04............................................................................................................... 7-52
7-18 Troubleshooting Tree 7: Word Recognizer (WR A01 A02)........................................................................... 7-54
7-19 Troubleshooting Tree 8: Data Acquisition (ACQ A01 A02)........................................................................... 7-57
7-20 Troubleshooting Tree 9: SQRAM A03........................................................................................................... 7-63
7-21 Troubleshooting Tree 10: N&DL A03............................................................................................................ 7-67
7-22 Troubleshooting Tree 11: SEQ A03.............................................................................................................. 7-69
7-23 Troubleshooting Tree 12: T/H A01, A02........................................................................................................ 7-73
7-24 Troubleshooting Tree 13: T/H A04................................................................................................................ 7-74
7-25 Troubleshooting Tree 14: SER A07 (TSTSR2)............................................................................................. 7-75
7-26 Troubleshooting Tree 15: RMT A07 (TSTRM2)............................................................................................ 7-79
7-27 Troubleshooting Tree 16: Non-Volatile Memory (NVM A07)......................................................................... 7-83
7-28 Troubleshooting Tree 17: Can’t Get Glitch.................................................................................................... 7-85
7-29 Troubleshooting Tree 18: Can’t Get Good Data............................................................................................ 7-86
7-30 Troubleshooting Tree 19: Diagnostics Pass Can’t Stop................................................................................ 7-88
7-31 Troubleshooting Tree 20: Can’t Get Glitch Trigger....................................................................................... 7-90
7-32 Troubleshooting Tree 21: Test Output - Doesn’t Work ................................................................................. 7-91
7-33 338 Keyboard test schematic........................................................................................................................ 7-96
7-34 338 CRT calibration and check..................................................................................................................... 7-97
7-35 338 Memory map .......................................................................................................................................... 7-98
7-36 338 MPU memory address assignment........................................................................................................ 7-101
7-37 338 A03 and A04 partial ACQ address assignment...................................................................................... 7-103
7-38 338 Clock test................................................................................................................................................ 7-105
7-39 338 Word recognizer test.............................................................................................................................. 7-109
7-40 338 ACQ memory test................................................................................................................................... 7-112
7-41 338 SQRAM test ........................................................................................................................................... 7-114
7-42 338 N and Delay counter test........................................................................................................................ 7-118
7-43 338 Threshold test......................................................................................................................................... 7-119
7-44 Troubleshooting Tree 1: Power On............................................................................................................... 7-133
7-45 Troubleshooting Tree 2: Self Test................................................................................................................. 7-134
7-46 Troubleshooting Tree 3: Power Supplies A11, A12...................................................................................... 7-135
7-47 Troubleshooting Tree 4: CRT A10................................................................................................................ 7-137
7-48 Troubleshooting Tree 5: MPU A06................................................................................................................ 7-141
7-49 Troubleshooting Tree 6: Clock A04 (CLK).................................................................................................... 7-146
7-50 Troubleshooting Tree 7: Word Recognizer (WR A01 A02)........................................................................... 7-148
7-51 Troubleshooting Tree 8: Data Acquisition (ACQ A01 A02)........................................................................... 7-152
7-52 Troubleshooting Tree 9: SQRAM A03........................................................................................................... 7-159
7-53 Troubleshooting Tree 10: NDL A03............................................................................................................... 7-163
7-54 Troubleshooting Tree 11: SEQ A03.............................................................................................................. 7-165
7-55 Troubleshooting Tree 12: T/H A01, A02........................................................................................................ 7-169
7-56 Troubleshooting Tree 13: T/H A04................................................................................................................ 7-170
7-57 Troubleshooting Tree 14: SER A07 TSTSR2 ............................................................................................... 7-171
7-58 Troubleshooting Tree 15: REMOTE A07 TSTRM2 (RMT) ........................................................................... 7-175
7-59 Troubleshooting Tree 16: Non-Volatile Memory (NVM A07)......................................................................... 7-179
7-60 Troubleshooting Tree 17. Can’t Get Glitch................................................................................................... 7-181
7-61 Troubleshooting Tree 18: Can’t Get Good Data............................................................................................ 7-182
7-62 Troubleshooting Tree 19: Diagnostics Pass Can’t Stop................................................................................ 7-184
7-63 Troubleshooting Tree 20: Can’t Get Glitch Trigger....................................................................................... 7-185
7-64 Troubleshooting Tree 21: Test Output Doesn’t Work ................................................................................... 7-186
xviii
LIST OF TABLES
Figure Page
1-1 318/338 Electrical Specifications................................................................................................................... 1-4
1-2 318/338 Environmental Specifications.......................................................................................................... 1-16
1-3 318/338 Physical Specifications.................................................................................................................... 1-17
4-1 318 LSI-A Input Signals................................................................................................................................. 4-16
4-2 318 LSI-A Output Signals.............................................................................................................................. 4-17
4-3 318 LSI-B (A04U140) Input Signals.............................................................................................................. 4-21
4-4 318 LSI-B (A04U140) Output Signals ........................................................................................................... 4-21
4-5 Internal Clock (INTCLK)................................................................................................................................ 4-22
4-6 Memory Map.................................................................................................................................................. 4-24
4-7 I/O Map.......................................................................................................................................................... 4-25
4-8 Data Bus Buffer Control ................................................................................................................................ 4-32
4-9 Option I/O Device Addressing and Function................................................................................................. 4-33
4-10 Programmable Bit-Rate Generator Outputs.................................................................................................. 4-34
4-11 338 LSI-A Input Signals................................................................................................................................. 4-50
4-12 338 LSI-A Output Signals.............................................................................................................................. 4-51
4-13 338 LSI-B (A04U140) Input Signals.............................................................................................................. 4-56
4-14 338 LSI-B (A04U140) Output Signals........................................................................................................... 4-56
4-15 338 Internal Clock (INTCLK)......................................................................................................................... 4-57
5-1 Equipment needed for the Adjustment Procedures and the Performance Check Procedures..................... 5-5
5-2 Minimum Specifications for Test Equipment................................................................................................. 5-6
5-3 318 Adjustable Power Supply Tolerances..................................................................................................... 5-24
5-4 318 Non-adjustable Power Supply Tolerances............................................................................................. 5-25
5-5 318 Clock Delay With Extender..................................................................................................................... 5-37
5-6 318 Clock Delay Without Extender................................................................................................................ 5-37
5-7 318 Voltage Levels for Testing TTL .............................................................................................................. 5-46
5-8 318 Voltage Levels for Testing V1, V2, and V3............................................................................................. 5-46
5-9 318 Parallel Data Test Conditions and Expectations.................................................................................... 5-51
5-10 318 Positive Glitch Pulse Generator Setup................................................................................................... 5-57
5-11 318 Negative Glitch Pulse Generator Setup................................................................................................. 5-58
5-12 318 Serial State Analyzer Test Setup............................................................................................................ 5-62
5-13 338 Adjustabale Power Supply Tolerances................................................................................................... 5-80
5-14 338 Non-adjustable Power Supply Tolerances............................................................................................. 5-80
5-15 338 Data Threshold DC Balance................................................................................................................... 5-86
5-16 338 Clock Delay With Extender..................................................................................................................... 5-92
5-17 338 Clock Delay Without Extender................................................................................................................ 5-93
5-18 338 Voltage Levels for Testing TTL.............................................................................................................. 5-101
5-19 338 Voltage Levels for Testing V1, V2, and V3............................................................................................. 5-102
5-20 338 Parallel Data Test Oscilloscope Setup................................................................................................... 5-105
5-21 338 Parallel Data Test Pulse Generator Setup............................................................................................. 5-105
5-22 338 Test Conditions and Expectations.......................................................................................................... 5-107
5-23 338 Parallel Data Test Conditions and Expectations.................................................................................... 5-107
5-24 338 Positive Glitch Pulse Generator Setup................................................................................................... 5-113
5-25 338 Negative Glitch Pulse Generator Setup................................................................................................. 5-114
5-26 338 Serial State Analyzer Test Setup............................................................................................................ 5-119
xix
LIST OF TABLES (cont.)
Figure Page
6-1 Relative Susceptibility of Semiconductors to Static Discharge Damage....................................................... 6-3
7-1 318 Diagnostic Test Common Signal Paths.................................................................................................. 7-2
7-2 318 Keyboard Test Key Code and Interrupt Assignment.............................................................................. 7-3
7-3 318 ROM Test Address Assignment............................................................................................................. 7-9
7-4 318 Clock Test Program Ranges.................................................................................................................. 7-12
7-5 318 Word Recognizer Test Port Addresses.................................................................................................. 7-14
7-6 318 ACQ Test Port Addresses...................................................................................................................... 7-17
7-7 318 SQRAM Test Port Addresses................................................................................................................. 7-21
7-8 318 SQRAM Test SQRAM Data Connections .............................................................................................. 7-21
7-9 318 SQRAM Test SQRAM Address Connections......................................................................................... 7-22
7-10 318 Threshold Test Data Values................................................................................................................... 7-27
7-11 318 RS-232C Test I/O Addresses................................................................................................................. 7-31
7-12 318 Serial Test I/O Addresses...................................................................................................................... 7-33
7-13 318 Serial Test Baud Select Bits................................................................................................................... 7-34
7-14 318 Diagnostic Test Failure Codes............................................................................................................... 7-36
7-15 338 Diagnostic Test Common Signal Paths.................................................................................................. 7-94
7-16 338 Keyboard Test Key Code and Interrupt Assignment.............................................................................. 7-95
7-17 338 ROM Test Address Assignment............................................................................................................. 7-101
7-18 338 Clock Test Program Ranges.................................................................................................................. 7-106
7-19 338 Word Recognizer Test Port Addresses.................................................................................................. 7-107
7-20 338 ACQ Test Port Addresses...................................................................................................................... 7-111
7-21 338 SQRAM Test Port Addresses................................................................................................................. 7-113
7-22 338 SQRAM Test SQRAM Data Connections.............................................................................................. 7-115
7-23 338 SQRAM Test SQRAM Address Connections......................................................................................... 7-115
7-24 338 Threshold Test Data Values................................................................................................................... 7-120
7-25 338 RS-232C Test I/O Addresses................................................................................................................. 7-124
7-26 338 Serial Test I/O Addresses...................................................................................................................... 7-126
7-27 338 Serial Test Baud Select Bits................................................................................................................... 7-127
7-28 338 Diagnostic Test Failure Codes............................................................................................................... 7-129
E-1 Error Codes in Self Test................................................................................................................................ E-1
E-2 Error Codes of Parallel Tests in Diagnostics Menu....................................................................................... E-2
E-3 Error Codes of Serial Tests in Diagnostics Menu ......................................................................................... E-3
E-4 Error Codes of Remote Tests in Diagnostics Menu...................................................................................... E-4
E-5 Error Codes of NVM Tests in Diagnostics Menu........................................................................................... E-5
xx
OPERATOR’S SAFETY SUMMARY
The general safety information in this summ ary is for both operator and s ervice personnel. Specif ic cautions and warnings are found throughout the manual where they apply, but may not appear in this summary.
TERMS IN THIS MANUAL
CAUTION statements identify conditions or practices that could result in damage to the equipment or other property.
WARNING statements identify conditions or practices that could result in personal injury or loss of life.
TERMS AS MARKED ON EQUIPMENT
CAUTION indicates a personal injur y hazard not immediately accessible as one r eads the m ark ing, or a hazard to property including the equipment itself.
DANGER indicates a personal injury hazard immediately accessible as one reads the marking.
DANGER -High voltage.
3 Protective ground (earth) terminal.
ATTENTION - refer to manual.
xxi
GROUNDING THE PRODUCT
This product is intended to operate from a power source that does not apply more than 250 volts rm s between the supply conductors or between either supply conductor and ground. This product is grounded through the grounding conductor of the power cord. To avoid electrical shock, plug the power cord into a properly wired receptacle before connecting to the produc t. A protec tive- ground c onnec tion by way of the grounding conductor in the power cord is essential for safe operation.
DANGER ARISING FROM LOSS OF GROUND
Upon loss of the protective-ground connection, all ac cessible conductive parts (including k nobs and controls that may appear to be insulating) can render an electric shock.
USE THE PROPER POWER CORD
Use only the power cord and connector specified for your product, and be sure it is in good condition. Refer to the
USE THE PROPER FUSE
To avoid fire hazard, use only a fuse of the correct type, voltage rating, and current rating as spec ified in the parts list for this product. Also, ensur e that the line selector s witch is in the proper position f or- the power sourc e being used.
BATTERY REPLACEMENT
Refer lithium battery replacement to qualified service personnel.
DO NOT OPERATE IN EXPLOSIVE ATMOSPHERES
To avoid explosion. do riot operate this product in an explosive atmosphere unless it has been specifically certified for such operation.
Operating Information
section of this manual for information on power cords and connectors.
xxii
SERVICE SAFETY SUMMARY
FOR QUALIFIED SERVICE PERSONNEL ONLY
Refer also to the Operator’s Safety Summary.
DO NOT SERVICE ALONE
Do not perform internal service or adjustment of this product unles s another person capable of render ing first aid and resuscitation is present.
USE CARE WHEN SERVICING WITH POWER ON
Dangerous voltages exist at several points in this product. To avoid personal injury, do not touch exposed connections and components while power is on. Dis connect power before removing protec tive panels, soldering, or replacing components.
USE CAUTION WHEN SERVICING THE CRT
The CRT should be serviced only by qualified personnel familiar with CRT servicing procedures and precautions. CRTs retain hazardous voltages for long periods of time after power-down. Before attem pting any work inside the
monitor, discharge the CRT by shorting the anode to chassis ground. W hen discharging the CRT, connect the discharge path to ground and then the anode.
Use extreme caution when handling the CRT. Rough handling may cause it to implode. Do not nick or scr atch the glass or subject it to undue pressure during removal or installation. W hen handling the CRT, wear safety goggles and heavy gloves for protection.
REMOVE LOOSE OBJECTS
During disassembly or installation procedures, screws or other small objects may fall to the bottom of the mainfram e. To avoid shorting out the power s upply, do not power up the instrument until such obj ects have been removed.
LITHIUM BATTERY REPLACEMENT
To avoid personal injury, observe proper procedures for handling and disposal of lithium batteries. Improper handling may cause fire, explosion, or severe bur ns. Don’t recharge, crush, disas semble, heat the battery above
212° F (100° C), incinerate, or expose contents of the battery to water. Dispose of battery in accordance with local, state, and national regulations.
xxiii/(xxiv blank)

SECTION 0

INTRODUCTION
0-1. SCOPE
This manual describes Logic Analyzer, TEK Model 318/338 and provides instructions for operation and maintenance.
0-2. CONSOLIDATED INDEX OF ARMY PUBLICATIONS AND BLANK FORMS
Refer to the latest issue of DA. Pam 310-1 to determine whether there are new editions, changes or additional publications pertaining to the equipment.
0-3. MAINTENANCE FORMS, RECORDS, AND REPORTS
a. Reports of Maintenance and Unsatisfactory Equipment
equipment maintenance will be those prescribed by DA Pam 738-750, as contained in Maintenance Management Update.
b. Report of Packaging and Handling Deficiencies
prescribed in AR 735-11-2/DLAR 4140.55/ NAVMATINST 4355.73A/AFR 400-54/MCO 4430-3F.
c. Discrepancy in Shipment Report (DISREP) (SF 361
(DISREP) (SF 361) as prescribed in AR 55-38/NAVSUPINST 4610.33C/AFR 75-18/MCO P4610.19D/DLAR 4500.15.
0-4. REPORTING EQUIPMENT IMPROVEMENT RECOMMENDATIONS (EIR)
If your Logic Analyzer, TEK Model 318/388 needs improvement, let us k now. Send us an EIR. You, the user , ar e the only one who can tell us what you don’t like about your equipment. Let us know why you don’t like the design. Put if on an SF 368 (Quality Deficiency Report). Mail it to Commander, US Army Communications- Electronics Command and Fort Monmouth, ATTN: AMSEL-ME-MP, Fort Monmouth, NJ 07703-5007. We’ll send you a reply.
0-5. ADMINISTRATIVE STORAGE
Administrative storage of equipment iss ued to and used by Army activities will have preventive maintenance per form ed in accordance with the PMCS charts before s toring. W hen rem oving the equipment from adminis trative storage, the PMCS should be performed to assur e operational readiness. Disassembly and repacking of equipm ent for shipment or lim ited storage are covered in section 6.
0-6. DESTRUCTION OF ARMY ELECTRONICS MATERIEL
Destruction of Army electronics materiel to prevent enemy use shall be in accordance with TM 750-244-2.
. Fill out and forward SF 364 (Report of Discrepancy (ROD)) as
. Department of the Army forms and procedur es used for
). Fill out and forward Discrepancy in Shipment Report
0-1/(0-2 blank)
INTRODUCTION AND SPECIFICATIONS
INTRODUCTION
This manual will help you service both the Sony/Tektronix 318 Logic Analyzer and the Sony/Tektronix 338 Logic Analyzer. The procedures and descriptions contained herein apply to both Instruments. Unless otherwise specified, all screen displays have been developed from the 338S1. The 338S1 contains all the basic features of the standard 338 plus the following additional features: serial state analysis, an RS-232C interface, and non-volatile memory.
DESCRIPTION
The Sony/Tektronix 318 and 338 are keyboard-controlled, multifunction, portable logic analyzers. Each can operate as a parallel tim ing analyzer or a parallel state analyzer, and each is provided with composite video
output. The Sony/Tektronix 318S1 and 338S1 provide several additional features: serial state analysis, RS-232C interface, and non-volatile memory.
The instruments ar e m enu-driven s ystems. T his m eans that all operations ar e set up via m enus that are displayed on the monitor screen. There are three m enus for setting up parallel data acquisition, three menus for setting up serial data acquisition, one menu for remote operation, one menu for non-volatile memory operation, and two menus for data display.
MODES OF OPERATION
When used as a parallel timing analyzer, the 318 provides a 16-channel-wide input, 50 MHz (maxim um ) clock speed, and 256 bits/channel memory for data. Glitches are captured on all 16 channels. The 338 provides a 32-channel-wide input, 20 MHz (maximum) clock speed, and 256 bits/channel m emor y for data. Glitches are captur ed on eight channels. T hree word recognizers can be specified on all c hannels and used in several different triggering s equences. The digital delay counts up to 65,000 clock cycles. In the 318, data before or after the occurrence of a spec ified trigger s equence can be acquired and stored at sample intervals ranging from 20 ns to 500 ms with two lock and trigger qualif iers. In the 338, data before or after the occurrence of a spec if ied tr igger s equenc e c an be acquir ed and s tored at s ample intervals ranging from 50 ns to 500 ms with four clock and trigger qualif iers. The s tored data can be displayed on the CRT sc reen in a timing or state format.
A composite video output for har d-copy units or video terminals is provided. This feature allows doc umentation of test results and operating parameters.
As a serial state analyzer, the 318S1/338S1 acquires serial data in five, six, seven, eight, or nine bits/character in asynchronous or synchronous timing. Two continuous word recognizers provide triggering upon recognition of preset words. The digital delay counts up to 65,000 words. Data before or after the occ urrence of a specif ied trigger sequence can be acquired and stored at baud rates ranging from 50 to 19.2K baud. T he s tored data is dis played on the CRT scr een in binary, octal, decimal, hexadecimal, ASCII, or EBCDIC format.
The RS-232C interface port allows the 318S1/338S1 to be link ed with terminal equipment through an asynchronous, full­duplex modem. In remote control mode, the 318S1/338S1 c an r eceive all c ontr ol commands, m emory control commands, or reference mem ory data from the ter minal equipm ent instead of the keyboard. It can send the CRT display inform ation or memory data to the terminal equipment via the RS-232C port.
1-1
Introduction & Specifications-318/338 Service
The non-volatile mem ory can retain three setups and one set of reference or ac quired data for about five years. Each memory area is selectable f or the use of parallel or serial inform ation. The current setup of the instrum ent is stored by keyboard control or control comm ands from the term inal. The stored setup inform ation is recalled in the same manner. The data can be stored and recalled only by the 318S1/338S1 keyboard.
All functional parameters and operation of the instrument ar e programmable from the front panel or over the RS-232C port.
CONFIGURATIONS
The Sony/Tektronix 318/338 is available in the following configurations:
• 318 Logic Analyzer
• 338 Logic Analyzer
• 318S1 Logic Analyzer (with serial analysis, RS-232C interface, and non-volatile memory). A standard 318 can be upgraded to 318S1 status by installing the 318F1 package.
• 338S1 Logic Analyzer (with serial analysis, RS-232C interface, and non-volatile memory). A standard 338 can be upgraded to 338S1 status by installing the 338F1 upgrade package.
318F1 Package: Optional field-installable circuit board, probe, and connectors that upgrade the 318 Logic Analyzer to 318S1 status. The package adds serial analysis, an RS-232C interface, and non-volatile mem ory to the basic 318 features.
338F1 Package: Optional field-installable circuit board, probe, and connectors that upgrade the 338 Logic Analyzer to 338S1 status. The package adds serial analysis, an RS-232C interface, and non-volatile mem ory to the basic 338 features.
RELATED DOCUMENTS
In addition to this service manual, the 318/338 Operator 's Manual, the 318/338
318/338 Logic Analyzer Workbook
will also help you understand and operate the 318/338.
1-2
Logic Analyzer Reference Guide
, and the
Introduction & Specifications-318/338 Service
STANDARD AND OPTIONAL ACCESSORIES
Standard Accessories:
016-0697-00 Accessory Pouch 070-4433-00 070-4435-00 070-7061-00 010-6107-03 P6107 Probe
010-6451-07 P6451 Probe
161-0104-00 Power Cord
Options:
A1-A5 Power Cords 318F1/338F1 Field-installable upgrade package; adds serial analysis, RS-232C interfac e, and non-volatile
318/338 Logic Analyzer Operator’s Manual 318/338 Logic Analyzer Reference Guide 318/338 Logic Analyzer Workbook
(1 probe with 318/338) (2 probes with 318S1/338S1)
(2 probes with 318) (4 probes with 338)
memory to standard 318/338.
Optional Accessories:
070-4434-00 067-1159-00 Service Maintenance Kit 012-0530-00 Null Modem Cable 013-0173-01 Self Test Adapter 175-1178-00 Trig in/out Cable
318/338 Logic Analyzer Service Manual
1-3
Tables 1-1 through 1-3 list the electrical, environmental, and physical characteristics of the 318, 338, 318S1 ,and 338S1 logic analyzers. The electrical characteristic s are valid for logic analyzers that have been adjusted as described in this manual (refer to the Verification and Adjustment Procedures section). The instruments are adjusted at an
ambient temperature between +20° to +30°C (+68° to 68° F), and are designed to operate in an ambient temperature between 0° to +50°C (+32° to +122°F) after having warmed up for at least 15 minutes.
Characteristics Requirements Information
PARALLEL ANALYZER FUNCTION
Introduction & Specifications-318/338 Service
SPECIFICATIONS
Table 1-1.
318/338 ELECTRICAL SPECIFICATIONS
Performance Supplemental
Data Input (P6451 Probe) See P6451 literature for more
information.
Channels 318
16 channels. Glitch data is detected on all 16 channels.
338
32 channels. Glitch data is detected on low­order 8 channels (Pod A).
Input R and C 1 MΩ ± 5%, paralleled by approx. 5 pF
(without leads). Minimum logic swing 500 mV p-p 4% of threshold voltage. Maximum logic swing -15 V to threshold voltage plus 10 V. Maximum non-destructive ± 40 V max. Glitch data width 5 ns minimum with 350 mV overdrive from
threshold. Threshold Voltage Accuracy
V1 (0.1 V step variable) -10 V to +10 V ±0.2 V V2 (0.1 V step variable) -10 V to -+10 V ±0.2 V V3 (V1 + V2) /2 ±0.2 V TTL +1.4 V ±0.2 V
One of four levels is selectable for each pod.
1-4
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