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TEK933 (PCI-933)
PENTIUM PROCESSOR
PCI-ISA SINGLE BOARD COMPUTER
TECHNICAL REFERENCE MANUAL
VERSION 2.2, JUNE 1997
TEKNOR INDUSTRIAL COMPUTERS INC.
616 Cure Boivin
Boisbriand, Quebec
J7G 2A7 CANADA
NOTE:
This manual is for reference purposes only.
Reproduction in whole or in part is authorized
provided TEKNOR INDUSTRAL COMPUTERS
INC. is cited as the original source.
ref: M933S_2-2
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FOREWORD
The information in this document is provided for reference purposes only. TEKNOR
does not assume any liability for application of the information or use of the products
described herein.
This document may contain or reference information and products protected by the
copyrights or patents of others and does not convey any license under the patent right
of TEKNOR, nor the rights of others.
Printed in Canada.
Copyright 1996 by TEKNOR INDUSTRIAL COMPUTER INC., Boisbriand, Qc J7G
2A7.
Foreword iii
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TABLE OF CONTENTS
Foreword iii
List of Diagrams xi
List of Tables xiii
READ ME FIRST 1
INTRODUCTION 1
PART ONE
QUICK INSTALLATION
1 INSTALLING SYSTEM MEMORY 1-1
1.01 Static Electricity Precautions 1-1
1.02 Location of SIMM Sockets 1-2
1.03 SIMM Configuration 1-3
1.04 SIMM Installation 1-6
2 JUMPER LOCATIONS & CONFIGURATION 2-1
2.01 Jumper Locations 2-1
2.02 Jumper Settings 2-5
3 INSTALLING TEK933 IN PASSIVE BACKPLANE 3-1
4 CONNECTOR LOCATIONS & PIN-OUTS 4-1
4.01 Location of Connectors on the Board 4-1
4.02 Connector Pin-Outs 4-5
5 SOFTWARE SETUPS 5-1
5.01 Accessing AMIBIOS Setup Program 5-1
5.02 Accessing VIP-UP Program 5-2
Table of Contents v
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PART TWO
HARDWARE REFERENCE
6 SYSTEM 6-1
6.01 Location of System Components 6-1
6.02 Microprocessor 6-8
6.03 Fan Connector 6-10
6.04 PCI/ISA System Controller 6-11
6.05 Cache 6-16
6.06 System Memory (DRAM) 6-17
6.07 BIOS (Flash EPROM & EPROM) 6-18
6.08 Battery 6-19
6.09 Supervisor Utilities 6-20
6.10 Real Time Clock AT Keyboard & PS/2 Mouse Controller 6-21
6.11 Multi-Function Connector
(Keyboard, Speaker, Reset, LED) 6-22
6.12 PS/2 Mouse Connector 6-24
7 PCI-ISA BUS 7-1
7.01 Location of PCI-ISA Bus Connector 7-1
7.02 PCI-ISA Connector Pin-Outs 7-2
7.03 PCI-ISA Connector Description 7-6
8 SYSTEM I/O CONTROLLER 8-1
8.01 Location of System I/O Controller 8-1
8.02 System I/O Controller Features 8-2
9 IDE & FLOPPY 9-1
9.01 Installing IDE Devices 9-1
9.02 Installing Floppy Devices 9-6
10 SERIAL & PARALLEL PORTS 10-1
10.01 Serial Ports 10-1
10.02 Parallel Port 10-8
11 SCSI 11-1
11.01 Installing SCSI Devices 11-1
Table of Contents vi
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12 ETHERNET 12-1
12.01 Ethernet Features 12-1
12.02 Setting Up Ethernet 12-1
12.03 Ethernet Connectors 12-2
13 VIDEO 13-1
13.01 Location of Video Components 13-1
13.02 Flat Panel / CRT VGA Controller 13-3
13.03 Connecting CRT Video Display 13-4
13.04 Connecting Flat Panel Video Display 13-5
13.05 Video Feature Connector (J11) 13-7
14 POWER MANAGEMENT 14-1
14.01 Power Management Modes 14-1
14.02 Reset Circuit 14-2
14.03 Power Fail Detection Circuit 14-3
14.04 Watchdog Timer 14-4
Table of Contents vii
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PART THREE
SOFTWARE REFERENCE
15 AMIBIOS SETUP 15-1
15.01 Accessing AMIBIOS Setup Program 15-1
15.02 AMIBIOS Setup Main Menu 15-2
15.03 Making Selections, Saving Configurations
& Exiting AMIBIOS Setup 15-3
15.04 Setup Window 15-6
15.05 Utility Window 15-24
15.06 Security Window 15-25
15.07 Default Window 15-26
16 VIP-UP SETUP 16-1
16.01 Accessing VIP-UP Setup Program 16-1
16.02 VIP-UP Screen 16-2
17 UPDATING BIOS WITH UBIOS 17-1
17.01 UBIOS - Interactive Mode 17-2
17.02 UBIOS - Batch Mode 17-7
18 VT100 MODE 18-1
18.01 VT100 Requirements 18-1
18.02 VT100 Setup & Configuration 18-2
18.03 Running Without a Terminal 18-4
Table of Contents viii
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APPENDICES
A TEK933 SPECIFICATIONS A-1
A.01 Board Specifications A-1
A.02 MTBF A-2
A.03 Meeting Industry Standards A-9
B MEMORY & I/O MAPS B-1
C TEK933 BOARD DIAGRAMS C-1
D RECOMMENDED DEVICES & MATING CONNECTORS D-1
E POST CODES & ERROR CODES E-1
E.01 Post Codes E-1
E.02 Word Check-Points E-7
E.03 Beep Error Codes E-8
GETTING HELP 1
Table of Contents ix
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LIST OF DIAGRAMS
1-1 SIMM Sockets Location 1-2
2-1 Jumper Locations With Default Settings 2-3
4-1 Connector Locations 4-3
6-1 System Components Location (Bottom of Board) 6-3
6-2 System Components Location (Top of Board) 6-5
7-1 PCI-ISA Bus Connector Location 7-1
8-1 System I/O Controller Location 8-1
9-1 IDE Connectors Location 9-2
9-2 Floppy Connector Location 9-7
9-3 Floppy Disk Cable 9-9
10-1 Serial Ports Location 10-2
10-2 Parallel Port Location 10-9
13-1 Video Components Location (Top of Board) 13-2
13-2 Video Components Location (Bottom of Board) 13-2
18-1 VT100 Full Setup 18-3
18-2 VT100 Partial Setup 18-3
B-1 Memory Map Diagram B-1
C-1 TEK933 Assembly (Top) C-3
C-2 TEK933 Assembly (Bottom) C-5
LIST OF DIAGRAMS (Continued)
List of Diagrams xi
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C-3 TEK933 Configuration C-7
C-5 TEK933 Mechanical Specifications C-9
C-7 TEK933 Block Diagram C-11
List of Diagrams xii
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LIST OF TABLES
1-1a TEK933 SIMM Configurations: 2MB - 24MB 1-4
1-1b TEK933 SIMM Configurations: 32MB - 128MB 1-5
2-1a Jumper Settings: W1 - W6, W14 - W17 2-6
2-1b Jumper Settings: W7-W9, W23 2-7
2-1c Jumper Settings: W13, W18 - W22 2-8
2-1d Jumper Settings: W24 - W27, J14 2-9
4-1 Fan Connector (J1) - Pin-Out 4-6
4-2 SCSI Interface Connector (J2) - Pin-Out 4-6
4-3 Hard Disk Connector #1 (J3) - Pin-Out 4-7
4-4 Floppy Disk Connector (J4) - Pin-Out 4-8
4-5 Multi-Function Connector - Keyboard, Speaker,
Reset, LED (J5) - Pin-Out 4-9
4-6 Serial Port 1 (J6) - RS232 - Pin-Out 4-9
4-7a Serial Port 2 (J7) - RS232 - Pin-Out 4-10
4-7b Serial Port 2 (J7) - RS485/RS422 - Pin-Out 4-10
4-8 Hard Disk Connector #2 (J8) - Pin-Out 4-11
4-9 Flat Panel Connector (J9) - Pin-Out 4-12
4-10a Parallel Port Connector (J10) - Standard Mode - Pin-Out 4-13
4-10b Parallel Port Connector (J10) - EPP Mode - Pin-Out 4-14
4-10c Parallel Port Connector (J10) - ECP Mode - Pin-Out 4-15
LIST OF TABLES (Continued)
List of Tables xiii
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4-11 Video Feature Connector (J11) - Pin-Out 4-16
4-12 Optional Analog Encoder Connector (J12) - Pin-Out 4-16
4-13 PS/2 Mouse Connector (J13) - Pin-Out 4-17
4-14 Emergency BIOS Boot (J14) - Pin-Out 4-17
4-15 VGA Connector (J15) - Pin-Out 4-18
4-16 Ethernet 10 Base-T RJ45 Connector (J16) - Pin-Out 4-18
4-17 Ethernet 10 Base-2 BNC Connector (J23) - Pin-Out 4-18
6-1 Fan Connector (J1) - Pin-Out 6-10
6-2 DMA Controller Channels 6-12
6-3 8259 Interrupt Controllers Lines 6-13
6-4 Emergency BIOS Boot (J14) - Pin-Out 6-18
6-5 Register 190H, 290H or 390H 6-20
6-6 Multi-Function Connector - Keyboard, Speaker,
Reset, LED - (J5) - Pin-Out 6-22
6-7 PS/2 Mouse Connector (J13) - Pin-Out 6-24
7-1a ISA Bus Connector (A, B) 7-2
7-1b ISA Bus Connector (C, D) 7-3
7-2a PCI Bus Connector (A1-A30, B1-B30) 7-4
7-2b PCI Bus Connector (A31-A62, B31-B62) 7-5
LIST OF TABLES (Continued)
9-1a Hard Disk Connector #1 (J3) - Pin-Out 9-3
List of Tables xiv
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9-1b Hard Disk Connector #2 (J8) - Pin-Out 9-4
9-2 Floppy Disk Connector (J4) - Pin-Out 9-8
10-1a Serial Port 1 (J6) RS232 - Pin-Out 10-3
10-1b IBM 9-Pin DSUB Standard - Pin-Out 10-3
10-2a Serial Port 2 (J7) RS232 - Pin-Out 10-4
10-2b IBM 9-Pin DSUB Standard - Pin-Out 10-4
10-3 Serial Port 2 (J7) RS485 - Pin-Out 10-5
10-4 Parallel Port Connector (J10) - Standard Mode 10-10
10-5 Parallel Port Connector (J10) - EPP Mode 10-11
10-6 Parallel Port Connector (J10) - ECP Mode 10-12
11-1 Common SCSI Target IDs 11-3
11-2 SCSI Connector (J2) - Pin-Out 11-4
12-1 Ethernet 10 Base-T RJ45 Connector (J16) - Pin-Out 12-2
12-2 Ethernet 10 Base-2 BNC Connector (J23) - Pin-Out 12-2
13-1 VGA Connector (J15) - Pin-Out 13-4
13-2 Flat Panel Connector (J9) - Pin-Out 13-5
13-3 Video Feature Connector (J11) - Pin-Out 13-7
LIST OF TABLES (Continued)
14-1 Watchdog Timer Register 14-4
A-1 Supply Current A-1
A-2a Reliability Prediction (Options 1-5) A-2
List of Tables xv
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A-2b Reliability Prediction (Options 6-10) A-3
A-2c Reliability Prediction (Options 11-15) A-4
A-2d Reliability Prediction (Options 16-20) A-5
A-2e Reliability Prediction (Options 21-25) A-6
A-2f Reliability Prediction (Options 26-30) A-7
B-1 Memory Map B-2
B-2 I/O Map B-3
E-1 Beep Error Codes E-8
List of Tables xvi
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INTRODUCTION
The high performance TEK933 (also called the PCI-933) PentiumTM PCI-ISA Single
Board Computer has the special characteristics of supporting Intel’s Pentium
microprocessor, as well as both the PCI bus and the ISA bus. It has the following
features:
• The TEK933 fully complies with the PCI INDUSTRIAL COMPUTER
MANUFACTURERS GROUP (PICMG), Revision 2.0 specification. As a result, the
TEK933 is fully IBM AT compatible, as well as complying with the PCI Local Bus
Specification, Revision 2.1. This board may be installed in the TEK950 PCI-ISA
Passive Backplane, which has three PCI slots, five ISA slots and one dedicated PCIISA CPU slot (for more information, see the TEK950 TECHNICAL REFERENCE
MANUAL).
• The TEK933 has an interchangeable microprocessor design, with the following
PentiumTM microprocessors available: 75, 100, 120, 133, 150 and 166 MHz.
• Each microprocessor has separate Code and Data Caches: 8KB Code, and 8KB
Write Back Data.
• The TEK933 standard configuration also has 256KB of direct-mapped, write-back /
write-through External Cache Memory (optional: none).
• System memory can be configured from 2MB to 128MB (256MB when available)
of Dynamic RAM (DRAM) with 32-bit or 36-bit modules installed on the board's
four vertical, 72-pin SIMM sockets.
• The board is ideal for industrial applications with features like:
- Watchdog timer;
- SMM (System Management Mode) support and full SMI (System Management
Interrupt) interface for power management;
- Power failure detector;
- Low battery detector;
- Shadow RAM BIOS support for fast execution;
- Flash EPROM boot;
- Real-Time Clock (RTC) with battery backup.
• The TEK933 has a multi-function connector which provides all the necessary
signals for connecting the keyboard, speaker, reset, and keylock interface devices.
Introduction 1
Page 15
• The local bus SVGA video controller is from Cirrus Logic and provides high
resolution Flat Panel and CRT displays. The board also comes with 1MB of video
memory (DRAM) and a Feature Connector for video overlay and color keying.
• A PS/2 mouse port is included.
• The board includes two enhanced onboard IDE interfaces, which support PIO
(Programmed Input/Output) mode-4 and mode-5 transfer rates.
• The TEK933 includes an enhanced super Floppy controller which supports two
Floppy disk drives of up to 2.88MB each, 16 bytes of FIFO buffering and a 48mA
drive buffer.
• The TEK933 board has one parallel printer port (the hardware supports ECP and
EPP modes).
• Two 16550 compatible serial ports with internal 16-byte FIFO buffers can be
defined as two of the following: COM1, COM2, COM3 or COM4. Serial Port 2 is
available as RS232 or RS485/RS422. Serial Port 1 is only available as RS232.
• The onboard Ethernet port, compliant with IEEE 802.3/ANSI 8802-3, can function
with either the 10 Base-T or 10 Base-2 interface.
• The Ethernet Controller supports the Plug and Play standard. It has a serial
EEPROM onboard for Plug and Play compatibility and configuration storage.
• An optional onboard SCSI controller supports up to seven SCSI peripherals and
Fast SCSI II.
Introduction 2
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The TEK933 TECHNICAL REFERENCE MANUAL is divided as follows:
Part One - QUICK INSTALLATION - includes essential information to get your
TEK933 up and running quickly:
• 1: INSTALLING SYSTEM
MEMORY: How to configure and install system memory.
• 2: JUMPER LOCATIONS
& CONFIGURATION: Convenient diagram and graphical tables give
you an easy reference for setting jumpers.
• 3: INSTALLING TEK933
IN PASSIVE BACKPLANE: Explains which passive backplanes are
compatible with the TEK933 board.
• 4: CONNECTOR LOCATIONS
& PIN-OUTS: Convenient diagram and pin-out tables give
you the basics for wiring in all devices and
mating connectors. If you require more detail,
refer to the appropriate section in Part Two HARDWARE REFERENCE.
• 5: SOFTWARE SETUPS: This section shows you how to access the
AMIBIOS Setup and the VIP-UP Setup. If you
require more detail, see Section 15 - AMIBIOS
SETUP and Section 16 - VIP-UP SETUP (both in
Part Three - SOFTWARE REFERENCE).
Introduction 3
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Part Two - HARDWARE REFERENCE - divides the TEK933 PentiumTM PCI-ISA
Single Board Computer according to functional units; it includes detailed information
on the board's hardware features and on installation and setup procedures:
• 6: SYSTEM: Covers various components of the system
board: Microprocessor, Fan Connector, PCI/ISA
System Controller, System Cache, System
Memory, EPROM BIOS devices, Battery,
Supervisor Utilities, integrated Real Time Clock AT Keyboard & PS/2 Mouse Controller, MultiFunction Connector and PS/2 Mouse Connector.
• 7: PCI-ISA BUS: Covers the PCI and ISA buses.
• 8: SYSTEM I/O: Covers the System I/O Controller.
• 9: IDE & FLOPPY: Covers IDE and Floppy connectors and
related hardware and software configuration.
• 10:SERIAL &
PARALLEL PORTS: Covers Serial and Parallel ports and related
hardware and software configuration.
• 11:SCSI: Covers installation, configuration and termination
of SCSI devices.
• 12:ETHERNET: Covers Ethernet connectors and related software
configuration.
• 13:VIDEO: Covers the Video Components: Video memory,
Video Controller, Flat Panel Connector, VGA
Connector and Feature Connector.
• 14:POWER MANAGEMENT: Covers the System Controller's power
management features, the Reset Circuit, the
Power Fail Detection Circuit and the Watchdog
Timer.
Introduction 4
Page 18
Part Three - SOFTWARE REFERENCE - describes in detail various software and
utilities that come with the TEK933 board.
• 15:AMIBIOS SETUP: AMIBIOS software setup program is used to
change operating system parameters.
• 16:VIP-UP SETUP: TEKNOR's own software setup program, which
complements AMIBIOS.
• 17:UPDATING BIOS
WITH UBIOS: This utility allows you to take BIOS files from a
disk and update the Flash EPROM BIOS with
them; it also allows you to copy the contents of
the Flash BIOS to files on disk.
• 18:VT100 MODE: This feature enables the Single Board Computer
to run without a local keyboard or screen:
Operation is controlled by a remote terminal, or a
computer emulating a terminal, via a serial link.
Introduction 5
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Following the above sections are APPENDICES A to E which comprise information
you can consult when you need it. These include:
• A: TEK933 SPECIFICATIONS;
• B: MEMORY & I/O MAPS;
• C: TEK933 BOARD DIAGRAMS;
• D: RECOMMENDED DEVICES
& MATING CONNECTORS;
• E: POST CODES & ERROR CODES.
These appendices are followed by a GETTING HELP section which includes Technical
Support information, the warranty and instructions on returning merchandise.
Introduction 6
Page 20
PART ONE
QUICK INSTALLATION
1 INSTALLING SYSTEM MEMORY
2 JUMPER LOCATIONS & CONFIGURATION
3 INSTALLING TEK933 IN PASSIVE BACKPLANE
4 CONNECTOR LOCATIONS & PIN-OUTS
5 SOFTWARE SETUPS
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1 INSTALLING SYSTEM MEMORY
Dynamic Random Access Memory (DRAM) is essential system memory. It can be
configured from 2MB to 128MB (256MB when available) using 32-bit or 36-bit
SIMMs (Single In-line Memory Modules). This is the only type of memory which can
be installed by the user.
1.01 STATIC ELECTRICITY PRECAUTIONS
Since static electricity can damage a board, the following precautions should be taken
whenever you handle the TEK933:
• Keep the board in its antistatic package, until you are ready to install it.
• Touch a grounded surface before removing the board from its package or wear a
grounding wrist strap; this will discharge any static electricity that may have built up
in your body.
• Handle the board by the edges.
• When handling the board, touch a grounded surface often or wear a grounding wrist
strap.
Installing System Memory 1-1
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1.02 LOCATION OF SIMM SOCKETS
The location of the four 72-pin vertical SIMM sockets appears on Diagram 1-1; these
sockets are labeled U23, U24, U25 and U26.
DIAGRAM 1-1: SIMM Sockets Location
Installing System Memory 1-2
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1.03 SIMM CONFIGURATION
At least 2MB of system memory must be installed on the TEK933 for proper operation.
Each of the 72-pin vertical SIMM sockets on the board can accept the following 32-bit
or 36-bit modules:
• 256K x 32-bit / 36-bit = 1MB module,
• 512K x 32-bit / 36-bit = 2MB module,
• 1M x 32-bit / 36-bit = 4MB module,
• 2M x 32-bit / 36-bit = 8MB module,
• 4M x 32-bit / 36-bit = 16MB module,
• 8M x 32-bit / 36-bit = 32MB module, and
• 16M x 32-bit / 36-bit = 64MB module (not available yet).
SIMM modules must be installed in either two or four sockets:
• In U23 and U24, or
• In U25 and U26, or
• In U23, U24, U25 and U26.
SIMMs installed in U23 and U24 must be of the same capacity; likewise, U25 and U26
must be of the same capacity (however, SIMMs in U23-U24 may be of a different
capacity than those in U25-U26).
Consult the tables on the following pages to see which SIMM configurations are
supported by the TEK933.
DRAM devices with fast page mode at 70ns maximum access time are recommended.
Please refer to Appendix D for a list of recommended devices.
Installing System Memory 1-3
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TABLE 1-1a: TEK933 SIMM Configurations: 2MB - 24MB
TOTAL
SYSTEM
MEMORY
2MB 1MB (256Kx36) 1MB (256Kx36) -- -2MB -- -- 1MB (256Kx36) 1MB (256Kx36)
4MB 1MB (256Kx36) 1MB (256Kx36) 1MB (256Kx36) 1MB (256Kx36)
4MB 2MB (512Kx36) 2MB (512Kx36) -- -4MB -- -- 2MB (512Kx36) 2MB (512Kx36)
6MB 2MB (512Kx36) 2MB (512Kx36) 1MB (256Kx36) 1MB (256Kx36)
6MB 1MB (256Kx36) 1MB (256Kx36) 2MB (512Kx36) 2MB (512Kx36)
8MB 2MB (512Kx36) 2MB (512Kx36) 2MB (512Kx36) 2MB (512Kx36)
8MB 4MB (1Mx36) 4MB (1Mx36) -- --
8MB -- -- 4MB (1Mx36) 4MB (1Mx36)
10MB 4MB (1Mx36) 4MB (1Mx36) 1MB (256Kx36) 1MB (256Kx36)
10MB 1MB (256Kx36) 1MB (256Kx36) 4MB (1Mx36) 4MB (1Mx36)
12MB 4MB (1Mx36) 4MB (1Mx36) 2MB (512Kx36) 2MB (512Kx36)
12MB 2MB (512Kx36) 2MB (512Kx36) 4MB (1Mx36) 4MB (1Mx36)
16MB 4MB (1Mx36) 4MB (1Mx36) 4MB (1Mx36) 4MB (1Mx36)
16MB 8MB (2Mx36) 8MB (2Mx36) -- -16MB -- -- 8MB (2Mx36) 8MB (2Mx36)
18MB 8MB (2Mx36) 8MB (2Mx36) 1MB (256Kx36) 1MB (256Kx36)
18MB 1MB (256Kx36) 1MB (256Kx36) 8MB (2Mx36) 8MB (2Mx36)
20MB 8MB (2Mx36) 8MB (2Mx36) 2MB (512Kx36) 2MB (512Kx36)
20MB 2MB (512Kx36) 2MB (512Kx36) 8MB (2Mx36) 8MB (2Mx36)
24MB 8MB (2Mx36) 8MB (2Mx36) 4MB (1Mx36) 4MB (1Mx36)
24MB 4MB (1Mx36) 4MB (1Mx36) 8MB (2Mx36) 8MB (2Mx36)
U23 U24 U25 U26
Note: 36-bit modules are shown, however 32-bit modules are supported.
Installing System Memory 1-4
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TABLE 1-1b: TEK933 SIMM Configurations: 32MB - 128MB
TOTAL
SYSTEM
MEMORY
32MB 8MB (2Mx36) 8MB (2Mx36) 8MB (2Mx36) 8MB (2Mx36)
32MB 16MB (4Mx36) 16MB (4Mx36) -- -32MB -- -- 16MB (4Mx36) 16MB (4Mx36)
34MB 16MB (4Mx36) 16MB (4Mx36) 1MB (256Kx36) 1MB (256Kx36)
34MB 1MB (256Kx36) 1MB (256Kx36) 16MB (4Mx36) 16MB (4Mx36)
36MB 16MB (4Mx36) 16MB (4Mx36) 2MB (512Kx36) 2MB (512Kx36)
36MB 2MB (512Kx36) 2MB (512Kx36) 16MB (4Mx36) 16MB (4Mx36)
40MB 16MB (4Mx36) 16MB (4Mx36) 4MB (1Mx36) 4MB (1Mx36)
40MB 4MB (1Mx36) 4MB (1Mx36) 16MB (4Mx36) 16MB (4Mx36)
48MB 16MB (4Mx36) 16MB (4Mx36) 8MB (2Mx36) 8MB (2Mx36)
48MB 8MB (2Mx36) 8MB (2Mx36) 16MB (4Mx36) 16MB (4Mx36)
64MB 16MB (4Mx36) 16MB (4Mx36) 16MB (4Mx36) 16MB (4Mx36)
64MB 32MB (8Mx36) 32MB (8Mx36) -- -64MB -- -- 32MB (8Mx36) 32MB (8Mx36)
66MB 32MB (8Mx36) 32MB (8Mx36) 1MB (256Kx36) 1MB (256Kx36)
66MB 1MB (256Kx36) 1MB (256Kx36) 32MB (8Mx36) 32MB (8Mx36)
68MB 32MB (8Mx36) 32MB (8Mx36) 2MB (512Kx36) 2MB (512Kx36)
68MB 2MB (512Kx36) 2MB (512Kx36) 32MB (8Mx36) 32MB (8Mx36)
72MB 32MB (8Mx36) 32MB (8Mx36) 4MB (1Mx36) 4MB (1Mx36)
72MB 4MB (1Mx36) 4MB (1Mx36) 32MB (8Mx36) 32MB (8Mx36)
80MB 32MB (8Mx36) 32MB (8Mx36) 8MB (2Mx36) 8MB (2Mx36)
80MB 8MB (2Mx36) 8MB (2Mx36) 32MB (8Mx36) 32MB (8Mx36)
96MB 32MB (8Mx36) 32MB (8Mx36) 16MB (4Mx36) 16MB (4Mx36)
96MB 16MB (4Mx36) 16MB (4Mx36) 32MB (8Mx36) 32MB (8Mx36)
128MB 32MB (8Mx36) 32MB (8Mx36) 32MB (8Mx36) 32MB (8Mx36)
U23 U24 U25 U26
Note: 36-bit modules are shown, however 32-bit modules are supported.
Installing System Memory 1-5
Page 26
1.04 SIMM INSTALLATION
When you are ready to install the SIMMs in the sockets, follow the steps outlined
below.
• With the board flat on the table, turn it so that the sockets are at the end of the board
farthest from you.
• Hold the module with the notch on the bottom right facing you, and insert the
connector into the socket at a 70° angle from the board.
• Snap the module to a vertical position in the socket. The module is fully inserted
when the retaining pegs snap into the holes at each end of the module.
Installing System Memory 1-6
Page 27
2 JUMPER LOCATIONS & CONFIGURATION
2.01 JUMPER LOCATIONS
Diagram 2-1 and the tables on the following pages show the TEK933 jumpers and their
initial setting. These jumpers are labeled from W1 to W9, W13 to W27, and J14. The
jumpers appear as rectangular boxes containing small numbers which represent the pin
numbers.
Jumper Locations & Configuration 2-1
Page 28
DIAGRAM 2-1: Jumper Locations With Default Settings
Note that W2, W3, W19, W20 and W21 are CPU dependent: See Jumper Settings Tables.
Jumper Locations & Configuration 2-3
Page 29
2.02 JUMPER SETTINGS
Table 2-1a to 2-1d on the following pages show all the possible jumper settings for W1
to W9, W13 to W27, and J14.
Jumper Locations & Configuration 2-5
Page 30
TABLE 2-1a: Jumper Settings: W1-W6, W14-W17
TABLE 2-1b: Jumper Settings: W7-W9, W23
Jumper Locations & Configuration 2-6
Page 31
Jumper Locations & Configuration 2-7
Page 32
TABLE 2-1c: Jumper Settings: W13, W18-W22
Jumper Locations & Configuration 2-8
Page 33
TABLE 2-1d: Jumper Settings: W24-W27, J14
Jumper Locations & Configuration 2-9
Page 34
3 INSTALLING TEK933 IN PASSIVE BACKPLANE
The TEK933 will work on any PCI-ISA passive backplane, provided it complies with
the PCI INDUSTRIAL COMPUTER MANUFACTURERS GROUP, Revision 2.0
specification. Therefore, the board may be installed on the TEK950 PCI-ISA Passive
Backplane, which has three PCI slots, five ISA slots, and a PCI-ISA connector where
you can insert the TEK933 (for more information, see the TEK950 TECHNICAL
REFERENCE MANUAL).
Since the TEK933 is also fully IBM AT compatible, it can also be installed on any
standard ISA passive backplane, if PCI expansion slots are not needed.
Note: The TEK933 chipset does not support address stepping (described in the PCI
Local Bus Specification). To ensure proper detection of PCI adapter cards,
resistors of 33Ω or less should be used on the backplane’s ID SELECT signal
address lines (between the CPU slot and each PCI slot). All TEKNOR PCI
backplanes include this specific feature. For more information, contact
TEKNOR’s Technical Support department.
Installing TEK933 in Passive Backplane 3-1
Page 35
4 CONNECTOR LOCATIONS & PIN-OUTS
4.01 LOCATION OF CONNECTORS ON THE BOARD
The connectors are labeled J1 to J16 and J23. They appear on the diagram on the
following page.
Connector Locations & Pin-Out 4-1
Page 36
DIAGRAM 4-1: Connector Locations
Connector Locations & Pin-Out 4-3
Page 37
4.02 CONNECTOR PIN-OUTS
Consult the tables on the following pages for the J1 to J16 and J23 connector pin-outs.
This information will help you wire all devices and mating connectors to the TEK933
board. For additional information, consult the appropriate section:
Connector Section which deals with it
J1 - Fan 6 SYSTEM
J2 - SCSI 11 SCSI
J3 - Hard Disk Connector #1 9 IDE & FLOPPY
J4 - Floppy Disk Connector 9 IDE & FLOPPY
J5 - Multi-Function (Keyboard,
Speaker, Reset, LED)
J6 - Serial Port 1 10 SERIAL & PARALLEL PORTS
J7 - Serial Port 2 10 SERIAL & PARALLEL PORTS
J8 - Hard Disk Connector #2 9 IDE & FLOPPY
J9 - Flat Panel 13 VIDEO
J10 - Parallel Port 10 SERIAL & PARALLEL PORTS
J11 - Feature Connector 13 VIDEO
J12 - Reserved for Optional Analog
Encoder Connector
J13 - PS/2 Mouse 6 SYSTEM
J14 - Emergency BIOS Boot
Selection
J15 - VGA 13 VIDEO
J16 - Ethernet (10 BASE-T) 12 ETHERNET
J23 - Ethernet (10 BASE-2) 12 ETHERNET
6 SYSTEM
6 SYSTEM
Connector Locations & Pin-Out 4-5
Page 38
TABLE 4-1: Fan Connector (J1) - Pin-Out
Pin Number Signal
1 +12V
2 GND
TABLE 4-2: SCSI Interface Connector (J2) - Pin-Out
Pin Number Signal Pin Number Signal
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Not Used
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
* Active low signal
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
SCSI D0
SCSI D1
SCSI D2
SCSI D3
SCSI D4
SCSI D5
SCSI D6
SCSI D7
SCSI DP*
GND
GND
GND
Term Power
GND
GND
ATN*
GND
BSY*
ACK*
RESET*
MSG*
SEL*
C/D*
REQ*
I/O*
Connector Locations & Pin-Out 4-6
Page 39
TABLE 4-3: Hard Disk Connector #1 (J3) - Pin-Out
Pin
Number
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal
Flow
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
O
O
O
I
I
I
O
* Active low signal
Signal Pin
RESET*
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
GND
REQ A
IOW*
IOR*
IOCHRDY
DACK A*
IRQ14
SA1
SA0
CS0 A*
ACTIVE*
Number
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Signal
Flow
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
O
I
I
-
Signal
GND
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
Not Used
GND
GND
GND
Not Used
GND
IOCS16*
Not Used
SA2
CS1 A*
GND
Connector Locations & Pin-Out 4-7
Page 40
TABLE 4-4: Floppy Disk Connector (J4) - Pin-Out
Pin
Number
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
* Active low signal
1
By default, these pins are not connected, however, by installing the W24 and W25
Signal
Flow
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Signal Pin
GND
GND
GND
GND
GND
GND
GND
GND
1
N. C.
GND
GND
GND
GND
1
N. C.
1
N. C.
GND
1
N. C.
Number
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Signal
Flow
O
-
I
O
O
O
O
O
O
O
O
I
I
I
O
I
Signal
RPM/LC
Not Used
Not Used
INDEX*
MOTOR ON 0,1*
DRIVE SELECT B
DRIVE SELECT A
MOTOR ON 2*
DIR CONTROL
STEP*
WRITE DATA*
WRITE ENABLE*
TRACK0*
WRITE PROTECT*
READ DATA*
HEAD SELECT
DSKCHG
jumpers, these configurations are possible (see also page 9-10 in the manual):
1) 17 - GND Or:2) 17 I EDOUT (2.88MB)
27 - GND 27 I HDOUT (2.88MB)
29 I EDOUT (2.88MB) 29 - GND
33 I HDOUT (2.88MB) 33 - GND
Connector Locations & Pin-Out 4-8
Page 41
TABLE 4-5: Multi-Function Connector - Keyboard, Speaker,
Reset, LED - (J5) - Pin-Out
Pin
Number
1 I/O KBDCLK 2 - GND
3 I/O KBDDATA 4 - GND
5 - VCC (Protected:
7 O SPEAKER 8 - VCC (Protected:
9 I KBDINH 10 - GND
11 I DOWNLD* 12 - GND
13 I PBRES* 14 - GND
15 O ACTIVE* 16 - VCC (Protected:
Signal
Flow
Signal Pin
Number
6 - VCC (Protected:
Resettable Fuse)
Signal
Flow
Signal
Resettable Fuse)
Resettable Fuse)
Resettable Fuse)
* Active low signal
TABLE 4-6: Serial Port 1 (J6) - RS232 - Pin-Out
Pin
Number
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
1 I DCD 2 I DSR
3 I RX 4 O RTS
5 O TX 6 I CTS
7 O DTR 8 I RI
9 - GND 10 - Not Used
Connector Locations & Pin-Out 4-9
Page 42
TABLE 4-7a: Serial Port 2 (J7) - RS232 - Pin-Out
Pin
Number
1 I DCD 2 I DSR
3 I RX 4 O RTS
5 O TX 6 I CTS
7 O DTR 8 I RI
9 - GND 10 - Not Used
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
TABLE 4-7b: Serial Port 2 (J7) - RS485/RS422 - Pin-Out
Pin
Number
1 I DCD 2 I DSR
3 I/O RXD(-) 4 I/O RXD(+)
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
5 O TXD(-) 6 I TXD(+)
7 O DTR 8 I RI
9 - GND 10 - Not Used
Connector Locations & Pin-Out 4-10
Page 43
TABLE 4-8: Hard Disk Connector #2 (J8) - Pin-Out
Pin
Number
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal
Flow
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
O
O
O
I
I
I
O
* Active low signal
Signal Pin
RESET*
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
GND
REQ B
IOW*
IOR*
IOCHRDY
DACK B*
IRQ15
SA1
SA0
CS0 B*
ACTIVE*
Number
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Signal
Flow
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
O
I
O
-
Signal
GND
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
Not Used
GND
GND
GND
Not Used
GND
IOCS16*
Not Used
SA2
CS1 B*
GND
Connector Locations & Pin-Out 4-11
Page 44
TABLE 4-9: Flat Panel Connector (J9) - Pin-Out
Pin Number Signal Pin Number Signal
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
FP4
FP6
FP12
FP14
FP19
FP11
FP23
FP21
GND
GND
GND
FP3 (MOD)
GND
GND
FP8
GP1
FPBL
LLCLK
FPVEE
FP2
STANDBY*
FP1
Not Used
VCC (+5V)
+12V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
FP5
FP7
FP13
FP15
FP18
FP10
FP22
FP20
FPVDCLK
FP9
LFS
FP0
FPDE
GND
GP0
GND
GND
GND
FPVCC
GP2
FP16
FP17
Not Used
VCC (+5V)
+12V
* Active low signal
Connector Locations & Pin-Out 4-12
Page 45
TABLE 4-10a: Parallel Port Connector (J10) - Standard Mode - Pin-Out
Pin
Number
1 O STROBE* 2 O AUTOFD*
3 I/O D0 4 I ERROR*
5 I/O D1 6 O INIT*
7 I/O D2 8 O SELECTIN*
9 I/O D3 10 - GND
11 I/O D4 12 - GND
13 I/O D5 14 - GND
15 I/O D6 16 - GND
17 I/O D7 18 - GND
19 I ACK* 20 - GND
21 I BUSY 22 - GND
23 I PE 24 - GND
25 I SELECT 26 - GND
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
* Active low signal
Connector Locations & Pin-Out 4-13
Page 46
TABLE 4-10b: Parallel Port Connector (J10) - EPP Mode - Pin-Out
Pin
Number
1 O WRITE* 2 O DATASTB*
3 I/O D0 4 - Not Used
5 I/O D1 6 - Not Used
7 I/O D2 8 O ADDRSTRB*
9 I/O D3 10 - GND
11 I/O D4 12 - GND
13 I/O D5 14 - GND
15 I/O D6 16 - GND
17 I/O D7 18 - GND
19 I INTR 20 - GND
21 I WAIT* 22 - GND
23 - Not Used 24 - GND
25 - Not Used 26 - GND
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
* Active low signal
Connector Locations & Pin-Out 4-14
Page 47
TABLE 4-10c: Parallel Port Connector (J10) - ECP Mode - Pin-Out
Pin
Number
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
1 O STROBE* 2 O AUTOFD*,
HOSTACK
3 I/O D0 4 I FAULT*1,
PERIPHRQST*
5 I/O D1 6 O INIT*1,
REVERSERQST*
7 I/O D2 8 O SELECTIN*
9 I/O D3 10 - GND
11 I/O D4 12 - GND
13 I/O D5 14 - GND
15 I/O D6 16 - GND
17 I/O D7 18 - GND
19 I ACK* 20 - GND
21 I BUSY,
PERIPHACK
23 I PERROR,
ACKREVERSE
2
22 - GND
24 - GND
2
25 I SELECT 26 - GND
2
2
2
1,2
* Active low signal
1
Compatible Mode
2
High Speed Mode
Note: For more information on the ECP protocol, please refer to the Extended
Capabilities Port Protocol and ISA Interface Standard (available from Microsoft
Corporation) or contact our Technical Support department.
Connector Locations & Pin-Out 4-15
Page 48
TABLE 4-11: Video Feature Connector (J11) - Pin-Out
I/O Pin Signal Name I/O Pin Signal Name
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
FCP0
FCP1
FCP2
FCP3
FCP4
FCP5
FCP6
FCP7
FCDCLK
FCBLANK*
FCHSYNC
FCVSYNC
GND
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
Z13
GND
GND
GND
FCEVIDEO*
FCESYNC*
Not Used
Not Used
GND
GND
GND
GND
FCVCLK
OVRW*
* Active low signal
TABLE 4-12: Optional Analog Encoder Connector (J12) - Pin-Out
Pin Number Signal Pin Number Signal
1 RED 2 GND
3 GREEN 4 GND
5 BLUE 6 GND
7 CSYNC 8 GND
9 TVON 10 NTSC_PAL
11 GND 12 OSC14M
13 VCC (+5V) 14 Not Used
15 VCC (+5V) 16 Not Used
Connector Locations & Pin-Out 4-16
Page 49
TABLE 4-13: PS/2 Mouse Connector (J13) - Pin-Out
Pin Number Signal
1 MCLK
2 GND
3 MDATA
4 VCC (Protected:
Resettable Fuse)
TABLE 4-14: Emergency BIOS Boot (J14) - Pin- Out
Pin Number Signal
1 EMER*
2 GND
* Active low signal
Connector Locations & Pin-Out 4-17
Page 50
TABLE 4-15: VGA Connector (J15) - Pin-Out
Pin Number Signal Pin Number Signal Pin Number Signal
1 RED 6 ANALOG
GND
2 GREEN 7 ANALOG
GND
3 BLUE 8 ANALOG
GND
4 NotUsed 9 Not Used 14 VSYNC
5 GND 10 GND 15 Not Used
11 Not Used
12 Not Used
13 HSYNC
TABLE 4-16: Ethernet 10 Base-T RJ45 Connector (J16) - Pin-Out
Pin
Number
1 O TD+ 2 O TD3 I/O RD+ 4 - Not Used
5 - Not Used 6 I RD7 - Not Used 8 - Not Used
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
TABLE 4-17: Ethernet 10 Base-2 BNC Connector (J23) - Pin-Out
Pin Number Signal Name
Center Conductor Signal
Shield GND
Note: The Ethernet 10 Base-2 Connector (J23) is a standard BNC connector.
Connector Locations & Pin-Out 4-18
Page 51
5 SOFTWARE SETUPS
There are two software setup programs on the TEK933:
• VIP-UP Setup: This is TEKNOR's own Setup program for enabling / disabling /
relocating various hardware features on the Single Board Computer.
• AMIBIOS Setup: This is a setup utility in ROM which is used to set configuration
data in CMOS RAM.
5.01 ACCESSING AMIBIOS SETUP PROGRAM
The AMIBIOS Setup program can be executed during boot-up. To run the AMIBIOS
Setup program incorporated into the ROM BIOS:
• Turn on or reboot the system.
• Hit the DELETE key before or when the message - "Hit <DEL> if you want to run
SETUP" appears near the top of the screen (DELETE will work, even if the message
display is disabled in AMIBIOS SETUP).
The screens and their options are explained in full in Section 15 - AMIBIOS SETUP.
Software Setups 5-1
Page 52
5.02 ACCESSING VIP-UP PROGRAM
This program can be executed during boot-up.
During boot-up, hit the CTRL and V keys simultaneously, before or when you see the
message "Press CTRL-V to enter TEKNOR VIP-UP" at the top of the screen (CTRL-V
will work, even if the message display is disabled in VIP-UP).
The screens and their options are explained in full in Section 16 - VIP-UP SETUP.
Software Setups 5-2
Page 53
PART TWO
HARDWARE REFERENCE
6 SYSTEM
7 PCI-ISA BUS
8 SYSTEM I/O CONTROLLER
9 IDE & FLOPPY
10 SERIAL & PARALLEL PORTS
11 SCSI
12 ETHERNET
13 VIDEO
14 POWER MANAGEMENT
Page 54
6 SYSTEM
This section deals with various components of the system board.
6.01 LOCATION OF SYSTEM COMPONENTS
Diagram 6-1 and 6-2 show the location of the system components described in sections
6.02 to 6.12.
System 6-1
Page 55
System components are numbered in Diagram 6-1 and 6-2. The following list shows
which components these numbers correspond to, as well as the sub-section in which
they are explained:
# COMPONENT SECTION
1 System Cache 6.05 - CACHE
2 System Memory (DRAM) 6.06 - SYSTEM MEMORY (DRAM)
3 Fan Connector 6.03 - FAN CONNECTOR
4 Microprocessor 6.02 - MICROPROCESSOR
5 Real Time Clock - AT Keyboard 6.10 - REAL TIME CLOCK - AT
& PS/2 Mouse Controller KEYBOARD & PS/2 MOUSE
CONTROLLER
6 Field Programmable Gate Array (FPGA)6.09 - SUPERVISOR UTILITIES
7 Multi-Function Connector 6.11 - MULTI-FUNCTION
CONNECTOR
(Keyboard, Speaker, Reset, LED) (KEYBOARD, SPEAKER, RESET,
LED)
8 PS/2 Mouse Connector 6.12 - PS/2 MOUSE CONNECTOR
9 Emergency BIOS Boot Selection 6.07 - BIOS (FLASH EPROM &
EPROM)
10 VBAT Internal Battery 6.08 - BATTERY
11 Flash EPROM BIOS 6.07 - BIOS (FLASH EPROM &
EPROM)
12 EPROM BIOS 6.07 - BIOS (FLASH EPROM &
EPROM)
13 System Controller 6.04 - PCI/ISA SYSTEM
CONTROLLER
14 PCI Bus Controller 6.04 - PCI/ISA SYSTEM CONTROLLER
15 Data Controllers 6.04 - PCI/ISA SYSTEM CONTROLLER
System 6-2
Page 56
DIAGRAM 6-1: System Components Location (Bottom of Board)
System 6-3
Page 57
DIAGRAM 6-2: System Components Location (Top of Board)
System 6-5
Page 58
As seen on page 6-2, each component shown in the diagram is explained in a section.
These sections are grouped and ordered as follows:
• CPU Related: 6.02 - MICROPROCESSOR
6.03 - FAN CONNECTOR
• Chipset Related: 6.04 - PCI/ISA SYSTEM CONTROLLER
6.05 - CACHE
6.06 - SYSTEM MEMORY (DRAM)
• BIOS Related 6.07 - BIOS (FLASH EPROM & EPROM)
• Battery Related 6.08 - BATTERY
• Field Programmable Gate Array 6.09 - SUPERVISOR UTILITIES
• Real Time Clock, Keyboard and
Mouse Related 6.10 - REAL TIME CLOCK -
AT KEYBOARD &
PS/2 MOUSE CONTROLLER
6.11 - MULTI-FUNCTION CONNECTOR
(KEYBOARD, SPEAKER, RESET, LED)
6.12 - PS/2 MOUSE CONNECTOR
System 6-7
Page 59
6.02 MICROPROCESSOR
The TEK933 board has an interchangeable microprocessor design; the following
supported microprocessors are available (maximum internal CPU clock speed
indicated):
• Pentium running at 75, 100, 120, 133, 150 and 166 MHz.
The following jumpers are related to the CPU:
• W2 & W3: Selects the desired multiplier for Pentium internal CPU clock speed:
- W2: pins 1 and 2 shorted for 1.5X,
W3: pins 1 and 2 shorted
- W2: pins 1 and 2 shorted for 2X,
W3: pins 2 and 3 shorted
- W2: pins 2 and 3 shorted for 2.5X.
W3: pins 2 and 3 shorted
• W19, W20 & W21: Selects the desired external CPU clock (Bus) speed:
- W19: pins 2 and 3 shorted for 50MHz,
W20: pins 1 and 2 shorted
W21: pins 2 and 3 shorted
- W19: pins 1 and 2 shorted for 60MHz,
W20: pins 1 and 2 shorted
W21: pins 1 and 2 shorted
- W19: pins 1 and 2 shorted for 66MHz.
W20: pins 2 and 3 shorted
W21: pins 2 and 3 shorted
External speed is set with jumpers W19, W20 and W21 (50, 60, 66 MHz) and internal
speed is set with the W2 and W3 jumpers (1.5, 2 or 2.5X the external speed, however
this cannot exceed the maximum internal speed for that microprocessor).
Jumper locations and settings appear in Section 2 of this manual.
System 6-8
Page 60
The Pentium processor family contains all of the features of the Intel486 CPU family,
with the addition of the following features:
• Superscalar architecture,
• Dynamic Branch Prediction,
• Pipelined floating-point unit,
• Improved instruction execution time,
• Separate 8KB Code and 8KB Data Caches,
• Write-back MESI protocol in the Data Cache,
• 64-bit data bus,
• Bus cycle pipelining,
• Address parity,
• Internal parity checking,
• Functional redundancy checking,
• Execution tracing,
• Performance monitoring,
• IEEE 1149.1 boundary scan,
• System Management Mode,
• Virtual mode extensions,
• Dual processing support,
• SL power management features,
• Upgradable with a future Pentium overdrive processor,
• Fractional bus operation,
• On-chip local APIC device.
System 6-9
Page 61
6.03 FAN CONNECTOR
The # 3 component on Diagram 6-2 is for connecting a CPU fan. Its pin-out is as
follows:
TABLE 6-1: Fan Connector (J1) - Pin-Out
Pin Number Signal
1 +12V
2 GND
System 6-10
Page 62
6.04 PCI/ISA SYSTEM CONTROLLER
The TEK933 board uses VIA’s VT82C570M Green PC Pentium/P54C PCI/ISA System
with plug and play and enhanced IDE controller. This chip set consists of the following
components:
• The VT82C575M System Controller, located at U17 (#13) on Diagram 6-2,
• The VT82C576M PCI Bus Controller located at U56 (#14) on Diagram 6-2,
• The two VT82C577M Data Controllers located at U41 and U60 (#15) on Diagram
6-2, and
• The VT82C416MV integrated real time clock and keyboard controller with PS/2
mouse support, located at U21 (#5) on Diagram 6-2.
As an integrated unit, the PCI/ISA System Controller offers the following features:
DRAM Controller
• CPU/Cache to DRAM write buffer,
• SIMM module support: 72-pin configuration,
• Integrated DRAM controller:
- Supports CPU and PCI master accesses to System Memory,
- Supports 2MB to 128MB (256MB when available) of Cacheable System
Memory (DRAM).
Cache Controller
• Direct mapped write back or write through secondary Cache,
• Cache hit cycle of 3-2-2-2 on reads and 4-2-2-2 on writes using standard
asynchronous SRAMs at 60 and 66 MHz clock speed,
- Flexible Cache size up to 1MB,
• Integrated 10-bit tag comparator,
• Concurrent DRAM write-back.
ISA Bus Interface
System 6-11
Page 63
• Synchronous ISA bus clock,
• Programmable command delay and I/O recovery time,
• One level of post write buffer,
• Flash EPROM and combined BIOS support,
• ISA Bus (P996 standard compliant),
• High-drive buffers to support up to 20 slots,
• Integrates the functionality of two 8237 DMA Controllers (see Table 6-2), two
8259 Interrupt Controllers (see Table 6-3) and one 8254 Counter/Timer,
• A steering logic feature insures that the slower ISA bus traffic does not block the
PCI bus traffic.
TABLE 6-2: 8237 DMA Controllers
DMA 0 Available
DMA 1 PnP available (ECP)
DMA 2 Floppy controller
DMA 3 PnP available (ECP or Ethernet)
DMA 4 Cascade controller # 1
DMA 5 PnP available (Ethernet)
DMA 6 PnP available (Ethernet)
DMA 7 PnP available (Ethernet)
According to Plug and Play standards, the System BIOS automatically allocates DMA
Channel 1 or 3 for the parallel port's ECP mode. Channel 2 is reserved for the Floppy
controller and Channel 4 is used to cascade Channels 0 through 7 to the
microprocessor. The DMA Channel for the Plug and Play Ethernet device is
automatically allocated by the System BIOS among those available (Channel 3, 5, 6 or
7).
System 6-12
Page 64
TABLE 6-3: 8259 Interrupt Controllers
Controller # 1 Controller # 2
IRQ 0 Timer 0 IRQ 8 Real-time clock
IRQ 1 Keyboard IRQ 9 Available
IRQ 2 Cascade controller # 2 IRQ 10 Available
IRQ 3 COM 2 * IRQ 11 Available
IRQ 4 COM 1 * IRQ 12 PS/2 Mouse Interface
IRQ 5 LPT2 * or available
IRQ 6 Floppy controller * IRQ 14 Primary IDE * or available
IRQ 7 LPT1 * or available
1
1
IRQ 13 Coprocessor Error
IRQ 15 Secondary IDE * or available
1
1
1
1
1
* All functions marked with an asterisk (*) can be disabled or reconfigured.
1
Available lines service on board and external PCI/PnP devices (when set to PCI/PnP
in AMIBIOS PCI/PnP Setup screen) or an external non-PnP device (when set to
ISA/EISA in AMIBIOS PCI/PnP Setup screen).
Two 8259 interrupt controllers handle the interrupts on the TEK933 as follow:
• Six interrupt lines are directly linked to the keyboard controller, timer, the real-time
clock, both serial ports and the mouse.
• The System BIOS automatically allocates IRQ5 or IRQ7 for the parallel port’s IRQ
line, depending on the settings in the AMIBIOS Peripheral Setup’s OnBoard
Parallel Port option: IRQ5 when the option is set to 278h or 3BCh; IRQ7 when set
to 378h; IRQ5 or IRQ7 when set to Auto; when the option is set to Disabled, IRQ5
and IRQ7 are available for onboard and external PCI/PnP devices, or for external
non-PnP devices (see note 1 above).
• The Primary and Secondary IDE Controller are configured to IRQ 14 and IRQ 15
respectively or to none by software:
IRQ 14: When the AMIBIOS Peripheral Setup screen’s OnBoard IDE option is set
to Primary or to Both, this line is linked to Primary IDE,
IRQ 15: When the AMIBIOS Peripheral Setup screen’s OnBoard IDE option is set
to Secondary or to Both, this line is linked to Secondary IDE,
None: When the AMIBIOS Peripheral Setup screen’s OnBoard IDE option is set
to Disabled, IRQ 14 and IRQ 15 are available for on board/external
PCI/PnP devices or external non-PnP devices (see note 1 above).
System 6-13
Page 65
• The on board PCI SCSI Controller is automatically allocated an IRQ line by the
System BIOS among the available PCI/PnP IRQ lines.
• The on board Plug and Play Ethernet is automatically allocated an IRQ line by the
System BIOS among the available PCI/PnP IRQ lines.
PCI Bus Controller
• 32-bit PCI interface,
• Concurrent PCI Master/CPU/IDE operations,
• High performance CPU/PCI/Memory interfaces via posted write and read prefetch
buffers,
• PCI Masters to DRAM posted write buffers,
• Prefetch buffers from DRAM for access by PCI Masters,
• CPU-to-PCI posted write buffers accelerate write performance,
• PCI 2.1 compliant,
• Zero wait state PCI Master and Slave burst transfer rates,
• High bus throughput via multiple accelerated schemes,
• Supports PCI Configuration Access Mechanisms #1 and #2,
• Automatic detection of data steaming burst cycles from CPU to the PCI bus.
System 6-14
Page 66
PCI IDE Controller
• Dual IDE channels control four peripheral devices, including support for non-disk
IDE devices such as CD-ROM,
• Sixteen-level 32-bit prefetch and write buffers for each IDE channel,
• Separate IDE data bus and control signals from the PCI and ISA bus, providing
load reduction and enhanced performance,
• Supports PIO mode-4 and mode-5 transfer rates,
• Complete software driver support,
• A steering logic feature ensures that the slower IDE traffic does not block the PCI
bus traffic.
Plug and Play Controller
• Microsoft Windows 95 and Plug and Play BIOS compliant.
Power Management Unit
• Normal, Sleep and Suspend modes,
• Monitoring through idle, peripheral and general purpose timers,
• Preset I/O range,
• Multiple internal and external SMI sources.
System 6-15
Page 67
6.05 CACHE
There are two separate Caches in the Host subsystem: Internal Cache and External
Cache. The Cache inside the Pentium processor (Internal Cache) is referred to as the
first level Cache (also primary Cache). The External Cache (called System Cache in this
manual) comprises the System Controller’s Cache control circuitry and associated
external memory array; it is referred to as the second level Cache (also secondary
Cache). The second level Cache is unified, which means that both CPU data and
instructions are stored in the Cache.
6.05.1 SYSTEM CACHE
The System Controller integrates a high performance write-back / write-through second
level Cache controller, tag RAM and a full first and second level Cache coherency
mechanism. The System Controller supports a direct-mapped secondary Cache.
System Cache is located at the back of the card at U34, U35, U44, U45, U54, U55, U67
and U68 (#1) on Diagram 6-1; it accepts a total of 256KB standard asynchronous
SRAM.
System Cache copies the most recently accessed data and places it in an area of high
speed memory called SRAM (Static RAM). Cache SRAM is positioned between
System Memory (DRAM) and the CPU. Data is transferred from System Memory to
Cache and then from Cache to the CPU.
Since most program executions are sequential and repetitive, the likelihood is great that
the CPU will find data already stored in either Cache. When the CPU retrieves data
from Cache, a Cache hit occurs. On the other hand, when the CPU must access data
from System Memory, a Cache miss occurs.
System Cache is enabled and configured in the AMIBIOS Setup program (see Section
15).
System 6-16
Page 68
6.06 SYSTEM MEMORY (DRAM)
A local DRAM controller is integrated in the System Controller. Dynamic Random
Access Memory (DRAM) is essential system memory. The memory array is 64 bits
wide and ranges in size from 2MB to 128MB (256MB when available). The array is
implemented using single-sided or double-sided SIMMs (Single In-line Memory
Modules). See section 1 for instructions on configuring and installing SIMMs.
The location of the four 72-pin vertical SIMM sockets appears on Diagram 6-2 at U23,
U24, U25 and U26 (# 2).
The DRAM Controller supports CPU and PCI master accesses to System Memory. The
System Controller’s DRAM interface supplies the control signals and address lines; the
Data Controllers supply the data path from or to the CPU; and the PCI Controller’s
DRAM interface provides a 32-bit data link to the System Memory to allow for
concurrent CPU/Cache and PCI Master/DRAM operations.
System 6-17
Page 69
6.07 BIOS (FLASH EPROM & EPROM)
The Flash EPROM BIOS and the EPROM BIOS are factory installed. The Flash
EPROM BIOS appears on Diagram 6-2 at U50 (#11) and the EPROM BIOS at U49
(#12).
By default the TEK933 boots from the Flash EPROM BIOS. This is set by the J14
Emergency BIOS boot selection jumper (# 9 on Diagram 6-2), as follows:
• J14 : Selects the BIOS to boot from:
- Shorted: Emergency boot (from EPROM BIOS),
- Or open: Normal boot (from Flash EPROM BIOS): This is the initial setting.
The pin-out for J14 appears below:
TABLE 6-4: Emergency BIOS Boot (J14) - Pin-Out
Pin Number Signal
1 EMER*
2 GND
* Active low signal
System 6-18
Page 70
6.08 BATTERY
The TEK933 comes with a 360 mAh TL5186 TADIRAN battery, which is located at
B1 (#10 on Diagram 6-2). It powers the Real Time Clock and the CMOS Setup,
whenever the board is powered down.
The TL5186 TADIRAN battery has a shelf life of approximately 10 years (under "noload" conditions). The actual life of the battery depends on environmental (temperature)
conditions. The TADIRAN TL5186 has an operating range of -55o to 75oC and
discharge characteristics vary with temperature.
The voltage supplied by the battery is 3.6 volts. This can be verified with a standard
voltmeter at the battery socket's two extreme pins (if you use the pin on the soldered
side, you do not have to remove the battery).
Jumper W27 enables the Internal Battery's power. Removing the W27 jumper has the
same effect as putting the battery in storage; TEKNOR always ships its board with
battery jumper removed in order to increase the life of the battery. Please refer to
Section 2 for jumper location and setting.
The TADIRAN TL5186 is UL recognized. Its UL component recognition is
MH12193.
The TEK933 board has a special feature that allows the CMOS RAM Setup to be saved
in Flash EPROM memory. This feature eliminates battery dependency by saving and
recovering the CMOS RAM Setup from Flash (only the time and date could be lost).
In order to save your current CMOS RAM Setup in Flash, you must update the
VIP-UP Setup (with F10), while the "Use Flash To Store CMOS RAM SETUP"
(first screen) is set to "Yes". See section 16 for more information.
System 6-19
Page 71
6.09 SUPERVISOR UTILITIES
Component #6 on Diagram 6-2 is defined on page 6-2 as Field Programmable Gate
Array (FPGA); this memory device contains registers, one of which is described below.
TEKNOR computers utilize address space 190H, 290H or 390H (depending on the
setting of W9 jumper for I/O base address) to enable special features (see Table 6-5
below).
TABLE 6-5: Register 190H, 290H or 390H
Bit # Bit Value
0 0 Enable Watchdog
1 1 Watchdog activate
2 0 Flash VPP enable Same
3 0
4 0 Reserved, ENWF W8 (7-8) Status
5 0 Reserved, ENWB W8 (5-6) Status
6 1 Reserved, B64/16 W8 (3-4) Status
7 0
1
Contact TEKNOR Technical Support if a Video Standby software is required.
(Default)
Function:
WRITE READ
1=enable, R/W bit
1-0-1 to toggle, R/W bit
Enable direction control RS-485
1=enable RS-485 only, write only
Reserved (Video Standby)
1
Same
Same
Power Detection Output or
Battery Low output
W8 (1-2) Status
Not all bits are R/W. Therefore, be certain to keep a mirror image of the
register when programming it.
All bits are 0 after a hardware RESET or power up condition.
Write the values shown in the "Bit Value (Default)" column if you are unsure.
System 6-20
Page 72
6.10 REAL TIME CLOCK - AT KEYBOARD & PS/2 MOUSE CONTROLLER
The integrated real time clock generator and AT Keyboard and PS/2 Mouse Controller
is located at U21 (#5 on Diagram 6-2). Its features are as follows:
• Complete operating system independence.
• Works with DOS, Microsoft Windows®, OS/2®, and Unix.
• High-level functional integration.
System 6-21
Page 73
6.11 MULTI-FUNCTION CONNECTOR (KEYBOARD, SPEAKER, RESET,
LED)
Connector J5 (#7 on Diagram 6-2) provides all the necessary signals for connecting the
keyboard, speaker, reset, and keylock interface devices. The following diagram shows
the pin-out at J5:
TABLE 6-6: Multi-Function Connector - Keyboard, Speaker,
Reset, LED - (J5) - Pin-Out
Pin
Number
1 I/O KBDCLK 2 - GND
3 I/O KBDDATA 4 - GND
5 - VCC (Protected:
7 O SPEAKER 8 - VCC (Protected:
9 I KBDINH 10 - GND
11 I DOWNLD* 12 - GND
13 I PBRES* 14 - GND
15 O ACTIVE* 16 - VCC (Protected:
Signal
Flow
Signal Pin
Number
6 - VCC (Protected:
Resettable Fuse)
Signal
Flow
Signal
Resettable Fuse)
Resettable Fuse)
Resettable Fuse)
* Active low signal
System 6-22
Page 74
The following functions are available on the J5 Connector:
• Speaker: An 8 ohm speaker can be directly connected to pins 7 and 8 of
J5. All necessary drivers are on the board.
• Keyboard Disable: The keyboard can be disabled or locked up by shorting pins 9
and 10 of J5.
• Hard Disk LED: The onboard IDE interface activates an external LED. The
LED must be connected anode on pin 16 (J5) and cathode on
pin 15 (J5). No external current limiting resistor is required
since one is already present on the board.
• Reset: Manually reset the system by driving PBRES* to low state
(< 0.8 V).
System 6-23
Page 75
6.12 PS/2 MOUSE CONNECTOR
The board supports a mouse, through the PS/2 connector at J13 (#8 on Diagram 6-2).
With the PS/2 Mouse Cable (available from TEKNOR), this feature is compatible with
the standard IBM PS/2 mouse. The cable may be ordered by contacting our Sales
department.
During installation of the mouse, you must install the driver provided by the mouse
manufacturer.
TABLE 6-7: PS/2 Mouse Connector (J13) - Pin-Out
Pin Number Signal
1 MCLK
2 GND
3 MDATA
4 VCC (Protected:
Resettable Fuse)
To enable the mouse, set the Mouse Support option (PS/2) to Enabled in the Advanced
Setup screen of the AMIBIOS Setup program.
System 6-24
Page 76
7 PCI-ISA BUS
7.01 LOCATION OF PCI-ISA BUS CONNECTOR
The PCI-ISA bus connector appears on the diagram below.
DIAGRAM 7-1: PCI-ISA Bus Connector Location
PCI-ISA Bus 7-1
Page 77
7.02 PCI-ISA CONNECTOR PIN-OUTS
TABLE 7-1a: ISA Bus Connector (A, B)
A SIDE B SIDE
I/O PIN Signal Name I/O I/O PIN Signal Name I/O
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
IOCHK*
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
GND
RESET DRV
VCC (+5V)
IRQ9
Not Used
DRQ2
-12V
OWS*
+12V
GND
SMEMW*
SMEMR*
IOW*
IOR*
DACK3*
DRQ3
DACK1*
DRQ1
REFRESH*
SYSCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2*
T/C
BALE
VCC (+5V)
OSC
GND
-
O
I
I
I
-
O
O
I/O
I/O
O
I
O
I
I/O
O
I
I
I
I
I
O
O
O
-
O
-
* Active low signal
PCI-ISA Bus 7-2
Page 78
TABLE 7-1b: ISA Bus Connector (C, D)
C Side D Side
I/O PIN Signal Name I/O I/O PIN Signal Name I/O
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
SBHE*
MEMR*
MEMW*
* Active low signal
LA23
LA22
LA21
LA20
LA19
LA18
LA17
SD08
SD09
SD10
SD11
SD12
SD13
SD14
SD15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
MEMCS16*
IOCS16*
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DACK0*
DRQ0
DACK5*
DRQ5
DACK6*
DRQ6
DACK7*
DRQ7
VCC (+5V)
MASTER*
GND
I
I
I
I
I
I
I
O
I
O
I
O
I
O
I
I
-
PCI-ISA Bus 7-3
Page 79
TABLE 7-2a: PCI Bus Connector (E1-E30, F1-F30)
E SIDE F SIDE
I/O PIN Signal Name I/O I/O PIN Signal Name I/O
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
VCC (+5V)
+12V
Not Used
TD
VCC
INTA*
INTC*
VCC (+5V)
PCLK4-Slot 3
VCC (+5V)
PCLK4-Slot 4
GND
GND
GNT1*
RESET*
VCC (+5V)
GNT0*
GND
REQ2*
AD30
Not Used
AD28
AD26
GND
AD24
GNT2*
Not Used
AD22
AD20
GND
O
O
O
O
O
I/O
I/O
I/O
I/O
O
I/O
I/O
-
-
-
-
I
I
-
-
-
-
-
I
-
-
-
-
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
-12V
Not Used
GND
TD
VCC (+5V)
VCC (+5V)
INTB*
INTD*
REQ3*
REQ1*
GNT3*
GND
GND
PCLK3-Slot 1
GND
PCLK3-Slot 2
GND
REQ0*
VCC (+5V)
AD31
AD29
GND
AD27
AD25
Not Used
C/BE3*
AD23
GND
AD21
AD19
-
-
-
-
-
I
I
I
I
O
-
-
O
-
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
* Active low signal
PCI-ISA Bus 7-4
Page 80
TABLE 7-2b: PCI Bus Connector (E31-E62, F31-F62)
E SIDE F SIDE
I/O PIN Signal Name I/O I/O PIN Signal Name I/O
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
E41
E42
E43
E44
E45
E46
E47
E48
E49
E52
E53
E54
E55
E56
E57
E58
E59
E60
E61
E62
AD18
AD16
Not Used
FRAME*
GND
TRDY*
GND
STOP*
Not Used
SDONE
SBO*
GND
PAR
AD15
Not Used
AD13
AD11
GND
AD9
CONNECTOR KEY
CONNECTOR KEY
C/BE0*
Not Used
AD6
AD4
GND
AD2
AD0
VCC (+5V)
REQ64*
VCC (+5V)
VCC (+5V)
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
F31
-
I
I
-
-
-
-
-
-
-
-
-
F32
F33
F34
F35
F36
F37
F38
F39
F40
F41
F42
F43
F44
F45
F46
F47
F48
F49
F52
F53
F54
F55
F56
F57
F58
F59
F60
F61
F62
Not Used
AD17
C/BE2*
GND
IRDY*
Not Used
DEVSEL*
GND
PLOCK*
PERR*
Not Used
SERR*
Not Used
C/BE1*
AD14
GND
AD12
AD10
GND
CONNECTOR KEY
CONNECTOR KEY
AD8
AD7
Not Used
AD5
AD3
GND
AD1
VCC (+5V)
ACK64*
VCC (+5V)
VCC (+5V)
I/O
I/O
-
O
-
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
-
-
* Active low signal
PCI-ISA Bus 7-5
Page 81
7.03 PCI-ISA CONNECTOR DESCRIPTION
The PCI-ISA connector on the TEK933 conforms to the PCI INDUSTRIAL
COMPUTER MANUFACTURERS GROUP (PICMG), Revision 2 specification. The
basic architecture generally follows the PCI Local Bus and the ISA Bus.
The TEK933 PCI-ISA board is designed to interface with both ISA and PCI peripheral
boards mounted on a passive backplane via its ISA-bus connector and PCI-bus
connector.
The standard 32-bit PCI-ISA connector contains a total of 218 pins.
The PCI-ISA connector is defined as an ISA-bus connector followed by a PCI-bus
connector. The ISA connector contains all the signals defined for ISA bus interface.
The PCI connector contains all the signals defined for PCI bus interface.
PCI-ISA Bus 7-6
Page 82
8 SYSTEM I/O CONTROLLER
8.01 LOCATION OF SYSTEM I/O CONTROLLER
The System I/O Controller (for Floppy drives and Parallel and Serial ports) appears on
Diagram 8-1 at U22.
DIAGRAM 8-1: System I/O Controller Location
System I/O Controller 8-1
Page 83
8.02 SYSTEM I/O CONTROLLER FEATURES
The following features are incorporated in the System I/O Controller:
• Super I/O Floppy Disk Controller:
- Supports two floppy disk drives, including single, double and high density
drives with capacities ranging from 360KB up to 2.88MB.
- Supports vertical recording format.
- 100% IBM® compatible.
- Detects all overrun and underrun conditions.
- 48 mA drivers and Schmitt trigger inputs.
- DMA enable logic.
- Data rate and drive control registers.
- Swap drives A and B.
- Non-burst mode DMA option.
- Floppy Disk Controller primary/secondary address selection.
- 16 byte data FIFO.
• Enhanced Digital Data Separator:
- Data rates: 1MB/s, 500KB/s, 300KB/s and 250KB/s.
- Supports floppy disk drives and tape drives.
- Programmable precompensation modes.
System I/O Controller 8-2
Page 84
• Multi-Mode Parallel Port:
- Standard Mode: IBM PC/XT®, PC/AT®, and PS/2 compatible bidirectional
Parallel Port.
- Enhanced Mode: Enhanced Parallel Port (EPP) compatible.
- High Speed Mode: Microsoft and Hewlett Packard Extended Capabilities Port
(ECP) compatible.
- Incorporates ChiProtect circuitry for protection against damage due to printer
power-on.
- 24 mA output drivers.
• Serial Ports:
- Two high speed UARTs with send/receive 16 byte FIFOs.
- MIDI compatible.
- Programmable baud rate generator.
- Modem control circuitry.
• General Purpose 11 Bit Address Decoder.
System I/O Controller 8-3
Page 85
9 IDE & FLOPPY
9.01 INSTALLING IDE DEVICES
9.01.1 TYPE OF HARD DISK SUPPORTED
The TEK933 supports AT Integrated Disk Drives. The AT embedded drive architecture
incorporates drive electronics and controller circuitry on a single printed circuit board
which is mounted directly on the disk drive chassis.
The integration of drive and controller functions increases reliability and performance
by eliminating redundant circuitry, thus enhancing performance at a reduced cost.
IDE & Floppy 9-1
Page 86
9.01.2 IDE CONNECTORS LOCATION & PIN-OUT
The IDE connectors appear on Diagram 9-1 at J3 and J8.
DIAGRAM 9-1: IDE Connectors Location
IDE & Floppy 9-2
Page 87
The IDE Connectors’ pin-outs appear in Tables 9-1a and 9-1b.
TABLE 9-1a: Hard Disk Connector #1 (J3) - Pin-Out
Pin
Number
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal
Flow
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
O
O
O
I
I
I
O
* Active low signal
Signal Pin
RESET*
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
GND
REQ A
IOW*
IOR*
IOCHRDY
DACK A*
IRQ14
SA1
SA0
CS0 A*
ACTIVE*
Number
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Signal
Flow
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
O
I
O
-
Signal
GND
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
Not Used
GND
GND
GND
Not Used
GND
IOCS16*
Not Used
SA2
CS1 A*
GND
IDE & Floppy 9-3
Page 88
TABLE 9-1b: Hard Disk Connector #2 (J8) - Pin-Out
Pin
Number
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal
Flow
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
O
O
O
I
I
I
O
* Active low signal
9.01.3 IDE HOOK-UP
Signal Pin
RESET*
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
GND
REQ B
IOW*
IOR*
IOCHRDY
DACK B*
IRQ15
SA1
SA0
CS0 B*
ACTIVE*
Number
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
Signal
Flow
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
O
I
O
-
Signal
GND
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
Not Used
GND
GND
GND
Not Used
GND
IOCS16*
Not Used
SA2
CS1 B*
GND
For hooking up either connector, a 40-pin dual row header signal connector is required.
This connector handles all command, data and status I/O lines. Its recommended
maximum cable length is 18-24 inches. It connects directly with the onboard 40-pin
male header connector at J3 or J8.
The drive itself can be mounted on any horizontal or vertical plane.
For a list of recommended devices and connectors, see Appendix DRECOMMENDED DEVICES & MATING CONNECTORS.
IDE & Floppy 9-4
Page 89
9.01.4 IDE SOFTWARE SETUP
AMIBIOS Setup
Starting from the AMIBIOS Setup program's main menu, use the following procedure
to complete the setup:
• From the Setup window, select the Standard icon.
• From the Standard Setup screen, select the Pri Master icon, Pri Slave icon, Sec
Master icon or Sec Slave icon.
• Select TYPE: an options list displays all valid disk drive types. Select the correct
type and press ENTER.
• You can also enter the hard disk drive parameters: Type, Cylinders, Heads, Write
Precompensation, Landing Zone, Sectors, and Capacity. This is done by selecting
the type USER.
• By selecting BLOCK MODE, you can set the IDE BLOCK MODE option (ON or
OFF). This option enables or disables multiple sector reads and writes for IDE
drives.
• By selecting LBA/LARGE MODE, you can set AMIBIOS to support IDE hard disk
capacities greater than 500MB. This option enables or disables the LBA (Logical
Block Address) mode for the specified drive. This mode is needed to support IDE
partitions greater than 500MB. IMPORTANT: When you enable LBA mode, your
hard drive must not be partitioned. Remove partitions before enabling LBA mode
(under DOS, use the FDISK command).
• Return to the main menu, and select the Peripheral icon from the Setup window.
• In the Peripheral Setup screen, the ONBOARD IDE option may be set to Disabled,
Both (enable both IDE controllers), Primary (enable primary IDE controller) or
Secondary (enable secondary IDE controller).
For more detail, refer to Section 15 - AMIBIOS SETUP.
IDE & Floppy 9-5
Page 90
9.02 INSTALLING FLOPPY DEVICES
9.02.1 TYPES OF FLOPPY DEVICES SUPPORTED
The floppy disk controller is IBM PC XT/AT compatible (single and double density)
and supports Enhanced Floppy Mode (2.88MB). It handles 3.5 inch and 5.25 inch, low
and high density drives. Up to two drives can be supported in any combination.
IDE & Floppy 9-6
Page 91
9.02.2 FLOPPY CONNECTOR LOCATION & PIN-OUT
The Floppy connector appears on Diagram 9-2 at J4.
DIAGRAM 9-2: Floppy Connector Location
IDE & Floppy 9-7
Page 92
The Floppy Connector's pin-out appears in Table 9-2.
TABLE 9-2: Floppy Disk Connector (J4) - Pin-Out
Pin
Number
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
* Active low signal
1
By default, these pins are not connected; however, by installing the W24 and W25
Signal
Flow
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Signal Pin
GND
GND
GND
GND
GND
GND
GND
GND
1
N. C.
GND
GND
GND
GND
1
N. C.
1
N. C.
GND
1
N. C.
Number
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Signal
Flow
O
-
I
O
O
O
O
O
O
O
O
I
I
I
O
I
Signal
RPM/LC
Not Used
Not Used
INDEX*
MOTOR ON 0,1*
DRIVE SELECT B
DRIVE SELECT A
MOTOR ON 2*
DIR CONTROL
STEP*
WRITE DATA*
WRITE ENABLE*
TRACK0*
WRITE PROTECT*
READ DATA*
HEAD SELECT
DSKCHG
jumpers, these configurations are possible (see also page 9-10 in the manual):
1) 17 - GND Or:2) 17 I EDOUT (2.88MB)
27 - GND 27 I HDOUT (2.88MB)
29 I EDOUT (2.88MB) 29 - GND
33 I HDOUT (2.88MB) 33 - GND
IDE & Floppy 9-8
Page 93
9.02.3 FLOPPY HOOK-UP
Mechanical Floppy Disk Installation:
The installation of the floppy drives is done via a standard IBM 34-pin flat ribbon cable
that connects to J4.
DIAGRAM 9-3: Floppy Disk Cable
Enhanced Floppy Mode:
In order to connect your 2.88MB floppy drive, simply indicate the proper floppy disk
drive in the AMIBIOS Setup program (Section 15). It is not necessary to set the
HDOUT and EDOUT media detection signal jumpers.
IDE & Floppy 9-9
Page 94
9.02.4 FLOPPY JUMPERS
There are three possible jumper configurations for the 2.88MB High Density Floppy
EDOUT and HDOUT signals:
Note:
These jumpers are optional. Your 2.88 MB Floppy Drive will operate correctly if
2.88MB is indicated in the BIOS Setup. Not installing these jumpers will work for all
floppy disk drives, as long as the proper floppy type is indicated in AMIBIOS Setup.
For proper operation, we recommend you not install these jumpers.
(1) W24: No jumper: EDOUT left to software, and
W25: No jumper: HDOUT left to software: This is the initial setting.
(2) W24: Short Pins 1 and 3: EDOUT to Pin 29 (J4), and
Short Pins 2 and 4: Ground to Pin 17 (J4), and
W25: Short Pins 1 and 3: HDOUT to Pin 33 (J4), and
Short Pins 2 and 4: Ground to Pin 27 (J4).
(3) W24: Short Pins 1 and 2: EDOUT to Pin 17 (J4), and
Short Pins 3 and 4: Ground to Pin 29 (J4), and
W25: Short Pins 1 and 2: HDOUT to Pin 27 (J4), and
Short Pins 3 and 4: Ground to Pin 33 (J4).
For location and settings of jumpers, refer to Section 2 of this manual.
IDE & Floppy 9-10
Page 95
9.02.5 FLOPPY SOFTWARE SETUP
AMIBIOS Setup
Starting from the AMIBIOS Setup program's main menu, use the following procedure
to complete the setup:
• From the Setup window, select the Standard icon.
• From the Standard Setup screen, select the Floppy A icon (or the Floppy B icon).
• The settings are 360KB 5¼ inch, 1.2MB 5¼ inch, 720KB 3½ inch, 1.44MB 3½
inch, or 2.88MB 3½ inch.
IDE & Floppy 9-11
Page 96
10 SERIAL & PARALLEL PORTS
10.01 SERIAL PORTS
There are two 16C550 compatible serial ports. These have internal 16-byte FIFO
buffers for more efficient data transfers.
For information on the programming of serial ports with the use of FIFO buffers, you
can ask for Application Note # AN93007 from TEKNOR’s Technical Support
department.
Serial & Parallel Ports 10-1
Page 97
10.01.1 SERIAL PORTS LOCATION & PIN-OUTS
Serial Port 1 and Serial Port 2 appear on Diagram 10-1 at J6 and J7 respectively.
DIAGRAM 10-1: Serial Ports Location
Serial & Parallel Ports 10-2
Page 98
Serial Port 1 (J6) RS232
The Serial Port 1 is configured as RS232. With the IBM 9-pin DSUB Standard, Serial
Port 1 is 100% compatible with the IBM-AT serial port. The following tables show
their pin-outs:
TABLE 10-1a: Serial Port 1 (J6) RS232 - Pin-Out
Pin
Number
1 I DCD 2 I DSR
3 I RX 4 O RTS
5 O TX 6 I CTS
7 O DTR 8 I RI
9 - GND 10 - Not Used
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
TABLE 10-1b: IBM 9-Pin DSUB Standard - Pin-Out
Pin
Number
1 I DCD 2 I RX
3 O TX 4 O DTR
5 - GND 6 I DSR
7 O RTS 8 I CTS
9 I RI 10
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
TEKNOR offers a 10-pin header to 9-pin DSUB cable for IBM-AT compatibility. This
can be purchased from TEKNOR or a cable can be made with a flat cable, a 10-pin flat
cable crimp header and a 9-pin DSUB flat cable crimp connector. The use of Taïwanese
adapter cables is not recommended, since the pin-out is often incorrect. The direct
crimp design offered by TEKNOR allows the simplest cable assembly. All these cables
are available from TEKNOR by contacting the Sales department.
Serial & Parallel Ports 10-3
Page 99
Serial Port 2 (J7) RS232
The Serial Port 2 can be configured as RS232 or RS485. As a RS232 port, and with the
IBM 9-pin DSUB Standard, Serial Port 2 is 100% compatible with the IBM-AT serial
port. The following tables show their pin-outs:
TABLE 10-2a: Serial Port 2 (J7) RS232 - Pin-Out
Pin
Number
1 I DCD 2 I DSR
3 I RX 4 O RTS
5 O TX 6 I CTS
7 O DTR 8 I RI
9 - GND 10 - Not Used
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
TABLE 10-2b: IBM 9-Pin DSUB Standard - Pin-Out
Pin
Number
1 I DCD 2 I RX
3 O TX 4 O DTR
5 - GND 6 I DSR
7 O RTS 8 I CTS
9 I RI 10
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
TEKNOR offers a 10-pin header to 9-pin DSUB cable for IBM-AT compatibility. This
can be purchased from TEKNOR or a cable can be made with a flat cable, a 10-pin flat
cable crimp header and a 9-pin DSUB flat cable crimp connector. The use of Taïwanese
adapter cables is not recommended, since the pin-out is often incorrect. The direct
crimp design offered by TEKNOR allows the simplest cable assembly. All these cables
are available from TEKNOR by contacting the Sales department.
Serial & Parallel Ports 10-4
Page 100
Serial Port 2 (J7) RS485/RS422
If Serial Port 2 is configured for RS485 operation, it can support either full-duplex or
party line communication.
Full Duplex Operation (RS422): Upon power-up or reset, the COM2 interface circuits
are automatically configured for full duplex operation. Pins 3 and 4 of J7 act as the
receiver lines and pins 5 and 6 act as the transmitter lines.
Party Line Operation (RS485): In order to enable party line operation, the user must
first write "1" to bit 3 at I/O address 190H (or at 290H or 390H depending on W9
jumper). This allows the transceiver (pins 3 and 4 of J7) to be controlled by the RTS
signal. Upon power-up or reset, the transceiver is by default in "receiver mode" in
order to prevent unwanted perturbation on the line.
In party line operation, termination resistors R84 and R85 must be installed only on the
boards at both ends of the network.
The following table shows this connector's pin-out:
TABLE 10-3: Serial Port 2 (J7) RS485/RS422 - Pin-Out
Pin
Number
1 I DCD 2 I DSR
3 I/O RXD(-) 4 I/O RXD(+)
5 O TXD(-) 6 I TXD(+)
7 O DTR 8 I RI
9 - GND 10 - Not Used
Signal
Flow
Signal Pin
Number
Signal
Flow
Signal
Serial & Parallel Ports 10-5
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