Technologic Systems TS-ETH100 Getting Started

GETTING STARTED WITH TS-ETH100

10/100 ETHERNET PERIPHERAL BOARD

OVERVIEW

The TS-ETH100 is a PC/104 peripheral board (standard format) that provides a 10/100
Ethernet port. The TS-ETH100 is compatible with both Technologic Systems x86 and ARM
single board computers. TS-ETH100 features include:

✔ 10/100 Ethernet Port
✔ Jumper selectable I/O and IRQ
✔ PC/104 Dimensions 3.6 x 3.8 inches
✔ Wake-on-LAN
✔ Linux driver and utilities available
✔ RoHS compliant (Restriction of Certain Hazardous Substances)

The TS-ETH100 provides an integrated 10/100 ethernet port through the ASIX AX88796B
embedded MAC with on-chip PHY. It interfaces with the PC/104 connector via 16-bit data
bus and the register map is NE2000 compatible. The ASIX solution features Wake-on-LAN
functionality, enabling the Ethernet chip to enter in sleep mode with programmed wake-up on
the recepetion of a magic network package.

PRODUCT VIEW

HARDWARE CONFIGURATION

The TS-ETH100 jumpers select one-of-three IRQ lines and one-of-four I/O address regions.
Also, it is possible to do PC/104 16-bit access using only the 64-pin PC/104 connector in
ARM mode if the ARM jumper is ON. Jumpers IRQ5, IRQ6 and IRQ7 (ARM IRQs 22, 33 and
40, respectively) selects the desired ISA IRQ line for the TS-ETH100 MAC.

There are two on-board LEDs for the MAC, indicating speed of the link and network activity
on the cable.

I/O ADDRESS

The PLD and MAC I/O address locations can be configured using jumpers Add1 and Add2
according to the table below:

© Nov, 2007 www.embeddedARM.com 1

GETTING STARTED WITH TS-ETH100

10/100 ETHERNET PERIPHERAL BOARD

Jumper settings for I/O

address space selection

PLD I/O MAC I/O Add1 Add2

0x100 0x200 OFF OFF

0x110 0x240 ON OFF

0x120 0x300 OFF ON

0x130 0x340 ON ON

BASE REGISTER MAP

The TS-ETH100 has 4 registers of 4-bits each which are implemented on the PLD.

I/O Addr Description Data Access Bits and such

Base+0x0 Board identifier Read only returns 0x5 unique ID to verify presence
Base+0x4 PLD revision Read only Returns PLD revision
Base+0x8 SRAM control

register

Read only bit 3 = IRQ7 jumper status (1=ON, 0=OFF)

Note

TS-ARM (TS-7000 SBC's) I/O space
starts at 0x11E0_0000 physical address.
e.g. 0x100 I/O space is decoded at
0x11E0_0100 physical memory

bit 2 = IRQ6 jumper status (1=ON, 0=OFF)
bit 1 = IRQ5 jumper status (1=ON, 0=OFF)
bit 0 = ARM jumper status (1=ON, 0=OFF)

For a complete description of the MAC register map (which is NE2000 compatible), please
refer to the ASIX AX88796B documentation.

SOFTWARE SUPPORT

The register map of ASIX AX88796B ethernet chip is NE2000 compatible, so driver support
is straight-forward. Technologic Systems provides a Linux driver for the ASIX Ethernet
interface suitable for both Kernel versions 2.4 and 2.6. The Linux driver provided detects
jumper selection, automatically configuring IRQ and IO parameters. In case one wants to
skip this feature, the “mem” and “irq” parameters are available to set up I/O base address
and IRQ line, respectively. To load the driver using the auto-detection and Kernel 2.4, use:

# insmod –f ax88796b.o

To load the driver using the parameters and Kernel 2.4 for ARM, with a board with only the
IRQ5 jumper ON, use:

# insmod –f ax88796b.o mem=0x100 irq=33

Notice that in some systems the kernel module “crc32.o” must be loaded before the TS­ETH100 driver. In addition, Technologic Systems provides Linux tools to manage the Wake­on-LAN function. A Linux tool to program the MAC address on the EEPROM chip is also
provided. Contact Technologic Systems for further information regarding software support.

CONTACT TECHNOLOGIC SYSTEMS

16610 East Laser Drive #10

Fountain Hills, AZ 85268

TEL [phone]
FAX [phone]

www.embeddedARM.com

[e-mail]

DOCUMENT HISTORY

11.26.2007 – CREATED

© Nov, 2007 www.embeddedARM.com 2