Technicolor - Thomson ICC19 Principles And Maintenance

ICC19 CHASSIS TELEVISION SETS:

PRINCIPLES AND MAINTENANCE

50-Hz CHASSIS

100-HzCHASSIS

Code : 3504.93.50 - 07/97 - ICC19 CHASSIS TELEVISION SETS: PRINCIPLES AND MAINTENANCE.

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MENUS

NAVILIGHT

2

CONTENTS

GENERAL INFORMATION-----------------------------------------------------------------------------------------3

MANAGEMENT------------------------------------------------------------------------------------------------------- 5

POWER SUPPLY ---------------------------------------------------------------------------------------------------23

TIME BASES------- ------------------------------------------------------------------------------------------------- 57

HIGH FREQUENCIES/MEDIUM FREQUENCY------------------------------------------------------------ 73

SWITCHING --------------------------------------------------------------------------------------------------------- 79

50-HZ VIDEO-------------------------------------------------------------------------------------------------------- 89

100-HZ VIDEO----------------------------------------------------------------------------------------------------- 103

VIDEOTEXT AND OSD ----------------------------------------------------------------------------------------- 125

RGB AMPLIFIERS------------------------------------------------------------------------------------------------ 129

AUDIO PROCESSING ------------------------------------------------------------------------------------------ 133

DOLBY PROLOGIC --------------------------------------------------------------------------------------------- 139

123

GENERAL INFORMATION

4

CONTENTS

• IR001 POWER SUPPLY AND OPERATIONAL SIGNALS

• DATA MANAGEMENT

• CONTROLS

• RMICROCONTROLLER/EPROM COMMUNICATION

• BUSES

5

MANAGEMENT

• OTHER CONTROLS

• SWITCH-ON PROCEDURE

• FRONT PANEL LED CONTROL

• OFF/ON TIMING DIAGRAM

• ERROR CODES

• BUS EXPANDER

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FORMATION TECHNIQUE

5

6

IP130

DP130

DP133

CP130

CP141

DP134

IP140

REGULATOR

5V

CP142

+5V

IR001

ST90R92

TDA8139

CR009

CR010

QR001
27MHZ

46

48

9

6

3

49

23

RP147

40ms

1

MC7812

LP020

17

18

13V (L)

VCC

RESET

3v

1

2

3

RESET

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FORMATION TECHNIQUE

6

IR001 POWER SUPPLY AND OPERATIONAL SIGNALS

POWER SUPPLY

The power supply to the microcontroller at Pin 23 is active when the IP130
regulator (which produces a 10VSTBY) and the IP140 regulator (which
produces a 5VSTBY from the 10VSTBY) are on Standby. When they are On,
the 13 V (LINE) supply takes over from the 10VSTBY.

CLOCK.

A 27-MHz QR001 quartz stabilises the system clock of the IR001
microcontroller (Pins 46 and 48).

RESET.

CP142, Pin 3 of the IP140 is the Reset capacitor. When the voltage at Pin 9 of

7

the IP140 has reached 5 V, and after a delay of a few milliseconds given by
CP142, Pin 6 of the IP140 goes from 0 to 5 V. Pin 49 of IR001 receives this
Reset signal.

NOTES :

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FORMATION TECHNIQUE

7

RESET

+5VSTBY

RIR

STB-LED

CLAVIER

LDR

AFC

AV1

AV2

MUTE

MUTE C

SAT_ON_DEG

FB_DET

TV OFF

ZOOM
E-FIELD

I2C-1

I2C-2

SND-RESET

INT

BUS M3L

IR001

ST90R92

EEPROM

IR003

IR004

BE_STROB

EPROM

IR002

256 Ko

4 Ko

Expander

RAM

REGISTRES

TIMER

SAFETY

Bus µp

QR001

M-RESET

POWER-FAIL

Alim.

VIDEOTEXT

DEFLECTION
VIDEO MATRIX

PIP MODULE

DOLBY SOUND

TUNER CCT5000
CHROMA 1H / 2H

PSI 2H

MEGATEXT

VIDEO MODULE

100HZ

MODULE

27MHZ

MARK-E-TING

Data

Addresses

DS

46

48

23

51

53

43

42

44

45

62

52

54

27

40

41

49

55

28

63

64

65

25

39

29

33

32

31

34

VIDEO ADJUSTMENT

8

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FORMATION TECHNIQUE

8

DATA MANAGEMENT

ICC19 chassis are 50-Hz or 100-Hz compatible. They are controlled by an 8­bit microcontroller, the ST90R92.

It communicates via an address and data bus with its external program
memory, an EPROM, IR002, with a basic capacity of 256 KB that can be
extended to 1024 KB.

Two I2C buses dialog with the various programmable circuits installed on the
chassis.

In conjunction with IR003 (EEPROM), the I2C1 bus saves the parameters and
settings required by the television set.

It manages the ON/OFF command, the line and frame time base circuits, audio
and video switching, and settings including the USYST voltage.

9

In conjunction with the tuner frequency synthesis, the I2C2 bus controls video
processing and the 100-Hz digital converter.

It also controls an 8-bit IR004 universal register (EXP ANDER), which increases
the number of control ports.

NOTES :

The M3L bus is intended for the TELETEXT module (MEGATEXT version).
The microcontroller analyses and distributes the commands from peripheral

devices, the infrared receiver, the keypad, and the red LED via several input
and output lines.

The INT line is the HALT input of the microcontroller, and the MAIN RESET
output of the TELETEX module.

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FORMATION TECHNIQUE

9

A

B

C

D

58

59

60

53

VOL+

VOL-

PROG+

PROG-

INSTALL

EXIT

MENU

MUTE

INFO

RR

039

RR

040

RR

038

RR037

RR045

RR032

RR033

RR034

RR035

RR044

5VSTBY

5VSTBY

RIR

IR001

KEY OUT

KEY IN

RR924
OPTION

35

36

37

38

10

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FORMATION TECHNIQUE

10

CONTROLS

KEYPAD

The keypad is compatible with previous ICC10/11 chassis. It can support four
to 10 control keys. It is laid out in a matrix of rows and columns.
Pins 58 through 60 are the function inputs. They are at 5 V when idle. Pins 35
through 38, which are labelled A, B, C, and D, are the sweep outputs. Signals
with a period of 20 ms are present on these outputs when idle.
During the initialisation phase, Line C (Pin 36) is connected to the input and
analysed. In this way , an option prediction, determined by Resistor RR924, can
be read.
The four diodes protect the IR001 circuit inputs.

REMOTE CONTROL UNIT

LRemote control function codes (12 bits) arrive at Pin 53 of IR001. They consist

11

of the following:

• Four address bits,

• One call bit,

• Seven function bits, defined by the key pressed.
These codes are repetitive at 80-ms intervals.

NOTES :

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FORMATION TECHNIQUE

11

BS05

BS04

BS01

BS00

15 bits

8 bits

A0 - A14

D0 à D715 à 22

25

24

Data strobe line DS

16

17 à 21

5VSTBY

1 - 32

14

13

3

2

30

31

57

56

1 à12

et

66 à 68

4 à 12

23

25 à 29

13 à15

IR002

EPROM

IR001

µ C

12

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FORMATION TECHNIQUE

12

REMOTE CONTROL UNIT

ADDRESSING

The IR002, memory for the software and default values, is an EPROM with
capacity up to 512 KB or 4 Mbits.
The 8-bit ST90R92 microcontroller has an address bus (A0-A14) limited to 15
bits. This provides addressing of only 32 KB. Page-swapping is therefore
necessary.

Four output port lines (BS00 through BS05) swap the read-only memory for a
selection of 16 pages compatible with the use of an 8-Mbit memory capacity,
i.e. 1024 KB.

DATA

13

Data comprising eight bits, labelled D0 through D7, are sent via the data bus.
To prevent any conflict of addresses with the microcontroller internal RAM, an
enable line, called data-strobe, is activated in the low state when the
microcontroller communicates with its ROM. The rest of the time, the IR002 is
in tri-state to free the data bus.

NOTES :

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FORMATION TECHNIQUE

13

IR004

REGISTER

MC14094

IR003

EEPROM

M24C32

DR104

9,1V

RR

010

RR
011

+5VSTBY 13V L

M3L-CK

M3L-DA

M3L-ENAB

63
64

65

32
31

34

33

29

BE-STROBE

2

SDA

SCL

SDA

SCL

RR055

RR056

+5V

+5VSTBY

RR052RR053

IR001

1

11

8

14

6

3

12

13

16

15

5V

BG_INFO

L1_INFO

I_INFO

IIC2

IIC1

DEGAUSS

NORM

TUNER

VIDEO MODULE

PERITEL
AUDIO

IV001

8

7

5

6

VIDEOTEXT

TR095

µc

PIP

MEGATEXT

RR

012

14

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FORMATION TECHNIQUE

14

BUSES

The IIC1 bus is charged by pull-up resistors connected to the +5VSTBY. It is
active in Standby and On Modes.
It dialogs with the IR003 NVM (M24C32) to store the user parameters.
It distributes its commands to the SCART switching circuits, the Audio Module,
and the sweep and video processor (IV001).

The IIC2 bus, referenced by pull-up resistors connected to the +5V, is active in
On Mode only.
It communicates directly with the PLL built into the tuner. It controls the Video
Module as well as the IR004 expander circuit.

The M3L bus is used in controlling the Teletext or Megatext Module.

BUS EXPANDER

15

Integrated Circuit IR004 (MC14094) is an 8-bit serial/parallel register that
extends the interface capacity of the microcontroller.
It is equipped with a de-serialiser register and an output register. Its BE­STROBE (Pin 1) has the function of transferring a service byte to its outputs.

• Pin 6: NORM is used via Transistor TR095 by Integrated Circuit FI II050.

• Pin 11: DEGAUSS. According to chassis option, this output delivers a relay
command pulse to degauss the tube.

• Pin 12: I-INFO adjusts the video level to the I standard.

• Pin 13: L1-INFO is used for switching to Band 1 L'.

• Pin 14: BG-INFO is used to operate filters to reject the neighbouring channel
(31.9 MHz) and to reject FM sound intercarriers (5.5 MHz or 6.5 MHz).

NOTES :

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FORMATION TECHNIQUE

15

40

54

28

52

43

44

45

62

41
27

42

IR01

TV_OFF

RR910

TR102

RR103

MUTE CENTER

MARK_E_TING

MUTE

LDR

RR042

RR043

13V (L)

sensor

AV2 (8)

AV1 (8)

(A/D)

(A/D)

(A/D)

FB_DET

SAT_0N

AFC

DR091

(A/D)

ZOOM /E-FIELD

(PWM)

(A/D)

µC

SAFE

C MUTE

DR090

16

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FORMATION TECHNIQUE

16

OTHER CONTROLS

The function of Pin 27 is to switch the power supply separately from the satellite
tuner.

Pin 40 is used to switch off the television set using a control independent of the
buses. This is very useful in the event of the buses being blocked.
The breathing line is pulled down via Transistor TR102. In addition, this line is
analysed by software to indicate whether the TV is a 100-Hz or 50-Hz model.
This is indicated by RR910 (RR910 = 10K, 4 V at 40 = 100 Hz; RR910 = 0,

0.6 V at 40 = 50 Hz).

Pin 41 has two functions:

• To control the ZOOM Module if the television set is so equipped.

• On the 28" SF and 32" 16/9 modules, it delivers a PWM (pulse width
modulation) signal to compensate for the earth's magnetic field.

Pin 42 informs and analogue-to-digital converter for the AFC (automatic

17

frequency control). It operates in Automatic Programming and Manual Search
Modes.

Pin 43 informs an analogue-to-digital converter. This is used to regulate the
contrast according to the ambient lighting.

Pins 44 and 45 receive slow switching from SCART sockets AV1 and AV2.
They are used to recognise the formats of received images: 4/3 and 16/9.

NOTES

Pin 52 mutes the audio amplifiers. It is active at low level, and is present each
time the TV is switched on or off.

Pin 54 is reserved for the DOLBY SURROUND PROLOGIC function only, to
perform a software cut-off of the TV internal speakers, to free the central
channel. It does not act on the auxiliary external output sockets.

Pin 62 indicates the presence of fast switching from SCART socket AV1.
At Pin 28, the input when the microcontroller is initialised by its pull-up wiring

specifies the size of the read-only memory, IR002, by selecting the number of
pages to swap. It is completed by the wiring of Pins 63 and 61 to the 5VSBY.

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FORMATION TECHNIQUE

17

R

V

VCC1

RV001

TV002

RV002

20

24

44

22

M

V

19

18

65

31

32

IR003

24C32

IR001

REGISTER

INTERFACE BUS

65

M3-ENAB

DATA

CLK

43

I-CUT

38

17

37 25

CV246

DR104

9,1V

RR010

HORIZONTAL
DEFLECTION

TR002

RR031
RR036

RR29

51

REGULATION

CTL

VERTICAL

CTL

Cde

LIGNE

+5vSTBY

10VSTBY

+UVERT

8V

IV001

STV2161/
STV2162

ST90R92

13v

45
34

RV091

RR030

5V

REG.

RP148 RP149

RP142

RP143

TP146

+5V

5,8V

de DP140

2

4

8

7

IP140

DP134

18

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FORMATION TECHNIQUE

18

SWITCH-ON PROCEDURE

FRONT PANEL LED CONTROL

The 10VSTBY from the power supply is used. This is limited to 5 V by a Zener
diode inside the IV001, and powers its IIC1 bus interface.

After its power supply , clock, and reset, the IR001 microcontroller manages the
following commands:

• RAM reading,

• I/O configuration of ports,

• Reading EEPROM, IR003. To be programmed, if necessary, using the default
values contained in the IR002 program memory, if it is deprogrammed or
blank.

When an ON command is issued, the IR001 microcontroller initialises IV001
via its IIC1 bus with values stored in the EEPROM (loading of essential
parameters: on, geometry, etc.). Pin 24 on the IV001 is freed, and leads to the
presence of VCC1 = 8 V via TV002. This voltage powers Pins 22 and 44 of the

19

IV001.
The line time base, secondary regulation, and frame time base are gradually

powered up by the slow-starting capacitor, CV246 (Pin 17 of IV001).
The rising of the line 13 V transmitted by DR104 confirms that the On function

is fully established (5V at Pine 65 of IR001). This 13VL also makes it possible
to obtain a +5V via the IP140 regulator.

In Standby Mode, Pin 51 of microcontroller IR001 is in high impedance.
Switching transistor TR002 powers the red LED from the 5 V STBY.
In On Mode, the 13 V from the line time base powers the green LED. This is the
initialisation phase, and results in the indicator lamp glowing orange.
When the warm tube signal, sent by the I2C1 bus to IR001, is detected, Pin 51
of IR001 goes to 0. This blocks TR002 and cuts off the power supply to the red
LED.

The ICUT signal (Pin 43 of IV001) indicates when the tube is warmed up, and
frees the analogue controls. The image and sound appear. Orders routed in
from the outside, e.g. from the keypad or the remote control unit, are then
processed.

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FORMATION TECHNIQUE

19

20

Init.

IV001

40ms

10v STBY
5v STBY

400ms

Reset

IIC1

TV-OFF

H-DRIVE

+13v

+5V

IIC2

M3L

Interrupt

Power

fail

M-Reset

Mute C

Mute

I CUT

OFF to ON CHRONOGRAM

0V

+1,2V

100ms

RED ORANGE GREENOFF

1s

H

DRIVE

ON

4s

100ms

0,5ms

PB

NVM

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FORMATION TECHNIQUE

20

ERROR CODES

LIST OF ERROR CODES

These error codes are displayed by the red LED. They are displayed only if the
management microcontroller is operating.
A maximum of 81 codes (1 1 through 99) can be signalled. These codes consist
of two digits separated by a 0.7-second pause. The error codes are repeated
again and again, with a pause of 1.7 s between error codes.

SIGNAL RATE AT 2 OF BR001
There are four possible waveforms, according to whether the TV remains in

Standby Mode or is switched On, and whether LED pause status is Off, Red,
Orange, or Green.

pause

orange

21

0,7 sec. 1,7 sec.

24

0,7 sec.

0,7 sec.

1,7 sec.

pause

vert

250ms250ms

pause

rouge

1,7 sec.

34

0,7 sec. 1,7 sec.

pause

éteint

vert

orange

éteint

rouge

CODE

11

12

13

14

15

16

17

18

19

21

22

23

24

25

ERROR CODE

ACR MSP3410

ACR MSP3400

ACR DSP56004

ACR STV2161/2162

ACR STV2151ou
TDA9143

ACR DMU0

AUDIO MODULE NOT
DETECTED

ACR TEA6415C

ACR TUNER

IIC1 DATA EARTHED

IIC2 DATA EARTHED

IIC1 CLOCK EARTHED

IIC2 CLOCK EARTHED

SWITCHED 5 V ABSENT

26

27

28

29

31

32

33

34

35

36

37

38

39

ERROR

NO WARM TUBE SIGNAL
AFTER 15 s

STV216X DETECTED A CASE
OF PROTECTION 3 TIMES

MEGATEXT INTERFACE
NOT RESPONDING

MEGATEXT DRAM IS
DEFECTIVE

NO RAM AVAILABLE FOR THE
REQUESTED FUNCTION

TIMER OCCUPIED

ACR STV2165

ACR NVM M24C32

13V ABSENT

NVM ADDRESS NOT
FOUND

INCORRECT NMI LEVEL
(HALT)

M3L BUS IS BLOCKED

MEGATEXT NOT LISTE­NING

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FORMATION TECHNIQUE

21

22

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FORMATION TECHNIQUE

22

CONTENTS

INTRODUCTION
PRINCIPLE
CHARACTERISTICS
LP020 POWER SUPPLY
INTEGRATED CIRCUIT TEA2261
SECONDARY REGULATION

23

POWER SUPPLY

POWER SUPPLY INTERLOCKS
MAINS POWER CUT DETECTION

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FORMATION TECHNIQUE

23

24

+300V

TP060

220V

LP 070

LP020

14

Safety

2

9

IP060

TEA
2261

16

DP110

10

11

3

DP109

CP060

Usys

CP061

RP061

76

1

8

15

Logic

Processor

DP130

-US

Osc

PWM

Soft start

DP108

Power/

Deflection

safeties

RL81/82

RP054

CP

054

+US

+10V

STBY

GNDS

CP063

RP025

IP130

DP133

+13V

+U

VERT

RL80

+US

-US
+5V

IV001

(STV2161)
(STV2162)

SMPS

SMPS

CP020

Regulation/

Deflection

safeties

10V

Reg.

PFCPFC

(50Hz)

Contr.

(100Hz)

TP025

RP060

RP059

TP027

(Option)

RP065

RP020

CP062

CP064

DP053

DP050

DP

052

12

DP

134

TP161

DP140

IP140

5V

STBY

+5V

TDA8139

MIS

BREATHING

+U13

DP60

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FORMATION TECHNIQUE

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25

INTRODUCTION

The ICC19 power supply comes in two main versions: one operating at 16
kHz, and the other operating at 32 kHz. The main difference lies in the choice
of components.

PRINCIPLE

IThe power supply is a fixed-frequency flyback-type switching power supply
unit. Two specific regulating loops come into action according to the status
of the TVC.

In Standby Mode, the frequency is determined by an oscillator located on the
primary.
This is also where regulation occurs. To do this, a signal indicating the
overall consumption of the secondaries, picked up on a primary winding, is
used.
In Steady-State Mode, the line frequency synchronises the signal.
Regulation then takes place at the secondary, and is based on stabilising the
voltage USYS applied to the line time base.

CHARACTERISTICS

TMains voltage: 190 to 264 volts.
Secondary voltages:

NOTES :

U SYS 127 to 136 V for 50-Hz chassis.

130 to 142 V for 100-Hz chassis.

+ US approx. +18 V for stereo chassis

approx. +14 V for Dolby chassis.

- US approx. -18 V for stereo chassis
approx. -14 V for Dolby chassis.

UVERT 26 V on 50-Hz chassis

23 V on 100-Hz chassis.

U 7V 6 to 7 V5 according to chassis.

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FORMATION TECHNIQUE

25

220VAC

Um

C1

b

Um

Im

a

-

R

+

C2

L1 D1

n

c

2n

Im

-

R

+

C

Uc

RL

220VAC

26

Um

Uc

Im

Narrow current pulse including
a high harmonic level

Um

Ub

ID1

Im

D1 conduction
level when
T1 is ON

Without PFC

With PFC

T1

Ua

Um

WITHOUT PFC CIRCUIT

WITH PFC CIRCUIT

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FORMATION TECHNIQUE

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27

LP020 POWER SUPPLY

The new European standard, EN60555-2, limits pollution of the mains
voltage by harmonics. For this purpose, the main primary winding is
connected to the bridge rectifier via a power factor correction circuit.

PRINCIPLE

Harmonics are generated by the filter capacitor charging current.
The narrower the charge pulse, the higher the amplitude of the harmonics
(this occurs with a weak voltage residual and therefore a high capacitor
value).
The layout used for this chassis therefore operates on the principle of
widening these charging current pulses to reduce the amplitude of
harmonics. To do this, a condenser C1 is inserted between the diode bridge
and filter condenser C2 (C1 < < C2). It decouples the dc voltage between
Condenser C2, charged to 300 V, and the diode bridge, providing full-wave
rectification of the mains voltage.
An intermediate tap on the primary winding divides the winding so that when
Transistor T1 conducts, the voltage at Point C is about 2/3 the value of the
voltage at Point B. This, as soon as the rectified mains voltage exceeds this
value (Point A), Diode D1 conducts, and the current is tapped directly off the
diode bridge.
Because of this, a lower load is applied to Capacitor C2 (resulting in a lower
charging current), and the mains voltage takes effect over a longer period.
The current pulse taken from the mains therefore generates a lower level of
harmonics.

NOTES :

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FORMATION TECHNIQUE

27