TECHNEXION PICOIMX7 User Manual
PICO-PI-IMX7
REV B1
NXP i.MX7
April 5, 2017
PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
TABLE OF CONTENTS
1. PICO-PI-IMX7 Product Overview ........................................................................................................ 3
1.1. PICO-IMX7 WiFi+Bluetooth 4.0(HS) System no Module Overview ............................................. 4
1.2. PICO-PI-IMX7 Carrier Baseboard Overview ................................................................................ 5
2. Core Components ............................................................................................................................... 6
2.1. NXP i.MX7 ARM Cortex-A7 + Cortex-M4 Processor ................................................................... 6
2.2. Power Management IC (NXP PF3000) ........................................................................................ 7
2.2.1. NXP PF3000 Reset Signal .................................................................................................... 7
2.3. Memory ......................................................................................................................................... 9
2.4. eMMC Storage ............................................................................................................................. 9
2.5. WiFi/Bluetooth SIP Module ........................................................................................................ 10
3. PICO-PI-IMX7 Interfaces and Connectors ........................................................................................ 13
3.1. Power Input Connector ............................................................................................................... 13
3.2. System RESET Button ............................................................................................................... 13
3.3. Gigabit Ethernet .......................................................................................................................... 14
3.4. Audio Interface ........................................................................................................................... 15
3.5. Universal Serial Bus (USB) Host Interface ................................................................................. 16
3.6. Universal Serial Bus (USB) OTG Interface ................................................................................ 16
3.7. Debug Interface .......................................................................................................................... 17
3.8. Serial Boot or eMMC Boot Control Pins ..................................................................................... 18
3.9. Expansion Header Pins .............................................................................................................. 19
3.10. Display and Touch Connector .................................................................................................. 22
3.11. MIPI Connector ......................................................................................................................... 25
4. PICO Compute Module Pin Assignment ........................................................................................... 27
5. Disclaimer and Important Notice ....................................................................................................... 35
6. Schematics ........................................................................................................................................ 36
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
1. PICO-PI-IMX7 Product Overview
The PICO-PI-IMX7 is a 2 board development board consisting of a WiFi+Bluetooth 4.0(HS) System
no Module and a carrier baseboard and optimized for the Internet-of-Things (IoT).
Product operating temperature 60℃.
Figure 1 - PICO-PI-IMX7 IC Identification and Overview
Figure 2 - PICO-PI-IMX7 Connector Overview
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
Figure 3 – PICO-PI-IMX7 Bottom Side Connector Overview
1.1. PICO-IMX7 WiFi+Bluetooth 4.0(HS) System no Module Overview
The PICO-IMX7 WiFi+Bluetooth 4.0(HS) System no Module (PICO-IMX7-EMMC) has 3 Hirose highspeed 70 pin board-to-board connectors and integrates the NXP i.MX7, Memory, eMMC, Power
Management IC (PMIC) and WiFi / Bluetooth on the module.
Figure 4 - PICO-IMX7 WiFi+Bluetooth 4.0(HS) System no Module
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
Figure 5 - PICO-IMX7 WiFi+Bluetooth 4.0(HS) System no Module Block Diagram Overview
Figure 6 - PICO-IMX7 WiFi+Bluetooth 4.0(HS) System no Module Dimensions
1.2. PICO-PI-IMX7 Carrier Baseboard Overview
The PICO-PI-IMX7 Carrier Baseboard (PICO-PI-GL) has 3 Hirose high-speed 70 pin board-to-board
connectors that connect to the WiFi+Bluetooth 4.0(HS) System no Module and provides the real-world
interfaces such as audio, network, USB and a large number of signals on the various pin headers.
Figure 7 - PICO-PI-GL Carrier Board
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
2. Core Components
2.1. NXP i.MX7 ARM Cortex-A7 + Cortex-M4 Processor
The i.MX7 is an ultra-efficient processor family with featuring NXP’s advanced implementation of the
ARM Cortex® -A7+M4 core, which operates at speeds of up to 1 Ghz.
The device is composed of the following major subsystems:
o Upto Two ARM Cortex-A7 Cores (with TrustZone® technology)
o Up to 1GHz operation frequency
o 32 KByte L1 Instruction Cache, 32 KByte L1 Data Cache
o Private Timer and Watchdog
o NEON MPE coprocessor
One ARM Cortex-M4 Core dedicated for real-time tasks, with the following features:
o 200MHz operation frequency
o MPU, FPU
o 16 KByte instruction cache, 16 KByte data cache
o 64 KByte TCM (tightly-coupled memory)
Cryptographic acceleration and assurance module, containing cryptographic and hash
engines supporting DPA (differential power analysis) protection, 32 KB secure RAM, and true
and pseudo random number generator (NIST certified)
PXP—PiXel processing pipeline for imagine resize, rotation, overlay and CSC. Offloading key
pixel processing operations are required to support the display applications
Figure 8 - NXP i.MX7 Processor Blocks
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
CPU
BALL
CPU PAD
NAME
Pinmux (mode)
Signal
V
I/O
Description
D12
SAI1_RX
C
I2C4_SDA
SDA
3V3
I/O
I2C bus data line
C12
SAI1_RX
FS
I2C4_SCL
SCL
3V3
I/O
I2C bus clock line
AB8
PMIC_ON
_REQ
PMIC_ON_REQ
PWRON
3V3
I
PMIC Power ON/OFF
Input from processor
E10
SAI1_MC
LK
GPIO6_IO18
INT
3V3
I
PMIC Interrupt Signal
R6
POR_B
POR_B
RESETBMC
U
3V3
I
PMIC Reset Signal
AC7
PMIC_ST
BY_REQ
PMIC_STBY_RE
Q
STANDBY
3V3
I
PMIC Standby Input
Signal
CPU
BALL
CPU PAD
NAME
Pinmux (mode)
Signal
V
I/O
Description
N1
GPIO1_IO00
WDOG1_WDOG
RESET
3V3
I
Connected to the
PWRON signal of PMIC
Connector
Signal
V
I/O
Description
E1_36
RESET
1V8
I
Connected to the PWRON signal
2.2. Power Management IC (NXP PF3000)
The PICO-IMX7 has on onboard NXP PF3000 power management integrated circuit (PMIC) that
features a configurable architecture supporting the numerous outputs with various current ratings as
well as programmable voltage and sequencing required by the components on the PICO-IMX7
module.
Table 1 - PMIC Signal Description
2.2.1. NXP PF3000 Reset Signal
To perform a hard-reset of the PICO-IMX7 a software reset signal can be implemented.
Table 2 - PMIC Reset Signal Description
To perform a hard-reset of the PICO-IMX7 an external circuit (for example a button or external
watchdog IC) can be integrated on the carrier board.
Table 3 - PMIC Reset Signal Description
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
Figure 9 – RESET Button Location
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
CPU
BALL
CPU PAD NAME
Signal
V
I/O
Description
B2
SD3_DATA0
eMMC_DATA0
3V3
I/O
MMC/SDIO Data bit 0
A2
SD3_DATA1
eMMC_DATA1
3V3
I/O
MMC/SDIO Data bit 1
G2
SD3_DATA2
eMMC_DATA2
3V3
I/O
MMC/SDIO Data bit 2
F1
SD3_DATA3
eMMC_DATA3
3V3
I/O
MMC/SDIO Data bit 3
F2
SD3_DATA4
eMMC_DATA4
3V3
I/O
MMC/SDIO Data bit 4
E2
SD3_DATA5
eMMC_DATA5
3V3
I/O
MMC/SDIO Data bit 5
C2
SD3_DATA6
eMMC_DATA6
3V3
I/O
MMC/SDIO Data bit 6
B1
SD3_DATA7
eMMC_DATA7
3V3
I/O
MMC/SDIO Data bit 7
E1
SD3_CMD
eMMC_CMD
3V3
I/O
MMC/SDIO Command
C1
SD3_CLK
eMMC_CLK
3V3
O
MMC/SDIO Clock
2.3. Memory
The PICO-IMX7 integrates Double Data Rate III (DDR3) Synchronous DRAM in a single (16 bit)
channel configuration.
The following memory chips have been validated and tested on the PICO-IMX7 Compute Module:
SKHynix
Samsung
ISSI
Micron
2.4. eMMC Storage
The PICO-IMX7 can be ordered with onboard eMMC storage in different configurations and capacity.
The onboard eMMC device is connected on the SD3 pins of the i.MX7 processor in an 8 bit width
configuration.
The following eMMC chips have been validated and tested on the PICO-IMX7 WiFi+Bluetooth 4.0(HS)
System no Module:
Sandisk iNAND
Kingston eMMC
Micron eMMC
Table 4 - eMMC Signal Description
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
2.5. WiFi/Bluetooth SIP Module
The SIP module radio architecture & high integration MAC/BB chip provide excellent sensitivity with
rich system performance.
In addition to WEP 64/128, WPA and TKIP, AES, CCX is supported to provide the latest security
requirement on your network.
The SiP module is designed to operate with a single antenna for WiFi and Bluetooth to be connected
to the u.FL connector available on the PICO-IMX7.
Matching antenna’s are available with all distributors. “SKU : ANT-P150-A1380-45D-2450-BK
Figure 10 - PICO-IMX7 WiFi Module and Antenna Location
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
i.MX7
BALL
PAD NAME
Signal
I/O
Description
E4
SD2_DATA0
SD2_DATA_0
I/O
MMC/SDIO Data bit 0
E5
SD2_DATA1
SD2_DATA_1
I/O
MMC/SDIO Data bit 1
F5
SD2_DATA2
SD2_DATA_2
I/O
MMC/SDIO Data bit 2
E6
SD2_DATA3
SD2_DATA_3
I/O
MMC/SDIO Data bit 3
F6
SD2_CMD
SD2_CMD
I/O
MMC/SDIO Command
E3
SD2_CLK
SD2_CLK
I/O
MMC/SDIO Clock
H5
ECSPI1_SS0
GPIO4_IO19
O
Host wake up. Signal from the module
to the host indicating that the module
requires Attention.
• Asserted: Host device must wake-up
or remain awake.
• Deserted: Host device may sleep
when sleep criteria are met.
The polarity of this signal is software
configurable and can be asserted high
or low.
H3
ECSPI1_SCLK
GPIO4_IO16
O
WiFi device wake-up: Signal from the
host to the module indicating that the
host requires attention.
• Asserted: WiFi device must wake-up
or remain awake.
• Deserted: WiFi device may sleep
when sleep criteria are met.
The polarity of this signal is software
configurable and can be asserted high
or low.
Table 5 - WiFi Signal Description
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PICO-PI-IMX7 HARDWARE MANUAL – REV B1 – APR 5 2017
i.MX7
BALL
PAD NAME
Signal
I/O
Description
G6
ECSPI2_MOSI
UART7_TXD
O
Bluetooth UART Serial Input. Serial
data input for the HCI UART Interface
J5
ECSPI2_SCLK
UART7_RXD
I
Bluetooth UART Serial Output. Serial
data output for the HCI UART Interface.
J6
EIM_ECSPI2_SS0
UART7_CTS
I/O
Bluetooth UART Clear to Send. Activelow clear-to-send signal for the HCI
UART interface.
H6
ECSPI2_MISO
UART7_RTS
I/O
Bluetooth UART Request to Send.
Active-low request-to-send signal for the
HCI UART interface.
E9
SAI2_RXD
AUD2_RXD
I
Integrated Interchip Sound (I2S) channel
receive data line
E8
SAI2_TXD
AUD2_TXD
O
Integrated Interchip Sound (I2S) channel
transmit data line
D8
SAI2_TXC
AUD2_TXC
O
Integrated Interchip Sound (I2S) channel
word clock signal
D9
SAI2_TXFS
AUD2_TXFS
O
Integrated Interchip Sound (I2S) channel
frame synchronization signal
H4
ECSPI1_MISO
GPIO4_IO18
O
Low asserting reset for BT core
G3
SD2_RESET_B
GPIO5_IO11
I
Host UART wake up. Signal from the
module to the host indicating that the
module requires Attention.
• Asserted: Host device must wake-up
or remain awake.
• Deserted: Host device may sleep
when sleep criteria are met.
The polarity of this signal is software
configurable and can be asserted high
or low.
G5
ECSPI1_MOSI
GPIO4_IO17
O
Bluetooth device wake-up: Signal from
the host to the module indicating that
the host requires attention.
• Asserted: Bluetooth device must
wake-up or remain awake.
• Deserted: Bluetooth device may sleep
when sleep criteria are met.
The polarity of this signal is software
configurable and can be asserted high
or low.
Table 6 - Bluetooth Signal Description
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