TDK Semiconductor Corporation 73M2910L Datasheet

73M2910L

Microcontroller

April 2000

DESCRIPTION

The 73M2910L high performance micro-controller is
based on the industry standard 8-bit 8032
implemented in an advanced submicron CMOS
process. The processor has the attributes of the
8032, including instruction cycle time, UART, timers,
interrupts, 256 bytes of on-chip RAM and
programmable I/O. The architecture has been
optimized for low power portable modem or
communication applications by integrating unique
features with the core CPU.

A key feature is a user friendly HDLC Packetizer,
accessed through the special function registers. It
has a serial I/O, hardware support for 16 and 32-bit
CRC, zero insert/delete control, a dedicated interrupt
and a clear channel mode for by-passing the
packetizer.

Other features include additional user programmable
I/O with programmable bank select and chip select
logic, designed to eliminate board level glue logic. It
also includes two general-purpose input ports with
programmable wakeup capability.

For devices that require non-multiplexed address
and data buses, eight latched outputs for the low
byte of the address are available.

(continued)

FEATURES

• 8032 compatible instruction set

• 44 MHz Operation from 3.3 to 5.5V

• HDLC support logic (Packetizer, 16 and 32

CRC, zero ID)

• 24 pins for user programmable I/O ports

• 8 pins programmable chip select logic or I/O

for memory mapped peripheral eliminating
glue logic

• 3 external interrupt sources (programmable

polarity)

• 16 dedicated latched address pins

• Multiplexed data/address bus

• Instruction cycle time identical to 8032

• Buffered oscillator (or OSC/2) output pin

• 1.8432 MHz UART clock available

• Bank select circuitry to support up to 128k of

external program memory

• Also available in 100-Lead QFP and 100-Pin

PGA packages

BLOCK DIAGRAM

USR 1.0
USR 1.1

USR 1.2

USR 1.3

PTXCLK

PRXCLK

RXD

TXD

PTXD

PRXD

(2:0)

INTERRUPT

CONTROL

TIMERS

UART

HDLC

SFR BUS

OSCIN

OSCOUT

CLKOUT1

CLKOUT2

TIME GEN

CPU MEM I/O CTRL

RAM 256 X 8

USR I/O

USR I/O

ADD/DATA IO

USR5 (1:0)

CSB (7:0)

USR3 (7:0)

USR2 (7:0)

USR1 (7:0)

ALE

A (15:0)

D (7:0)

73M2910L
Microcontroller

DESCRIPTION (continued)

The 73M2910L has two extra interrupt sources, an
external interrupt and a HDLC interrupt. The HDLC
interrupt has two registers associated with it; the
HDLC Interrupt Register which is used to determine
the source of the interrupt, and the HDLC Interrupt
Enable Register that enables the source of the
interrupt.

The state of the external interrupts can be read
through a register allowing the interrupt pins to be
used as inputs. The interrupt pins INT0 and INT1
can be either negative edge, positive edge or level
triggered. The INT2 pin is always edge triggered.

Two buffered clock outputs have been added to
support peripheral functions such as UARTs,
modems and other clocked devices. The main
internal processor clock frequency can be divided by
2 for power conservation in functional modes that
only require half the clock speed.

Additional internal special function registers are
used for firmware control over the HDLC Packetizer,
the clocks and the programmable I/O ports.

To accommodate processor peripherals when
operating at higher frequencies, the processor’s
timing has been altered to allow more address setup
time for slower peripheral program ROM and
memory mapped peripherals.

For low power applications the 73M2910L supports
two power conservation modes: idle and power-down.
In the power-down state the total current consumption
is less than 10 µA at room temperature.

DEVELOPER’S NOTE:

The 73M2910L is also available in a
100-Pin PGA package for system developers. The
PGA package is more convenient and reliable for
development emulation systems than the other
package styles. Emulation systems for the
73M2910L are available through Signum Systems,
11992 Challenger Court, Moorpark, CA 93021
[phone].

8032 REFERENCE

This Document will describe the features unique to
the 73M2910L. Please refer to a 8032 Programmer’s
Guide, Architectural Overview and Hardware
Description for details on the instruction set, timers,
UART, interrupt control, and memory structure.

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REGISTER DESCRIPTION

INTERRUPTS

The core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt,
and an HDLC interrupt. An external interrupt and an HDLC interrupt are unique to the 73M2910L. They do not
exist in a normal 8032 product. Previously unused bits in the IE and IP registers are now serving functions for
these additional interrupt sources. The interrupt vector addresses are as follows:

SOURCE VECTOR ADDRESS

INT) (IE0) 003H

TF0 00BH

INT! (IE1) 013H

TF1 01BH

RI + TI 023H

TF2 + EXF2 02BH

INT@ - ADDED INTERRUPT 033H

HDLC - ADDED INTERRUPT 03BH

The external interrupt sources, INT(2:0), come from dedicated input pins. The apparent polarity of these pins
is individually controlled by bits in a special interrupt direction register, IDIR (address A9). The interrupt pins

INT! and INT) can be either edge or level generated interrupts as indicated by bits 1 and 3 in the TCON

Register (address 88). Pin
(rising if IDIR bit 2 is set) on this pin is detected. This flag is automatically cleared when the interrupt is
processed.

INTERRUPT ENABLE REGISTER (IE) SFR ADDRESS 0A8h

Bit Addressable
Reset State 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

EA EX2 ET2 ES ET1 EX1 ET0 EX0

NOTE: Bit 6 differs from the 8032. This is a reserved bit in the 8032 and is used as a mask bit for external

interrupt 2 in the core implementation. When bit 6 is set to a 0, external interrupt 2 is disabled.

The mask bit for the HDLC interrupt source is bit 0 of the HDLC Control Register.

INTERRUPT PRIORITY REGISTER (IP) SFR ADDRESS 0B8h

Bit Addressable
Reset State 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

PHDLC PX2 PT2 PS PT1 PX1 PT0 PX0

INT@ is always an edge generated interrupt. A flag is set when a falling transition

NOTE: Bit 6 and bit 7 differ from the 8032. These are reserved bits in the 8032 and are used to determine

the priority of external interrupt 2 and the HDLC in the core implementation. When bit 6 is set to a 1,
the interrupt is set to the higher priority level.

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Microcontroller

INTERRUPTS

EXTERNAL INTERRUPT DIRECTION REGISTER (IDIR) SFR ADDRESS 092h

Byte Addressable
Reset State 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00INT@ INT! INT) INTD2 INTD1 INTD0

These bits determine the polarity of the corresponding external signals INT(2:0) which will result in an interrupt
and will also allow the user to directly read the logic level at the pads INT(2:0).

BITS (5:3) INT(2:0)

Bits (5:3) are read only bits that reflect the logic value at the corresponding pin. The value is not affected by
bits (2:0).

BITS (2:0) Interrupt Polarity Control

If the bit is set to a 0, a falling edge will trigger the interrupt. If the bit is set to a 1, a rising edge will trigger the
interrupt. Also, if the bit is set to a 1, level generated interrupts will occur when the corresponding pin is high
and the internal pin signal to the timer controls will be inverted.

Bits 6 and 7 will always be read as 0’s.

CLOCK CONTROL REGISTER SFR ADDRESS 0DAh

Byte Addressable
Reset State 00h

(continued)

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

Activity CLK1

CTRL1

These bits determine the behavior at the CLK1OUT and CLK2OUT pins and allow the user to divide the main
internal processor clock frequency by two for power conservation.

BIT 7

Bit 7 is an activity bit. It is cleared by a read of this register. If the activity bit is set it will prevent the
73M2910L from entering sleep mode.

BIT 6

When bit 6 = 1, CLK1OUT will be OSC/1.5 if bit 1 is a 1 and bit 0 is 0.

BIT 5 CLOCK OUT

0OSC
1OSC/2

BIT 5 Master Clock Control

When bit 5 is set to a 1 the internal processor clock is the oscillator frequency divided by 2. If this bit is a 0, the
processor clock is the same frequency as the oscillator’s.

MCLK

CTRL

CLK2EN CLK2

CTRL1

CLK2

CTRL0

CLK1EN CLK1

CTRL0

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Microcontroller

BIT 4 Clock 2 Output Enable

Bit 4 enables the clock at the CLOCK 2 output pin if it is set to a 1. The CLOCK 2 pin output is held to a 0, by
writing this bit to a 0. This will reduce system power if the clock pin is not used or if a power reduction mode is
required.

BITS 3,2 Clock 2 Output Control

These bits determine the oscillator divisor for the CLOCK 2 output pin. They were designed to provide a

1.8432 MHz clock for an external UART given an oscillator frequency of 11.0592 MHz, 22.1184 MHz,

18.432 MHz, or 13.824 MHz.

BIT 3 BIT 2 CLK 2 OUT OSC FREQUENCY

0 0 OSC/7.5 13.824 MHz

0 1 OSC/6 11.059 MHz

1 0 OSC/12 22.118 MHz

1 1 OSC/10 18.432 MHz

BIT 1 Clock 1 Output Enable

Bit 1 enables the clock at the clock 1 output pin if it is set to a 1. The clock pin output is held to a 0, by writing a
0 to this bit. This will reduce system power if the clock pin is not used or if a power reduction mode is required.

Bit 6 is cleared to a 0 upon a reset.

BIT 0 Clock 1 Output Control

Bit 0 controls the frequency of the clock 1 output pin. The clock output is either the oscillator’s output signal
divided by two or a buffered oscillator output signal.

POWER SAVING MODES

Low Power Modes

The 73M2910L supports two power conservation modes, which are controlled by the PCON.1 and PCON.0
control bits of the PCON Register.

If PCON.0 is set, the 73M2910L will go into a power saving mode where the oscillator is running, clocks are
supplied to the UART, timers, HDLC, and interrupt blocks, but no clocks are supplied to the CPU. Instruction
processing and activity on the address and data ports is halted. Normal operation is resumed when an
unmasked interrupt is requested or when a reset occurs.

If PCON.1 is set, the 73M2910L goes into its lowest power mode where the oscillator is halted. The total current
consumption in this state should be less than 10 µa. The 73M2910L will start its oscillator and begin to return to
normal operation when either a reset occurs, when a falling (rising if corresponding direction bit is set) edge of
an unmasked external interrupt from pins INT(2:0) is detected, or when the USR5 (1:0) pins change to a state
according to the USR5 port register. Edges used in wakeup modes are not filtered in the
73M2910L, so the user must be cautious of noise or small glitches inadvertently waking up the chip. From the
time the edge that results in the wake up occurs, to the point at which an instruction is executed, depends on
the oscillator start-up time. Three good oscillator pulses must be detected before the main internal clocks are
generated.

During power-down mode, both the ALE and PSEN pins are pulled high since these signals often provide the
output enable and chip enable for the ROM (active low). This ensures that the external components are in their
lowest power state.

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Microcontroller

REGISTER DESCRIPTION (continued)

USR PROGRAMMABLE I/O

Port Control USR1, USR2, USR3, USR4, USR5

The core chip provides 32 user I/O pins. Each pin is programmed separately as either an input or as an output
by a bit in a direction register. If the bit in the direction register is set to a 1, the I/O control will treat the
corresponding pin as an input. If it is a 0, the pin will be treated as an output whose value is determined by the
port data register. The USR1 and USR2 port registers are accessed through the internal SFR bus. The USR3
and USR4 ports are accessed through the external memory bus by a MOVX instruction. The USR4 port
provides the user with an automatic chip select function if selected by the user. If the user does not require
some (or any) of the chip select pin options, he may program the USR4 port pins to operate in the same way as
USR3 port pins.

The USR Data Register contents determine pin values if chosen as an output. When reading from the data
register’s SFR address, the pin logic values are returned as data except when the port address is the
destination address for a read-modify-write instruction. In this case, the latched register values are returned as
data. When reading data from a data register that is mapped in the external memory space, the pin values are
always returned as data.

The USR5 Register allows for 2 additional input pins. In normal operation these pins can be used as general
purpose inputs. In power-down mode, the user can program either rising or falling transitions or logical
combinations of these pins to wake up the chip.

USR 1 PORT

USR1 DATA SFR Address 90h

Bit Addressable
Reset State 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

USR1.7 USR1.6 USR1.5 USR1.4 USR1.3 USR1.2 USR1.1 USR1.0

Bits in this register will be asserted on the USR1(7:0) pins if the corresponding direction register bit is a 0.
Reading this SFR’s address will return data reflecting the values of pins USR1(7:0) except when address 90h is
the destination address for a read-modify-write instruction. In this case, the latched register values are returned
as data.

USR1 port signals are also used as timer controls. In applications where the external signals are required for
timer count modes, the corresponding port pin should be configured as an input.

USR1.0 bit = TIMER0 T0 PIN
USR1.1 bit = TIMER1 T1 PIN
USR1.2 bit = TIMER2 T2 EX PIN
USR1.3 bit = TIMER2 T2 PIN

USR1 Port Direction (DIR1) SFR Address 91h

Byte Addressable
Reset State FFh

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DIR1.7 DIR1.6 DIR1.5 DIR1.4 DIR1.3 DIR1.2 DIR1.1 DIR1.0

This register is used to designate the USR1 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR1 pin is programmed as an output that will be driven by the corresponding USR1 data
register bit. If the register bit is a 1, the corresponding pin will be treated as an input.

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Microcontroller

After a reset, the USR1 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 1 internally. The pins will assume normal I/O operation once the processor
has written the port direction register. This feature will ensure a low current state at reset
(you don’t want to drive out against external inputs, and you don’t want floating inputs).

USR2 PORT

USR2 Port Data SFR Address 0D8H

Bit Addressable
Reset State 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

USR2.7 USR2.6 USR2.5 USR2.4 USR2.3 USR2.2 USR2.1 USR2.0

Bits in this register will be asserted on the USR2(7:0) pins if the corresponding direction register bit is a 0.
Reading this SFR’s address will return data reflecting the values of pins USR2(7:0) except when address 0D8h
is the destination address for a read-modify-write instruction. In this case, the latched register values are
returned as data.

USR2 Port Direction (DIR2) SFR Address 0D9H

Byte Addressable
Reset State FFh

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DIR2.7 DIR2.6 DIR2.5 DIR2.4 DIR2.3 DIR2.2 DIR2.1 DIR2.0

This register is used to designate the USR2 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR2 pin is programmed as an output that will be driven by the corresponding USR2 I/O data
register bit. If the register bit is a 1, the corresponding pin will treated as an input.

After a reset, the USR2 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 1 internally. The pins will assume normal I/O operation once the processor
has written the port direction register. This feature will ensure a low current state at reset (you don’t want to
drive out against external inputs, and you don’t want floating inputs).

USR3 PORT

USR3 Port Data External address 0000h

Byte Addressable
Reset State 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

USR3.7 USR3.6 USR3.5 USR3.4 USR3.3 USR3.2 USR3.1 USR3.0

Bits in this register will be asserted on the USR3(7:0) pins if the corresponding direction register bit is a 0.
Reading this SFR’s address will return data reflecting the values of pins USR3(7:0).

If the bank select feature is chosen, the USR3.7 pin acts as address bit 17 and USR3 data bit 7 is ignored.

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73M2910L
Microcontroller

USR3 PORT

USR3 I/O Port Direction (DIR3) External Address 0001h

Byte Addressable
Reset State FFh

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DIR3.7 DIR3.6 DIR3.5 DIR3.4 DIR3.3 DIR3.2 DIR3.1 DIR3.0

This register is used to designate the USR3 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR3 pin is programmed as an output that will be driven by the corresponding USR3 data
register bit. If the register bit is a 1, the corresponding pin will be treated as an input.

After a reset, the USR3 pins will present a high impedance output state and the input values will not be driven
from the pin, but will be driven to a 1 internally. The pins will assume normal I/O operation once the processor
has written the USR3 port direction register. This feature will ensure a low current state at reset.

If the bank select feature is chosen, USR3.7 pin is forced to be an output.

BANK SELECT (BNKSEL) EXTERNAL ADDRESS 0002h

Byte Addressable
Reset State 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

B7 B6 B5 B4 B3 BSEN BS1 BS0

This register is used to accommodate systems where more than 64 kBytes (up to 128 kBytes) of program
memory are required. Pin USR3.7 acts as an address pin, A16, if BSEN is set to a 1 and the processor is
fetching an instruction and not data memory. If BSEN is set to a 1, A15 is also modified during instruction
fetches as shown below. If BSEN is a 0, no alterations to address bit A15 are made, and pin USR3.7 is a
function of USR3 bit 7 and DIR3 bit 7.

(continued)

Bits (7:3) are general purpose read/write register bits.

A15 Value of the 16th address bit as it appears at pin A15.

A15’ Address from port 2 internal logic, the value that will appear as the most significant address bit if no

bank select feature is chosen.

A16

Value of the 17th and MSB of the instruction address seen at the USR3.7 port pin, if the bank select
feature is selected. If the bank select feature is not selected, USR3.7 acts as a normal USR3 I/O port
pin.

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Microcontroller

BSEN BS1 BS0 A15’ A15 A16 ADDRESS

0

0

*

*

*

*

0

1

0

1

USR3.7

USR3.7

0K - 32K

32K - 64K

1

1

1

1

1

1

1

1

* = Don’t care

0

0

0

0

1

1

1

1

BANK 3

BANK 2

BANK 1

BANK 0

0

0

1

1

0

0

1

1

96K - 128K

64K - 96K

32K - 64K

0 - 32K

0

1

0

1

0

1

0

1

Example: Bank 2 is selected

BSEN = 1, BS1 = 0, BS0 = 1

Bank 2 is selected
If A15' is a 1, fetches will come from Bank 2
Bank 2 will overlay Bank 1

That is all fetches that would normally occur
from Bank 1 will come from Bank 2

0

1

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0K- 32K

32K - 64K

0K - 32K

64K - 96K

0K - 32K

96K- 128K

0K- 32K

64K - 96K

FIGURE 1: Bank Select

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73M2910L
Microcontroller

USR PROGRAMMABLE I/O

USR4 PORT

USR4 Port Data External Address 0003h

Byte Addressable
Reset State 00h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

USR4.7 USR4.6 USR4.5 USR4.4 USR4.3 USR4.2 USR4.1 USR4.0

Bits in this register will be asserted on the USR4(7:0) pins if the corresponding direction register bit is a 0 and if
the corresponding bit in the Chip Select Enable Register, 0005, is set to a 0. Reading this register will return
data reflecting the values of pins USR4(7:0).

USR4 I/O Port Direction (DIR4) External Address 0004h

Byte Addressable
Reset State FFh

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DIR4.7 DIR4.6 DIR4.5 DIR4.4 DIR4.3 DIR4.2 DIR4.1 DIR4.0

This register is used to designate the USR4 pins as either inputs or outputs. If the register bit is reset to a 0, the
corresponding USR4 pin is programmed as an output that will be driven by the corresponding USR4 I/O data
register bit if the corresponding bit in the Chip Select Enable Register, 0005, is set to a 0. If the register bit is a
1, the corresponding pin will treated as an input only if the corresponding bit in register 0005 is set to a 0.

After a reset, the USR4 pins will act as chip select outputs.

(continued)

USR4 Port Chip Select Enable (CSEN) External Address 0005h

Byte Addressable
Reset State FFh

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CSEN 7 CSEN 6 CSEN 5 CSEN 4 CSEN 3 CSEN 2 CSEN 1 CSEN 0

This register is used to designate the USR4 pins as either user programmable I/Os or as chip select
(CS0B - CS7B) functions on a pin by pin basis. This feature is designed to help reduce external glue logic for
peripheral memory mapped devices. The chip select function is programmed by setting the appropriate bits in
the CSEN Register. When a chip select pin is enabled by setting the corresponding CSEN bit to a 1, all data
and direction information from registers 0003 and 0004 for this bit are ignored and the selected port becomes
an output. If the bit is reset to a 0, the pin will be treated as a normal programmable user I/O pin as defined by
registers 0003 and 0004.

The chip select pins have a defined memory map. The intent is that the outputs can be wire OR’ed together for
a flexible selection of peripheral chip selects. All chip selects will be disabled (forced to a logic 1. It is assumed
that all chip selects are active low) after the read or write is completed, and the appropriate chip select will be
enabled as the next new external addresses is asserted. After a reset, the CSB pull-up devices are all enabled,
that is, all chip select outputs are high. Users must account for this if these pins are intended to be general
purpose I/Os.

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Microcontroller

The chip selects partition a 64K memory space as follows:

CHIP SELECT PIN ADDRESS # BYTES

RESERVED FOR INTERNAL USE 0000H - 00FFH 256

CS0 (USR4.0) 0100H - 01FFH 256

CS1 (USR4.1) 0200H - 03FFH 512

CS2 (USR4.2) 0400H - 07FFH 1K

CS3 (USR4.3) 0800H - 0FFFH 2K

CS4 (USR4.4) 1000H - 1FFFH 4K

CS5 (USR4.5) 2000H - 3FFFH 8K

CS6 (USR4.6) 4000H - 7FFFH 16K

CS7 (USR4.7) 8000H - FFFFH 32K

NOTE:External addresses 0000H-00FFH may not be read. These are reserved for 73M2910L internally defined

registers

USR5 PORT

USR5 Port Register External Address 0006h

Byte Addressable
Reset State 60h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

USR5EN USR5.0 USR5.1 POL5.0 POL5.1 ACTE0 ACTE1 AND01

This register allows user programmable wakeup capability. If this is not required, this register can be used to
read external signals at the USR5.1 and USR5.0 pins.

Bit 7 USR5 Input Port Enable

Bit 7 is used to enable the USR5.1 and USR5.0 input circuitry. If this bit is a 0, the USR5 pin output circuitry is
driven to a known level internally and any signal level at the pin is ignored. When set to a 1 the pin input
circuitry is enabled and the values of these pins are reflected in bits 6 and 7. If these pins are not connected at
the board level, this bit should remain at a 0 to keep the pin input circuitry from drawing unnecessary current.

The USR5 Register can be programmed such that a transition (bit 4 determines rising or falling) of USR5.0, a
transition (bit 3 determines rising or falling) of USR5.1, or the logical combination of USR5.0 (bit 4 determines
high or low level) AND USR5.1 (bit 3 determines high or low level) can wakeup the processor from its
power-down mode.

BIT 6 USR5.0

Bit 6 reflects the value of chip pin USR5.0 if the USR5EN bit is set to a 1.

BIT 5 USR5.1

Bit 5 reflects the value of chip pin USR5.1 if the USR5EN bit is set to a 1.

11