TDK Semiconductor Corporation 73K224BL-IH, 73K224BL-IGT Datasheet
DESCRIPTION
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
April 2000
FEATURES
The 73K224BL is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 bit/s full-duplex operation over dial-up lines.
The 73K224BL is an enhancement of the 73K224L
single-chip modem which adds the hybrid hook
switch control, and driver to the 73K224L. The
73K224BL integrates analog, digital, and switchedcapacitor array functions on a single chip, offering
excellent perform ance and a high level of func tional
integration in a 32-Lead PLCC and 44-Lead TQFP
package.
The 73K224BL operates from a single +5 V supply
for low power consumption.
The 73K224BL is des igned to appear to the s ystems
designer as a microprocessor peripheral, and will
easily interface with popular single-chip microprocessors (80C51 typical) for control of modem
functions through its 8-bit multiplexed address/data
bus or via an optional serial control bus. An ALE
control simplifies address demultiplexing. Data
communications normally occur through a separate
serial port.
(continued)
• Includes features of 73K224L single-chip
modem
• On chip 2-wire/4-wire hybrid driver and off
hook relay buffer driver
• One-chip multi-mode V.22bis/V.22/V.21 and
Bell 212A/103 compatible modem data pump
• FSK (300 bit/s), DPSK (600, 1200 bit/s), or
QAM (2400 bit/s) encoding
• Software compatible with other TDK
Semiconductor K-Series one-chip modems
• Interfaces directly with standard micro-
processors (80C51 typical)
• Parallel or serial bus for control
• Selectable internal buffer/debuffer and
scrambler/descrambler functions
• All asynchronous and synchronous
operating modes (internal, external, slave)
(continued)
BLOCK DIAGRAM
OH
8-BIT
µP
BUS
INTERFACE
TXD
RXD
SERIAL
INTERFACE
BUFFER SCRAMBLER
DEBUFFER DESCRAMBLER
DI-BIT/
QUAD-BIT
ENCODER
DI-BIT/
QUAD-BIT
DECODER
FSK
MODULATOR
FIR
PULSE
SHAPER
DIGITAL
SIGNAL
PROCESSOR
RECEIVE
FUNCTIONS
TONE
DETECTION
QAM/
DPSK
MODULATOR
FILTER
A/D
DEMODULATOR
DTMF,
ANSWER,
GUARD &
CALLING
TONE
GENERATOR
EQUALIZER FILTER FILTER
FILTEREQUALIZER
FIXED
AGC
ATTENUATOR
GAIN
BOOST
2W/4W
HYBRID
FILTER
TXA1
TXA2
RXA
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
DESCRIPTION (continued)
The 73K224BL is pi n and software com patible with
the 73K222BL, allowing system upgrades with a
single component change.
The 73K224BL is designed to be a complete
V.22bis compatible modem on a chip. The
complete modem requires only the additio n of the
phone line interface, a control microprocessor, and
RS-232 level conv erter for a typical s ystem. Many
functions were included t o simplif y implementation
of typical modem designs. In addition to t he basic
2400 bit/s QAM, 600/1200 bit/s DPSK and 300
bit/s FSK modulator/demodulator sections, the
device also includes synch/asynch converters,
scrambler/descram bler, call progress tone detect,
DTMF tone generator c apabilities and handshake
pattern detectors. Test features such as analog
loop, digital loop, and remote digital loopbac k are
supported. Internal pattern generators are also
included for self-testing.
FEATURES (continued)
• Adaptive equalization for optimum perform-
ance over all lines
• Programmable transmit attenuation (16 dB,
1 dB steps), selectable receive boost (+18
dB)
• Call progress, carrier, answer tone,
unscrambled mark, S1, and signal quality
monitors
• DTMF, answer and guard tone generators
• Test modes available: ALB, DL, RDL, mark,
space, alternating b it, S1 patte rn generatio n
and detection
• CMOS technology for low power
consumption (typically 100 mW @ 5 V) with
power-down mode (15 mW @ 5 V)
• TTL and CMOS compatible inputs and
outputs
FUNCTIONAL DESCRIPTION
HYBRID AND RELAY DRIVER
To make designs more cost effective and space
efficient, the 73K224BL includes the 2-wire to 4wire hybrid with sufficient drive to inter face direc tly
to the telecom coupling transformers. In addition,
an off hook relay driver with 30mA dr ive capability
is also included to allow use of commonly
available mechanical telecom relays.
QAM MODULATOR/DEMODULATOR
The 73K224BL encodes incom ing data into quadbits represented b y 16 possible signal points with
specific phase and amplitude levels. The baseband signal is then filtered to reduce intersymbol
interference on the band limited telephone
network. The modulator transmits this encoded
data using either a 1200 Hz (originate mode) or
2400 Hz (answer mode) carr ier. The demodulator ,
although more complex, essentially reverses this
procedure while also recovering the data clock
from the incoming signal. Adaptive equalization
corrects for varying line conditions by
automatically changing filter parameters to
compensate for line characteristics.
DPSK MODULATOR/DEMODULATOR
The 73K224BL modulates a ser ial bit stream into
di-bit pairs that are represented by four possible
phase shifts as prescribed by the Bell 21 2A/V.22
standards. The base-ba nd signal is then filtere d to
reduce intersymbol int er f erenc e on t he b andlimited
2-wire PSTN line. T ransm ission occur s on e ither a
1200 Hz (originate mode) or 2400 Hz carrier
(answer mode). Demodulation is the reverse of
the modulation proces s, with the incom ing analog
signal eventually decoded into di-bits and
converted back to a serial bit stream. The
demodulator also recovers the clock which was
encoded into the analo g signal during m odulation.
Demodulation occurs using either a 1200 Hz
carrier (answer m ode or ALB orig inate mode) or a
2400 Hz carrier (originate mode or ALB answer
mode). Adaptive equalization is also used in
DPSK modes for optimum operation with varying
line conditions.
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency
modulated analog output sig nal using two d iscrete
frequencies to repres ent the binary data. The Bell
103 standard frequencies of 1270 and 1070 Hz
2
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
FUNCTIONAL DESCRIPTION (continued)
(originate mark and space) and 22 25 and 202 5 H z
(answer mark and space) are used when this
mode is selected. V.21 mode us es 980 and 1180
Hz (originate, mark and space) or 1650 and 1850
Hz (answer, mark and space). Demodulation
involves detecting the received frequencies and
decoding them into the appropriate binary value.
The rate converter and scram bler/descr ambler are
automatically bypassed in the FS K m odes .
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phas e response of the transm it and
receive signals and provide compromise delay
equalization and rejection of out-of-band signals.
Amplitude and phase equalization are necessary
to compensate for distortion of the transmission
line and to reduc e intersymbol interferenc e in the
band limited receive signal. The transmit signal
filtering corresponds to a 75% square root of
raised Cosine frequency response characteristic.
ASYNCHRONOUS MODE
The asynchronous mode is used for communication
with asynchronous terminals which may
communicate at 600,1200, or 2400 bit/s +1%, -
2.5% even tho ugh the m odem’s out put is limited to
the nominal bit rate ±.01% in DPSK and QAM
modes. When transmitting in this mode the serial
data on the TXD input is passed through a rate
converter which inserts or deletes stop bits in the
serial bit str eam in order to output a signal that is
the nominal bit rate ±.01%. This signal is then
routed to a data scrambler and into the analog
modulator where quad-bit/di-bit encod ing results in
the output signal. Both the rate converter and
scrambler can be bypassed for handshaking, and
synchronous oper ation as selected . Received data
is processed in a similar fashion except that the rate
converter now acts t o reinsert any del eted stop bits
and output data to the terminal at no greater than
the bit rate plus 1%. An incoming break signal (low
through two characters) will be passed through
without incorrectly inse rting a stop bi t.
The synch/asynch converter also has an extended
overspeed mode which allows selection of an output
overspeed range of either +1% or +2.3%. In the
extended overspeed mode, s top b its are output at 7/8
rising edge of TXCLK the normal width.
Both the synch/asynch rate c onv erter a nd the data
descrambler are automatically bypassed in the
FSK modes.
SYNCHRONOUS MODE
Synchronous operation is possible only in the
QAM or DPSK modes . Operati on is sim ilar to that
of the asynchronous m ode except that data mus t
be synchronized to a provided clock and no
variation in data transf er rate is allowable. Serial
input data appearing a t TXD must be valid on the
rising edge of TXCLK.
TXCLK is an internally derived 1200 or 2400 Hz
signal in internal m ode and is conn ected int ernall y
to the RXCLK pin in slave mode. Rece ive data at
the RXD pin is clock ed out on the falling edge of
RXCLK. The asynch/synch converter is bypassed
when synchronous mode is selected and data is
transmitted at the same rate as it is input.
PARALLEL BUS CONTROL INTERFACE MODE
Eight 8-bit registers are provided for control, option
select, and status m onitoring. These reg isters are
addressed with the AD0, AD1, and AD2
multiplexed address lines (latched by ALE) and
appear to a control microprocessor as seven
consecutive memory locations. Six control
registers are read/write memory. The detect and
ID registers are read on ly and cannot be modified
except by modem response to monitored
parameters.
3
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
SERIAL CONTROL INTERFACE MODE
The serial Command mode allows access to the
73K224BL control and s tatus registers via a serial
control port. In this mode the AD0, AD1, and AD2
lines provide register addresses for data passed
through the AD7 (DAT A) pin under control of the
RD and WR lines. A read operation is initiated
when the RD line is taken low. The next eight
cycles of EXCLK wil l then transf er out eight bits of
the selected address location LSB first. A write
takes place by shifting in eight bits of data LSB
first for eight consec utive cycles of EXCLK. W R is
then pulsed low and data transf er in to the s elec ted
register occurs on the rising edge of WR.
DTMF GENERATOR
The DTMF generator controls the sending of the
sixteen standard DTMF tone pairs. The tone pair
sent is determined b y se lect ing trans m it DT MF (bit
D4) and the 4 DTMF bits (D0-D3) of the Tone
Register. Transmission of DTMF tones from TXA
is gated by the trans mit enable bit of CR0 (bit D1)
as with all other analog signals.
4
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
PIN DESCRIPTION
POWER
NAME PIN TYPE DESCRIPTION
GND 1 I System ground
VDD 16 I Power supply input, 5 V ±10% (73K224BL). Bypass with 0.1
and 22 µF capacitors to GND.
VREF 31 O An internally generated reference voltage. Bypass with
0.1 µF capacitor to ground.
ISET 28 I
PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE
ALE 13 I ADDRESS LATCH EN ABLE: T he f alling edg e of AL E latch es
AD0-AD7 5-12 I/O ADDRESS/DATA BUS: These bi-directional tri-state
CS
CLK 2 O OUTPUT CLOCK: This pin is selectable under processor
INT 20 O
RD 15 I READ: A low requests a read of the 73K224BL internal
RESET 30 I
23 I CHIP SELECT: A low on this pin during the falling edge of
Chip current reference. Sets bias current for op-amps. The
chip current is set by connect ing this pin to VDD through a
2 MΩ resistor. ISET should be bypassed to GND with a
0.1 µF capacitor.
the address on AD0-AD2 and the chip select on
multiplexed lines carry information to and from the internal
registers.
ALE allows a rea d cycle or a write c ycle to occur. AD 0-AD7
will not be driven and no registers will be written if
(latched) is not active. The state of CS is latched on the
falling edge of ALE.
control to be either the crystal frequency (for use as a
processor clock ) or 16 times the data rate f or use as a baud
rate clock in DPSK modes only. The pin defaults to the
crystal frequency on reset.
INTERRUPT: This open drain outpu t signal is use d to inform
the processor that a detec t flag has occurr ed. The process or
must then read the Detect Register to determine which detect
triggered the interrupt.
reads the detect register or does a full reset.
registers. Data can not be output unless both
latched
RESET: An active h igh sig nal on this pin will put the chip i nto
an inactive state. All Control Register bits (CR0, CR1, tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on-reset using a capacitor to VDD.
CS are active or low.
INT will stay low until the processor
CS.
RD and the
CS
5
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
PARALLEL MICROPROCESSOR INTERFACE (continued)
NAME PIN TYPE DESCRIPTION
WR 14 I WRITE: A low on this informs the 73K224BL that data is
available on AD0-AD7 for writing into an internal register.
Data is latched on the r ising edge of
unless both
SERIAL MICROPROCESSOR CONTROL INTERFACE MODE
NAME PIN TYPE DESCRIPTION
AD0-AD2 5-7 I REGISTER ADDRESS SELECTION: These lines carry
register addresses and should be valid during any read or
write operation.
DATA (AD7) 12 I/O
RD 15 I
WR
14 I WRITE: A low on this input informs the 73K224 BL that data
SERIAL CONTROL DATA: Data for a read/write o peration is
clocked in or out on th e falling edge of the EXCLK pin. The
direction of data flow is controlled by the
outputs data.
READ: A low on this input inf orm s the 73K2 24BL t hat dat a or
status information is being read b y the processor. The f alling
edge of the
register. The
of EXCLK in order to read all eight bits of the referenced
register. Read data is provided LSB first. Data will not be
output unless the
or status information has been sh ifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on the
DATA pin for eight cons ecutive falling edges of EXCLK and
then to pulse
WR.
WR and the latched CS are low.
RD high inputs data.
RD signal will initiate a re ad from the address ed
RD signal must c ontinue for eight falling edges
RD signal is active.
WR low. Data is wr itten on the rising edge of
WR. No data is written
RD pin. RD low
NOTE: The serial co ntr ol mode is provided by tying ALE hi gh a nd CS l ow. In this conf igurat ion AD7 bec om es
DATA and AD0, AD1 and AD2 become the register address.
6
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
DTE USER
NAME PIN TYPE DESCRIPTION
EXCLK 22 I EXTERNAL CLOCK: This signal is used in synchronous
transmission when the external timing option has been
selected. In the external timing mode the rising edge of
EXCLK is used to strobe synchronous DPSK transmit data
applied to on the TXD pin. Also used for serial control
interface.
RXCLK 26 O
RXD 25 O RECEIVED D ATA OUTPUT: Serial receive dat a is available
TXCLK 21 O TRANSMIT CLOCK: This signal is used in synchronous
TXD 24 I TRANSMIT DATA INPUT: Serial data for transmission is
.
RECEIVE CLOCK: The falling edge of this clock output is
coincident with the transitions in the serial received data
output. The rising edge of RXCLK can be used to latch the
valid output data. RX CLK will be v alid as long as a carrier is
present.
on this pin. The data is always valid on the rising edge of
RXCLK when in synchronous mode. RXD will output
constant marks if no carrier is detected.
transmission to latch s erial input data on the TXD pin. Data
must be provided so tha t valid data is available on the rising
edge of the TXCLK. The transmit clock is derived from
different sources depend ing upon the synchronizat ion mode
selection. In intern al mode the clock is generated internally.
In external mode TXCLK is phas e locked to the EXCLK pin.
In slave mode TXCLK is phase locked to the RXCLK pin.
TXCLK is always active.
applied on this pin. I n synchronous modes, the d ata must be
valid on the risin g ed ge of the TXCLK clock. In as ync hr ono us
modes (1200/600 bit/s or 300 baud) no clocking is
necessary. DPSK data must be 1200/600 bit/s +1%, -2.5% or
+2.3%, -2.5 % in extended over speed mode.
7
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
PIN DESCRIPTION (continued)
ANALOG INTERFACE AND OSCILLATOR
NAME PIN TYPE DESCRIPTION
RXA 32 I
TXA1 / TXA2 18 / 17 O Tr ansmit Analog (diff er ential out puts ): These pins pr o vid e t he
XTL1 / XTL2 3 / 4 I These pins are for the internal crystal oscillator requiring a
OH
.
27 O OFF-HOOK RELAY DRIVER: This signal is an open drain
Received modulated a nalog signal input from the tele phone
line interface.
analog output signals to be transm itted to the tel ephone line .
The drivers will d ifferentially drive the im pedance of the line
transformer and the li ne matching resistor. An external hybrid
can also be built using TXA1 as a single ended transmit
signal.
11.0592 MHz parallel mode crystal. Load capacitors should
be connected from XT L1 and X TL2 to ground. X TL2 can also
be driven from an external clock.
output capable of sinking 30mA and is used fo r controlling a
relay. The output is the complem ent of the OH reg ister bit in
the ID Register.
8
REGISTER ADDRESS TABLE
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
ADDRESS
AD2 - AD0REGISTER
CONTROL
REGISTER
CONTROL
REGISTER
DETECT
REGISTER
READ ONLY
TONE
CONTROL
REGISTER
CONTROL
REGISTER
CONTROL
REGISTER
SPECIAL
REGISTER
REGISTER
READ ONLY
00XX=73K212AL, 322L, 321L
01XX=73K221AL, 302L
10XX=73K222AL, 222BL
1100=73K224L, 224BL
1110=73K324L, 324BL
CR0
0
CR1
1
DR
TR
CR2 100 0
2
CR3 101 TXDALT
3
SR 101 0
ID
10 110 1 1 0 0XXXX
D7 D6 D5 D4 D3 D2 D1 D0
MODULATION
000
001
010
011
OPTION
QAM: 0 = 2400 BIT/S
DPSK: 0=1200 BIT/S
1 = 600 BIT/S
FSK: 0 = 103 MODE
1 = V.21
TRANSMIT
PATTERN
1
00 = TX DATA
01 = TX ALTERNATE
(DOTTING)
10 = TX MARK
11 = TX SPACE
RECEIVE
LEVEL
INDICATOR
0=SIGNAL
BELOW
THRESHOLD
1=ABOVE
THRESHOLD
RXD
OUTPUT
CONTROL
RXD PIN
0 = NORMAL
1 = OPEN
ALTERNATE
TRANSMIT
DATA
SOURCE
0 = Only write zeros to these locations
X = Undefined, mask in software
MODULATION
TYPE
1
10=QA,
00=DPSK
01=FSK
TRANSMIT
PATTERN
0
S1
PATTERN
DETECT
0=NOT PRESENT
1=PATTERN
FOUND
TRANSMIT
GUARD/
TONE
0 = OFF
1 = ON
SPECIAL
REGISTER
ACCESS
0=ACCESS CR3
1=ACCESS
SPECIAL
REGISTER
TRISTATE
TX/RXCLK
0=NORMAL
1=TRISTATE
TX BAUD
CLOCK
OUTPUTS
TXBAUD
CLOCK
MODULATION
TYPE
0
0000 = PWR DOWN
0001 = INT SYNCH
0010 = EXT SYNCH
0011 = SLAVE SYNCH
0100 = ASYNCH 8 BITS/CHAR
0101 = ASYNCH 9 BITS/CHAR
0110 = ASYNCH 10 BITS/CHAR
0111 = ASYNCH 11 BITS/CHAR
1X00 = FSK
ENABLE
DETECT
INTERRUPT
0 = DISABLE
1 = ENABLE
RECEIVE
DATA
OUTPUTS
RECEIVED
DATA STREAM
TRANSMIT
ANSWER
TONE
0 = OFF
1 = ON
CALL
INTIALIZE
0=DSP IN
DEMOD MODE
1=DSP IN CALL
PROGRESS
MODE
OH
0=OH RELAY
DRIVER OPEN
1=OH OPEN
DRAIN
DRIVER PULLING
LOW
RX UNSCR.
DATA
OUTPUTS
UNSCR.
DATA
DATA BIT NUMBER
TRANSMIT
MODE
2
BYPASS
SCRAMBLER
0 = NORMAL
1 = BYPASS
SCRAMBLER
UNSCR.
MARKS
DETECT
TRANSMIT
DTMF
0 = DATA
CARRIER
1=TX DTMF
TRANSMIT
S1
0=NORMAL
DOTTING
1=S1
RECEIVE
GAIN
BOOST
0=NO BOOST
1=18 dB BOOST
0
TRANSMIT
MODE
CLK
CONTROL
0 = XTAL
1 = 16 X DATA
RATE OUTPUT
AT CLK PIN IN
QAM/DPSK MODE
ONLY
CARRIER
DETECT
0 = CONDITION NOT DETECTED
1 = CONDITION DETECTED
DTMF3
16 WAY
0=RX=TX
1=RX=16WAY
TX=4WAY
IN DPSK
TRANSMIT
ATTEN.
TXD
SOURCE
0=TXD PIN
1=TXALT BIT
TRANSMIT
1
3
MODE
0
RESET
0 = NORMAL
1 = RESET
ANSWER
TONE
DETECT
DTMF2/
4W/FDX
4 BIT CODE FOR 1 OF 16
DUAL TONE COMBINATIONS
RESET
RESET
RESETRESET
DSP
0=DSP
INACTIVE
1=DSP
ACTIVE
TRANSMIT
ATTEN.
2
0000-1111,SETS
TRANSMIT ATTENUATOR
16 dB RANGE
DEFAULT=0100 -10 dBm0
SQ
SELECT 1
00 10-5 BER
01 10-6 BER
10 10-4 BER
11 10-3 BER
0 = DISABLE
TXA OUTPUT
1 = ENABLE
TXA OUTPUT
0=ADAPT EQ
ACTIVE
1=ADAPT EQ
FROZEN
TRANSMIT
ENABLE
TEST
MODE
1
00 = NORMAL
01 = ANALOG LOOPBACK
10 = REMOTE DIGITAL
LOOPBACK
11 = LOCAL DIGITAL
LOOPBACK
CP
TONE
DETECT
DTMF1/
EXTENDED
OVERSPEED
0 = 1800 Hz G.T.
2225 Hz ANNS TONE
GENERATED
1 = 550 Hz ANS TONE
2100 Hz ANS TONE
GENERATED &
DETECTED (V.21, V.22)
TRAIN
INHIBIT
TRANSMIT
ATTEN.
1
SQ
SELECT 0
ORIGINATE/
ANSWER
0 = ANSWER
1 = ORIGINATE
TEST
MODE
0
SIGNAL
QUALITY
INDICATOR
0=GOOD
1=BAD
DTMF0/
GUARD/
ANSWER
EQUALIZER
ENABLE
0=ADAPT EQ
IN RESET STATE
1=ADAPT EQ
ACTIVE
TRANSMIT
ATTEN.
0
0
9
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
CONTROL REGISTER 0
CR0 D7 D6 D5 D4 D3 D2 D1 D0
ADDR
000
BIT NAME CONDITION DESCRIPTION
D0 Answer/ 0 Selects answer mode (transmit in high band, receive
D1 Transmit 0 Disables transmit output at TXA1 & TXA2
D5,D4 Transmit D5 D4 D3 D2
D3,D2 Mode 0 0 0 0 Selects Power down mode. All functions disabled except
D6,D5 Modulation D6 D5
MODUL.
OPTION
MODUL.
TYPE 1
Originate in low band).
Enable 1 Enables transmit output at TXA1 & TXA2
Type 1 0 QAM
MODUL.
TYPE 0
0 0 0 1
0 0 1 0
0 0 1 1 Slave synchronous mode Same operation as other
0 1 0 0 Selects a synchronous mode 8 bits/character (1 start bit,
0 1 0 1 Selects asynchronous mode - 9 bits/character (1 start bit,
0 1 1 0 Selects asynchronous mode - 10 bits/character (1 start
0 1 1 1 Selects asynchronous mode - 11 bits/character (1 start
1 X 0 0 Selects FSK operation.
TRANSMIT
MODE 2
1
0 0 DPSK
0 1 FSK
TRANSMIT
MODE 1
Selects originate m ode (transmit in low ban d, receive in
high band).
Note: Transmit enable must be set to 1 to allow
activation of answer tone or DTMF.
digital interface..
Internal synchronous mode in this mode TXCLK is an
internally derived 600,1200 or 2400 Hz signal. Serial
input data appearing a t TXD must be valid on the rising
edge of TXCLK. Receive data is clocked out of RXD on
the falling edge of RXCLK.
External synchronous mode. Operation is identical to
internal synchronous , but TXCLK is connected interna lly
to EXCLK pin, and a 600, 1200 or 2400 Hz clock must be
supplied externally.
synchronous modes TXCLK is connected internally to
the RXCLK pin in this mode.
6 data bits, 1 stop bit).
7 data bits, 1 stop bit).
bit, 8 data bits, 1 stop bit).
bit, 8 data bits, 1 stop bit) or 2 stop bits)..
TRANSMIT
MODE 0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
10
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