TDK Semiconductor Corporation 73K222BL-IH, 73K222BL-IGT Datasheet

DESCRIPTION

73K222BL

V.22, V.21, Bell 212A, Bell 103 Single-Chip

Modem with Integrated Hybrid

April 2000

FEATURES

The 73K222BL is a highly integrated single-chip
modem IC which provides the functions needed to
construct a CCITT V.22, V.21, Bell 212A and Bell
103, compatible modem, capable of 1200 bit/s full­duplex operation over dial-up lines. The 73K222BL
is an enhancement of the 73K222AL single-chip
modem which adds the hybrid hook switch control,
and driver to the 73K222AL. In Bell 212A mode, the
73K222BL provides the normal Bell 212A and Bell
103 functions and employs a 2225 Hz answer tone.
The 73K222BL in V.22 mode produces either 550 or
1800 Hz guard tone, recognizes and generates a
2100 Hz answer tone, and allows 600 bit/s V.22 or
0-300 bit/s V.21 operation. The device integrates
analog, digital, and switched-capacitor array
functions on a single substrate, offering excellent
performance and a high level of functional
integration in a 32-Lead PLCC and 44-Lead TQFP
package. It operates from a single +5 V supply.

The 73K222BL includes the DPSK and FSK
modulator/demodulator functions, call progress and
handshake tone monitor and a tone generator
capable of tones required for European applications.
This device supports V.22 (except mode v) and V. 21
modes of operation, allowing both synchronous and
asynchronous communication. Test features such as
analog loop, digital loop, and remote digital loopback
are supported. Internal pattern generators are also
included for self-testing.

(continued)

• Includes features of 73K222AL single-chip

modem

• One-chip CCITT V.22, V.21, Bell 212A and Bell

103 standard compatible modem data pump

• Full-duplex operation at 0-300 bit/s (FSK) or

600 and 1200 bit/s (DPSK)

• On chip 2-wire/4-wire hybrid driver and off-

hook relay buffer driver

• Serial or parallel microcontroller control

interface

• Interfaces directly with standard

microcontroller (8048, 80C51 typical)

• Serial port for data transfer

• Both synchronous and asynchronous modes

of operation including V.22 extended
overspeed

• Call progress, carrier, precise answer tone

(2100 or 2225 Hz), and long loop detectors

• DTMF, and 550 or 1800 Hz guard tone

generators

• Test modes available: ALB, DL, RDL, Mark,

Space, Alternating bit patterns

• Precise automatic gain control allows 45 dB

dynamic range

• CMOS technology for low power consumption

using 60 mW @ 5 V

• Single +5 V supply

BLOCK DIAGRAM

RD
WR

ALE

CS

RESET

INT

TXD

RXD

AD0-AD7

DATA

BUS

BUFFER

READ

WRITE

CONTROL

LOGIC

STATUS

AND

CONTROL

LOGIC

8-BIT

BUS

FOR

CONTROL

AND

STATUS

SERIAL

PORT

FOR

DATA

RXCLK

DIGITAL

PROCESSING

TESTS:

ALB, DLB

RDLB

PATTERNS

CLOCK

GENERATOR

CLK

EXCLK

TXCLK

XTL1

XTL2

FSK

MODULATOR/

DEMODULATOR

PSK

MODULATOR/

DEMODULATOR

SMART

DIALING

&

DETECT

FUNCTIONS

POWER

VDD

GND

ISET

VREF

DTMF &

TONE

GENERATORS

TRANSMIT

FILTER

RECEIVE

FILTER

2W/4W

HYBRID

OH

TXA1

TXA2

RXA

73K222BL
V.22, V.21, Bell 212A, Bell 103
Single-Chip Modem with Integrated Hybrid

DESCRIPTION (continued)

The 73K222BL is designed to appear to the systems
designer as a microprocessor peripheral, and will
easily interface with popular one-chip
microprocessors (80C51 typical) for control of
modem functions through its 8-bit multiplexed
address/data bus. An ALE control line simplifies
address demultiplexing. Data communications
occurs through a separate serial port only.

The 73K222BL is ideal for use in either free standing
or integral system modem products where full­duplex 1200 bit/s data communications over the 2­wire switched telephone network is desired. Its high
functionality, low power consumption and efficient
packaging simplify design requirements and
increase system reliability. A complete modem
requires only the addition of the phone line interface,
a control microprocessor, and RS-232 level
converter for a typical system.

The 73K222BL is part of TDK Semiconductor’s
K-Series family of single-chip modem products.
These devices allow systems to be configured for
higher speeds and Bell or CCITT operation with only
a single component change.

FUNCTIONAL DESCRIPTION

HYBRID AND RELAY DRIVER

To make designs more cost effective and space
efficient, the 73K222BL includes the 2-wire to 4-wire
hybrid with sufficient drive to interface directly to the
telecom coupling transformers. In addition, an off
hook relay driver with 40 mA drive capability is also
included to allow use of commonly available
mechanical telecom relays.

ASYNCHRONOUS MODE

Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous
fashion. The 73K222BL includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data within a ±0.01% rate. In
asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided
on the TXD pin which normally must be 1200 or 600
bit/s +1.0%, -2.5%. The converter will then insert or
delete stop bits in order to output a signal which is
1200 or 600 bit/s ± 0.01% (± 0.01% is required
synchronous data rate accuracy).

The serial data stream from the ASYNC/SYNC
converter is passed through the data scrambler and
onto the analog modulator. The data scrambler can
be bypassed under processor control when
unscrambled data must be transmitted. The
ASYNC/SYNC converter and the data scrambler are
bypassed in all FSK modes. If serial input data
contains a break signal through one character
(including start and stop bits) the break will be
extended to at least 2 • N + 3 bits long (where N is
the number of transmitted bits/character).

2

73K222BL

V.22, V.21, Bell 212A, Bell 103

Single-Chip Modem with Integrated Hybrid

Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC converter. The SYNC/ASYNC
converter will re-insert any deleted stop bits and
transmit output data at an intra-character rate (bit-to­bit timing) of no greater than 1219 bit/s. An incoming
break signal (low through two characters) will be
passed through without incorrectly inserting a stop bit.

The SYNC/ASYNC converter also has an extended
overspeed mode which allows selection of an
overspeed range of either +1% or +2.3%. In the
extended overspeed mode, stop bits are output at
7/8 the normal width.

SYNCHRONOUS MODE

The CCITT V.22 standard defines synchronous
operation at 600 and 1200 bit/s. The Bell 212A
standard defines synchronous operation only at
1200 bit/s. Operation is similar to that of the
asynchronous mode except that data must be
synchronized to a provided clock and no variation in
data transfer rate is allowable. Serial input data
appearing at TXD must be valid on the rising edge of
TXCLK.

TXCLK is an internally derived signal in internal
mode and is connected internally to the RXCLK pin
in slave mode. Receive data at the RXD pin is
clocked out on the falling edge of RXCLK. The
ASYNCH/SYNCH converter is bypassed when
synchronous mode is selected and data is
transmitted out at the same rate as it is input.

DPSK MODULATOR/DEMODULATOR

The 73K222BL modulates a serial bit stream into
di-bit pairs that are represented by four possible
phase shifts as prescribed by the Bell 212A or V.22
standards. The baseband signal is then filtered to
reduce intersymbol interference on the bandlimited
2-wire telephone line. Transmission occurs using
either a 1200 Hz (originate mode) or 2400 Hz carrier
(answer mode). Demodulation is the reverse of the
modulation process, with the incoming analog signal

eventually decoded into di-bits and converted back
to a serial bit stream. The demodulator also recovers
the clock which was encoded into the analog signal
during modulation. Demodulation occurs using either
a 1200 Hz carrier (answer mode or ALB originate
mode) or a 2400 Hz carrier (originate mode or ALB
answer mode). The device uses a phase locked loop
coherent demodulation technique for optimum
receiver performance.

FSK MODULATOR/DEMODULATOR

The FSK modulator produces a frequency
modulated analog output signal using two discrete
frequencies to represent the binary data. In Bell 103,
the standard frequencies of 1270 and 1070 Hz
(originate, mark and space) or 2225 and 2025 Hz
(answer, mark and space) are used. V.21 mode
uses 980 and 1180 Hz (originate, mark and space),
or 1650 and 1850Hz (answer, mark and space).
Demodulation involves detecting the received
frequencies and decoding them into the appropriate
binary value. The rate converter and
scrambler/descrambler are bypassed in the Bell 103
or V.21 modes.

PASSBAND FILTERS AND EQUALIZERS

High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay
equalization and rejection of out-of-band signals in
the receive channel. Amplitude and phase
equalization are necessary to compensate for
distortion of the transmission line and to reduce
intersymbol interference in the bandlimited receive
signal. The transmit signal filtering approximates a
75% square root of raised Cosine frequency
response characteristic.

AGC

The automatic gain control maintains a signal level
at the input to the demodulators which is constant
to within 1 dB. It corrects quickly for increases in
signal which would cause clipping and provides a
total receiver dynamic range of > 45 dB.

(continued)

3

73K222BL
V.22, V.21, Bell 212A, Bell 103
Single-Chip Modem with Integrated Hybrid

FUNCTIONAL DESCRIPTION (continued)

PARALLEL BUS INTERFACE

Four 8-bit registers are provided for control, option
select and status monitoring. These registers are
addressed with the AD0, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations.
Two control registers and the tone register are
read/write memory. The detect register is read only and
cannot be modified except by modem response to
monitored parameters.

SPECIAL DETECT CIRCUITRY

The special detect circuitry monitors the received
analog signal to determine status or presence of carrier,
call-progress tones, answer tone and weak received
signal (long loop condition). An unscrambled mark
request signal is also detected when the received data
out of the DPSK demodulator before the descrambler
has been high for 165.5 ms ± 6.5 ms minimum. The
appropriate detect register bit is set when one of these
conditions changes and an interrupt is generated for all
purposes except long loop. The interrupts are disabled
(masked) when the enable interrupt bit is set to 0.

DTMF GENERATOR

The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone register.
Tone generation is initiated when the DTMF mode is
selected using the tone register and the transmit enable
(CR0 bit D1) is changed from 0 to 1.

4

73K222BL

V.22, V.21, Bell 212A, Bell 103

Single-Chip Modem with Integrated Hybrid

PIN DESCRIPTION

POWER

NAME PIN TYPE DESCRIPTION

GND 1 I System Ground

VDD 16 I Power supply input, 5 V ±10%. Bypass with 0.1 and 22 µF capacitors to

GND.

VREF 31 O An internally generated reference voltage. Bypass with 0.1 µF capacitor

to ground.

ISET 28 I Chip current reference. Sets bias current for op-amps. The chip current is

set by connecting this pin to VDD through a 2 MΩ resistor. ISET should
be bypassed to GND with a 0.1 µF capacitor.

PARALLEL CONTROL INTERFACE

ALE 13 I Address latch enable. The falling edge of ALE latches the address on

AD0-AD2 and the chip select on

AD0-AD7 5-12 I/O

Tristate

CS 23 I Chip select. A low on this pin during the falling edge of ALE allows a read

CLK 2 O Output clock. This pin is selectable under processor control to be either

INT 20 O Interrupt. This open drain output signal is used to inform the processor

RD 15 I Read. A low requests a read of the 73K222BL internal registers. Data

RESET 30

I/with

Pulldown

Address/data bus. These bi-directional tri-state multiplexed lines carry
information to and from the internal registers.

cycle or a write cycle to occur. AD0-AD7 will not be driven and no
registers will be written if
latched on the falling edge of ALE.

the crystal frequency (for use as a processor clock) or 16 times the data
rate for use as a baud rate clock in DPSK modes only. The pin defaults
to the crystal frequency on reset.

that a detect flag has occurred. The processor must then read the detect
register to determine which detect triggered the interrupt.
until the processor reads the detect register or does a full reset.

cannot be output unless both

Reset. An active high signal on this pin will put the chip into an inactive
state. All control register bits (CR0, CR1, Tone) will be reset. The output
of the CLK pin will be set to the crystal frequency. An internal pull-down
resistor permits power-on-reset using a capacitor to VDD.

CS.

CS (latched) is not active. The state of CS is

INT will stay low

RD and the latched CS are active or low.

5

73K222BL
V.22, V.21, Bell 212A, Bell 103
Single-Chip Modem with Integrated Hybrid

PARALLEL CONTROL INTERFACE

NAME PIN TYPE DESCRIPTION

WR 14 I Write. A low on this pin informs the 73K222BL that data is available on

SERIAL CONTROL INTERFACE

NAME PIN TYPE DESCRIPTION

AD0-AD2 5-7 I Register Address Selection. These lines carry register addresses and

DATA (AD7) 12 I/O Serial Control Data. Data for a read/write operation is clocked in or out on

RD 15 I Read. A low on this input informs the 73K222BL that data or status

(continued)

AD0-AD7 for writing into an internal register. Data is latched on the rising
edge of
low.

should be valid during any read or write operation.

the falling edge of the EXCLK pin. The direction of data flow is controlled
by the

information is being read by the processor. The falling edge of the
signal will initiate a read from the addressed register. The RD signal must
continue fort eight falling edges of EXCLK in order to read all eight bits of
the referenced register. Read data is provided LSB first. Data will not be
output unless the

WR. No data is written unless both WR and the latched CS are

RD pin. RD low outputs data. RD high inputs data.

RD signal is active.

RD

WR

NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes

DATA and AD0, AD1 and AD2 become the address only.

14 I Write. A low on this input informs the 73K222BL that data or status

information has been shifted in through the DATA pin and is available for
writing to an internal register. The normal procedure for a write is to shift
in data LSB first on the DATA pin for eight consecutive falling edges of
EXCLK and then to pulse

WR.

WR low. Data is written on the rising edge of

6

Single-Chip Modem with Integrated Hybrid

DTE USER

NAME PIN TYPE DESCRIPTION

73K222BL

V.22, V.21, Bell 212A, Bell 103

EXCLK 22 I

RXCLK 26 O

RXD 25 O/

Weak

Pull-up

TXCLK 21 O Transmit Clock. This signal is used in synchronous transmission to latch

TXD 24 I Transmit Data Input. Serial data for transmission is applied on this pin.

External Clock. This signal is used in synchronous transmission when the
external timing option has been selected. In the external timing mode the
rising edge of EXCLK is used to strobe synchronous DPSK transmit data
applied to on the TXD pin. Also used for serial control interface.

Receive Clock. The falling edge of this clock output is coincident with the
transitions in the serial received data output. The rising edge of RXCLK
can be used to latch the valid output data. RXCLK will be valid as long as
a carrier is present.

Received Data Output. Serial receive data is available on this pin. The
data is always valid on the rising edge of RXCLK when in synchronous
mode. RXD will output constant marks if no carrier is detected.

serial input data on the TXD pin. Data must be provided so that valid data
is available on the rising edge of the TXCLK. The transmit clock is derived
from different sources depending upon the synchronization mode
selection. In internal mode the clock is generated internally. In external
mode TXCLK is phase locked to the EXCLK pin. In slave mode TXCLK is
phase locked to the RXCLK pin. TXCLK is always active.

In synchronous modes, the data must be valid on the rising edge of the
TXCLK clock. In asynchronous modes (1200/600 bit/s or 300 baud) no
clocking is necessary. DPSK data must be 1200/600 bit/s +1%, -2.5%
or +2.3%, -2.5 % in extended over speed mode.

ANALOG INTERFACE AND OSCILLATOR

NAME PIN TYPE DESCRIPTION

RXA 32 I Received modulated analog signal input from the telephone line

interface.

TXA1
TXA2

XTL1
XTL2

OH 27 O

18
17

3
4

O Transmit analog output to the telephone line interface.

I
I

These pins are for the internal crystal oscillator requiring a 11.0592
MHz parallel mode crystal. Load capacitors should be connected from
XTL1 and XTL2 to ground. XTL2 can also be driven from an external
clock.

Off-hook relay driver. This signal is an open drain output capable of
sinking 40 mA and is used for controlling a relay. The output is the
complement of the OH register bit in the ID Register.

7

73K222BL
V.22, V.21, Bell 212A, Bell 103
Single-Chip Modem with Integrated Hybrid

REGISTER DESCRIPTIONS

Four 8-bit internal registers are accessible for
control and status monitoring. The registers are
accessed in read or write operations by
addressing AD0, AD1 and AD2 lines. The address
lines are latched by ALE. Register CR0 controls
the method by which data is transferred over the
phone line. CR1 controls the interface between the
microprocessor and the 73K222BL internal state.

REGISTER BIT SUMMARY

ADDRESS

CONTROL
REGISTER

0

CONTROL
REGISTER

1

CR0

CR1

AD2 - AD0REGISTER

000

001

D7 D6 D5 D4 D3 D2 D1 D0

MODULATION

OPTION

0 = 1200 BIT/S DPSK
1 = 600 BIT/S DPSK
0 = BELL 103 FSK
1 = V.21 FSK

TRANSMIT

PATTERN

1

0

TRANSMIT

PATTERN

0

TRANSMIT

MODE

ENABLE
DETECT

INTERRUPT

DR is the Detect Register which provides an
indication of monitored modem status conditions.
TR, the Tone Control Register, controls the DTMF
generator, answer and guard tones and RXD
output gate used in the modem initial connect
sequence. All registers are read/write except for
DR which is read only. Register control and status
bits are identified below:

DATA BIT NUMBER

TRANSMIT

3

0000 = PWR DOWN
0001 = INT SYNCH
0010 = EXT SYNCH
0011 = SLAVE SYNCH
0100 = ASYNCH 8 BITS/CHAR
0101 = ASYNCH 9 BITS/CHAR
0110 = ASYNCH 10 BITS/CHAR
0111 = ASYNCH 11 BITS/CHAR
1100 = FSK

MODE

2

BYPASS

SCRAMBLER

TRANSMIT

MODE

1

CLK

CONTROL

TRANSMIT

MODE

0

RESET

TRANSMIT

ENABLE

0 = DISABLE
TXA OUTPUT
1 = ENABLE
TXA OUTPUT

TEST

MODE

1

ORIGINATE/

ANSWER

0 = ANSWER
1 = ORIGINATE

TEST

MODE

0

00 = NORMAL
01 = ANALOG LOOPBACK
10 = REMOTE DIGITAL
LOOPBACK
11 = LOCAL DIGITAL
LOOPBACK

CALL

PROGRESS

DTMF1/

OVERSPEED

0 = 2225 Hz A.T.
1800 Hz G.T.
1 = 2100 Hz A.T.
500 Hz G.T.

LONG

LOOP

DTMF0/
GUARD/

ANSWER/

TONE

DETECT
REGISTER

TONE
CONTROL
REGISTER

ID
REGISTER

00XX = 73K212AL, 322L, 321L
01XX = 73K221AL, 302L
10XX = 73K222AL, 222BL
1100 = 73K224L, 224BL
1110 = 73K324L, 324BL

DR

TR

10 110 1 0 X OH

00 = TX DATA
01 = TX ALTERNATE
10 = TX MARK
11 = TX SPACE

010

RXD

011

OUTPUT

CONTROL

RXD PIN
0 = NORMAL
1 = WEAK PULL-UP

X = Undefined, mask in software 0 = OH Relay driver open

XX

TRANSMIT

GUARD/

TONE

0 = OFF
1 = ON

0 = DISABLE
1 = ENABLE

RECEIVE

DATA

OUTPUTS
RECEIVED
DATA STREAM

TRANSMIT

ANSWER

TONE

0 = OFF
1 = ON

0 = NORMAL
1 = BYPASS
SCRAMBLER

UNSCR.
MARKS

TRANSMIT

DTMF

0 = Disable DTMF
1 = TX DTMF

0 = XTAL
1 = 16 X DATA
RATE OUTPUT
AT CLK PIN IN
DPSK MODE
ONLY

CARRIER

DETECT

XX XX

1 = OH Open drain driver pulling low

0 = NORMAL
1 = RESET

0 = CONDITION NOT DETECTED
1 = CONDITION DETECTED

4 BIT CODE FOR 1 OF 16
DUAL TONE COMBINATIONS

ANSWER

TONE

DTMF2DTMF3

NOTE: When a register containing reserved control bits is written into, the reserved bits must be

programmed as 0's.

X = Undefined, mask in software

8