TDK Semiconductor Corporation 5504-CGT Datasheet
DESCRIPTION
The 5504 is a low cost, high performance direct
conversion receiver (DCR) specifically designed for
digital wireless applications. The DCR architecture
provides a receiver design with fewer external
components than the conventional dual conversion
approach. The 5504 is designed to operate over an
input frequency range of 950 to 2150 MHz. The
device accepts an input signal in this frequency
range and down converts directly to baseband. The
local oscillator signal is generated by a completely
integrated phase lock loop that is fully
programmable through a standard serial port
interface.
5504 DCR
Direct Conversion Receiver
Advanced Information
April 2000
FEATURES
• Wideband I/Q demodulator
– RF input 950 to 2150 MHz
– External lowpass filter
- Integrated post-filter baseband drivers
• Integrated VCO and frequency synthesizer
• AGC Amplifier
APPLICATIONS
• Digital Satellite
• VSAT Receivers
BLOCK DIAGRAM
AGC
XTLP
FILN
EON
Rext
RFp
RFn
Dclk
Din
1
A
P
V
Serial
Osc.XTLN
Port
Xtal
a
b
a
b
1
3
3
5
5
4
A
A
A
A
A
P
P
P
P
V
V
R3 R2 R1
Divide
10-bit
C1 C0
Charge
Pump
P
V
Power
Splitter
R0
V
V
6
A
D
P
P
V
V
Phase
Detect
Divide
11-bit
216 26
.............
2
D
1
2
P
P
P
V
T
T
0
90
25 20
.............
Modulo
6-bit
Div
32/33
S
N
V
1
1
n
O
i
O
I
b
a
1
3
3
A
A
A
N
N
N
V
V
V
n
i
Q
Q
I
IO2
QO2
VCO1
VCO0
RSHP
RSHN
VCO
RSLP
RSLN
a
b
5
4
A
A
N
N
V
V
1
6
6
D
A
A
N
N
N
V
V
V
1
5504 DCR
Direct Conversion Receiver
FUNCTIONAL DESCRIPTION
AGC Amplifier
The 5504 RF input can be driven differentially or
single ended. The RFp and RFn inputs are selfbiasing and are designed to be driven from a 50
Ohm source. For single-ended operation, the RFn
pin should be AC coupled to analog ground. A gain
control input, AGC, provides a 25 dB gain variation
with 0V providing minimum gain and 4V providing
maximum gain.
I/Q Mixer
BB835
Vtune
10 kΩ
12pF
12pF
10 kΩ
L2 L2
47 Ω
L1
L1
+5
47 Ω
29
High
28
32
Low
C1
33
5503
The AGC amplifier drives the RF port of two identical
double balanced mixers. The LO ports of these
mixers are driven from an on-chip quadrature
network.
Low Pass Filtering and Buffering
Following each mixer, a buffer amplifier is provided
for driving an external passive low-pass filter. The
nominal output impedance for IO1 and Q01 is 50
ohms. A second high impedance buffer amplifier is
provided (IIN or QIN) for additional gain and isolation
after the filter. The figure below shows a typical filter
designed for 20 Megasymbol per second operation:
0.1 F
IO1/QO1
680nH470nH
12pF
68pF68pF
IIN/QIN
Dual VCO
The 5504 uses two VCOs to cover the entire
specified tuning range. Both VCOs use nearly
identical architecture with the only difference being
slight design modifications to optimize the range of
operation. The lower range VCO requires an
external resonator that supports a tuning range of
950 to 1473 MHz. The higher range VCO requires a
similar resonator with inductor values designed to
support the range of 1390 to 2150 MHz. A typical
lumped-element resonator circuit incorporating
varactor tuning is shown in the following figure:
Note: A separate resonator circuit is required for
each oscillator
PLL Synthesizer
The synthesizer derives its reference from a source
which can be either an externally derived clock or an
external crystal coupled to the internal oscillator.
This source drives a programmable reference divider
with 15 preset divide ratios from 2 to 320. This
divider output provides the PLL reference by driving
one input of a phase/frequency detector. The VCO
output drives a divider chain incorporating a variable
modulus prescaler and divider. The divider is
programmed by a 17-bit control word. This divider
chain output drives the other input of the
phase/frequency detector.
Loop Filter
The phase/frequency detector interface consists of
two ports, FILN and EON. The EON drives the base
of an external NPN transistor, and the FILN provides
a feedback path for the loop filter elements. The
external transistor permits VCO tune voltages of
greater than 30V and also provides the final stage of
the loop amplifier. Below is shown a typical loop
filter:
+28V
FILN
EON
1000pF
10 k
10 kW
0.1 F
Vtune
Q1
2
5504 DCR
Direct Conversion Receiver
DUAL VCO
RSLP32RSHN
LOW
LOW PASS
FILTER
LOW PASS
FILTER
QO1
IO1
21
14
HIGH
RESONATOR
QIN
23
29 26
IIN
18
RSHP
TP1C TP2C
43
44
37
39
FILN
EON
PLL
LOOP
FILTER
Rxt
24
17 IO2
22 QO2
VNS
12
VNA4
41
VNA5b
9
VNA5a
8
7.68k
DEMOD/FEC
ADC
ADC
+5V
VPA3b AGC
LNA
PIN
ATTEN.
VPA3a
VPA1
VPD2
VPD1
XTALP 46
XTALN
DIN
DCLK
31 42
30
15
2
3
RFP
7
RFN
VND1 VNA1
AGC
6
AMP
XTAL
45
OSC
47
48
119
VPA4 VPA5a VPA5b
11
PLL SYNTH.
SHIFT REGISTER/
RAM
25 36
VNA3a
45
QUAD
GEN
35
RSLN
VNA3b
RESONATOR
DCR Application Drawing
3
5504 DCR
Direct Conversion Receiver
PIN DESCRIPTIONS
ANALOG PINS
NAME TYPE DESCRIPTION
RFP, RFN I RF inputs: balanced differential inputs to the receiver. The input signals placed on this
line are amplified with a variable gain amplifier before being passed to the I/Q
demodulator.
AGC I Automatic gain control input. A voltage from 0 to 4 volts on this pin varies the input
amplifier gain from minimum to maximum. The gain increase is 25 dB typical
Eon, Filn I/O
XTLP, XTLN I Reference crystal input. An external crystal connected between these pins
IO2, QO2 O Baseband outputs. These typically drive an A/D converter prior to digital
IO1, QO1 O I and Q channel outputs to external low pass filter. An external series resistor can be
IIN, QIN I I and Q channel inputs from external low pass filter. These are high impedance inputs
Rxt I External reference resistor. This resistor is connected to ground and must be 7.68k
RSHP, RSHN I High range VCO resonator inputs
RSLP, RSLN I Low range VCO resonator inputs
External loop filter interface. Eon drives the base of an external common emitter
transistor. Filn is the feedback input from the loop filter capacitor.
establishes the reference frequency for the PLL synthesizer. Following this oscillator is
a programmable divider that establishes the synthesizer step size.
demodulation and processing.
connected between this output and the filter to provide the source match.
(>5000Ω). The low pass filter must be designed for low input and high output
impedance.
±1%. It is used as a reference for internal bias currents.
DIGITAL PINS
Din I/O I2C data. This signal is connected to the I2C internal block. An external resistor
(typically 2.2 k
Dclk I
I2C clock Input. Dclk should nominally be a square wave with a maximum frequency
of 400kHz. SCL is generated by the system I2C master.
Ω) is connected between Din and Vcc for proper operation
4
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