Product Description: T260XW02 TFT-LCD PANEL with ROHS Guarantee
AUO Model Name: T260XW02 VM
Customer Part No/Project Name:
Customer Signature Date AUO 2008/03/31
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Document Version: 0.1
Date: 2008/3/31
Product Specifications
26.0” WXGA Color TFT-LCD Module
Model Name: T260XW02 VM
() Preliminary Specifications
(*) Final Specifications
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Contents
No
1
2
3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
4
ITEM
COVER
CONTENTS
RECORD OF REVISIONS
GENERAL DESCRIPTION
ABSOLUTION MAXIMUM RATINGS
ELECTRICAL SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
INTERFACE CONNECTIONS
SIGNAL TIMING SPECIFICATIONS
SIGNAL TIMING WAVEFORMS
COLOR INPUT DATA REFERENCE
POWER SEQUENCE for LCD
POWER SEQUENCE for INVERTER
OPTICAL SPECIFICATIONS
5
5-1
5-2
6
7
7-1
7-2
7-3
8
9
MECHANICAL CHARACTERISTICS
Front view
Rear view
RELIABILITY
INTERNATIONAL STANDARDS
SAFETY
EMC
Green
PACKING
PRECAUTIONS
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Record of Revision
Version Date No Old Description New Description Remark
0.0
0.1
2008 /
1/7
2008 /
3/31
First release
Electrical Characteristics
LCD Power Consumption: 4.8W
Electrical Characteristics
LCD Power Consumption: 5.04W
Final Spec
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1. General Description
This specification applies to the 26.0 inch Color TFT-LCD Module T260XW02. This LCD module
has a TFT active matrix type liquid crystal panel 1366x768 pixels, and diagonal size of 26.0 inch.
This module supports 1366x768 XGA-WIDE mode (Non-interlace).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 8-bit gray scale
signal for each dot.
The T260XW02 has been designed to apply the 8-bit 1 channel LVDS interface method. It is
intended to support displays where high brightness, wide viewing angle, high color saturation, and
high color depth are very important.
* General Information
Items Specification Unit Note
Active Screen Size
Display Area
Pixel Pitch
Outline Dimension
Driver Element
Display Colors
Number of Pixels
Pixel Arrangement
Display Mode
BL Structure
Surface Treatment
Green
26.0
575.769 (H) x 323.712(V)
0.4215 mm
626.0 (H) x 373.0 (V) x
47.2(D)
a-Si TFT active matrix
16.7M
1366 x 768
RGB vertical stripe
Normally Black
6 U-Lamps
AG, Haze=11%, 3H
RoHS compliance
inches
mm
mm With inverter
Colors
Pixel
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2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to
the unit.
Item Symbol Min Max Unit Condition
s
Logic/LCD Drive Voltage
LVDS Option Control Voltage
BLU Input Voltage
External Analog Dimming Control
Voltage
On/Off Control Voltage
Internal PWM Dimming Control
Voltage
Operating Temperature
Operating Humidity
Storage Temperature
Storage Humidity
VCC -0.3 13.2 [Volt] Note 1
V
LVDSOPT
-0.3 3.6 [Volt] Note 1
VDDB -0.3 27.0 [Volt] Note 1
VDIM -0.3 6.0 [Volt] Note 1
VBLON -0.3 6.0 [Volt] Note 1
VDIM -0.3 6.0 [Volt] Note 1
TOP 0 +50 [oC] Note 2
HOP 10 90 [%RH] Note 2
TST -20 +60 [oC] Note 2
HST 10 90 [%RH] Note 2
Note 1: Duration = 1 sec
Note 2: Maximum Wet-Bulb should be 39℃ and No condensation.
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Input High Threshold
Differential Input Low Threshold
s
µ
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3. Electrical Specification
The T260XW02 requires two power inputs. One is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second input power for the BLU is to power inverter.
3-1 Electrical Characteristics
Parameter
Symbol
Min. Typ. Max.
Values
Unit Notes
LCD:
Power Supply Input Voltage Vcc 10.8
Power Supply Input Current Icc - 0.42
Power Consumption Pc - 5.04
Inrush Current I
- - 3.0 A 2
RUSH
12 13.2
A 1
Watt 1
V
LVDS Interface:
Differential
Voltage
Voltage
Common Input Voltage VCIM 1.10 1.25 1.40
VTH +100
VTL -100
mV
mV
V
CMOS Interface:
Input High Threshold Voltage VIH(High) 2.4 3.3 Vdc
Input Low Threshold Voltage VIL(Low)
Backlight Power Consumption - - 79.4
Life Time 50,000 60,000
0 0.7 Vdc
Watt 3
Hours
4
Note :
1. Vcc=12.0V, Fv=60Hz, Fclk= 85.0 MHz , 25℃. , Test Pattern : White Pattern
2. Vcc rising time = 470
3.
VDDB=24V, VDIM=3.3V, PDIM=100%, test in the whole period from VDDB power on to power off.
4. The performance of the Lamp in LCM, for example: lifetime or brightness, is extremely influenced by the
characteristics of the DC-AC Inverter. So all the parameters of an inverter should be carefully designed so as
not to produce too much leakage current from high-voltage output of the inverter. When you design or order
the inverter, please make sure unwanted lighting caused by the mismatch of the lamp and the inverter (no
lighting, flicker, etc) never occurs. When you confirm it, the LCD Assembly should be operated in the same
condition as installed in your instrument.
5. Do not attach a conducting tape to lamp connecting wire. If the lamp wire attach to conducting tape, TFT-LCD
Module have a low luminance and the inverter has abnormal action because leakage current occurs between
lamp wire and conducting tape.
6. The relative humidity must not exceed 80% non-condensing at temperatures of 40℃ or less. At temperatures
greater than 40
brightness of CCFL will drop and the lifetime of CCFL will be reduced.
℃
, Vcc=12.0V
, the wet bulb temperature must not exceed 39℃. When operate at low temperatures, the
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3-2 Interface Connections
LCD connector (CN1): Starconn 093G30-B0001A-1
Note:
1. All GND (ground) pins should be connected together and should also be connected to the LCD’s metal frame. All
Vcc (power input) pins should be connected together.
Pin No
1 VCC +12V, DC, Regulated
2 VCC +12V, DC, Regulated
3 VCC +12V, DC, Regulated
4 VCC +12V, DC, Regulated
5 GND Ground and Signal Return
6 GND Ground and Signal Return
7 GND Ground and Signal Return
8 GND Ground and Signal Return
9 LVDS Option Low/Open for Normal (NS), High for JEIDA
10 Reserved Open or High
11 GND Ground and Signal Return for LVDS
12 RIN0- LVDS Channel 0 negative
13 RIN0+ LVDS Channel 0 positive
14 GND Ground and Signal Return for LVDS
15 RIN1- LVDS Channel 1 negative
16 RIN1+ LVDS Channel 1 positive
17 GND Ground and Signal Return for LVDS
18 RIN2- LVDS Channel 2 negative
19 RIN2+ LVDS Channel 2 positive
20 GND Ground and Signal Return for LVDS
21 RCLK- LVDS Clock negative
22 RCLK+ LVDS Clock positive
23 GND Ground and Signal Return for LVDS
24 RIN3- LVDS Channel 3 negative
25 RIN3+ LVDS Channel 3 positive
26 GND Ground and Signal Return for LVDS
27 Reserved Open or High
28 Reserved Open or High
29 GND Ground and Signal Return
30 GND Ground and Signal Return
Symbol Description Default
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LVDS Option = H (3.3V) JETDA Format
Previous CycleCurrent CycleNext Cycle
Clock
RIN0+
RIN0-
RIN1+
RIN1-
RIN2+
RIN2-
RIN3+
RIN3-
G7
LVDS Option = L (GND) or N.C. NS Format
Previous CycleCurrent CycleNext Cycle
Clock
R2R7G2G2R2R3R4R5R6R3
G3B2B3B3G3G4G5G6G4
B4NADEDEB4B5B6B7NAB5
R0B1NANAR0R1G0G1B0R1
RIN0+
RIN0-
RIN1+
RIN1-
RIN2+
RIN2-
RIN3+
RIN3-
R0R5G0G0R0R1R2R3R4R1
G1B0B1B1G1G2G3G4G5G2
B2NADEDEB2B3B4B5NA
B3
R6B7NANAR6R7G6G7B6R7
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