TCL LCD20V8NTR Schematic

5

GM21 LCD TV

4

3

2

1

D D

C C

CONTENTS

SCHEMATIC

01. Contents

02. Input

03. GM5221

04.SPI/RESET/KEYPAD

05. TTL_ Out

06. Power

07. Video Decoder

08. Nicam

SHEET

1
2
3
4
5
6
7
8

B B

Approval

A A

SignatureOrganization

Date

CHY 04-05-17

5

4

3

2

1

5

DVI INPUT
CONNECTOR

CN1

25

Shell

1

RX2-

2

RX2+

3

GND

4

RX4-

5

RX4+

6

SCL

7

SDA

8

VS

D D

26

GND

9

RX1-

10

RX1+

11

GND

12

RX3-

13

RX3+

14

5V

15

GND

16

HP

17

RX0-

18

RX0+

19

GND

20

RX5-

21

RX5+

22

GND

23

RXC+

24

RXC-

C1

RED

C2

GRN

C3

BLU

C4

HS

C5

GND

Shell

DVI-I

C C

BAT54C

VGA_5V

A1

EDID VGA

U2

VCCA0

2

A1A2WP

3

SCL

4

GND

SDA

24AA02

GND

ANALOG DDC

B B

A A

+5V

D5

A2

C

5V_VGA

C2

0.1uF

81

GND

7
6
5

GND

GND

GND

DNP

R15

47K

P1

3 4

GND2 SIG2

1 2

GND1 SIG1

COMPONENT

RX1+IN

+5V

GND

R16
2K7

SIG3GND3

DVI_SCL
DVI_SDA

DVI_5V

HOT_PLUG

D6

3

BAV99

1 2

65

R1 10K

+5V

D4

3

BAV99

1 2

GND

R17 100R

R18 100R

C220

0.1UF

GND

FB1

21

FB2

21

FB3

21

+5V

D3

3

BAV99

1 2

GND

VGASCL
VGASDA

VGA_SCL

VGA_SDA

+5V

D7

3

BAV99

1 2

GND GND

A-VS

R30
10K

GNDGND

A-PB

A-PR

A-Y

DVI_SCL

DVI_SDA

3

3

GND

15
14
13
12
11

+5V

BAV99

1 2

+5V

1 2

GND

DB15 HD
D8

R23 20R

R31
10K

YPrPB Video In

D1

BAV99

R4 100R
R6 100R

R12 10K

R13 0R

CN2

5
10
4
9
3
8
2
7
1
6

1%

1%

4

3

2

DVI test points right on the trace to avoid extra length

RX2- 5
RX2+ 5

RX1- 5
RX1+ 5

RX0- 5
RX0+ 5

RXC+ 5
RXC- 5

BAT54C

D2

A2

5V_DV

C

R3
2K7

U1

VCCA0

A1A2WP

SCL

GND

SDA

24AA02

DIGITAL DDC

VGACON

VGA_5V

VGA RGB In

R1982

R2082

GND

GND

GND

A-Y

GND

A-GREEN

A-PB

GND

+5V

81
7
6
5

R32

R49

GND

R2182

10uF/16V

82

10uF/16V

10uF/16V

82

DVI For
DVI Port

DVISCL
DVISDA

C1

0.1uF

GND

+5V_MUX

SEL_RGB3

R24

Q1

22k

C11

BC847c

12

1

R33

10k

R42

Q4

22k

C15

BC847c

1

12

R45

10k

GND

R47

Q6

22k

C17

BC847c

1

12

R50

10k

2 3

+5V_MUX

2 3

+5V_MUX

2 3

Y/G

R29

1k

GND

R37

Pb/B

1k

GND

R5 22R
R7 22R

R10 100R
R11 100R

1

IN

2

SA1

3

SA2

4

DA

5

SB1

6

SB2

7

DB

8

GND

13-PI5V33-0QB

GND

U3

PI5V330

2 3

BC847c

DDC_SCL_DVI 5
DDC_SDA_DVI 5

NOT TO BE MOUNTED

+5V

R8

R9

10K

10K

+5V_MUX

L1

33R FB

+

C4

C5 0.01uF

+5V_MUX

16

VCC

15

EN

14

SD1

GND

13

SD2

Pr/R

12

DD

11

SC1

10

SC2

R34

9

DC

1k

GND

+5V_MUX

R46

22k

A-BLUE

1

1 2

Q5

C16

10uF/16V

10k

R48

GND

10uF

GND

2 3

Q2

BC847c

1

+5V_MUX

2 3

Q3

R35

10k

BC847c

1

R26
22k

C13

1 2

10uF/16V

82

R36

R41

22k

C14

1 2

10uF/16V

R43

10k

GND

Pr/R

R22 47R 1%

Y/G

R25 47R 1%

Pb/B

R28 47R 1%

A-PR

GND

A-RED

R3884.5 1%

R3984.5 1%

GND GND GND

R4084.5 1%

DDC_SCL_VGA 5
DDC_SDA_VGA 5

C3 0.01uF

C6 0.01uF
C7 0.01uF

C8 0.01uF
C9 0.01uF

C10 0.01uFR27 20R
C12 0.01uF

DVI_5V

A1

R2

2K7

EDID DVI

2
3
4

GND

R14
10K

A-BLUE
A-GREEN
A-RED

GND

Near VGA pins

HSYNC 5

VSYNC 5 BLUE+ 5

1

DVI SIGNAL GND's at 2mm from the respective DVI

test points

MUXED RGB
TO 5221ADC
INPUT

SOG_MCSS 5

RED+ 5
RED- 5

GREEN+ 5
GREEN- 5

BLUE- 5

5

4

3

2

1

5

+3.3V_AVDD

D D

C C

B B

A A

L2

33R FB

+1.8V_DVDD

RMADDR[6:0]

RMADDR[12:7]
RMADDR[14:13]

RMADDR15

RMADDR16

RMADDR17

3.3V_AVDD

C18

C19

22uF/16V

0.1uF

GND

+3.3V_DVDD 3.3V_DVDD

L3

33R FB

CVDD_1.8

L4

33R FB

L5

33R FB

BootStrap Signals

HSYNC3

C38
22uF/16V

GND

AVDD_1.8

C48
22uF/16V

GND

For I2C address [6:0] to JTAG bridge
Host I/F, to determine device address.

User_Bits[5:0] for configuration setting
OP_MODE[1:0]:

00 = Normal op. UART in 186 on system pins.
01 = I2C to JTAG bridge.
10 = JTAG port, 5 wires
11 = External parallel control bus using
ROM Addr/Data

SPI_EN: 0 = parallel ROM I/F. 1 = SPI
serial ROM and Cache control

Initial state of OCM ROM:
0 = internal ROM on, and mapped to top 32K
of OCM and OCM boot will be from internal
ROM codes.

1 = Internal ROM off. The external ROM
mapped to entire upper 512K of OCM address.
OCM boot from external ROM code.

OSC_SEL: 0 = Xtal and internal oscillator.
1 = TTL oscillator (on TCLK pin)

VGAHS

5

Close to respective power Pins

C20

0.1uF

C21

0.1uF

C22

0.1uF

C23

0.1uF

Close to respective power Pins

C30

0.1uF

C31

0.1uF

C29
22uF/16V

GND

Close to respective power Pins

C40

0.1uF

1
2

3
4

11
10

74LCX14

C50

0.1uF

1
2

3
4

11
10

C41

0.1uF

3.3V_AVDD

U5

14

14

7

7

GND

C39

0.1uF

C49

0.1uF

C24

0.1uF

C32

0.1uF

C42

C43

0.1uF

0.1uF

C52

C51

0.1uF

0.1uF

13

13

12

12

8

8

9

9

6

6

5

5

C26

C25

0.1uF

0.1uF

C33

C34

0.1uF

0.1uF

C44

0.1uF

Close to respective power Pins

C53

0.1uF

VGAVS

VSYNC
3

4

C28

C27

0.1uF

0.1uF

Close to respective power Pins

C35

0.1uF

C45

C46

0.1uF

C54

0.1uF

C47

220pF

220pF

C55
220pF

3.3V_AVDD

C58
5pF

14.318MHz

BOOTSTRAP OPTIONS SELECT
(NOT POPULATED SHOULD BE
HARD WIRED)

+5V

4

3

3.3V_DVDD

3.3V_AVDD

C36

C37

0.1uF

0.1uF

+5V

R5110K

R5210K

J1

GPROBE

OR40R

RMDATA[0..7]

RS232

GND

DDC_SCL_VGA
DDC_SDA_VGA
DDC_SCL_DVI
DDC_SDA_DVI

R56 10K
R59 10K

VCC

OE

WE

CE

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

GND

1
2
3
4

RESET

32
24

31
22

21
20
19
18
17
15
14
13

16

TCLK
XTAL

3.3V_AVDD

DEBUG
PORT

ADC_TEST

RX2+
RX2­RX1+
RX1­RX0+
RX0­RXC+
RXC-

R53 250/1%

RMADDR17
RMADDR16
RMADDR15
RMADDR14
RMADDR13
RMADDR12
RMADDR11
RMADDR10
RMADDR9
RMADDR8
RMADDR7
RMADDR6
RMADDR5
RMADDR4
RMADDR3
RMADDR2
RMADDR1
RMADDR0

RMDATA7
RMDATA6
RMDATA5
RMDATA4
RMDATA3
RMDATA2
RMDATA1
RMDATA0

+5V

C62

0.1uF

GND

RMDATA7
RMDATA6
RMDATA5
RMDATA4
RMDATA3
RMDATA2
RMDATA1
RMDATA0

GND

TP10

TP11

ROM_OEn
ROM_WEn
ROM_CSn

HOST_SDA/UART_DO
HOST_SCL/UART_DI
DDC_SCL_VGA

GND GND

T2

1
2

RMADDR8

DDC_SDA_VGA

SW1
SW PUSHBUTTON

For_Update

C57

0.1uF

RMADDR17

RMADDR16
RMADDR15
RMADDR14
RMADDR13
RMADDR12
RMADDR11
RMADDR10
RMADDR9
RMADDR8
RMADDR7
RMADDR6
RMADDR5
RMADDR4
RMADDR3
RMADDR2
RMADDR1
RMADDR0

TP14 VP

OR30R

OR20R

OR10R

DDC_SCL_VGA3
DDC_SDA_VGA3
DDC_SCL_DVI3
DDC_SDA_DVI3

BLUE+3
BLUE-3
SOG_MCSS3
GREEN+3
GREEN-3
RED+3
RED-3

VGAHS
VGAVS

RX2+3
RX2-3
RX1+3
RX1-3
RX0+3
RX0-3
RXC+3
RXC-3

+5V

U6

30

2

3
29
28

4
25
23
26
27

5

6

7

8

9
10
11
12

1

AT49HF/F010-45JC

32-Pin PLCC Socket

NC/A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

NC

3

JTAG
DEBUG
I2C SEL

3.3V_AVDD

C59

X1

5pF

TCLK

XTAL

10KR54

RMADDR0

10KR55

RMADDR1

10KR57

RMADDR2

10KR58

RMADDR3

10KR60

RMADDR4

10KR61

RMADDR5

10KR62

RMADDR6

10KR63

RMADDR7

10KR64
10KR65

RMADDR9

10KR66

RMADDR10

10KR67

RMADDR11

10KR68

RMADDR12

10KR69

RMADDR13

10KR70

RMADDR14

10KR71

RMADDR15

10KR72

RMADDR16

10KR73

RMADDR17

U4

AVDD_OUT_LV_E_33

24

AVDD_OUT_LV_E_33

26

AVDD_LV_33

27

AVDD_OUT_LV_O_33

40

AVDD_OUT_LV_O_33

113

AVDD_IMB_33

120

AVDD_RX2_33

125

AVDD_RX1_33

130

AVDD_RX0_33

134

AVDD_RXC_33

141

AVDD_BLUE_33

145

AVDD_GREEN_33

150

AVDD_RED_33

154

AVDD_ADC_33

172

LBADC_VDD_33

171

AVDD_RPLL_33

12

AVSS_OUT_LV_E

23

AVSS_OUT_LV_E
AVSS_LV

28

AVSS_OUT_LV_O

39

AVSS_OUT_LV_O

115

AGND_IMB

117

AGND_RX2

122

AGND_RX1

127

AGND_RX0

131

AGND_RXC

144

AGND_BLUE

149

AGND_GREEN

153

AGND_RED

156

AGND_ADC

168

AGND_RPLL

177

LBADC_GND

136

GND_RXPLL

GND

170

TCLK

169

XTAL

71

HOST_SCL/UART_DI

72

HOST_SDA/UART_DO

77

DDC_SCL_VGA

78

DDC_SDA_VGA

79

DDC_SCL_DVI

80

DDC_SDA_DVI

178

RESETn

142

BLUE+

143

BLUE-

146

SOG_MCSS

147

GREEN+

148

GREEN-

151

RED+

152

RED-

181

HSYNC

182

VSYNC

155

ADC_TEST

118

RX2+

119

RX2-

123

RX1+

124

RX1-

128

RX0+

129

RX0-

132

RXC+

133

RXC-

138

CLKOUT

114

REXT

183

ROM_ADDR17

184

ROM_ADDR16

185

ROM_ADDR15

186

ROM_ADDR14

187

ROM_ADDR13

188

ROM_ADDR12

189

ROM_ADDR11

192

ROM_ADDR10

193

ROM_ADDR9

194

ROM_ADDR8

195

ROM_ADDR7

196

ROM_ADDR6

197

ROM_ADDR5

198

ROM_ADDR4

199

ROM_ADDR3

200

ROM_ADDR2

201

ROM_ADDR1

202

ROM_ADDR0

203

ROM_DATA7

204

ROM_DATA6

207

ROM_DATA5

208

ROM_DATA4

1

ROM_DATA3

2

ROM_DATA2

3

ROM_DATA1

4

ROM_DATA0

5

ROM_OEn

6

ROM_WEn

7

ROM_CSn

gm5221

PQFP-208

SOCKET:
IC51-2084-1052

R74

10K

GND

RMDATA[0..7]

Route (LBADC_IN1, LBADC_RET) and
(LBADC_IN2, LBADC_RET) as differential
tracks close to each other and ground the
return track of each pair very close to the
5221 and ground pin

3.3V_DVDD

5073190

3.3V_A

AGND

VDATA7/GPIO16

VDATA6/GPIO17

VDATA5/GPIO18

VDATA4/GPIO19

102

103

106

107

108

YUV6

YUV7

YUV5

YUV4

YUV3

2

AVDD_1.8

205

116

12125126

95

RVDD_33

RVDD_33

VDATA3/GPIO20

VDATA2/GPIO21

109

110

YUV2

YUV1

2

13711164

RVDD_33

RVDD_33

RVDD_33

VDD_RX2_18

VDD_RX1_18

VDD_RX0_18

VDD1_ADC_18

VDD_RXPLL_18

VDATA1/GPIO22

VDATA0/GPIO23

VCLKNCNCNCNCNCNCNCNCNCNC

111

112

5253104

C63
8P2

YUV0

GND

DECCLK

DECCLK

YUV[0..7]

YUV[0..7]

CVDD_1.8

CVDD_1.8

1669417596

86

CVDD_18

CVDD_18

CVDD_18

VDD_RPLL_18

CH3P_LV_E(PD0/ER0)
CH3N_LV_E(PD1/ER1)
CLKP_LV_E(PD2/ER2)
CLKN_LV_E(PD3/ER3)
CH2P_LV_E(PD4/ER4)
CH2N_LV_E(PD5/ER5)
CH1P_LV_E(PD6/ER6)
CH1N_LV_E(PD7/ER7)
CH0P_LV_E(PD8/EG0)
CH0N_LV_E(PD9/EG1)

CH3P_LV_O(PD10/EG2)
CH3N_LV_O(PD11/EG3)
CLKP_LV_O(PD12/EG4)
CLKN_LV_O(PD13/EG5)
CH2P_LV_O(PD14/EG6)
CH2N_LV_O(PD15/EG7)
CH1P_LV_O(PD16/EB0)
CH1N_LV_O(PD17/EB1)
CH0P_LV_O(PD18/EB2)
CH0N_LV_O(PD19/EB3)

GPIO8/IRQout

PWM0/GPIO11
PWM1/GPIO12
PWM2/GPIO13
PWM3/GPIO14

STI_TM1/GPIO15

VBUFC_RPLL

LBADC_RETURN

NC

54

105

157

158

159

160

161

139

179

CVDD_18

CVDD_18

CVDD_18

VCO_LV

PD20/EB4
PD21/EB5
PD22/EB6
PD23/EB7

PD24/OR0
PD25/OR1
PD26/OR2
PD27/OR3
PD28/OR4
PD29/OR5
PD30/OR6
PD31/OR7
PD32/OG0
PD33/OG1
PD37/OG5

DCLK

PPWR
PBIAS

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

GPIO7/IRQin

GPIO9/SCL

GPIO10/SDA

VBUFC_DVI

STI_TM2

CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS

CRVSS
GND_RPLL
GND1_ADC

LBADC_IN1
LBADC_IN2
LBADC_IN3

162

1

CVDD_18

TP9

10

LV_E9

13

LV_E8

14

LV_E7

15

LV_E6

16

LV_E5

17

LV_E4

18

LV_E3

19

LV_E2

20

LV_E1

21

LV_E0

22

LV_O9

29

LV_O8

30

LV_O7

31

LV_O6

32

LV_O5

33

LV_O4

34

LV_O3

35

LV_O2

36

LV_O1

37

LV_O0

38

PD20

43

PD21

44

PD22

45

PD23

46

56
57
58
59
60
61
62
63
64
65
66

47

DEN

48

DHS

49

DVS

55
67

68
81

82
83
84
85
88
89
90
91
92
93

98
99
100
101

69
167

135
70

206
191
180
140
97
94
76
74
51
42
8
87
165
163

173
174
175
176

LBADC_RET

GND

PPWR
PBIAS

GPIO0
GPIO1
GPIO2
GPIO3

GPIO5
GPIO6

MCSCL
MCSDA

TP12

GND

GND

DEN

DHS
DVS
DCLK

SEL_RGB
VGACON
VBI_INTR
LED
DEC_PWN
RET_OTHER
POWER
IR_IN
SWS1
MCSCL
MCSDA

PWM0

AMP_MUTE
SWS0

KEYBOARD
INPUT TO
LBW ADC

C60

C61

0.1uF

0.1uF

1

LV_E[0..9] 7,8

LV_O[0..9] 7,8

PD[20..23] 8

PPWR 7,8
PBIAS 7

I2C
PWM
OUPUT
FOR AMP
VOLUME,
BL
BRITNESS

ADC_IN1
SCART_FB1
SCART_FB2

DEN
DHS
DVS
DCLK

MUX SEL,VGA
CONNECTOR
SIGNAL,VBI
INTR, LED, AMP
AND AUDIO
DISABLE

5

4

3

2

1

D D

Keypad
INTERFACE

NV RAM
INTERFACE

+5V

R77

R76
10K

GPIO9/SCL

MCSCL

GPIO10/SDA

MCSDA

C C

J3

1
2
3
4
5
6
7
8

9
10
11
12

J5

CON8

CON5

CON15

1
2
3
4
5
6
7
8

J8

1
2
3
4
5

13
14
15

GND

GND

IR REMOTE SENSOR
INTERFACE

B B

J7

CON5

A A

+5V

1
2

GND

3
4
5

C66

220pF

+5V

R75
10K
C64
220pF

GND

LED TV_IN
IR_IN

GND

ADC_IN1

1x5x2.0mm

C65

10K

0.1uF

GND GND

CVBS2

CVBS1
SVIDEO_Y
SVIDEO_C

+9V

SCART_R

SCART_G

SCART_B

MCSCL
MCSDA

TUNER_L
TUNER_R

+9V

+5V

C67

0.1uF

CVBS2
CVBS1
SVIDEO_Y
SVIDEO_C

SCART_R
SCART_G
SCART_B

C68

0.1uF

+12V

8
7
6

C69

0.1uF

U7

VCC
WP
SCK

24LC16B

1

A0

2

A1

3

A2

45

VSSSI

J4

SCART_FB1

1

SCART_FB2

2
3
4
5

GND

CON5

EXTERAL AV
BOARD
INTERFACE

J6

1
2
3
4
5
6

CON6

SCART_FB1
SCART_FB2
POWER
RET_OTHER

AV_L1
AV_R1

AV_L2
AV_R2

5

4

3

2

1