TCL LCD1510 Schematic

5

GM21 LCD TV

4

3

2

1

D D

C C

B B

CONTENTS

SCHEMATIC

01. Contents

02. Input

03. GM2221

04.SPI/RESET/KEYPAD

05. LVDS_ Out

05. TTL_ Out

06. Power

07. VIDEO DECODER

08.AUDIO
09 AV Board
10 Front Control Board
11 Interface
12 Nicam Board
13 Power_New

14 Receiver

SHEET

1
2
3
4
5
6
7
8

9
10
11
12
13

14

Approval

A A

SignatureOrganization

Date

CHY 04-05-17

Wangdc 05-05-17

5

4

3

2

Title

GM21

Size Document Number Rev

040108 chy

B

of

Date: Sheet

114Friday, August 19, 2005

1

5

VGASCL
VGASDA

D6

3

BAV99

65

+5V

D4

3

BAV99

1 2

GND

R17 100R

R18 100R

C220

0.1UF

GND

FB1

21

FB2

21

FB3

21

VGA_SCL

VGA_SDA

+5V

D7

3

3

BAV99

1 2

GND GND

A-VS

R30
10K

GNDGND

A-PB

A-PR

A-Y

+5V

DNP

R15

47K

P1

3 4

GND2 SIG2

1 2

GND1 SIG1

COMPONENT

+5V

1 2

GND

R16
2K7

SIG3GND3

D D

EDID VGA

U2

2

A1A2WP

3
4

GND

24AA02

GND

ANALOG DDC

C C

VGA_5V

VCCA0
SCL

SDA

BAT54C

+5V

D5

A1

A2

C

5V_VGA

C2

0.1uF

81

GND

7
6
5

GND

GND

YPrPB Video In

B B

R12 10K

CN2

GND

15
14
13
12
11

DB15 HD
D8

BAV99

1 2

R23 20R

R31
10K

4

R13 0R

5
10
4
9
3
8
2
7
1
6

GND

Near VGA pins

1%

1%

3

+5V

R8

R9

10K

R10 100R

R37

Pb/B

1k

GND

R11 100R

1

IN

2

SA1

3

SA2

4

DA

5

SB1

6

SB2

7

DB

8

GND

13-PI5V33-0QB

GND

U3

PI5V330

2 3

BC847c

3.3V

L1

16

VCC

15

EN

14

SD1

GND

13

SD2

Pr/R

12

DD

11

SC1

10

SC2

R34

9

DC

1k

GND

+5V_MUX

R46

22k

A-BLUE

1

1 2

Q5

C16

10uF/16V

10k

R48

GND

VGACON

R14
10K

VGA_5V

VGA RGB In

A-BLUE
A-GREEN
A-RED

R1982

R2082

R2182

HSYNC 5

VSYNC 5 BLUE+ 5

A-Y

A-GREEN

A-PB

C11

12

10uF/16V

82

R36

GND

C15

12

10uF/16V

C17

12

10uF/16V

82

R32

GND

GND

GND

GND

+5V_MUX

SEL_RGB3

R24

Q2

22k

BC847c

1

R33

10k

R42

Q4

22k

BC847c

1

R45

10k

GND

R47

Q1

22k

BC847c

1

R50

10k

2 3

+5V_MUX

2 3

+5V_MUX

2 3

Y/G

R29

1k

GND

10K

+

C4

10uF

GND

Q6

BC847c

1

2 3

R35

10k

+5V_MUX

R41

Q3

22k

BC847c

1

R43

2 3

10k

C5 0.01uF

+5V_MUX

R26
22k

GND

1 2

10uF/16V

2

NOT TO BE MOUNTED

C13

A-PR

82

R49

GND

C14

A-RED

1 2

10uF/16V

Pr/R

R22 47R 1%

Y/G

R25 47R 1%

Pb/B

R28 47R 1%

R3884.5 1%

R3984.5 1%

GND GND GND

R4084.5 1%

DDC_SCL_VGA 5
DDC_SDA_VGA 5

C3 0.01uF

C6 0.01uF
C7 0.01uF

C8 0.01uF
C9 0.01uF

C10 0.01uFR27 20R
C12 0.01uF

1

MUXED RGB
TO 5221ADC
INPUT

SOG_MCSS 5

RED+ 5
RED- 5

GREEN+ 5
GREEN- 5

BLUE- 5

A A

Title

40-LD2010-DIC4X(40-LD2010-DIC4X)

Size Document Number Rev

040108 chy

C

5

4

3

2

Date: Sheet

1

of

214Friday, August 19, 2005

5

+3.3V_AVDD

D D

C C

B B

A A

L2

33R FB

+1.8V_DVDD

RMADDR[6:0]

RMADDR[12:7]
RMADDR[14:13]

RMADDR15

RMADDR16

RMADDR17

3.3V_AVDD

C18

C19

22uF/16V

0.1uF

GND

+3.3V_DVDD 3.3V_DVDD

L3

33R FB

CVDD_1.8

L4

33R FB

L5

33R FB

BootStrap Signals

HSYNC3

C38
22uF/16V

GND

AVDD_1.8

C48
22uF/16V

GND

For I2C address [6:0] to JTAG bridge
Host I/F, to determine device address.

User_Bits[5:0] for configuration setting
OP_MODE[1:0]:

00 = Normal op. UART in 186 on system pins.
01 = I2C to JTAG bridge.
10 = JTAG port, 5 wires
11 = External parallel control bus using
ROM Addr/Data

SPI_EN: 0 = parallel ROM I/F. 1 = SPI
serial ROM and Cache control

Initial state of OCM ROM:
0 = internal ROM on, and mapped to top 32K
of OCM and OCM boot will be from internal
ROM codes.

1 = Internal ROM off. The external ROM
mapped to entire upper 512K of OCM address.
OCM boot from external ROM code.

OSC_SEL: 0 = Xtal and internal oscillator.
1 = TTL oscillator (on TCLK pin)

VGAHS

+5V

GPIO9/SCL

MCSCL

GPIO10/SDA

MCSDA

5

Close to respective power Pins

C20

0.1uF

C21

0.1uF

C22

0.1uF

Close to respective power Pins

C30

C29

0.1uF

22uF/16V

GND

Close to respective power Pins

C40

C39

0.1uF

C49

0.1uF

R76
10K

C41

0.1uF

0.1uF

C50

0.1uF

5.5V

14

U5

1

1

2

2

3

3

4

4

11

11

10

10

7

74LCX14

GND

R77

C65

10K

0.1uF

8
7
6

GND GND

C23

0.1uF

C31

0.1uF

1N4148

14

7

U7

VCC
WP
SCK

24LC16B

C24

0.1uF

C32

0.1uF

C42

C43

0.1uF

0.1uF

C52

C51

0.1uF

0.1uF

13

13

12

12

8

8

9

9

6

6

5

5

1

A0

2

A1

3

A2

45

VSSSI

C26

C25

0.1uF

0.1uF

C33

C34

0.1uF

0.1uF

C44

0.1uF

Close to respective power Pins

C53

0.1uF

VGAVS

VSYNC
3

4

C28

C27

0.1uF

0.1uF

Close to respective power Pins

C35

0.1uF

C45

C46

0.1uF

220pF

C55

C54

220pF

0.1uF

3.3V_AVDD

C58
5pF

BOOTSTRAP OPTIONS SELECT
(NOT POPULATED SHOULD BE
HARD WIRED)

+5V

4

C47
220pF

X1

14.318MHz

C36

0.1uF

3.3V_AVDD

C37

0.1uF

JTAG
DEBUG
I2C SEL

C59
5pF

TCLK

XTAL

10KR54

RMADDR0

10KR55

RMADDR1

10KR57

RMADDR2

10KR58

RMADDR3

10KR60

RMADDR4

10KR61

RMADDR5

10KR62

RMADDR6

10KR63

RMADDR7

10KR64
10KR65

RMADDR9

10KR66

RMADDR10

10KR67

RMADDR11

10KR68

RMADDR12

10KR69

RMADDR13

10KR70

RMADDR14

10KR71

RMADDR15

10KR72

RMADDR16

10KR73

RMADDR17

GND GND

T2

1
2

RMADDR8

HOST_SDA/UART_DO
HOST_SCL/UART_DI
DDC_SCL_VGA

DDC_SDA_VGA

SW1
SW PUSHBUTTON

For_Update

C57

0.1uF

RMADDR17

RMADDR16
RMADDR15
RMADDR14
RMADDR13
RMADDR12
RMADDR11
RMADDR10
RMADDR9
RMADDR8
RMADDR7
RMADDR6
RMADDR5
RMADDR4
RMADDR3
RMADDR2
RMADDR1
RMADDR0

TP14 VP

R5110K

R5210K

OR30R

OR20R

OR10R

DDC_SCL_VGA3
DDC_SDA_VGA3
DDC_SCL_DVI3
DDC_SDA_DVI3

BLUE+3
BLUE-3
SOG_MCSS3
GREEN+3
GREEN-3
RED+3
RED-3

VGAHS
VGAVS

RX2+3
RX2-3
RX1+3
RX1-3
RX0+3
RX0-3
RXC+3
RXC-3

+5V

U6

30

2

3
29
28

4
25
23
26
27

5

6

7

8

9
10
11
12

1

AT49HF/F010-45JC

32-Pin PLCC Socket

3

NC/A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

NC

3

OR40R

+5V

GND

RMDATA[0..7]

R56 10K
R59 10K

VCC

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

GND

J1

1
2
3
4

RS232

DDC_SCL_VGA
DDC_SDA_VGA
DDC_SCL_DVI
DDC_SDA_DVI

OE

WE

CE

3.3V_AVDD

GPROBE
DEBUG
PORT

TCLK
XTAL

RESET

ADC_TEST

RX2+
RX2­RX1+
RX1­RX0+
RX0­RXC+
RXC-

3.3V_AVDD

+5V

32

GND
24
31

22

RMDATA7

21

RMDATA6

20

RMDATA5

19

RMDATA4

18

RMDATA3

17

RMDATA2

15

RMDATA1

14

RMDATA0

13

16

RMADDR17
RMADDR16
RMADDR15
RMADDR14
RMADDR13
RMADDR12
RMADDR11
RMADDR10
RMADDR9
RMADDR8
RMADDR7
RMADDR6
RMADDR5
RMADDR4
RMADDR3
RMADDR2
RMADDR1
RMADDR0

RMDATA7
RMDATA6
RMDATA5
RMDATA4
RMDATA3
RMDATA2
RMDATA1
RMDATA0

C62

0.1uF

GND

3.3V_DVDD

TP10

TP11

R53 250/1%

ROM_OEn
ROM_WEn
ROM_CSn

2

3.3V_DVDD

5073190

3.3V_A

AGND

VDATA7/GPIO16

VDATA6/GPIO17

VDATA5/GPIO18

VDATA4/GPIO19

102

103

106

107

108

YUV6

YUV7

YUV5

YUV4

YUV3

95

RVDD_33

RVDD_33

VDATA3/GPIO20

VDATA2/GPIO21

109

110

YUV2

YUV1

2

U4

AVDD_OUT_LV_E_33

24

AVDD_OUT_LV_E_33

26

AVDD_LV_33

27

AVDD_OUT_LV_O_33

40

AVDD_OUT_LV_O_33

113

AVDD_IMB_33

120

AVDD_RX2_33

125

AVDD_RX1_33

130

AVDD_RX0_33

134

AVDD_RXC_33

141

AVDD_BLUE_33

145

AVDD_GREEN_33

150

AVDD_RED_33

154

AVDD_ADC_33

172

LBADC_VDD_33

171

AVDD_RPLL_33

12

AVSS_OUT_LV_E

23

AVSS_OUT_LV_E
AVSS_LV

28

AVSS_OUT_LV_O

39

AVSS_OUT_LV_O

115

AGND_IMB

117

AGND_RX2

122

AGND_RX1

127

AGND_RX0

131

AGND_RXC

144

AGND_BLUE

149

AGND_GREEN

153

AGND_RED

156

AGND_ADC

168

AGND_RPLL

177

LBADC_GND

136

GND_RXPLL

GND

170

TCLK

169

XTAL

71

HOST_SCL/UART_DI

72

HOST_SDA/UART_DO

77

DDC_SCL_VGA

78

DDC_SDA_VGA

79

DDC_SCL_DVI

80

DDC_SDA_DVI

178

RESETn

142

BLUE+

143

BLUE-

146

SOG_MCSS

147

GREEN+

148

GREEN-

151

RED+

152

RED-

181

HSYNC

182

VSYNC

155

ADC_TEST

118

RX2+

119

RX2-

123

RX1+

124

RX1-

128

RX0+

129

RX0-

132

RXC+

133

RXC-

138

CLKOUT

114

REXT

183

ROM_ADDR17

184

ROM_ADDR16

185

ROM_ADDR15

186

ROM_ADDR14

187

ROM_ADDR13

188

ROM_ADDR12

189

ROM_ADDR11

192

ROM_ADDR10

193

ROM_ADDR9

194

ROM_ADDR8

195

ROM_ADDR7

196

ROM_ADDR6

197

ROM_ADDR5

198

ROM_ADDR4

199

ROM_ADDR3

200

ROM_ADDR2

201

ROM_ADDR1

202

ROM_ADDR0

203

ROM_DATA7

204

ROM_DATA6

207

ROM_DATA5

208

ROM_DATA4

1

ROM_DATA3

2

ROM_DATA2

3

ROM_DATA1

4

ROM_DATA0

5

ROM_OEn

6

ROM_WEn

7

ROM_CSn

gm5221

PQFP-208

SOCKET:
IC51-2084-1052

R74

10K

GND

RMDATA[0..7]

Route (LBADC_IN1, LBADC_RET) and
(LBADC_IN2, LBADC_RET) as differential
tracks close to each other and ground the
return track of each pair very close to the
5221 and ground pin

AVDD_1.8

205

RVDD_33

RVDD_33

VDATA1/GPIO22

VDATA0/GPIO23

111

112

YUV0

YUV[0..7]

1669417596

116

12125126

13711164

RVDD_33

VDD_RX2_18

VDD_RX1_18

VDD_RX0_18

VDD_RPLL_18

VDD1_ADC_18

VDD_RXPLL_18

CH3P_LV_E(PD0/ER0)
CH3N_LV_E(PD1/ER1)
CLKP_LV_E(PD2/ER2)
CLKN_LV_E(PD3/ER3)
CH2P_LV_E(PD4/ER4)
CH2N_LV_E(PD5/ER5)
CH1P_LV_E(PD6/ER6)
CH1N_LV_E(PD7/ER7)
CH0P_LV_E(PD8/EG0)
CH0N_LV_E(PD9/EG1)

CH3P_LV_O(PD10/EG2)
CH3N_LV_O(PD11/EG3)
CLKP_LV_O(PD12/EG4)
CLKN_LV_O(PD13/EG5)
CH2P_LV_O(PD14/EG6)
CH2N_LV_O(PD15/EG7)
CH1P_LV_O(PD16/EB0)
CH1N_LV_O(PD17/EB1)
CH0P_LV_O(PD18/EB2)
CH0N_LV_O(PD19/EB3)

GND

DECCLK

C63
8P2

5253104

DECCLK
YUV[0..7]

NC

54

105

157

VCLKNCNCNCNCNCNCNCNCNCNC

CVDD_1.8

CVDD_1.8

86

CVDD_18

CVDD_18

CVDD_18

CVDD_18

GPIO7/IRQin

GPIO8/IRQout

GPIO10/SDA

PWM0/GPIO11
PWM1/GPIO12
PWM2/GPIO13
PWM3/GPIO14

STI_TM1/GPIO15

VBUFC_RPLL

VBUFC_DVI

LBADC_RETURN

158

159

160

161

1

139

179

CVDD_18

CVDD_18

CVDD_18

VCO_LV

PD20/EB4
PD21/EB5
PD22/EB6
PD23/EB7

PD24/OR0
PD25/OR1
PD26/OR2
PD27/OR3
PD28/OR4
PD29/OR5
PD30/OR6
PD31/OR7
PD32/OG0
PD33/OG1
PD37/OG5

DEN
DHS
DVS

DCLK

PPWR
PBIAS

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

GPIO9/SCL

STI_TM2

CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS

CRVSS
GND_RPLL
GND1_ADC

LBADC_IN1
LBADC_IN2
LBADC_IN3

162

Title

Size Document Number Rev

Date: Sheet

LV_E9

13

LV_E8

14

LV_E7

15

LV_E6

16

LV_E5

17

LV_E4

18

LV_E3

19

LV_E2

20

LV_E1

21

LV_E0

22

LV_O9

29

LV_O8

30

LV_O7

31

LV_O6

32

LV_O5

33

LV_O4

34

LV_O3

35

LV_O2

36

LV_O1

37

LV_O0

38

PD20

43

PD21

44

PD22

45

PD23

46

56
57
58
59
60
61
62
63
64
65
66

47
48
49
55

67
68

81
82
83
84
85
88
89
90
91
92
93

98
99
100
101

69
167

135
70

206
191
180
140
97
94
76
74
51
42
8
87
165
163

173
174
175
176

LBADC_RET

GND

PPWR
PBIAS

GPIO0
GPIO1
GPIO2
GPIO3

GPIO5
GPIO6

MCSCL
MCSDA

TP12

GND

GND

40-LD2010-DIB4X(40-LD2010-DIC4X)

040108 chy

C

TP9

10

DEN

DHS
DVS
DCLK

SEL_RGB
VGACON
VBI_INTR
LED
DEC_PWN
RET_OTHER
POWER
IR_IN
SWS1
MCSCL
MCSDA

PWM0

AMP_MUTE
SWS0

KEYBOARD
INPUT TO
LBW ADC

C60

C61

0.1uF

0.1uF

1

LV_E[0..9] 7,8

LV_O[0..9] 7,8

PD[20..23] 8

ADC_IN1
SCART_FB1
SCART_FB2

DEN
DHS
DVS
DCLK

PPWR 7,8
PBIAS 7

MUX SEL,VGA
CONNECTOR
SIGNAL,VBI
INTR, LED, AMP
AND AUDIO
DISABLE

I2C
PWM
OUPUT
FOR AMP
VOLUME,
BL
BRITNESS

of

314Friday, August 19, 2005

5

+5V

R80 470R

3

Q7

1

MMBT3904L

2

GND

U8

1

S1

2

G1

3

S2

4

G2

SI9953ADY

Panel Power Switch

3

Q9
MMBT3904L

2

R82 1K

+12V

+5V+3.3V_DVDD

R86

R88

R87 0

+5V

R89
47K

R90

1K

C75

C74

22uF/16V

0.1uF

GND

GND

D D

C C

B B

Panel Power Voltage Selection

PPWR5

PWM0

PPWR

R91 4K7 C223

1

GND

4

R79

100R

100

D1
D1
D2
D2

0R

GND

F1

8
7

33R FB

6
5

C72

0.1uF

C56

0.1uF

GND GND

BKLT_ADJ

PANEL_POWER

0.1uF

0.1uF

+12V

L6

31R FBL831R FBL731R FB

C71

C70

0.1uF

GND

LV_O[0..9]

LV_E[0..9]

L10

L11

31R FB

GND

31R FBL931R FB

Backlight
Inverter
Connector

J9

1
2
3
4
5
6
7

CON7

3

+5V

R78
10K

BKLT_ENBKLT_EN

R81 0R

4k7

GND

R85 0R

3

1

2

Q8

MMBT3904L

GND

LVDS test points right on the trace to avoid extra length

TXO0-

LV_O0 TXO0-EB3

LV_O2
LV_O3 EB0

LV_O4 EG7
LV_O5 EG6

LV_O6 EG5
LV_O7 EG4

LV_O8 EG3
LV_O9 EG2

TXE0+

TXE1-

TXE1+

EB2

EB1

LV_E0 EG1
LV_E1 EG0

LV_E2 ER7
LV_E3 ER6

TXO0+

TXO1-

TXO1+

TXO2-

TXO2+

TXOC-

TXOC+

TXO3-

TXO3+

2

20
19
18
17
16
15
14
13
12
11
10
9
8
7

TXO0+LV_O1
TXO1­TXO1+
TXO2­TXO2+

TXOC­TXOC+
TXO3­TXO3+
TXE0­TXE0+

TXE1­TXE1+

TXE2­TXE2+
TXEC­TXEC+
TXE3­TXE3+

6
5
4
3
2
1

PANEL_POWER

DF14A-20P-1.25H

TP15

LVDS Output
Connector

GND

R84 1KR83

PBIAS

PBIAS 5

CN3

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

DF14A-30P-1.25H

1

15"SAMSUNG

连接到 屏

TXE2-

TXE2+

TXEC-

TXEC+

TXE3-

TXE3+

A A

5

4

3

LV_E4 ER5
LV_E5 ER4

LV_E6 ER3
LV_E7 ER2

LV_E8 ER1
LV_E9 ER0

Title

40-LD2010-DIB4X(40-LD2010-DIC4X)

Size Document Number Rev

040108 chy

C

Date: Sheet

2

1

of

414Friday, August 19, 2005

5

D D

4

3

2

1

PANEL_POWER PANEL_POWER

LV_E[0..9]

C C

LV_O[0..9]

PD[20..23]

LV_E9
LV_E8
LV_E7
LV_E6 ER3
LV_E5
LV_E4
LV_E3
LV_E2

LV_E1
LV_E0
LV_O9
LV_O8
LV_O7
LV_O6
LV_O5
LV_O4

LV_O3
LV_O2
LV_O1
LV_O0
PD20
PD21
PD22
PD23

22Rx4
22Rx4

22Rx4

8
7
6
5 4
8
7

RN1

6
5 4

8
7
6
5 4
8
7
6
5 4

8
7
6
5 4
8
7
6
5 4

ER0

1

ER1

2

ER2

3

ER4

RN222Rx4

1

ER5

2

ER6

3

ER7
EG0

1

EG1

2

EG2

3

EG3
EG4

RN3

1

EG5

2

EG6

3

EG7

RN422Rx4

EB0

1

EB1

2

EB2

3

EB3
EB4

RN5

1

EB5

2

EB6

3

EB7

RN622Rx4

ER[0..7] SHT-6

EG[0..7] SHT-6

EB[0..7] SHT-6

CLK
VS
EB6
EB2

EB0 EB1
EG6

EG4
EG2
EG0

ER6
ER4
ER2
ER0

J10

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

87089-40

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DE
HS

EB7
EB5EB4
EB3

EG7
EG5
EG3
EG1

ER7
ER5
ER3
ER1

GNDGND

B B

DENSHT-5,6
DHSSHT-5,6
DVSSHT-5,6
DCLKSHT-5,6

DEN
DHS
DVS
DCLK

R92 22R
R93 22R
R94 22R
R95 22R

C76
47PF

DE
HS
VS
CLK

GND

A A

Title

GM21-TTL out

Size Document Number Rev

040108 chy

B

of

Date: Sheet

5

4

3

2

514Friday, August 19, 2005

1