Tatung VL5A9DA Schematic

SER VICE MANUAL

LCD Monitor

VL5A9DA

TABLE OF CONTENTS

PAGE

1. SPECIFICATIONS .................................................................................................... 3

1-1 GENERAL SPECIFICATIONS ...................................................….............. 3

1-2 LCD MONITOR DESCRIPTION .................................................................. 4

1-3 INTERFACE CONNECTOR .................................................................……. 4

2. PRECAUTION AND NOTICES ................................................................................ 5

2-1 ASSEMBLY PRECAUTION ......................................................................... 5

2-2 OPERATIONG PRECAUTION ..................................................................... 5

2-3 STORAGE PRECAUTION …........................................................................ 5

2-4 HIGH VOLTAGE WARNING ....................................................................... 5

3. OPERATING INSTRUCTIONS ................................................................................ 6

4. ADJUSTMENT .......................................................................................................... 7

4-1 ADJUSTMENT CONDITIONS AND PRECAUTIONS ............................... 7

4-2 ADJUSTMENTS METHOD .& DESCRIPTION......................... 7-8

4-3 FRONT PANEL CONTROL KNOBS ............................................................ 9

5. CIRCUIT & SOFTWARE DESCRIPTION ................ 10

5-1 THE DIFFERENT BETWEEN EACH PANEL ……………………………. 10 5-2 SPECIAL FUNCTION WITH PRESS KEY ……………………………….. 10 5-3 THE OPTIONAL ON MAINBOARD USING SHUTTLE & 4 KEY.. 10 5-4 THE OPTIONAL ON MAINBOARD OR OTHER ACCESSORY USING

10

DIFFERENT PANEL 5-5 SIMPLE INTRODUCTION ABOUT LM500 CHIPSET …………………... 11 5-6 SOFTWARE FLOW-CHART 12

6. A). INTERFACE-BOARD TROUBLE SHOOTING CHART .................... 14

B). INVERTER - MODULE TROUBLE SHOOTING CHART .................... 23

I. Hannstar-inverter spec & trouble shooting chart

23 II. LG-inverter spec & trouble shooting chart 32 III. CPT-inverter spec & trouble shooting chart 41

C). ADAPTER – MODULE TROUBLE SHOOTING CHART & BOM....... 50

D). Main-chip GMZAN1 specifications

54

7. MECHANICAL OF CABINET FRONT DIS-ASSEMBLY...................................... 80

8. PARTS LISTING .........................................................................................………... 81

9. POWER SYSTEM AND CONSUMPTION CURRENT............................................ 86

9-1 HARDWARE BLOCK DIAGRAM ………………………………………… 87

10. PCB LAYOUT .....................................................................………………………... 88

11. SCHEMATIC DIAGRAM …..................................................................................... 89

1. SPECIFICATIONS FOR LCD MONITOR

1-1 General specifications

1. LCD-PANEL : Active display area 15 inches or 15.1 inches diagonal

Pixel pitch 0.298 mm x 0.298 mm or 0.3 mm x0.3mm Pixel format 1024 x 768 RGB vertical stripe arrangement

2. Display Color : 6-bit, 262144 colors or 8-bit, 16.7 million colors

•

External Controls :

3. a).Power On/Off, Auto key, Ro tary-knob ( for shuttle) b).Power On/Off, Auto key, Left key, Right key ( for 4-key )

•

OSD menu Controls Contrast, Brightness, Focus, Clo ck,H-position, V-position, Language, Recall-7800, Recall-6500, Reset, Exit-osd, Red, Green, Blue

4. Input Video Signal : Analog-signal 0.7Vpp

Video signal termination impedance 75 OHM

5. Scanning Frequencies : Horizontal: 29 KHz - 61 KHz Vertical: 55 Hz – 75 Hz Pixel clock: 80 MHz

6. Factory Preset Timing : 18 User Timings : 19 Input signal tolerance : H tolerance ±1 K, V tolerance

7. Power Source : Switching Mode Power Supply AC 100 – 240 V, 50/60 Hz Universal Type

8. Operating Temperature : 0• - 50• Ambient

Non-operating Temperatur e : -20• - 60•

9. Humidity :

Operating : 20% to 80% RH (non-condensing) Non Operating : 5% to 95%RH (38.7• maximu m wet bulb temperat ure)

10. Weight :

4.5 kg

11. External Connection : 15Pin D-type Connector, AC power-Cord

12. View Angle : x-axis right/left = 60, y-axis up/down = 45 ,40

13. Outside dimension : Width x Height x Thickness = 398mm x 401mm x 250mm

14. Plug and Play : VESA DDC1/DDC2B

15. Power saving : VESA DPMS

±1 Hz

AC-IN 100v-240v

1-2 LCD MONITOR DESCRIPTION

The LCD MONITOR will contain an main board, an Inverter module, Adapter module and a keyboard. The main board will house the fla t panel control lo gic, brightness co ntrol logic, DDC a nd DC-DC conversio n to supply the appropriate power to the whole board and LCD panel.

The Inverter module will drive the backlight of panel . The Adapter module will provides the 12V DC-power 3.5 Amp to Main-board and Inverter module .

Monitor Block Diagram

Inverter

CCFT Drive.

Flat Panel and CCFL backlight

Main Board or Interface Board

ADAPTER

Keyboard

HOST Computer

Video signal, DDC

1-3 Interface Connectors

(A) AC-Power Cable (B) Video Signal Connectors and Cable

RS232 Connector For white balance adjustment in factory mode

2. PRECAUTIONS AND NOTICES

2-1 ASSEMBLY PRECAUTION

(1) Please do not press or scratch LCD panel surface with anything hard. And do not soil LCD panel surface

by touching with bare hands (Polarizer film, surface of LCD panel is easy to be flawed)

In the LCD panel, the gap between two glass plates is kept perfectly even to maintain display

characteristic and reliability. If this panel is subject to hard pressing, the following occurs : (a) Uniform color (b) Orientation of liquid crystal becomes disorder (2) Please wipe out LCD panel surface with absorbent cotton or soft cloth in case of it being soiled. (3) Please wipe out drops of adhesive like saliva and water in LCD panel surface immediately.

They might damage to cause panel surface variation and color change. (4) Do not apply any strong mechanical shock to the LCD panel.

2-2 OPERATING PRECAUTIONS

(1) Please be sure to unplug the power cord before remove the back-cover. (be sure the power is turn-off) (2) Please do not change variable resistance settings in MAIN-BOARD, they are adjusted to the most suitable

value. If they are changed, it might happen LUMINANCE does not satisfy the white balance spec. (3) Please consider that LCD backlight takes longer time to become stable of radiation characteristic in low

temperature than in room temperature. (4) Please p ay attention to displaying the same pattern for very long-time. Image might stick on LCD.

2-3 STORAGE PRECAUTIONS

(1) When you store LCD for a long time, it is recommended to keep the temperature between 0

without the exposure of sunlight and to keep the humidity less than 90% RH.

(2) Please do not leave the LCD in the environment of high humidity and high temperature such as 60•

90%RH.

(3) Please do not leave the LCD in the environment of low temperature; below -15•.

2-4 HIGH VOLTAGE WARNING

The high voltage was only generated by INVERTER module, if carelessly contacted the transformer on this module, can cause a serious shock. (the lamp voltage after stable around 600V, with lamp current around 8mA, and the lamp starting voltage was around 1500V, at Ta=25•)

•-40•

3. OPERATING INSTRUCTIONS

This procedure gives you instructions for installing and using the LM500 LCD monitor display.

1. Position the display on the desired operation and plug the power cord into a convenient AC outlet. Threewire power cord must be shielded and is provided as a safety precaution as it connects the chassis and cabinet to the electrical conduct ground. If the AC outlet in your location does not have provisions for the grounded type plug, the installer should attach the proper adapter to ensure a safe ground potential.

2. Connect the 15-pin color display shielded signal cable to your signal system device and lo ck both screws on the connector to ensure firm grounding. The connector information is as follow:

PIN NO.

DESCRIPTION

1. RED 9. 5V power from VGA-card

2. GREEN 10. GND

3. BLUE 11. SYNC. GND

4. GND 12. SDA

5. GND 13. HORIZ. SYNC

6. GND-R 14. VERT. SYNC

7. GND-G 15. SCL

8. GND-B

3. Apply power to the display by turning the power switch to the "ON" position and allow about thirty seconds for Panel warm-up. The Power-On indicator lights when the display is on.

4. With proper signals feed to the display, a pattern or data should appear on the screen, adjust the brightness and contrast to the most pleasing display, or press auto-key to get the best picture-quality.

5. This monitor has po wer saving f unction follo wing the VES A DPMS. B e sure to connect the signal cable to the PC.

6. If your LM500 LCD mo nitor requires service, it must be returned with the power cord.

1

6

11 15

5

10

15 - Pin Color Display Signal Cable

PIN NO.

DESCRIPTION

4. ADJUSTMENT

4-1 ADJUSTMENT CONDITIONS AND PRECAUTIONS

Adjustments should be undertaken only on following function : contrast, brightness focus, clo ck, h-position, vposition, red, green, blue since 6500 color & 7800 color.

4-2 ADJUSTMENT METHOD

Press MENU button to activate OSD Menu or make a confirmation on desired function, Press Left/Right button to select the function or done the adjustment.

1. White-Balance, Luminance adjustment

Approximately 30 minutes should be allowed for warm up before proceeding white balance adjustment

Before started adjust white balance ,please setting the Chroma-7120

MEM. channel 4 to 6500

and 6500 parameter is x = 313 ±10, y = 329 ±10, Y = 135 ±5 cd/m

How to setting MEM.channel you can reference to chroma 7120 user guide or simple use “ SC” key and

.

MEM. Channel 3 to 7800

color, ( our 7800 parameter is x = 296 ±10, y = 311 ±10, Y = 135 ±5cd/m2

” key to modify xyY value and use “ID” key to modify the TEXT description

2

)

Following is the procedure to do white-balance adjust

Press MENU button during 2 seconds along with plug in the AC-power cord will activate the factory mode, and the OSD screen will located at

I. Bias (Low luminance) adjustment :

1. Press “ AUTO” button , and wait for message “ Pass” ,check the Blacklevel value on OSD should be large than 30, if less than 30 that means the offset calculation FAIL, please manual adjust the blacklevel to value 43

2. set the contrast and brightness on OSD window to

3. adjust the value Y=210 cd/m

II. Gain adjustment :

a. adjust 7800 color-temperature

4. Set the Contrast of OSD function to 15, Brightness to –10

5. Switch the chroma-7120 to

6. switch the MEM.channel to Channel 03 ( with up or down arrow on chroma 7120 )

7. The lcd-indicator on chroma 7120 will show x = 296 cd/m

8. Adjust the RED on OSD window until chroma 7120 indicator reached the value R=100

9. adjust the GREEN on OSD, until chroma 7120 indicator reached G=100

10. adjust the BLUE on OSD, until chroma 7120 indicator reached B=100

11. repeat above procedure ( item 8,9,10) until chroma 7120 RGB value under the tolence =100±2

VR501 on

2

left top of panel

INTERFACE board until chroma 7120 measurement reach the

2

±5 cd/m2

RGB-mode

.

maximal

(with press “MODE” button )

value , RGB to “50”

±10

, y = 311

±10

, Y = 135 ±5

color and

2

xyY mod

e With press “MODE” button

12. switch the chroma-7120 to

13. Adjust the Contrast on OSD window until the Y measurement on chroma 7120 reached the value Y= 155 cd/m

14. Press 78 on OSD window to save the adjustment result

b. adjust 6500 color-temperature

1 Set the Contrast of OSD function to 15, Brightness to –10 2 Switch the chroma-7120 to

RGB-mode

(with press “MODE” button ) 3 switch the MEM.channel to Channel 04 ( with up or down arrow on chroma 7120 ) 4 The lcd-indicator on chroma 7120 will show x = 313

cd/m

2

±10

, y = 329

±10

, Y = 135 ±5

5 Adjust the RED on OSD window until chroma 7120 indicator reached the value R=100 6 adjust the GREEN on OSD, until chroma 7120 indicator reached G=100 7 adjust the BLUE on OSD, until chroma 7120 indicator reached B=100 8 repeat above procedure ( item 5,6,7) until chroma 7120 RGB value under the tolence

=100±2

2

xyY mod

e With press “MODE” button

9 switch the chroma-7120 to 10 Adjust the Contrast on OSD window until the Y measurement on chroma 7120 reached

the value Y= 155 cd/m

11 Press 65 on OSD window to save the adjustment result

Turn the POWER-button off to on to quit from factory mode ( in USER-mode, the OSD window location was placed at middle of screen)

2. Clock adjustment Set the Chroma at pattern 63 (cross-talk pattern) or WIN98/95 shut-down mode (dot-pattern). Adjust until the vertical-shadow as wid e as possible or no visible. This function is adjust the PLL divider of ADC to generate an accurate pixel clock Example : Hsyn = 31.5KHz Pixel freq. = 25.175MHz (from VESA spec)

The Divider number is (N) = (Pixel freq. x 1000)/Hsyn

From this formula, we get the Divider number, if we fill this number in ADC register (divider register), the PLL of ADC will generate a clock which have same period with above Pixel freq.(25.175MHz) the accuracy of this clock will effect the size of screen.(this clock was called PIXEL-CLOCK)

3. Focus adjustment Set the Chroma at pattern 63 (cross talk pattern) or WIN98/95 shut down mode (dot-pattern). Adjust the horizontal interference as less as possible This function is adjust the phase shift of PIXEL-CLOCK to acquire the right pixel data . If the relationship of pixel data and pixel clock not so match, we can see the horizontal interference at screen only at crosstalk pattern and dot pattern we can find this phenomena, other pattern the affect is very light

4. H/V-Position adjustment Set the Chroma at pattern 1 (crosshatch pattern) or WIN98/95 full-white pattern confirm above item 2 & 3 functions (clock & focus) was done well, if that 2 functions failed, the H/V position will be failed too. Adjust the four edge until all four-edges are visible at the edge of screen.

5. MULTI-LANGUAGE function There have 5 language for select ion, press “MENU” to selected and confirm , press “ LEFT” or “ RIGHT” to change the kind of language ( English , Deut ch , Francais, Espanol, Italian)

6. Reset function Clear each old status of auto-configuration and re-do auto-configuration ( for all mode) This function also recall 7800 color-temperature , if the monitor status was in “ Factory-mode” this reset function will clear Power-on counter ( backlight counter) too.

7. OSD-LOCK function Press Left & Right key during switching on the monitor, the access to the OSD is locked, user only has access to “ Contrast, Brightness, Auto-key “. If the opera tor pressed the Left & Right during switching on the monitor again , the OSD is unlocked.

8. View Power-on counter and reset the Power-on counter( if not necessary , not suggest to entry factory mode) The Power-on counter was used to record how long the backlight of panel already working, the backlight life time was guarantee minimal 25000 hours, the maintainer can check the record only in factory mode. Press MENU button for 2 seconds along with plug-in AC power cord will be in factory mode, and the OSD screen will located at press 78/65 , your white-balance data will overlap with the new-one, and you must perform the whitebalance process again. The result of counter was place at top of OSD, the maximal of record memory was 65000 hours, if exceed 65000 hours the counter will keep in 65000 hours until press “ RESET” at osd-menu in factory mode. The “ RESET” function in factory mode will execute following function:

1. clear the Power-on counter to zero hours

2. clear old auto-configuration status for all mode , so the monitor will automatically re-do auto-config

when change to next mode or power on-off

4-3 FRONT PANEL CONTROL KNOBS

Power button : Press to switch on or switch off the monitor. Auto button : to perform the automatic adjustment fro m CLOCK, FOCUS, H/V POSITION, but no affect the

color-temperature Left/Right button : select function or do an adjustment. MENU button : to activate the OSD window or to confirm the desired function

left top of panel but take cautions

don’t press icon “78” & “65”, if you

5. CIRCUIT-DESCRIPTION

5-1 THE DIFFERENT between LG-Panel & Samsung-Panel & CPT-Panel & Hannstar- Panel in

ELECTRICAL Charateristic

LG-Panel

2. Single Pixel, 6 bit color (262144 colors)

3. Panel Vdd = 3.3V (in JP202 select 3.3V)

Samsung-Panel

2. Double Pixel, 6 bit color (262144 colors)

3. Panel Vdd = 5V (in JP201 select 5V)

Chung-Hwa Panel

2. Double Pixel, 8 bit color (16.7 Million colors)

3. Panel Vdd = 5V (in JP201 select 5V)

Hannstar Panel

2. Double Pixel, 6 bit color (262144 colors)

3. Panel Vdd = 3.3V (in JP202 select 3.3V)

5-2 SPECIAL FUNCTION with PRESS-KEY

A)

B)

. Press

OSD-INDEX EXPLANATION

1.

2.

3.

5-3 THE OPTIONAL on MAINBOARD for using SHUTTLE interface or KEYB OARD ( 4-KEY) interface.

The RESISTOR for choosing KEYBOARD interface or SHUTTLE interface

1). for KEYBOARD interface ( 4-key) , the R319 = 0 ohm resistor

2). For SHUTTLE interface , the R319 = OPEN

5-4 THE OPTION on MAINBOARD or other ACCESSORY when using different PANEL type

1). The MCU software should be change

2). the PANEL power should be switch ( JP202 is supply 3.3V, JP201 is supply 5V)

1. Two CCFL (Cold Cathode Fluorescent Tube)

1. Four CCFL (Cold Cathode Fluorescent Tube)

1. Two CCFL (Cold Cathode Flourescent Tube)

. press

Menu

button during 2 seconds along with That operation will set the monitor into “Factory- mode”, in Factory mode we can do the White balance adjustment with RS232 , and view the Backlight counter (this counter is use to record the panel activate hours ,for convenient the maintainer to check the panel backlight life time) In Factory mode, OSD-screen will locate in left top of screen. Press POWER-button off to on once will quit from factory mode and back to user-mod e .

both Left & Right button along with Power button

function, repeat this procedure will disable OSD-LOCK In OSD-LOCK function, all OSD function will be lock , except Contrast and Brighness

CABLE NOT CONNECTED

INPUT NOT SUPPORT

a. INPUT frequency out of range: H > 62kHz, v > 75Hz or H < 28kHz, v < 55Hz b. INPUT frequency out of VESA-spec. (out of tolerance too far)

UNSUPPORT mode, try different Video-card Setting

Input frequency out of tolerance, but still ca n catch-up by our system (if this message show, that means, this is new-user mode, AUTO-CONFIG will disable)

R319 ( 0 ohm

example : for HANNSTAR panel , the MCU part-number is 56A-1125-61-H

for LG panel , the MCU part-number is 56A-1125-61-L

for CPT panel , the MCU part-number is 56A-1125-61-C

example : for HANNSTAR panel, the jumper on Mainboard JP202 = 0 ohm, JP201 = OPEN

for LG panel, JP202=0 ohm, JP201 = OPEN

for CPT panel, JP202=OPEN , JP201 = 0 ohm

: Signal-cable not connected.

:

) which placement between Regulator LM2596 and MCU will be the controller

plug-in the AC Power cord

off to on once will activate the OSD-LOCK

:

and the other ACCESSORY when use different panel type should be change as following:

1). The INVERTER module for HANNSTAR panel part-number is 79AL15-6-S for LG panel the INVERTER part number is 79A-L15-1-S for CPT panel the INVERTER part number is 79A-L15-2-S

2). The FPC cable for HANNSTAR panel part number is for LG panel the FPC part number is for CPT panel the FPC part number is

3). The

MAIN-FRAME FRONT BEZEL FPC SHIELD Front Inverter Shield Panel Shield ( for EMI)

Adding following Mechanical accessory will

1. BASE-PLATE 15A5676-1

2. EARTH SPRING 19A550-2

3. EARTH CLIP 85A562-1

5-5 SIMPLE-INTRODUCTION about LM500 chipset

1. GMZAN1 ( all-in-one chip solution for ADC, OSD, scalar and interpolation) :

2. M6759 (ALI- MCU, type 8052 series with 64k Rom-size and 512 byte ram) :

3. 24LC21 (MicroChip IC) :

4. 24C04 (ATMEL IC) :

5. LM2569S( NS brand switching regulator 12V to 5V with 3A load current) .

6. AIC 1084-33CM (AIC brand linear regulator 5V to 3.3V)

MODULE-TPYE COMPONENT :

1. ADAPTER : CONVERSION-module to convert AC 110V-240V to 12VDC, with 3.5 AMP

2. INVERTER : CONVERSION-module to convert DC 12V to High-Voltage around 1600V, with frequency

Mechanical accessory

following differ ent is for TCO9 2 only

USE for computer graphics images to convert analog RGB data to digital data with interpolation process, zooming, generated the OSD font , perform overlay function and generate drive-timing for LCD-PANEL.

Use for calculate frequency, pixel-dot , detect change mode, rs232-communication, power-consumption control, O S D-index warning , …etc.

EePROM type, 1K ROM-SIZE, for saving DDC-CONTENT.

EePROM type, 4K ROM-SIZE, for saving AUTO-config data, White-balance data, and Power-key status and Backlight-counter data.

30K-50Khz, 7mA-9Ma

is change or adding as follow;

LG PANEL LM151X2 CPT PANEL HANNSTAR PANEL

15A5679-3 15A5675-2 15A5683-2 34A679-1-AL 34A798-1-AL 34A798-1-AL 85A556-1 85A560-1 NONE 85A558-1 85A561-1 85A580-1 NONE NONE 85A581-1

UPGRADE

your monitor to

TCO99

5-6 SOFTWARE FLOW CHART

I. Power-On Subrotine CHART

POWER-ON START

Initial MCU I/O, Interrupt vector & Ram

Check Eeprom is empty ?

Check White-balance data(6500 & 7800) same with the backup data ? Check POC( backlight counter) data same with the backup data ?

IF not same, overwrite the data with backup value.

Check Previous power-switch status from Eeprom, & other system status

Check if in Factory mode?(when power-on,press the MENU Button will be in FACTORY mode)

Clear factory mode flag

Initial 1.POC (backlight counter)

2. Clr all mode value

Check Keyboard interface (if PORT P2.7 =High 5V denoted Shuttle interface, otherwise is 4-key interface)

MAIN-SUBROTINE LOOP

Yes

SET factory mode flag

No

been c

No

II. MAIN SUBROTINE LOOP

Main loop start

Process Power-saving status ( according to below flow-chart result)

Check GMZAN IFM status .is change or not. And check Signal cable status ( cable not connected or not ) ** IFM is the register which measured the HSYN & Vsyn status

Check Auto-config mode flag already been set?

Monitoring the time-out of osd status ( if no key input persist for 10 sec , the osd time-out counter will trigger )

Yes, IFM have change

Is current system status in Po wer-sa vi ng ?

Check the IFM result is in the standard Mode table ?

Check the IFM result is in the user mode table ?

Out of range ( input not support) be confirm

confirm the frequency ( Hsyn or Vsyn) from IFM already

been changed ? ( check the change mode flag)

Process ( turn off OSD , setting GMZAN1according to above parameter,set LED status, set backlight status)

Read Key status and Process on OSD-screen

Yes

Check Factory mode flag= 1

)

Yes

Wake-up GMZAN1 (because GMZAN1 was in partial sleeping state)

Set mode index & parameter Set change mode flag

Yes , freq had

hange

Do Auto-config automatically

if the RS232 buffer is full, process the command( while adjust white-balance in factory mode)

6. A). Interface-Board Trouble-Shooting chart

.

n

NG, led

NG,

NG, s

N

NG

*Use the PC Win 98/95 white pattern, with some icon on it, and Change the Resolution to 640x480 60 Hz / 31

KHz

**NOTICE : The free-running freq. of our system is 48 KHz / 60 Hz, so we recommend to use another

resolution to do trouble shooting, this trouble shooting is proceed with 640x480 @60Hz 31Khz

I. NO SCREEN APPEAR

OK, led in green-state But still no screen

NG, led in orange

If LED in ORANGE-state, that means your PC or CHROMA was in Power-saving status or the resolution had over-range too far ( or the resolution of PC is in interlace mode, or over 1280x1024 @75Hz ) so please fix the resoluti on to our spec.( you can check the freq with CRT monitor, or install our LM500 driver disk

OK, still no screen But led is in Green

Replace INVERTER to new-one, and Check the screen is normal ??

Measured the inveter connector CN303 Pin 1=12V, pin 3 on/off control=5V (on)

Check Panel type, was it match with the JP201 or JP202 definition? Measured the R225 with turn on & turn off the power button, check R225 should have response from 12V To 0V or vice versa

Check the FPC cable from CN201,CN202 was tight enough?, check the FPC of panel side too

Measured TCLK(pin 141 from U200) PVS,PHS (pin 73,74 from U200) Is there has any transition? Tclk around 31.25MHZ ,PVS=60.09Hz , PHS around 50.4KHz ??(for input signal=31K 60 Hz, and LED is green)

Re-plug in AC-power cord & make sure LED was in green-state? If led is in off-state(dark), press POWER-button to turn-on the monitor

till no screen

Yes, but still no screen

in dark state.

still in led Orange

Check INVERTER-module

G

Check the Pbias relative circuit, R314, Q303, Q304, R315, R225.. In normal operation, when LED =green, R314 Pbias should =3.3v, If Pbias no-response when the power switch turn on-off, replace the GMZAN1

If LED in DARK-state, check the keyButton ,it could be stuck by mechanical

,especially the POWER-butto

Keyboard circuit

Check

and check

Mechanical key button, why be stuck?

Check GMZAN1-BLOCK

White-balance

RE-do (see 4-2)

adjust

Check the PPWR panel power relative circuit, R400,Q250, Q200,Q201,R225 In normal operation, when LED =green, R400 should =3.3v, R225=12V,R226=5V (for CPT),or =3.3v for LG,HANNSTAR If PPWR no-response when the power button Turn on- turn off, replace the GMZAN1

RE-assemble the FPC cable for both side (Cn201,202 & panel-side)

GMZAN1 BLOCK

Check

O

NG , no

n

No

es,

Measured PCLK(pin 44 from CN201) PVS,PHS (pin 40,38 from CN201) Is there have any transition? Pclk around 31.25MHZ ,PVS=60.09Hz , PHS around 50.4KHz ??(for input signal=31K 60 Hz, and LED is green)

Change PANEL to new one

K

II THE SCREEN is Abnormal , stuck at white screen, OSD window can’t appear, but keyboard & LED was normal operation.

Check the PCLK at CN201 pin 44 ( or L201) , PVS at CN201 pin 40, PHS at CN201 pin 38, Pdispe at CN201 pin 42, is there have any transition? Pclk around 31.25MHZ ,PVS=60.09Hz , PHS around 50.4KHz ??(for input signal=31K 60 Hz, and LED is green)

Y

have transition

Check RGB data from bead-array (PD14-1•PD42-1) At CN201 ,Is there have any transition ?

Y

have transition

Check panel power (R226) have DC voltage? R226 ( Panel_P) =5V fro CPT,and 3.3V for others panel The maintainers must make sure the Power button state is ON , ( check the LED should be green state)

NO voltage

Check PERIPHERALS PANEL BLOCK

transition

Check the bead-array & cap array(LP201•LP212 ,CP201•CP212 was cold solder or bad)

White-balance

RE-do (see 4-2)

adjust

transition

Check the bead-array & cap array(LP201•LP212 ,CP201•CP212 was cold solder or bad)

Check all pin on GMZAN1 ( U200) for cold-solder ?

Measured TCLK(pin 141 from U200),PVS, PHS (pin 73,74 from U200) Is there has any transition? Tclk around 31.25MHZ ,PVS=60.09Hz , PHS around

50.4KHz ??(for input signal=31K 60 Hz, and LED is green) And check Gmzan1 RGB output ( PD14• PD42) have a transition?

Check GMZAN1 BLOCK

O

NG

O

GMZAN1 BLOCK check Note : set the input signal ( PC or CHROMA) to 640x480 31k 60 hz

Check input connector CN200 is loose?? Measure R212,R211= 31K & 60 hz ? Measure R200,R201,R202 (RGB input ) had signal??

K

NG

Tighten CN200 cable & check relative circuit

NG

Screen is normal ?

Measure U201 oscillator 50MHz is normal?? (you can measure R215)

NG

Replace

U201 oscillator 50 MHz

Set chroma or PC to power-save mode Check LED in ORANGE state ?

Set chroma or PC to 640x480 @60Hz or Other frequency, check LE D in GREEN State?

Measured PCLK(pin 44 from CN201) PVS,PHS (pin 40,38 from CN201) Is there has any transition? Pclk around 31.25MHZ , PVS=60.09Hz , PHS around

50.4KHz ? (for input signal=31K 60 Hz)

Re-plug AC power-cord, and check again Previous function, if still no screen, then Replace

GMZAN1

K

OK, partial of Gmzan1 is good

chip

NG

Replace

GMZAN1

Check

END

Peripheral-panel block

PERIPHERAL PANEL BLOCK

NG

,

O

Note: “Panel vdd “ and “backlight on-off ” can be direct control by :

GMZAN1 or MCU Some panel can direct control by GMZAN1 ,if the relative timing between panel-vdd and backlight on-off is short ( under 80 ms) , otherwise, will be control by MCU If J211 be connected, that means Panel-VDD control was by GMZAN1 ,otherwise by MCU( JP212) If J300 be connected, that means Backlight control was by GMZAN1 ,otherwise by MCU ( JP301)

BUT Hannstar panel & CPT panel still control by J211 & J300

Press on-off ke y once, make-sure Led is in Green state .check panel-VDD = 3.3V for HANNSTAR And 5V for CPT-panel , measured Panel-p (pin 4,5 from CN201)??

Check CN303 pin 3 = 5 V ? ( that is Backlight controller, On-state= 5V)

Check CN303 pin 4•4.6V ??(that VR is for Backlight luminance control)

FOR HANNSTAR-PANEL , there is the relative timing between input resolution to output timing for panel ( output timing from GMZAN1 chip) as follow :

RESOLUTION( from PC or chroma) PCLK(U200.44) PHS ( U200.74) PVS (U200.73) 640X480 @60 Hz 31.25MHz 50.4 KHz 60.09 Hz 640X480 @70 Hz 35.56MHz 55.93KHz 69.83 Hz 640X480 @72 Hz 36.76MHz 57.64KHz 71.94 Hz 640X480 @75 Hz 37.71MHz 60.12KHz 74.96 Hz 800X600 @60 Hz 28.65MHz 48.45KHz 60.39 Hz 800X600 @70 Hz 32.94MHz 56.05KHz 70.03 Hz 800X600 @72 Hz 34.25MHz 57.61KHz 72.04 Hz 800X600 @75 Hz 35.71MHz 60.10KHz 75.08 Hz 1024x768@60 Hz 28.57MHz 48.36KHz 60.09 Hz 1024x768@70 Hz 32.77MHz 56.05KHz 70.03 Hz 1024x768 @72 Hz 33.97MHz 57.60KHz 71.84 Hz 1024x768@75 Hz 5.41MHz 60.24KHz 74.96 Hz

TURN VR until CN303

Pin 4= 4.7 V??

NG, still no screen

If JP211 was connected, check PPWR relative circuit ( R400,R401,Q250,R223,Q200,R224,R225,C245,Q201 cold-solder or open loop)?? make-sure LED in Green-state, and PPWR (U200.pin 76)= high 3.3V If JP212 was connected, check Backlight_En relative circuit (R223,Q200,R224,R225,Q201,C245), make sure Backlight_E n = low 0V ??

K

If JP300 was connected ,check Pbias relative circuit( R314,R309,R315 Q303,Q304,R311 cold-solder or open loop)?? make-sure LED in Green-state, and Pbias (U200.pin 75)= high 3.3V If JP301 was connected, check Panel-en relative circuit( R315,Q304 R311 cold-solder or open loop ??) make-sure LED in green-state And Panel-en= low 0V ??

If JP300 was connect, replace GMZAN1 Chip, if JP301 was connect , replace MCU

OK

Replace PANEL, maybe the lamp or Driver board was bad

O

NG

,

O

OK, no keep

KEYBOARD BLOCK check

Check U302 MCU pin 43,42,41,40,39 at High state(5V)? without press any key

Press power key and check U302 pin 43 = low (0V) ?

Check U302 pin 38 (LED green) will have transition from hi to low or low to hi when we press the power key??

Check U302 pin 20= 20MHz ? and pin 44 (VDD)=5V ? and pin 10 (reset)=0V ? at normal condition

Without press key and change mode, Check U302 pin 16,17(sda,scl)= hi 5V ? or keep transition ?

Replace U302 MCU

K

NG, MCU no response

transition

NG

Keep transition, that means eeprom no response

Mechanical was stuck, Check !

Replace no work replace U302 MCU at main-board and check MCU relative reset circuit, and crystal

K

If still no Led green indicator, check Q102, R106 & LED at keyboard !! cold solder or bad

If one of this item was NG, check the relative circuit

Tact-switch SW105

Check U300 eeprom 24LC04 relative circuit, check U300 pin 7 = low?

Check JP202 is connect ?

at keyboard if still

Check U300 pin 8 (vdd)= 5V, and check R300

Replace eeprom

R301 cold solder

K

POWER-BLOCK check

O

p

*

*Note : the waving of U304 pin 2 can determined the power situation

1. stable rectangle wave with equal duty, freq around 150K-158KHz that means all power of this interface board is in normal operation ,all status of 5V & 3.3V is normal working

2. unstable rectangle wave without same duty, that means ABNORMAL operation was happened check 3.3V or 5V ,short-circuit or bad component

3. rectangle wave with large spike & harmonic pulse on front side of rectangle wave, that means all 3.3v is no load,

Measure input power at U304 LM2596 pin 1= 12V ?

Check U304 pin 2 is a stable rectangle wave? Around 150k-158kHz stable rectangle wave with equal duty without any spike or harmonic pulse?

The interface board power is good

Gmzan1

was shut-down, and only

K

MCU

still working ,the monitor is in power saving state

NG

ADAPTER

Check

NG

Check U304 pin 2 is a unstable rectangle wave ?

OK, unstable wave

Check all 3.3V & 5V power, there is short circuit or bad component was happened

and connector if

The interface board is in powersaving state, pre ss power key to wake up & check your signal input

loose?

NG, with harmonic

ulse

O

III.ALL SCREEN HAS INTERFERENCES OR NOISE, CAN’T BE FIXED BY AUTO KEY

** NOTE:

Use DOT-pattern, or win98/99 shut-down mode pattern, press “AUTO” key, was the interferences disappear ??

Adjust “FOCUS” step by step, until the horizontal interferences disappear

Does your signal-cable have an additional cable for extension ??

Does your noise only exist in one mode only? (ex: only at 1024x768 @ 75 Hz, other is normal)

That was cause by you VGA-CARD setting, your VGA card timing backporch/frontporch exceed vesa timing too far, for some ne w AGP-VGA-CARD such situation always happened So in your

advance ,screen-adjust,at Size icon,

key every step you increase the procedure( increase/decrease SIZE one-step and press AUTO) until the interferences disappear, press “APPLY” to save in your VGA

There is so many kind of interferences, 1). One is cause by some VGA-CARD that not meet VESA spec or

power grounding too bad that influence our circuit

2).other is cause by external interferences, move the monitor far from electronic equipment.( rarely happened)

Yes, has extension

NO additional extension

Yes, only happened on one

control-panel

increase step by step slowly, press “”AUTO”

icon ,select

monitor ,setting ,

SIZE .

repeat the

cable

K

END

Put away the additional cable May be the additional cable grounding is not quite well

Change the Signal-cable to new-one or Try other brand VGA-CARD (make sure just only that brand VGACARD has this problem ,contact RDtaipei)

DOS MODE has jitter

p

e

f

es No

N

NOTE :the rule of doing AUTO-CONFIGURATION : must be a full-size screen, if the screen not full , the autoconfiguration will fail. So in do s mode ,just set your “CLOCK” i n OSD-MENU to zero or use some full screen edit file (ex: PE2, HE) and press “AUTO”

. THERE WAS SNOW PHENOMENA or BRIGHT NOISE ON THE SCREEN

I•

When use pattern 32 Gray-scale / or 16 Gray scale, there is a inside) that means some output bit to panel was bad, may be cause by FPC loose, or bead-array cold-solder There were some panel (ex :LG),also have this phenomena too, the noise will reduce or increase depend on the contrast/brightness value, this kind of proble m was cause b y P anel-driver-boa rd it sel f, we can’t fix it ,the o nly wa y to do was find the best-point of brightness/contrast, that the noise is more light

Use following pattern :

1. pure-white 2. Pure Red 3. Pure Green

4. Pure Blue 5. Pure White 6. Character repeat measure GMZAN1 (U200) all output pins must have some transition pulse, but notice

1. For LG panel and HANNSTAR panel , only 6 bit has output, (PD0~ PD17 , PD36 ~ PD41) the corresponding beads was LP201 ~ LP206

2.

For Chung-hwa panel or other’s 8 bit panel, all output are available (PD0-PD47 ), the corresponding beads was LP201-LP212

snow phenomena on the screen (like a noise spread

Ex : HANNSTAR Panel 6 bits

With 16 gray-scale, adjust contrast /brightness slowly

and observe the noise was increase or reduce or no-

influence at all ?especially at low luminance scale

No-

That was the panel noise, no solution, Just set the brightness to the best point

which noise is more light

Set pattern to full-white, adjust contrast to 50

Check U200 GMZAN1 Pin 71,70,69,68,67,66 ( Red, Pd0 -Pd5) Pin 64,63,62,57,56,55 (Green ,Pd6-Pd11) Pin 54,53,52,51,50,48 (Blue, Pd12- Pd17) There must be have some transition pulse in

each

in

Some pins no transition

Set pattern to Pure-Red or Pure Green or Pur Blue repeat above-step until all pins had transition

All pins has transition

Denotes U200 GMZAN1 work well

Check bead-array LP201~LP206, both side o bead must have the same transition signal

o

All 5 pattern already change yet? ?

Check FPC cable for loose, or FPC bad, if FPC bad, replace it

Y

Replace the correpondens beads array and check the capacitor arrays too

If all pattern already change but still had some pins no transition. That means GMZAN1 (U200) fail, replace U200

V. THE PANEL LUMINANCE WAS DOWN

NG

Use white pattern and resolution 1024x768 @ 60Hz , CHROMA 7120 measured the center of panel

Set Contrast, brightness =maximal, RGB= 50 Quit from OSD-screen, measured Y(luminance) With chroma 7120, check Y= 210±10 CD/M2 ?

Adjust VR201 until maximal, measured Y = 210±10 cd/m2 ?

If the Y less than 160 cd/m2 (after the VR201= MAX, contrast, brightness = max) then change the LAMP of panel

If Y can reach •180 cd/m2 that means The lamp still working well, so we just re-do the white-balance process As following procedure

Use white-pattern, press MENU button along with AC power-plug in ( you will in factory mode) The OSD-menu will be at left-top of screen,

press AUTO button to automatically adjust blacklevel value, you will see the sign PASS ,if FAIL , manual adjust the blacklevel until value 43 !

Set contrast, brightness to max, and turn the VR201 to max , wait for 20 minutes until the luminance Y stable The Y should be larger than 200 cd/m2 (for panel which already use for a year, the Y luminance might be a little down, around 180 cd/m2, there is acceptable too)

Follow this manual page 7 item 4-2 method to more detail procedure for do a white-balance adjust

Inverter –MODULE Spec &Trouble Shooting Chart

6 B).

In LM500 model , we use 3 kind of panel, each panel have their own inverter spec,therefore

following spec is Hannstar-panel Inverter, LG-panel Inverter,CPT-panel Inverter offer from

SAMPO-CORPORATION

I.) TROUBLE SHOOTING OF HANNSTAR-INVERTER (part no : 79AL15-6-S)

TYPE: L0048 FOR HANNSTAR 15”PANEL

SAMPO CORPORATION

T R O U B L E S H O O T I N G O F H ANN S T AR- IN V E R T E R ( DIVTL0048-D21- -)

1.SAMPO PART NO .:

2.SCOPE :

HANNSTAR(HSD150MX41) 15

this is to specify the requirements of the subject parts used in

L0048 ,AOC PART NO.: 79AL15-6-S

inch (2 C.C.F.L.) LCD monitor.

3.CONNECTOR PIN ASSIGMENT:

4-1. CON1: INPUT

MODEL NO.: S5B-PH-SM3-TB

PIN SYMBOL DESCRIPTION

1 Vin Input voltage: 12V 2 GND GND 3 ON/OFF ON: 3V OFF:0V 4 Dimming Dimming range (0V~+5.0V)

5 Dimming Dimming range (0V~+5.0V)

4-2. CON2,CON3 : OUTPUT

MODEL NO. : SM04(4.0)B-BHS-1-TB

PIN SYMBOL DESCRIPTION

1 HV OUTPUT Input H.V to lamps 2 RETURN Return to c ont rol

2

SAMPO CORPORATION

T R O U B L E S H O O T I N G O F H ANN S T AR- IN V E R T E R ( DIVTL0048-D21- -)

5.FUNCTION SPECIFICATIONS:

The data test with the set of SAMPO, and the test circuit is as below.

ITEM

SYMBOL MIN. TYP. MAX. UNIT REMARK

Input voltage

Vin

Input current Iin -- 800 1300 mA output current

Iout

adj:0v( min.)

(min)

Output current

Iout

adj.:5 v(max.)

(max)

Frequency H.V open

H.V Load

F 40

Vopen

Vload

FUNCTION LOAD CIRCUIT:

6.

10.8 12 13.2 V

1.7

5.8

2.2

6.2

2.7

6.7

mA

50 60 KHZ

1250 1400 1550 Vrms

580 680 780 Vrms

FOR 1 CCFL LOAD:110K•

FOR 1 CCFL LOAD:100K•

NO LOAD RL=110K•

10•

CON1

1 2 3 4 5

1

110K•

VT

1

10•

PIN SYMBOL

110K•

1 Vin 12V 2 GND 3 ON/OFF 4 Dimming 5 DIMMING

VT

DDD

SSS

GD

8.PART LIST

8-1 COMPONENTS LIST:

NO. REF. PART NAME PART NUMBER QTY DESCRIPTION SUPPLIER REMARK

1. CON1 CONNECTOR VCNCP0015-EJSTA 1 S5B-PH-SM3-TB JST

2. CON2,3

3. R1 RESISTOR VRMHNVA--303J-A 1 SMD 0603 30K• 5% YAGEO

4. R2

5. R3

•

VCNCP0012-ZJSTA

VCNCP0012-ZGLEA 2 2

VRMHNVA--512J-A 1 SMD 0603 5.1K• 5% YAGEO

VRMHNVA--272J-A 1 SMD 0603 2.7K• 5% YAGEO

SM02(8.0)B.BHS-1-TB

GL SM02(8.0)-WH2

JST

GEAN-LEA

6. R4

7. R5

8. R6,10

9. R8

10. R9

11. R11

12. R12

13. R13

14. R14

15. R15,16

16. R17,18

17. Q1 TRANSIST0R VSTDTC144WKA--A 1 SMD DTC144WKA ROHM

18. Q2

19. Q3

20. Q4

21. Q5,6 Q7 TRANSIST0R VSTDTC143EKA--A 1 SMD DTC143EKA ROHM

22. C1 CAPACITOR VCEATU1EC336M--

23. C6

•

VRMHNVA--222J-A 1 SMD 0603 2.2K• 5% YAGEO VRMHNVA--563J-A 1 SMD 0603 56K• 5% YAGEO

VRMHNVA--R00J-A 2 SMD 0603 0• 5% YAGEO

VRMHNVA--683J-A 1 SMD 0603 68K• 5% YAGEO VRMHNVA--333J-A 1 SMD 0603 33K• 5% YAGEO VRMHNVA--271J-A 1 SMD 0603 270• 5% YAGEO VRMHNVA--103J-A 1 SMD 0603 10K• 5% YAGEO VRMHNVA--472J-A 1 SMD 0603 4.7K• 5% YAGEO VRMHNVA--363J-A 1 SMD 0603 36K• 5% YAGEO VRMHNV4--122F-A 2 SMD 1206 1.2K• 1% YAGEO VRMCNV8--102F-A 2 SMD 0805 1K• 1% YAGEO

VSTDTA144WKA--A 1 SMD DTA144WKA ROHM

VSTSST3904----A VSTMMBT3904-A

VSTCEM9435A-----A

VSTSI9435DY---A

VST2SD2150----A 2 SMD 2SD2150 ROHM

VCEATU1VC476M-VCEBCU1EC107M--

VCLRCN1EB104K-A 1 SMD 0805 0.1 µF/25V TDK

1 SMD SST3904T116

SMD MMBT3904

1 SMD CEM9435A

SMD SI9435DY

1

DIP UGX 33 µF/25V

1

DIP UGX 47µF/35V

1

DIP NK-CON 100µF/25V

ROHM

MOTOROLA

CEM

VISHAY

SANYO SANYO

NK-CON

8-2 COMPONENTS LIST:

NO. REF. PART

24. C2,3,5,8,12 CAPACITOR VCLFCN1EY105Z-A 5 SMD 0805 1µF/25V TDK

NAME

PART NUMBER QTY DESCRIPTION SUPPLIER REMARK

25. C4

26. C7

27. C9

28. C10,11

29. C13

30. D1 DIODE VSDRLS4148----A

31. D2

32. D3

33. D4

34. I.C I.C VSITL5001CDR--A 1 SMDTL5001CDR TEXAS

35. F1 FUSE QFS-N152FIDZD-A

36. L1 COIL RCHOL0007ID151A 1 DIP 150µH 8% YST Attachment 1

37. PT1 TRANS RCVT-1508ID-Z-A 1 SMD YST-1508 YST Attachment 2

38. PCB PCB QPWBGL986IDLE2- 1 QPWBGL986IDLE2- LONGMAW

•

VCLRCN1HB103K-A 1 SMD 0805 0.01

µF/50V

VCLFCN1CY225Z-A 1 SMD 0805 2.2 µF/16V TDK

VCMECF2AC184J-P

VCMEBF2AB184J-P

VCMPH2AG184J--

VCDSEU3SL220K-- 2 DIP 22PF/3KV 10% TDK

VCLFBN1CY475Z-A 1 SMD 1206 4.7 µF/16V TDK

VSDLL4148-----A

VSDRB160L40---A

VSDB140-------A VSZRLZ9.1B-----A 1 SMD RLZ9.1B ROHM VSDDA204K-----A

VSDBAV99-7----A

QFS-Z152FIDZD-A

1 DIP 0.18µF/100V

DIP 0.18µF/100V DIP 0.18µF/100V

1 SMD RLS4148

SMD LL4148

1 SMD RB160L40

SMD B140

1 SMD DA204K

SMD BAV99-7

1 SMD FUSE 1.5A/63

SMD FUSE 1.5A/63

TDK

THOMSON

ARCO

TAIWAN

TAI

ROHM

VISHAY

ROHM

DIODES

ROHM

DIODES

LITTLE

BUSSMANN

Attachment (FEC1Q2)

9. TROUBLE SHOOTING

9-1 NO POWER:

CHECK ON FUSE

. FAIL

F1 Vin=12

TO CHANGE F1= 1.5A/63Z

PASS FAIL

TO CHECK ON Q4&Q6 Vout = 8 V

PASS

TO CHECK ON L1&L2 INPUT 9V TO L1 OR L2

FAIL

PASS

FUNCTION TEST OK!

TO CHANGE L: Q4&Q3&D1 R: Q5&Q6&D2

TO CHANGE L: Q7&Q8&C12&PT1 R: Q9&Q10&C13&PT2

9-2 HIGHT VOLTAGE PROTECTION:

1. SHORT R30 OPEN LOAD

FAIL

2. TEST C14 INPUT POINT

PASS

VOLTAGE Vh=1400 ±150V rms

FUNCTION TEST OK!

TO CHANGE ON PT1 OR PT2

9-3 OUTPUT CURRENT ABNORMALITY:

FAIL

1 CHECK ON C6 FREQUNCY &CHIP&IC CPIP 2 OSCILLATOR FREQUNCY

PASS

RANGE = 150 ~ 290 KHZ

FUNCTION TEST OK!

TO CHANGE ON C6 CHIP OR IC CHIP

9-4. ENBALE

ABNORMALITY:

IF ENBALE ABNORMALITY

1. TO CHECK IC PIN 9 TURN NO

FAIL

HAVE 8.5 VOLTAGES

PASS

9-5 DIMMING CONTROL ABNORMALITY:

TO CHANGE ON Q1&Q2

FUNCTION TEST OK!

IF DIMMING ABNORMALITY TO

FAIL

CHECK R1&R2&C6 HAVR BREAK

PASS

TO CHANGE ON R1 OR R2 OR C6

FUNCTION TEST OK!

9-6 TRANSFORMER ABNORMALITY:

FAIL

IF TRANSFORMER ABNORMALITY TO CHECK C3&C4 CHIP OUTLINE OR TRANSFORMER

PASS

10. INSTRUMENTS FOR TEST:

TO CHANGE ON C3&C4 OR TRANSFORMER

FUNCTION TEST OK!

1. DC POWER SUPPLY GPS-3030D

2. AC VTVM VT:-181E

3. DIGITAL MULTIMERTER MODEL-34401

4. HIGHTVOLT PROB MODEL-1137A

5.SCOPE MODEL-V-6545

6. AC mA METER MODEL-2016 (YOKOGAWA)

1.SAMPO PART NO .:

2.SCOPE :

L.G(LM151X4) 15

this is to specify the requirements of the subject parts used in

L0023 ,AOC PART NO.: 79AL15-1-S

inch (2 C.C.F.L.) LCD monitor.

3.CONNECTOR PIN ASSIGMENT:

4-1. CON1: INPUT

MODEL NO.: S5B-PH-SM3-TB

PIN SYMBOL DESCRIPTION

1 Vin Input voltage: 12V 2 GND GND 3 ON/OFF ON: 3V OFF:0V 4 Dimming Dimming range (1V~+5.0V) 5 N.C

4-2. CON2,CON3 : OUTPUT MODEL NO. : SM04(4.0)B-BHS-1-TB

PIN SYMBOL DESCRIPTION

1 HV OUTPUT Input H.V to lamps 2 RETURN Return to c ont rol

1

2

5.FUNCTION SPECIFICATIONS:

The data test with the set of SAMPO, and the test circuit is as below.

ITEM

SYMBOL MIN. TYP. MAX. UNIT REMARK

Input voltage

Vin

Input current Iin -- -- 1500 mA output current

Iout

adj:0v( min.)

(min)

Output current

Iout

adj.:5 v(max.)

(max)

Frequency H.V open

H.V Load

F 43

Vopen

Vload

FUNCTION LOAD CIRCUIT:

6.

80K•

10•

2

10.8 12 13.2 V

2.2

8.1

2.6

8.5

3.0

8.9

mA

48 53 KHZ

1350 1500 1650 Vrms

460 560 660 Vrms

CON1

1

1 2 3 4 5

FOR 1 CCFL LOAD:80K•

NO LOAD RL=80K•

10•

80K•

VT

PIN SYMBOL

1 Vin 12V 2 GND 3 ON/OFF 4 Dimming 5 N.C

VT

8.PART LIST

8-1 COMPONENTS LIST:

NO. REF. PART NAME PART NUMBER QTY DESCRIPTION SUPPLIER REMARK

1. CON1 CONNECTOR VCNCP0015-EJSTA 1 S5B-PH-SM3-TB JST

2. CON2,3

3. R1,2 RESISTOR VRMCNV8--153F-A 2 SMD 0805 15K• 1% YAGEO

4. R3,4,21 ,22

5. R5,6

•

VCNCP0012-ZJSTA

VCNCP0012-ZGLEA

VRMCNV8--203F-A 4 SMD 0805 20K• 1% YAGEO

VRMCNV8--362F-A 2 SMD 0805 3.6K• 1% YAGEO

2 SM02(8.0)B.BHS-1-TB

GL SM02(8.0)-WH2

JST

GEAN-LEA

6. R7,8,19 ,20

7. R9,10,

30

8. R11,12,

9. R13,14

10. R15,16

11. R17,18

12. R27

13. R28,29,

14. R31,32

15. R33

16. R23,24, 25,26

17. Q1 TRANSIST0R VSTDTC114EKA--A 1 SMD DTC114EKA ROHM

18. Q2

19. Q3,5

20. Q4,6

21. Q7,8,9,

10

22. C1,2 CAPACITOR VCLFCN1EY224Z-A 2 SMD 0805 0.22 µF/25V TDK

23. C3,4,7, 16,17

•

VRMCNV8--103F-A 4 SMD 0805 10K• 1% YAGEO

VRMCNV8--R00J-A 3 SMD 0805 0• 5% YAGEO

VRMCNV8--152F-A 2 SMD 0805 1.5K• 1% YAGEO VRMCNV8--133F-A 2 SMD 0805 13K• 1% YAGEO VRMCNV8--243F-A 2 SMD 0805 24K• 1% YAGEO VRMCNV8--471F-A 2 SMD 0805 470• 1% YAGEO VRMCNV8--512F-A 1 SMD 0805 5.1K• 1% YAGEO VRMCNV8--393F-A 2 SMD 0805 39K• 1% YAGEO VRMCNV8--102F-A 2 SMD 1206 1K• 1% YAGEO VRMCNV8--562F-A 1 SMD 0805 5.6K• 1% YAGEO VRMBNV4--102F-A 4 SMD 1206 1K• 1% YAGEO

VSTDTA114EKA--A 1 SMD DTA114EKA ROHM

VSTSST3904----A VSTMMBT3904-A

VST2SJ503------A 2 SMD 2SJ503 SANYO VST2SD2150----A 4 SMD 2SD2150 ROHM

VCLFCN1EY105Z-A 5 SMD 0805 1 µF/25V TDK

2 SMD SST3904-T116

SMD MMBT3904

ROHM

MOTOROLA

8-2 COMPONENTS LIST:

NO. REF. PART NAME PART NUMBER QTY DESCRIPTION SUPPLIER REMARK

DIP UGX 33 µF/25V

24. C5 CAPACITOR VCEATU1EC336M--

25. C6

26. C10,11

•

VCEATU1VC476M-VCEBCU1EC107M-VCLRCN1HB102K-A 1 SMD 0805 1000PF/50V TDK VCLRCN1EB333K-A 2 SMD 0805 0.033

27 C12,13

28. C14,15 29 C9

30. D1,2 DIODE VSDRLS4148----A

31. D3,4

32. D5,6

33. D7,8

34. I.C I.C VSITL1451ACNS-A 1 SMD TL1451ACNS TEXAS

35. F1 FUSE QFS-N202FIDZD-A

36. L1,2 COIL RCHOL0005ID121A

37. PT1,2 TRANS RCVT-2010ID-Z-A 2 SMD YST-2010 YST Attachment 2

38. PCB PCB QPWBGL023IDLF-- 1 QPWBGL023IDLF-- EISO

•

VCMEBF2AB154J-P VCMECF2AC154J-P VCMPHF2AG154J-P

VCDSEU3SL220K-- 2 DIP 22PF/3KV 10% TDK

VCLRCN1EB104K-A 1 SMD 0805 0.1 µF/25V TDK

VSDLL4148-----A

VSDRB160L40---A

VSDB140-------A

VSZRLZ7.5B-----A 2 SMD RLZ7.5B ROHM

VSDDA204K-----A VSDBAV99-7----A

QFS-Z202FIDZD-A

RCHOL0005ID121-

1

DIP UGX 47 µF/35V

1

DIP NK-CON 00µF/25V

1

µF/25V

2 DIP 0.15µF/100V

DIP 0.15µF/100V DIP 0.15µF/100V

2 SMD RLS4148

SMD LL4148

2 SMD RB160L40

SMD B140

2 SMD DA204K

SMD BAV99-7

1 SMD FUSE 2.0A/63

SMD FUSE 2.0A/63

2 DIP 120µH 10%

DIP 120µH 10%

SANYO SANYO

NK-CON

TDK

ARCO

THOMSON

TAIWAN

TAI

ROHM

VISHAY

ROHM

DIODES

ROHM

DIODES

LITTLE BUSSMANN

YST

• •

LONGMAW

••

Attachment (FEC1Q2) Attachment 1

9. TROUBLE SHOOTING

9-1 NO POWER:

CHECK ON FUSE

. FAIL

F1 Vin=12

PASS FAIL

TO CHECK ON Q4&Q6 Vduot = 9 V

PASS

TO CHECK ON L1&L2 INPUT 9V TO L1 OR L2

FAIL

TO CHANGE F1= 2.0A/63Z

TO CHANGE L: Q4&Q3&D1 R: Q5&Q6&D2

TO CHANGE L: Q7&Q8&C12&PT1 R: Q9&Q10&C13&PT2

PASS

FUNCTION TEST OK!

9-2 HIGHT VOLTAGE PROTECTION:

FAIL

1. SHORT R30 OPEN LOAD

2. TEST C14 INPUT POINT VOLTAGE Vh=1500 ±150V rms

PASS

TO CHANGE ON PT1 OR PT2

FUNCTION TEST OK!

9-3 OUTPUT CURRENT ABNORMALITY:

FAIL

1. CHECK ON C6 FREQUNCY

PASS

&CHIP&IC CPIP

2. OSCILLATOR FREQUNCY RANGE = 100 ~ 250 KHZ

FUNCTION TEST OK!

TO CHANGE ON C6 CHIP OR IC CHIP

9-4. ENABLE

ABNORMALITY:

IF ENBALE ABNORMALITY

1. TO CHECK IC PIN 9 TURN NO HAVE 12 VOLTAGES

PASS

9-5 DIMMING CONTROL ABNORMALITY:

IF DIMMING ABNORMALITY TO

FAIL

CHECK R1&R2&C6 HAVR BREAK

TO CHANGE ON Q1&Q2

FAIL

FUNCTION TEST OK!

TO CHANGE ON R1 OR R2 OR C6

PASS

FUNCTION TEST OK!

9-6 TRANSFORMER ABNORMALITY:

IF TRANSFORMER ABNORMALITY TO

FAIL

CHECK C3&C4 CHIP OUTLINE OR TRANSFORMER

TO CHANGE ON C3&C4 OR TRANSFORMER

PASS

FUNCTION TEST OK!

10. INSTRUMENTS FOR TEST:

1. DC POWER SUPPLY GPS-3030D

2. AC VTVM VT:-181E

3. DIGITAL MULTIMERTER MODEL-34401

4. HIGHTVOLT PROB MODEL-1137A

5.SCOPE MODEL-V-6545

6. AC mA METER MODEL-2016 (YOKOGAWA)

1.SAMPO PART NO .:

L0026 , AOC PART NO. : 79AL15-2-S

2.SCOPE :

CHUNGHWA (CLAA150XA03) 15

this is to specify the requirements of the subject parts used in

inch (2 C.C.F.L.) LCD monitor.

3.CONNECTOR PIN ASSIGMENT:

4-1. CON1: INPUT

MODEL NO.: S5B-PH-SM3-TB

PIN SYMBOL DESCRIPTION

1 Vin Input voltage: 12V 2 GND GND 3 ON/OFF ON: 3V OFF:0V 4 Dimming Dimming range (1V~+5.0V) 5

4-2. CON2,CON3 : OUTPUT MODEL NO. : SM04(4.0)B-BHS-1-TB

PIN SYMBOL DESCRIPTION

1 HV OUTPUT Input H.V to lamps 2 RETURN Return to c ont rol

5.FUNCTION SPECIFICATIONS:

1

2

The data test with the set of SAMPO, and the test circuit is as below.

ITEM

SYMBOL MIN. TYP. MAX. UNIT REMARK

Input voltage

Vin

Input current Iin -- -- 1500 mA output current

Iout

adj:0v( min.)

(min)

Output current

Iout

adj.:5 v(max.)

(max)

Frequency

6.

H.V open H.V Load

FUNCTION LOAD CIRCUIT:

F 40

Vopen

Vload

80K• 10•

10•

2

CON1

1 2 3 4 5

10.8 12 13.2 V

2.2

8.1

2.5

8.5

2.8

8.9

mA

45 50 KHZ

1600 1750 1900 Vrms

460 560 660 Vrms

FOR 1 CCFL LOAD:80K•

NO LOAD RL=80K•

1

80K•

VT

PIN SYMBOL

1 Vin 12V 2 GND 3 ON/OFF 4 Dimming 5 N.C

VT

8.PART LIST

8-1 COMPONENTS LIST:

NO. REF. PART NAME PART NUMBER QTY DESCRIPTION SUPPLIER REMARK

1. CON1 CONNECTOR VCNCP0015-EJSTA 1 S5B-PH-SM3-TB JST

2. CON2,3

3. R1,2,19

4. R3,4,

5. R5,6

,20

•

RESISTOR VRMCNV8--133F-A 4 SMD 0805 13K• 1% YAGEO

•

VCNCP0012-ZJSTA

VCNCP0012-ZGLEA

VRMCNV8--273F-A 2 SMD 0805 27K• 1% YAGEO VRMCNV8--302F-A 2 SMD 0805 3K• 1% YAGEO

2 SM02(8.0)B.BHS-1-TB

GL SM02(8.0)-WH2

JST

GEAN-LEA

6. R7,8,

7. R9,10

8. R11,12,

9. R13,14

10. R15,16

11. R17,18

12. R21,22

13. R27

14. R28,29

15. R33

16. R31,32

17. R23,24, 25,26

18. Q1 TRANSIST0R VSTDTC114EKA--A 1 SMD DTC114EKA ROHM

19. Q2

20. Q3,5

21. Q4,6

22. Q7,8,9,

10

23. C1,2 CAPACITOR VCLFCN1EY224Z-A 2 SMD 0805 0.22 µF/25V TDK

24. C3,4,7, 16,17

•

VRMCNV8--243F-A 2 SMD 0805 24K• 1% YAGEO VRMCNV8--222F-A 2 SMD 0805 2.2K• 1% YAGEO VRMCNV8--112F-A 2 SMD 0805 1.1K• 1% YAGEO VRMCNV8--432F-A 2 SMD 0805 4.3K• 1% YAGEO VRMCNV8--473F-A 2 SMD 0805 47K• 1% YAGEO VRMCNV8--471F-A 2 SMD 0805 470• 1% YAGEO VRMCNV8--203F-A 2 SMD 0805 20K• 1% YAGEO VRMCNV8--512F-A 1 SMD 0805 5.1K• 1% YAGEO VRMCNV8--393F-A 2 SMD 0805 39K• 1% YAGEO VRMCNV8--822F-A 1 SMD 0805 8.2K• 1% YAGEO VRMCNV8--102F-A 2 SMD 0805 1K• 1% YAGEO

VRMBNV4--102F-A 4 SMD 1206 1K• 1% YAGEO

VSTDTA114EKA--A 1 SMD DTA114EKA ROHM

VSTSST3904----A VSTMMBT3904-A

VST2SJ503------A 2 SMD 2SJ503 SANYO VST2SD2150----A 4 SMD 2SD2150 ROHM

VCLFCN1EY105Z-A 5 SMD 0805 1 µF/25V TDK

2 SMD SST3904-T116

SMD MMBT3904

ROHM

MOTOROLA

8-2 COMPONENTS LIST:

NO. REF. PART NAME PART NUMBER QTY DESCRIPTION SUPPLIER REMARK

25. C5 VCEATU1EC336M--

26. C6 CAPACITOR VCLRCN1HB102K-A 1 SMD 0805 1000PF/50V TDK

27 C10,11

28. C12,13

•

29 C14,15

30. C9

31. C20

32. D1,2 DIODE VSDRLS4148----A

33. D3,4

34. D5,6

35. D7,8

36. I.C I.C VSITL1451ACNS-A 1 SMD TL1451ACNS TEXAS

37. F1 FUSE QFS-N202FIDZD-A

38. L1,2 COIL RCHOL0005ID121A

39 PT1,2 TRANS RCVT-2010ID-Z-A 2 SMD YST-2010 YST Attachment 2

PCB PCB QPWBGL023IDLF-- 1 QPWBGL023IDLF-- EISO

•

VCEATU1VC476M--

VCEBCU1EC107M--

VCLRCN1EB333K-A 2 SMD 0805 0.033

VCMEBF2AB184J-P VCMECF2AC184J-P VCMPHF2AG184--P

VCDSEU3SL220K-- 2 DIP 22PF/3KV 10% TDK VCLRCN1EB104K-A 1 SMD 0805 0.1 µF/25V TDK VCLFCN1CY225Z-A 1 SMD 0805 2.2µF/25V TDK

VSDLL4148-----A

VSDRB160L40---A

VSDB140-------A

VSZRLZ9.1B-----A 2 SMD RLZ9.1B ROHM

VSDDA204K-----A VSDBAV99-7----A

QFS-Z202FIDZD-A

RCHOL0005ID121-

DIP UGX 33 µF/25V

1

DIP UGX 47 µF/35V

1

DIP NK-CON 00µF/25V

1

µF/25V

2 DIP 0.18µF/100V

DIP 0.18µF/100V DIP 0.18µF/100V

2 SMD RLS4148

SMD LL4148

2 SMD RB160L40

SMD B140

2 SMD DA204K

SMD BAV99-7

1 SMD FUSE 2.0A/63

SMD FUSE 2.0A/63

2 DIP 120µH 10%

DIP 120µH 10%

SANYO SANYO

NK-CON

TDK

ARCO

THOMSON

TAIWAN TAI

ROHM

VISHAY

ROHM

DIODES

ROHM

DIODES

LITTLE BUSSMANN

YST

• •

LONGMAW

••

Attachment (FEC1Q2) Attachment 1

9. TROUBLE SHOOTING

9-1 NO POWER:

CHECK ON FUSE

. FAIL

F1 Vin=12

PASS FAIL

TO CHECK ON Q4&Q6 Vduot = 9 V

PASS

TO CHECK ON L1&L2 INPUT 9V TO L1 OR L2

FAIL

TO CHANGE F1= 2.0A/63Z

TO CHANGE L: Q4&Q3&D1 R: Q5&Q6&D2

TO CHANGE L: Q7&Q8&C12&PT1 R: Q9&Q10&C13&PT2

PASS

FUNCTION TEST OK!

9-2 HIGHT VOLTAGE PROTECTION:

1. SHORT R30 OPEN LOAD

FAIL

2. TEST C14 INPUT POINT

PASS

VOLTAGE Vh=1750 ±150V rms

TO CHANGE ON PT1 OR PT2

FUNCTION TEST OK!

9-3 OUTPUT CURRENT ABNORMALITY:

FAIL

1. CHECK ON C6 FREQUNCY

PASS

&CHIP&IC CPIP

2. OSCILLATOR FREQUNCY RANGE = 100 ~ 250 KHZ

TO CHANGE ON C6 CHIP OR IC CHIP

FUNCTION TEST OK!

9-4. ENABLE

ABNORMALITY:

IF ENBALE ABNORMALITY

1. TO CHECK IC PIN 9 TURN NO HAVE 12 VOLTAGES

FAIL

PASS

9-5 DIMMING CONTROL ABNORMALITY:

IF DIMMING ABNORMALITY TO CHECK R1&R2&C6 HAVR BREAK

FAIL

TO CHANGE ON Q1&Q2

FUNCTION TEST OK!

TO CHANGE ON R1 OR R2 OR C6

PASS

FUNCTION TEST OK!

9-6 TRANSFORMER ABNORMALITY:

IF TRANSFORMER ABNORMALITY TO CHECK C3&C4 CHIP OUTLINE OR

FAIL

TRANSFORMER

PASS

10. INSTRUMENTS FOR TEST:

TO CHANGE ON C3&C4 OR TRANSFORMER

FUNCTION TEST OK!

1. DC POWER SUPPLY GPS-3030D

2. AC VTVM VT:-181E

3. DIGITAL MULTIMERTER MODEL-34401

4. HIGHTVOLT PROB MODEL-1137A

5.SCOPE MODEL-V-6545

6. AC mA METER MODEL-2016 (YOKOGAWA)

6 C). ADAPTER-MODULE Trouble shooting chart

The following spec & block-diagram is offer by LINEARITY –COMPANY, for Adapter-module

part number : 80AL15-2-LI

I.) Circuit Construction LAD4212BBL

90-265Vac

INPUT

AC

FILTER

BRIDGE

RECTIFIER

CIRCUITS

SOFT

START

CIRCUIT

SMOTH

an

CAPACITANCES

PWM

CONTROL

IC

TRANSFORMER

PROTECTION

OVER

VOLTAGE

CKT

POWER

MOSFET

RECTIFIER

& FILTER

CK

T

VOLTAGE

and

CURRENT

DETECTOR

CKT

LIMIT POWER CKT

(FEEDBACK CKT

PHOTO

COUPLING

)

12V

OUTPUT

II. ADAPTER MODULE TROUBLE SHOOTING CHART

p

Check Fuse (F01) is broken or destroyed ?

Check all PAD on PCB board was short circuit or cold solder?

Check the polar “+” of BRIDGE Rectifier CKT ( BD01) have DC Voltage around = 1.414 * AC Input voltage

Check IC3842 pin 7 have a voltage ?

a). Replace U04 Photo-coupler b). Replace U05 TL431 c). Replace U06 NPN945 d). Replace Q01 PNP733

Check the limitation Resistor R09 is open or wrong component insertion or cold-solder?

Check the feedback resistor R08=1Kohm had open or coldsolder?

Check the trigger Resistor R15=47 ohm had open or coldsolder?

Check the Power Mos (K2645) had broken, short circuit or o

en ?

Check diode D13 is broken ,short circuit or open ?

BD01 broken

a).IC3842 broken b).Start-up Resistor R05 (200K/2W) had open or

broken c).U03 SCR broken d).Replace U01 SCR e).EYE inspection polar of C04 is correct ? or

wrong polar insertion ?

Replace or resolder

IV. ADAPTER BOM LIST ( PART no. 80AL15-2-LI)

Location Description Location Description Location Description

R 01 CFR 1 M• R 03 MOFR 91K R 04 CFR 510K R 05 MOFR 200K R 06 CFR 750K R 07 CFR 750K

R 08 CFR 1 K R 09 MOFR 0.56 R 10 CFR 4.7K• R 11 CFR 4.7K R 12 CFR 3.9K R 13 CFR 47K R 14 CFR 1K R 15 CFR 47R R 16 CFR 20K R 17 CFR 2.7K R 18 CFR 300• R 19 MFR 4.32K R 20 MFR 1.07K R 21 CFR 20K R 22 CFR 510K

R 23 CFR 24R R 24 CFR 1KR R 26 CFR 1KR R 27 CFR 2KR NTC NT C 16R

C 01 SC ×2 0.22• C 02 EC 120• C 04 EC 47• C 05 CC 104P C 06 CC 472P C 07 PC 682P

C 08 CC 102P C 09 CC 104P C 10 CC 104P C 11 CC 104P C 12 CC 103P C 13 CC 104P C 14 CC 472P C 17 CC 332P C 18 EC 1000• C 19 EC 1000• C 21 Y1 101P C 23 Y1 222P C 24 CC 104P C 26 Y2 222P C 27 Y2 222P

D 01 FR 107 D 02 1N 4148 D 03 ZENER D 05 FR107 D 13 N90F10P10Q

U 01 SCR IC U 02 UC3842BN U 03 SCR IC U 04 TCET1103 PC-817 U 05 TL431 U 06 NPN 945 F 01 B 02 B 04 B 05 L 03

BD 01 BRIDGE KBP206

V 01 T 01 T 02

Q 1 Q 2

N152FIDZD Bead Bead Bead Bead

Varistor Filter Transformer 2SA733 125mW 2SK2645

GMZAN1

The gmZAN1device utilizes Genesis’ patented third-generation Advanced Image Magnification technology as well as a proven integrated ADC/PLL to provide excellent image quality within a cost effective SVGA/XGA LCD monitor solution. As a pin-compatible replacement for the gmB120, the gmZAN1 incorporates all of the gmB120 features plus many enhanced features; including 10-bit gamma correction, Adaptive Contrast Enhancement (ACE) filtering, Sync On Green (SOG), and an enhanced OSD.

1.1 Features

!

Fully integrated 135MHz 8-bit triple-ADC, PLL, and pre-amplifier

!

GmZ2 scaling algori thm featuring new Adaptive Contra st Enhancement (ACE)

!

On-chip programmable OSD engine

!

Integrated PLLs

!

10-bit programmable gamma correction

!

Host interface with 1 or 4 data bits

!

Pin-compatible with gmB120

Integrated Analog Front End

!

Integrated 8-bit triple ADC

!

Up to 135MHz sampling rates

!

No additional components needed

!

All color depths up to 24-bits/pixel are supported

High-Quality Advanced Scaling

!

Fully programmable zoom

!

Independent horizontal / vertical zoom

!

Enhanced and adaptive scaling algorithm for optimal image quality

!

Recovery Mode / Native Mode

Input Format

!

Analog RGB up to XGA 85Hz

!

Support for Sync On Green (SOG)

!

Support for composite sync modes

Output Format

!

Support for 8 or 6-bit panels (with high quality dithering)

!

One or two pixel output format

Built In High-Speed Clock Generator

!

Fully programmable timing parameters

!

On-chip PLLs generate clocks for the on-chip ADC and pixel clock from a single reference oscillator

Auto-Configuration / Auto-Detection

!

Phase and image positioning

!

Input format detection

Operation Modes

!

Bypass mode with no filtering

!

Multiple zoom modes:

#

With filtering

#

With adaptive (ACE) filtering

Integrated On-Screen Display

!

On-chip character RAM and ROM for better customization

!

External OSD supported for greater flexibility

!

Supports both landscape and portrait fonts

!

Many other font capabilities including: blinking, overlay and transparency

1.3 Pin Description

Unless otherwise state d, unused input pins must be tied to ground, and unused output pins left open.

Table 1 : Analog-to-Digital Converter

PIN #

77 ADC_VDD2

78 ADC_GND2

79 ADC_VDD1

80

81 SUB_GNDA

82 ADC_GNDA

84 ADC_VDDA

83 Reserved 85 ADC_BGNDA

88 ADC_BVDDA

86 BLUE- I 87 BLUE+ I 89 ADC_GGNDA

92 ADC_GVDDA

90 GREEN- I 91 GREEN+ I 93 ADC_RGNDA

96 ADC_RVDDA

94 RED- I 95 RED+ I

Name

ADC_GND1

I/O Description

Digital power for ADC encoding logic. Must be bypassed with 0.1uF capacito r to pin 78 (ADC_GND2) Digital GND for ADC encoding logic. Must be directly connected to the digital system ground plane. Digital power for ADC clocking circuit. Must by passed with 0.1uF capacitor to pin 80 (ACD_GND1). Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground plane. Dedicated pin for substrate guard ring that protects the ADC reference system. Must be directly connected to the analog system ground plane. Analog ground for ADC analog blocks that are shared by all three channels. Includes bandgap reference, master biasing and full scale adjust. Must be directly connected to analog system ground plane. Analog power for ADC analog blocks that are shared by all three channels. Includes bandgap reference, master biasing and full scale adjust. Must be bypassed with 0.1uF capacitor to pin 82 (ADC_GNDA). For internal testing purpose only. Do not connect.

Analog ground for the blue channel. Must be directly connected to the analog system ground plane. Analog power for the blue channel. Must be bypassed with 0.1uF capacitor to pin 85(BGNDA). Negative analog input for the Blue channel.

Positive analog input for the Blue channel. Analog ground for the green channel. Must be directly connected to the analog

system ground plane. Analog power for the green channel. Must be bypassed with 0.1uF capacitor to pin 89 (ADC_GGNDA). Negative analog input for the Green channel.

Positive analog input for the Green channel. Analog ground for the red channel. Must be directly connected to the analog

system ground plane. Analog power for the red channel. Must be bypassed with 0.1uF capacitor to pin 93 (ADC_RGNDA).

Negative analog input for the Red channel. Positive analog input for the Red channel.

Table 2 : Host Interface (HIF) / External On-Screen Display

PIN #

98 HFS I

103 HCLK I

99 HDATA I/O 100 RESETn I 101 IRQ O 115 OSD-HREF O 116 OSD-VREF O 117 OSD-Clk O 118 OSD-Data0 I 119 OSD-Data1 I 120 OSD-Data2 I 121 OSD-Data3 I 122 OSD-FSW I

123 MFB11 I/O 124 MFB10 I/O 102 MFB9 I/O

104 MFB8 I/O

105 MFB7 I/O

106 MFB6 I/O

107 MFB5 I/O

109 MFB4 I/O 110 MFB3 I/O 111 FMB2 I/O 112 MFB1 I/O 113 MFB0 I/O

Name

I/O Description

Host Frame Sync. Frames the packet on the serial channel. Clock signal input for the 3-wire serial communication. Data signal for the 3-wire serial communication. Resets the gmZAN1 chip to a known state when low. Interrupt request output. HSYNC output for an external OSD controller chip. VSYNC output for an external OSD controller chip. Clock output for an external OSD controller chip. Data input 0 from an external OSD controller chip. Data input 1 from an external OSD controller chip. Data input 2 from an external OSD controller chip. Data input 3 from an external OSD controller chip.

External OSD window display enable. Displays data from external OSD controller when high.

Multi-Function Bus 11. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 10. One of twelve multi-function signals MFB[11:0].

Multi-Function Bus 9. One of twelve multi-function signals MFB[11:0]. Also used as HDATA3 in a 4-bit host interface configuration. Multi-Function Bus 8. One of twelve multi-function signals MFB[11:0]. Also used as HDATA2 in a 4-bit host interface configuration. Multi-Function Bus 7. One of twelve multi-function signals MFB[11:0]. Also used as HDATA1 in a 4-bit host interface configuration. Multi-Function Bus 6. One of twelve multi-function signals MFB[11:0]. Internally pulled up. When externally pulled down (sampled at reset ) the host interface is configured for 4 bits wide. In this configuration, MFB9:7 are used as HDATA 3:1. Multi-Function Bus 5 One of twelve multi-function signals MFB[11:0]. Internally pulled up. When externally pulled down (sampled at reset ) the chip uses an external crystal resonator across pins 141 and 142, instead of an oscillator.

Multi-Function Bus 4. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 3. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 2. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 1. One of twelve multi-function signals MFB[11:0]. Multi-Function Bus 0. One of twelve multi-function signals MFB[11:0].

Table 3 : Clock Recovery / Time Base Conversion

PIN #

125 DVDD

127 DAC_DGNDA

128 DAC_DVDDA

129 PLL_DVDDA

130 Reserved 131 PLL_DGNDA

132 SUB_DGNDA

133 SUB_SGNDA

134 PLL_SGNDA

135 Reserved 136 PLL_SVDDA

137 DAC_SVDDA

138 DAC_SGNDA

139 SVDD 141 TCLK I Reference clock(TCLK) input from the 50 MHz crystal oscillator

142 XT AL O If using an external oscillator, leave this pin floating. If using an external crystal,

143 PLL_RVDDA Analog power for the Reference DDS PLL. Must be bypassed with a 0.1uF

144 PLL_RGNDA Analog ground for the Reference DDS PLL. Must be directly connected to the

145 Reserved For testing purposes only. Do not connect. 146 SUB_RGNDA Dedicated pin for the substrate guard ring that protects the Reference DDS. Must

148 VSYNC I CRT Vsync input. TTL Schmitt trigger input. 149 SYN_VDD Digital power for CRT Sync input. 150 HSYNC/CSYNC I CRT Hsync or CRT composite sync input. TTL Schmitt trigger input.

Name

I/O Description

Digital power for Destination DDS (direct digital synthesizer). Must be bypassed with a 0.1uF capacitor to digital ground plane. Analog ground for Destination DDS DAC. Must be directly connected to the analog system ground plane. Analog power for Destination DDS DAC. Must be bypassed with a 0.1uF capacitor to pin 127 (DAC_DGNDA). Analog power for the Destination DDS PLL. Must be bypassed with a 0.1uF capacitor to pin 131 (PLL_DGNDA).

For testing purposes only. Do not connect. Analog ground for the Destination DDS PLL. Must be directly connected to the

analog system ground plane. Dedicated pin for the substrate guard ring that protects the Destination DDS. Must be directly connected to the analog system ground plane. Dedicated pin for the substrate guard ring that protects the Source DDS. Must be directly connected to the analog system ground plane. Analog ground for the Source DDS PLL. Must be directly connected to the analog system ground.

For testing purposes only. Do not connect. Analog power for the Source DDS DAC. Must be bypassed with a 0.1uF

capacitor to pin 134 (PLL_SGNDA) Analog power for the Source DDS DAC. Must be by passed with a 0.1uF capacitor to pin 138 (DAC_SGNDA) Analog power for the Source DDS DAC. Must be directly connected to the analog system ground. Digital power for the Source DDS. Must be bypassed with a 0.1uF capacitor to digital ground plane.

connect crystal between TCLK(141) and XTAL(142). See MFB5(pin 107).

capacitor to pin 144(PLL_RGNDA)

analog system ground plane.

be directly connected to the analog system ground plane.

Table 4. TFT Panel Interface

PIN #

6 PD47 O OB1 - - -

7 PD46 O OB0 - - -

9 PD45 O OG1 - - 10 PD44 O OG0 - - 13 PD43 O OR1 - - 14 PD42 O OR0 - - 15 PD41 O EB1 - B1 16 PD40 O EB0 - B0 17 PD39 O EG1 - G1 19 PD38 O EG0 - G0 20 PD37 O ER1 - R1 22 PD36 O ER0 - R0 23 PD35 O OB7 OB5 - 24 PD34 O OB6 OB4 - 25 PD33 O OB5 OB3 - 26 PD32 O OB4 OB2 - 27 PD31 O OB3 OB1 - 28 PD30 O OB2 OB0 - 29 PD29 O OG7 OG5 - 31 PD28 O OG6 OG4 - 32 PD27 O OG5 OG3 - 34 PD26 O OG4 OG2 - 35 PD25 O OG3 OG1 - 36 PD24 O OG2 OG0 - 37 PD23 O OR7 OR5 - 38 PD22 O OR6 OR4 - 39 PD21 O OR5 OR3 - 42 PD20 O OR4 OR2 - 46 PD19 O OR3 OR1 - 47 PD18 O OR2 OR0 - 48 PD17 O EB7 EB5 B7 B5 50 PD16 O EB6 EB4 B6 B4 51 PD15 O EB5 EB3 B5 B3 52 PD14 O EB4 EB2 B4 B2 53 PD13 O EB3 EB1 B3 B1 54 PD12 O EB2 EB0 B2 B0 55 PD11 O EG7 EG5 G7 G5 56 PD10 O EG6 EG4 G6 G4 57 PD9 O EG5 EG3 G5 G3 62 PD8 O EG4 EG2 G4 G2

Name

I/O

2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk

8bit 6-bit 8-bit 6-bit TFT

Description

PIN #

63 PD7 O EG3 EG1 G3 G1 64 PD6 O EG2 EG0 G2 G0 66 PD5 O ER7 EG5 R7 R5 67 PD4 O ER6 ER4 R6 R4 68 PD3 O ER5 ER3 R5 R3 69 PD2 O ER4 ER2 R4 R2 70 PD1 O ER3 ER1 R3 R1 71 PD0 O EG2 ER0 R2 R0 43 P dispE O This output provides a panel display enable signal that is active when flat panel

74 PHS O This output provides the panel line clock signal. 73 PVS O This output provides the frame start signal. 44 PCLKA O This output is used to drive the flat panel shift clock. 45 PCLKB O Same as PCLKA above.

75 Pbias O This output is used to turn on/off the panel bias power or controls backlight. 76 Ppwr O This output is used to control the power to a flat panel.

Name

I/O

2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk

8bit 6-bit 8-bit 6-bit TFT

data is valid.

The polarity and the phase of this signal are independently programmable.

Description

Table 5. Test Pins

PIN # Name I/O Description

3 PSCAN I

155 SCAN_IN1 I 157 SCAN_IN2 I 159 SCAN_OUT1 O 160 SCAN_OUT2 O 153 Reserved 154 Reserved

Enable automatic PCB assembly test. When this input is pulled high, the automatic PCB assembly test mode is entered. An internal pull-down resistor drives this input low for normal operation.

Scan input 1 used for automatic PCB assembly tesing. Scan input 2 used for automatic PCB assembly tesing. Scan output 1 used for automatic PCB assembly tesing. Scan output 2 used for automatic PCB assembly tesing.

Table 6. VDD / VSS for Core Circuitry, Host Interface, and Panel/Memory Interface

PIN # Description

65, 40, 33, 12

149, 108, 58, 21, 11

158, 151, 140, 126, 114, 72, 61, 49, 41, 30, 18, 8, 1

PVDD4~PVDD1 for panel / memory interface. Connect to +3.3V. Must be the same voltage as the CVDD’s SRVDD2-1, CVDD4, CVDD2-1 for core circuitry. Connect to +3.3V. Must be the same voltage as the PVDD’s.

Digital grounds for core circuiry and panel / memory interface.

1.4 System-level Block Diagram

ADC_VDD

ADC_GND

R1RR1RR1

R

Red Blue Green

R1RR1 R

L1

Video Connector

L2

RVDDA

Hsync Vsync

C1 C

C2 C

To Clock Generator

On-Screen Display Controller

R+,G+,B+

4

OSD-FSW OSD-FSW OSD-CLK

OSD-HREF OSD-VREF

MPU with EPROM

MFBs

RESETn

IRQ HES HCLK

HDATA

12

Figure 2. Typical Stand-alone Configuration

gmZAN1 Core

ADC

Host Interface

CVDD

CVSS

RVDDA

RGNDA

TCLK

Clock Generator

24

Pbias

Panel Interface

Pbias

SVDDA

SGNDA

DVDDA

DGNDA

Even Data

PCLKA

PHS PVS PDISPE

Odd Data

24

Power

Power Switching

Switching Module

Module

OSC

+5/3.3V

TFT Panel

+12V

1.5 Operating Modes

The Source Clock (also called SCLK in this document) and the Panel Clock are defined as follows:

!

The Source Clock is the sample clock regenerated from the input Hsync timing (called clock recovery) by SCLK DDS (direct digital synthesis) and the PLL.

!

The Panel Clock is the timing clock for panel data at the single pixel per clo ck rate. The actual PCLK to the panel may be one-half of this frequency for double-pixel panel data format. When its frequency is different from that of source clock, the panel clock is generated by Destination Clock (or DCLK) DDS/PLL.

There are six display modes: Native, Slow DCLK, Zoom, Downscaling, Destination Stand Alone, and Source Stand Alone. Each mode is unique in terms of:

!

Input video resolution vs. panel resolution

!

Source Clock frequency / Panel Cloc k frequency ratio

!

Source Hsync frequency / Panel Hsync freque nc ratio

!

Data source (analog RGB, panel background color, on-chip pattern generator

1.5.1 Native

Panel Clock frequency = Source Clock frequency

Panel Hsync frequency = Input Hsync frequency

Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is the same as the panel resolution and the input data clock frequency is within the panel clock frequency specification of the panel being used.

1.5.2 Slow DCLK

Panel Clock frequency < Source Clock frequency

Panel Hsync frequency = Input Hsync frequency

Panel Vsync frequency = Input Vsync frequency

This mode is used when the input re solution is the sa me as the panel resol ution, but the i nput data clock freque ncy is exceeds the panel clock frequency specification of the panel being used. The panel clock is scaled to the Source Clock, and the internal data buffers are used to spread out the timing of the input data by making use of the large CRT blanking time to extends the panel horizontal display time.

1.5.3 Zoom

Panel Clock frequency > Source Clock frequency

Panel Hsync frequency > Input Hsync frequency

Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is less than the panel resolution. The input data clock is then locked to the pnael clock, which is at a higher frequency. The input data is zoomed to the panel resolution.

1.5.4 Downscaling

Panel Clock frequency < Source Clock frequency Panel Hsync frequency < Input Hsync frequency Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is greater than the panel resolution, to provide enough of a display to enable the user to recover to a supported resolution. The input clock is operated at a frequency less than that of the input pixel rate(under-sampled horizontally) and the scaling filter is used to drop input lines. In this mode, zoom scaling must be disabled

1.5.5 Destination Stand Alone

Panel Clock = DCLK in open loop (not locked) Panel Hsync frequency = DCLK frequency / (Destination Htotal register value) Panel Vsync frequency = DCLK frequency / (Dest. Htotal register value * Dest. Vtotal register value)

This mode is used when the input is changing or not a vailable. The OSD may still be used as in all other display modes and stable panel timing signals are produced. This mode may be automatically set when the gmZAN1 detects input timing changes that could cause out- of-spec operation of the panel.

1.5.6 Source Stand Alone

Panel Clock = DCLK in open loop (not locked to input Hsync) Panel Hsync frequency = SCLK frequency / (Source Htotal register value) Panel Vsync frequency = SCLK frequency / (Source Htotal register value *Source Vtotal register value)

This mode is used to display the pattern generator data. This mode may be useful for testing an LCD panel on the manufacturing line (color temperature calibration, etc.).

2. FUNCTIONAL DESCRIPTION

Figure 3 below shows the main functional blocks inside the gmZAN1

2.1 Overall Architecture

Figure 3. Block Diagram for gmZAN1

On-Screen Display Control

Analog RGB

Triple ADC

Source Timing Measurement / Generation

Scaling Engine

Gamma Control (CLUT) + Dither

Panel Timing Control

Panel

MCU

Host Interface

Clock Recovery

Pixel Clock Generator

Clock Reference

2.2 Clock Recovery Circuit

The gmZAN1 has a built-in clock recovery circuit. This circuit consists of a digital clock synthesizer and an analog PLL. The clock recovery circuit generates the clock used to sample analog RGB data (SCLK or source clock). This circuit is locked to the HSUNC of the incoming video signal. The RCLK generated from the TCLK input is used as a reference clock.

The clock recovery circuit adjusts the SCLK period so that the feedback pulse generated every SCLK period multiplied by the Source Horizontal To tal value (as programmed into the registers) locks to the rising edge of the Hsync input. Even though the initial SCLK frequency and the final SCLK frequency are as far apart as 60MHz , locking can be achieved in less than 1ms across the operation voltage/temperature range.

The SCLK frequency (1/SCLK period) can be set to the range of 10-to-135 MHz. Using the DDS (direct digital

p

synthesis) technology the clock recovery cir cuit can generate any SCLK clock frequency within this range.

The pixel clock (DCLK or destination clock) is used to drive a panel when the panel clock is different from SCLK (or SCLK/2). It is generated by a circuit virtually identical to the clock recovery circuit. The difference is that DCLK is locked to SCLK while SCLK is locked to the Hsync input. DCLK frequency divided by N is locked to SCLK frequency divided by M. The value M and N are calculated and programmed in the register by firmware. The value M should be close to the Source Htotal value.

Figure 4. Clock Recovery Circuit

Hsync

Sample

Phase

Delay

DDS Digital

Clock

Synthesis

Course

Adjust

DDS Output

Analog

PLL & VCO

VCO

Out

ut

Clock

Divider

÷ n

SCLK

Fine

Adjust

PLL

Divider

÷

Prescaler ÷ 2 (or 1)

Source

Horizontal

Total Divider

TCLK

Analog

PLL & VCO

Post Scale

÷ 2 (or 1)

RCLK

PLL Divider

÷

PLL Divider

÷

The table below summarizes the characteristics of the clock recovery circuit.

Table 7. Clock Recovery Characteristics

Minimum Typical Maximum

SCLK Frequency 10MHz 135 MHz Sampling Phase Adjustment 0.5 ns/step, 64 steps

Patented d igital clock synt hesis technology makes the gmZAN1 clock circuits very immune to t emperature/volta ge drift.

2.2.1 Sampling Phase Adjustment

The ADC sampling phase is adjusted by delaying the Hsync input at the programmable delay cell inside the gmZAN1. The delay value can be adjusted in 64 steps, 0.5 ns/step. The accuracy of the sampling phase is checked by the gmZAN1 and the “score” can be read in a register. This feature will enable accurate auto-adjustment of the ADC sampling phase.

2.2.2 Source Timing Generator

The STG module defines a capture window and sends the input data to the data path block. The figure below shows how the window is defined. For the horizontal direction, it is defined in SCLKs (equivalent to a pixel count). For the vertical direction, it is defined in lines. All the parameters in the figure that begin with “Source” are programmed into the gmZAN1 registers. Note that the vertical total is solely determined by the input. The reference point is as follows:

!

The first pixel of a line: the pixel whose SCLK risin g edge sees the transition o f the HSYNC polarity fro m low to high.

!

The first line of a frame: the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to high.

The gmZAN1 also supports the use of analog composite sync and digital sync signals as described in Section 2.3.2

Figure 5. Capture Window

Reference Point

Source Hstart

Source

Vstart

Source Height

Source Vertical Total (lines)

Source Horizontal Total (pixels)

Source Width

Capture Window

2.3 Analog-to-Digital Converter

2.3.1 Pin Connection

The RGB signals are to be connected to the gmZAN1 chip as described in Table 8 and Table 9.

Table 8. Pin Connection for RGB Input with Hsync/Vsync

GmZAN1 Pin Name (Pin Number) CRT Signal Name

Red+(#95) Red Red- (#94) N/A (Tie to Analog GND for Red on the board) Green+(#91) Green Green- (#90) N/A (Tie to Analog GND for Green on the board) Blue+(#87) Blue Blue- (#86) N/A (Tie to Analog GND for Blue on the board) HSYNC/CS (#150) Horizontal Sync VSYNC (#148) Vertical Sync

Table 9. Pin Connection for RGB Input with Composite Sync

GmZAN1 Pin Name (Pin Number) CRT Signal Name

Red+(#95) Red Red- (#94) N/A (Tie to Analog GND for Red on the board) Green+(#91) Green

When using Sync-On-Green this signal also carries the sync pulse. Green- (#90) N/A (Tie to Analog GND for Green on the board) Blue+(#87) Blue Blue- (#86) N/A (Tie to Analog GND for Blue on the board) HSYNC/CS (#150) Digital composite sync. Not applicable for Sync-On-Green

The gmZAN1 chip has three ADC’s (analog-to-digital converters), one for each color (red, green, and blue). Table 10 summarizes the characteristics of the ADC.

Table 10. ADC Characteristics

MIN TYP MAX NOTE

RGB Track & Hold Amplifiers

Band Width 160MHz Settling Time to 1/2% 8.5ns Full Scale Input = 0.75V, BW=160MHz(*) Full Scale Adjust Range @ R,G,B Inputs 0.45V 0.95V Full Scale Adjust Sensitivity +/-1 LSB Measured @ ADC Output (**) Zero Scale Adjust Range For a larger DC offset from an external

video source, the AC coupling feature is used to remove the offset.

Zero Scale Adjust Sensitivity +/-1 LSB Measured @ ADC Output

ADC+RGB Track & Hold Amplifiers

Sampling Frequency (fs) 20MHz 110MHz DNL +/- 0.9LSB fs = 80 MHz INL +/- 1.5LSB fs = 80 MHz Channel to Channel Matching +/- 0.5LSB Effective Number of Bits (ENOB) 7 Bits fin = 1MHz, fs=80 MHz Vin= -1db below

full scale=0.75V Power Dissipation 400mW fs=110 MHz, Vdd=3.3V Shut Down Current 100uA (*) Guaranteed by design (**) Independent of full scale R,G,B input

The gmZAN1 ADC has a built-in clamp circuit. By inserting series capacitors (about 10 nF) the DC offset of an external video source can be removed. The clamp pulse position and width are programmable.

2.3.2 Sync. Signal Support

The gmZAN1 chip supports digital separate sync (Hsync/Vsync), digital composite sync, and analog composite sync (also known as sync-on-green). All sync types are supported without external sync separation / extraction circuits.

Digital Composite Sync

The types of digital composite sync inputs supported are:

!

OR/AND type: No Csync pulses toggling during the vertical sync period

!

XOR type: Csync polarity changes during the vertical sync period

The gmZan1 provides enough sync status information for the firmware to d etect the digital c omposite sync type.

Sync-On-Green (Analog Composite Sync)

The voltage level of the sync tip during the vertical sync period can be either –0.3V or 0V

2.3.3 Display Mode Support

A mode calculation utility (MODECALC.EXE) provided by Genesis Microchip may be run before compilation of the firmware to determine which input modes can be supported. Refer to firmware documents for more details.

2.4 Input Timing Measurement

As described in section 2.2.2 above, input data is sent from the analog-to-digital converter to the source timing generator ( S TG) block. The STG block defines a capture window (Figur e5).

The input timing measurement block consists of the source timing measurement (STM) block and interrupt request (IRQ) controller. Input timing parameters are measured by the STM block and stored in registers. Some input conditions will generate an IRQ to an external micro-controller. The IRQ generating conditions are programmable.

2.4.1 Source Timing Measurement

When it receives the active CRT signal (R,G,B and Sync signals) the Source Timing Measurement unit begins measuring the horizontal and vertical timing of the incoming signal using the sync signals and TCLKi as a reference. Horizontal measurement occurs by measuring a minimum and a maximum value for each parameter to account for TCLKi sampling granularity. The measured value is updated every line. Vertical parameters are measured in terms of horizontal lines. The trailing edge of the Hsync input is used to check the polarity of the Vsync input. The table below lists all the parameters that may be read in the source timing measurement (STM) registers of the gmZAN1.

Table 11. Input Timing Parameters Measured by the STM Block

Parameter Unit Updated at:

HSYNC Missing N/A Every 4096 TCLKs and every 80ms (2-bits) VSYNC Missing N/A Every 80ms HSYNC/VSYNC Timing Change N/A When the horizontal period delta or the vertical

period delta to the previous line / frame exceeds the

threshold value (programmable). HSYNC Polarity Positive/Negative After register read VSYNC Polarity Positive/Negative Every frame Horizontal Period Min/Max TCLKs and SCLKs After register read HSYNC High Per iod Min/Max TCLKs After register read Vertical Period Lines Every frame VSYNC High Period Lines Every frame Horizontal Display Start SCLKs Every frame Horizontal Display End SCLKs Every frame Vertical Display Start Lines Every frame Vertical Display End Lines Every frame Interlaced Input Detect N/A Every frame CRC Data/Line Data N/A Every frame CSYNC Detect N/A Every 80ms

The display start/end registers store the first and the last pixels/lines of the last frame that have RGB data above a

8

programmed threshold. The reference point of the STM block is the same as that of the source timing generator (STG) block:

!

The first pixel: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high.

!

The first line: the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to high.

The CRC data and the line data are used to detect a test pattern image sent to the gmZAN1 input port.

2.4.2 IRQ Controller

Some input timing conditions can cause the gmZAN1 chip to generate an IRQ. The IRQ-generating conditions are programmable, as given in the following table.

Table 12. IRQ-Generation Conditions

IRQ Event Remark

Timing Event One of the three events:

!

Leading edge of Vsync input,

!

Panel line count (the line count is programmable),

!

Every 10ms

Only one event may be selected at a time.

Timing Change Any of the following timing changes:

!

Sync loss,

!

DDS tracking error beyond threshold,

!

Horizontal/vertical timing change beyond threshold

Threshold values are programmable.

Reading the IRQ status flags will not affect the STM registers. Note that if a new IRQ event occurs while the IRQ status register is being read, the IRQ signal will become inactive for minimum of one TCLK period and then get re-activated. The polarity of the IRQ signal is programmable.

2.5 Data Path

The data path block of gmZAN1 is shown in Figure 6.

Figure 6. gmZAN1 Data Path

Sampled Data

(or from

pattern

generator

Scaling

Filter

Gamma

Table

10

RGB

Offset

Panel Dither

Background

Color

Internal

OSD

External

OSD

Data

8 or 6

1

0 S

1

0 S

8 or 6

1

0 S

Panel Data

2.5.1 Scaling Filter

The gmZAN1 scaling filter uses an advanced adaptive scaling technique proprietary to Genesis Microchip Inc. and provides high quality scaling of real time video and graphics images. This is Genesis’ third generation scaling technology that benefits from the expertise and feedback gained by supporting a wide range of solutions and applications.

2.5.2 Gamma Table

The gamma table is used to adjust the RGB data for the individual display characteristics of the TFT panel. The overall gamma of the display may be set, as well as separate corrections for each of the three display channels. In addition, the gamma table may be used for contrast, brightness, and white balance (temperature) adjustments. The lookup table has an 8-bit input (256 different RGB entries) and produces a 10-bit output.

2.5.3 RGB Offset

The RGB offsets provide a simple shift (positive or negative) for each of the three color channels. This may be used as a simple brightness adjustment within a limited range. The data is clamped to zero for negative offsets, and clamped to FFh for positive offsets. This adjustment is much faster than recalculating the gamma table, and could be used with the OSD user controller to provide a quick brightness adjust. An offset range of plus 127*4 to minus 127*4 is available.

2.5.4 Panel Data Dither

For TFT panels that have fewer than eight bits for each R,G,B input, the gmZAN1 provides ordered and random dithering patterns to help smoothly shade colors on 6-bit panels.

2.5.5 Panel Background Color

A solid backgr ound color may be selected for a bor der around t he active disp lay area. The background color is mo st often set to black.

2.6 Panel Interface

The gmZAN1 chip interfaces directly with all of today’s commonly used active matrix flat panels with 640x480, 800x600 and 1024x768 resolutions. The resolution and the aspect ratio are NOT limited to specific values.

2.6.1 TFT Panel Interface Timing Specification

The TFT panel interface timing parameters are listed in Table 13 below. Refer to three timing diagrams of Figure 7 and Figure 8 for the timing parameter definition. All aspects of the gmZAN1 interface are programmable. For horizontal parameters, Horizontal Display Enable Start, Horizontal Display Enable End, Horizontal Sync Start and Horizontal Sync End are programmable. Vertical Display Enable Start, Vertical Display Enable End, Vertical Sync Start and Vertical Sync End are also fully programmable. In order to maximize panel data setup and hold time, the panel clock (PCLKA, PCLKB) output skew is programmable. In addition, the current drive strength of the panel interface pins is programmable.

Table 13. gmZAN1 TFT Panel Interface Timing

Signal Name Min Typical Max Unit

PVS

Period t1 0 16.67 2048 - lines

ms Frequency 60 - Hz Front porch t2 0 2048 lines Back porch t3 0 2048 lines Pulse width t4 0 2048 lines PdispE t5 0 Panel height 2048 lines Disp. Start from VS t6 0 2048 lines PVS set up tp PHS t18 1 2048 PCLK *1 PVS hold from PHS t19 1 2048 PCLK *1

PHS

Period t7 0 2048 [1024 PCLK *1 Front porch t8 0 2048 PCLK *1 Back porch t9 0 2048 PCLK *1 Pulse width t10 0 2048 PCLK *1 PdispE t11 0 Panel width 2048 [1024] PCLK *1 Disp. Start fom HS t12 0 2048 PCLK *1

PCLKA, PCLKB*4

Frequency t13 120 [60] MHz Clock (H) *2 t14 DCLK/2-3 [DCLK-3] DCLK/2-2 [DCLK-2] ns Clock (L) *2 t15 DCLK/2-3 [DCLK-3] DCLK/2-2 [DCLK-2] ns Type - One pxl/clock

-

[two pxl/clock]

Data

Set up *3 t16 DCLK/2-5 [DCLK-5] DCLK/2-2 [DCLK-2] ns Hold *3 t17 DCLK/2-5 [DCLK-5] DCLK/2-2 [DCLK-2] ns width 3 bits 18 bits [36 bits] 24 bits [48 bits] bits/pixel

NOTE: Numbers in [ ] are for two pixels/clock mode. NOTE: The drive current of the panel interface signals is programmable as shown in Table 1. The drive current is to be

programmed through the API upon chip initialization. Output current is programmable from 2 mA to 20mA in increments of 2 mA. Drive strength should be programmed to match the load presented by the cable and input of the panel. Values shown are based on a loading of 20pF and a drive strength of 8 mA.

NOTE *1: The PCLK is the panel shift clock. NOTE *2: The DCLK stands for Destination Clock (DCLK) period. Is equal to:

-PCLK period in one pixel/clock mode,

-twice the PCLK period in two pixels/clock mode. NOTE *3: The setup/hold time spec. for P CLK also applies to PHS and PdispE. The setup time (t16) and the hold time (t17) listed

in this table are for the case in which no clock-to -dat a skew is added. The PVS/P HS/Pd ispE/Pd ata signals are assert ed o n the rising edge of the P CLK. The polarity of the PCLK and its ske w are programmable. Clock to Data ske w can be adjusted in sixteen 800-ps incremen ts. In combin ation with th e PCLK polarit y inversion, the clock-to -data phase can be adjusted in total of 31 steps.

NOTE *4: The polarity of the PCLKA and the PCLKB are independently programmable.

The micro controller must have all the timing parameters of the panel used for the monitor. The parameters are to be stored in a non-volatile memory. As can be seen from this table, the wide range of timing programmability of the gmZAN1 panel interface makes it possible to support various kinds of panels known today:

Figure 7. timing Diagrams of the TFT Panel Interface (One pixel per clock)

(a) Vertical size in TFT

PVS

PHS

(b) Vsync width and display po sition in TFT

PDE

PVS

PHS

RGBs

(c) Horizontal size in TFT

PHS

PCLK

PDE

RGB data from data paths

(d) Hsync width in TFT

t18

t4

t19

t12

Panel Background Color Displayed

t1

t5t3

t2

t6

t10

t7

t11

t10

t8

t9

t14

t13

t15

t16

Figure 8. Data latch timing of the TFT Panel Interface

(a) Two pixel per c lock mode in TFT

PDE

PCLK

t16

t14

t13

t15

t16

t17

ER

R0,(N:0)

R2,(N:0)

R4,(N:0)

EG

G0,(N:0)

G2,(N:0)

EB

B0,(N:0)

B2,(N:0)

OR

R1,(N:0)

R3,(N:0)

OG

G1,(N:0) G3,(N:0)

(b) One pixel per clock mode in TFT

OB

PDE PCLK

R(n:0

t1

B1,(N:0)

R0

t1

R1

B3,(N:0)

t1

G(n:0

G0

B(n:0

B0

2.6.2 Power Manager

LCD panels require logic power, panel bias power, and control signals to be sequenced in a specific order, otherwise severe damage may occur and disable the panel permanently. T he gmZAN1 has a built in power sequencer (Power Manager) that prevents this kind o f damage. The Power Mana ger controls the p ower up/down seque nces for LCD panel s within the four state s described belo w. See the timing diagram Figure 9.

2.6.2.1 State 0 (Power Off)

The Pbias signal and Ppower signal are low (inactive). The panel controls and data are forced low. This is the final state in the power down sequence. PM is kept in state 0 until the panel is enabled.

2.6.2.2 State 1 (Power On)

Intermediate step 1. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is forced low (inactive).

2.6.2.3 State 2 (Panel Drive Enabled)

Intermediate step 2. The Ppower is high (active), the Pbias is low (inactive), and the panel interface is active.

2.6.2.4 State 3 (Panel Fully Active)

This is the final step in the power up sequence, with Ppower and Pbias high (active), and the panel interface active. PM is kept in this state until the internal TFT_Enable signal controlled by Panel Control register is disabled. The panel can be disabled through either an API call under program control or automatically by the gmZAN1 to prevent damage to the panel.

Figure 9. Panel Power Sequence

In Figure 9 above, t2=t6 and t3=t5. t1,t2,t3 and t4 are independently programmable from one to eight steps in length. The length of each step is in the range of 511 * X* (TCLKi cycle) or (TCLKi cycle) * 32193 *X, where X is any positive integer value equal to or less than 256. TCLKi is the reference clock to the gmZAN1 chip, and ranges from

14.318 MHz to 50 MHz in frequency. This programmability provides enough flexibility to meet a wide range of power sequencing requirements by various panels.

TFT_EN Bit (register bit)

PPWR Output

Data/Controls Signals

PBias Output

t1

t4

t6

t2

t5

t3

2.6.3 Panel Interface Drive Strength

As mentioned previously, the gmZAN1 has programmable output pads for the TFT panel interface. Three groups of panel interface pads (panel clock, data, and control) are independently controllable and are programmed using API calls. See the API reference manual for details.

Table 14. Panel Interface Pad Drive Strength

Value (4 bits) Drive Strength in mA

0 Outputs are in tri-state condition 1 2mA 2 4mA 3 6mA 4 8mA 5 10mA 6 12mA 7 14mA 8 16mA 9 18mA 10,11,12,13,14,15 20mA

2.7 Host Interface

The host microcontroller interface of the gmZAN1 has two modes of operation: gmB120 compatible mode, and a 4bit serial interface mode.

!

GmB120 compatible mode-Four signals consisting of 1 data bit, a frame synchronization signal, a clock signal and an Interrupt Request signal (IRQ). This mode is entered when a pull-down resistor is not connected to MFB6(pin number 106).

!

4-bit serial interface mode-Same as gmB120 compatible mode with the addition of three data bits so that four data bits are transferred on each clock edge. This mode is entered when a (10K ohm) pull-down resistor is connected to MFB6(pin number 106).

When the chip is configured for 4-bit host interface, MFB9:7 are used as HDATA3:1 and HDATA is used as HDATA0. For instruction, Read Data, or W rite Data, the data order is D3:0, D7:4 , D11:8, The burst mode operation then uses three clocks (instead of twelve) for each 12-bit data (or address) transmission.

In both modes, a reset pin sets the chip to a known state when the pin is pulled low. The RESETn pin must be low for at least 100ns after the CVDD has become stable (between +3.15V and +3.45V) in order to reset the chip to a known state.

The gmZAN1 chip has an on-chip pull-down resistor in the HFS input pad. No external pull-up is required. The signal stays low until driven high by the microcontroller.

2.7.1 Serial Communication Protocol

In the serial communication between the microcontroller and the gmZAN1, the microcontroller always acts as an initiator while the gmZAN1 is always the target. The following timing diagram describes the protoco l of the serial channel of the gmZAN1 chip.

Figure 10. Timing Diagram of the gmZAN1 Serial Communication

Table 15 summarizes the serial channel specification of the gmZAN1. Refer to Figure 10 for the timing parameter definition.

Table 15. gmZAN1 Serial Channel Specification

Parameter Min. Typ. Max.

Word Size (Instruction and Data) --- 12 bits --HCLK low to HFS high (t1) 100 ns HFS low to HCLK inactive (t2) 100 ns HDATA Write to Read Turnaround Time (t3) 1 HCLK cycle 1 HCLK cycle HCLK cycle (t4) 100 ns Data in setup time (t5) 25 ns Data in hold time (t6) 25 ns Data out valid (t7) 5 ns 10

In the read operation, the microcontroller (Initiator) issues an instruction lasting 12 HCLKs. After the last bit of the command is transferred to the gmZAN1 on the 12 rising edge of HCLK at which point the gmZAN1 will start driving data. At the 13

th

clock, the microcontroller must stop driving data before the next

th

rising edge of HCLK, the

gmZAN1 will begin driving data.

Figure 11. Serial Host Interface Data Transfer Format

2 bits 10 bits 12 bits

Command Address Data

Command: 01 Write 00 = Read 1x = Reserved

Note that when the chip is configured for a 4-bit host interface, MFB9:7 are used as HDATA 3:1 and HDATA is used as HDATA0. The command and address information are transferred as Address 1:0+Command1:0, Address5:2 and Address9:6. The data information is transferred as Data3:0,Data 7:4, Data 11:8. Thus, in this mode the HDATA pin carries Command0, Address2, Address6, Data0, Data4 and Data8. On the gmZAN1 reference design board, the microcontroller toggles the HCLK and HDATA lines under program control. Genesis Microchip provides API calls to facilitate communication between the microcontroller and the gmZAN1. Refer to the API reference manual for details.

2.7.2 Multi-Function Bus (MFB)

The Multi-Function Bus provides additional 12 pins that are used as general purpose input and output (GPIO) pins. Each pin can be independently configured as input or output. MFB pins 9 thr ough 5 have special funct i ons:

!

When a 10K ohm pull-down resistor is connected to MFB6 (MFB6 has an internal pull-up resistor) MFB9:7 are used as host data bits HDATA3:1.

!

When a 10K ohm pull-down resistor is connected to MFB5 (MFB5 has an internal pull-up resistor) a crystal can be placed between XTAL and TCLK instead of using an external oscillator for the TCLK input.

Note that all pins on the multi-function bus MFB11:0 are internally pulled-up.

2.8 On-Screen Display Control

The gmZAN1 chip has a built-in OSD (On-Screen Display) controller with an integrated font ROM. The chip also supports an external OSD controller for monitor vendors to maintain a familiar user interface. The internal and external OSD windows may be displayed anywhere the panel Display Enable is active, regardless of whether the panel would otherwise display panel background color or active data.

2.8.1 OSD Color Map

Both the internal and external OSD display use a 16 location SRAM block for the color programming. Each color location is a twelve-bit value that defines the upper four bits of each of the 8 bit Red, Blue and Green color components as follows:

!

D3:0 Blue; D7:4 of blue component of color

!

D7:4 Green; D7:4 of green component of color

!

D11:8 Red; D7:4 of red component of color To extend the 4-bit color value programmed to the full 8 bits the following rule is applied: if any of the upper four color bits are a “1”, then R (G, B) data 3:0=1111b, otherwise R (G, B) data 3:0=0000b

2.8.2 On-Chip OSD Controller

The internal OSD uses a block of SRAM of 1536x12 bits and a ROM of 1024x12 bits. The SRAM is used for both the font data and the character-codes while the ROM is used to store the bit data for 56 commonly used characters. The font data is for 12 pixel x 18 line characters, one bit per pixel. The font data starts at address zero. The character-codes start at any offset (with an address resolution of 16) that is greater than the last location at which font data has been written . It is the programmer’s responsibility to ensure that there is no overlap between fonts and character-codes. This implementation results in a trade-off between the number of unique fonts on-screen at any one time and the total number of characters displayed. For example, one configuration would be 98 font maps (56 fonts in ROM and 42 fonts in SRAM) and 768 characters (e.g. in a 24x32 array).

The on-chip OSD of the gmZAN1 can support a portrait mode (in which the LCD monitor screen is rotated 90 degrees). In this portrait mode, all the fonts must be loaded in the SRAM, because the ROM stores fonts for a landscape mode (typical orientation) only. The font size in the portrait mode is 12 pixels b y 12 lines. As is the case in landscape mode, the SRAM is divided into a font storage area and a character code storage area. For example, 64 fonts can be stored in RAM and an OSD window of 768 characters (such as 24x32) can still be displayed.

The first address of SRAM to be read for the first character displayed (upper left corner of window)is also programmable, with an address resolution of 16 (8-bits as the top bits of the 12-bit SRAM address). The charactercode is a 12-bit value used as follows:

!

D6:0 font-map select, this is the top seven bits of the address for the first line of font bits

!

D8:7 Background color, 00=bcolor0, 01=bcolor1, 10=bcolor2, 11=transparent background

!

D10:9 Foreground color (0, 1, 2 or 3)

!

D11 Blink enable if set to 1, otherwise no blink

Although the OSD color map has room for sixteen colors, only seven are used by the internal OSD: three background colors and four foreground colors.

The blink rate is based on either a 32 or 64 frame cycle and the duty cycle may be selected as 25/75/50/50% or 75/25%. The 2-bit foreground and background attributes directly select the color (there is no indirect “look-up”, i.e. there is no TMASK function). The 2560 addresses of the ROM/SRAM are mapped as 10 segments of 256 contiguous addresses each, to the OSD memory page of 100h-1FFh in the host interface. A 4-bit register value selects the segment to map to the host R/W page.

The character cell height and width are programmable from 5-66 pixels or 2-65 lines. The X/Y offset of the font bitmap upper-left pixel relative to the upper-left pixel of the character cell is also programmable from 0-63 (pixels or lines). The OSD window height and width in characters/rows is programmable from 1-64.

The Start X/Y position for the upper left corner of the OSD window is programmable (in panel pixels and lines) from 0-2047. There is an optional window border (equal width on all four sides of the window) or a window shadow (the window bottom and right side) the border is a solid color that is selected by an SRAM location as RGB444. The border width may be set as 1, 2, 4 or 8 pixels/lines. These parameters are summarized in Figure 12 and Table 16. The Font Data D11:0 for each line is displayed with bit D11 first (leftmost) and D0 last. The reference point for the OSD start is always the upper left corner of the Panel display, which is the start (leading edge) of Panel Display Enable for both Horizontal and Vertical timing.

The OSD Window start position sets the location of the first pixel of the OSD to display, including any border. That is; if the border is enabled, the start of the character display of the OSD is offset fro m the OSD start position by the width/height of the border.

To improve the appearance and make it easy to find the OSD window on the screen, the user may select optional shadowing (3D effect). The “Shadow” feature operates in the same manner as in the B120; that is, it produces a region of half intensity (scaler data) pixels of the same width and height as the OSD window, but offset to the right and down by 8 pixels/l ines (the bord er width settin g has no effect) . OSD foregro und and backgro und colors alwa ys cover the OSD window region of the “shadow”, but transparent background pixels in the OSD will show the half intensity panel data. Therefore, it is not recommended to use both the “shadow” feature and transparent background OSD pixels together. The ”shadow” does not The border and shadow are mutually exclusive, only one may be selected at a time.

The OSD window is not affected by the scaling operation. The size will stay the same whether the source input data is scaled or not.

change the intensity o f any panel b ackground col or over whic h it may be lo cated.

2.9 TCLK Input

The source timing is measured by using the TCLK input as a reference. Also, the reference clock to the on-chip PLLs are derived from the TCLK. It is therefore crucial to have a jitter-free clock reference. Table 19 shows the requirements for the TCLK signal.

Table 19. TCLK Specification

Frequency 20 MHz to 50 MHz Jitter 250 ps maximum Rise Time (10% to 90%) 5 ns Duty Cycle 40-60

There is also an option to use a crystal (instead of an oscillator) for the TCLK input. This option is selected by pulling down MFB5 and connecting the crystal between XTAL and TCLK.

3. ELECTRICAL CHARACTERISTICS

Table 20. Absolute Ratings

Parameter Min. Typ. Max. Note

PVDD 5.6 volts CVDD 5.6 volts Vin Vss-0.5 volt Vcc+0.5V Operating temperature 0 degree C 70 degree C Storage temperature -65 degree C 150 degree C Maximum power consumption ~2W

Table 21. DC Electrical Characteristic

Parameter Min. Typ. Max. Note

PVDD 3.15 volts 3.3 volts 3.47 volts CVDD 3.15 volts 3.3 volts 3.47 volts Vil (COMS inputs) Vil (TTL inputs) Vih (COMS inputs) Vih (TTL inputs) Voh 2.4 volts CVDD Vol 0.2 volts 0.4 volts Input Current -10 uA 10 uA PVDD operating supply current 0 mA 20 mA/pad @ 10pF (2) CVDD operating supply current 0 mA 500 mA (3) NOTE 1:5V-Tolerent TTL Input pads are as follows:

!

CRT Interface: HSYNC (pin #150), VSYNC (#148)

!

Host Interface: HFS (#98), HCLK (#103), HDATA (#99), RESETN (#100), MFB[11:0]: MFB11 (#123), MFB10 (#124), MFB9 (#102), MFB8 (#104), MFB7 (#105), MFB6 (#106), MFB5 (#107), MFB4 (#109), MFB3 (#110), MFB2 (#111), MFB1 (#112), MFB0 (#113)

!

OSD Interface: OSD_DATA3 (#121), OSD_DATA2 (#120), OSD_DATA1 (#119), OSD_DATA0 (#118), OSD_FSW (#122)

!

Non-5V-Tolerant TTL Input Pad is: TCLK(#141) NOTE 2: When the panel interface is disabled, the supply current is 0 mA. The drive current of each pad can be programmed in the range of 2 mA to 20 mA (@capacitive loading = 10 pF) NOTE 3: When all circuits are powered down and TCLK is stopped, the CVDD supply current becomes 0 mA.

0.3*CVDD

0.8 volts

0.7 * CVDD

2.0 volts

1.1*CVDD

5.0+0.5 volts

(1)

7. MECHANICAL OF CABINET FRONT DIS-ASSEMBLY

REAR COVER

34A675

SHIELD

85A548

MAIN BOARD

MAIN FRAME

15A5683(HANNSTAR)

INVERTER SHIELD

LCD PANEL

750ALCDX41-1

FRONT BEZEL

34A785

KEPC

KEPC560EKMN

KEY PAD

33A4095

POWER LENS 33A3782

SHIELD 85A580

SCREW Q1A1030-10-128 X 4

SUPPORT(FRONT)

34E676

BASE

34A787

TURN BASE 34A786

BASE SHIELD 15A5687

RUBBER FOOT 12A385-1 X 4

85A577

INVERTER BOARD

79AL15-6-S

SCREW Q1A1020-6-120

SCREW

Q1A340-16-128X4

ADAPTER BOARD

80AL15-2-L1

HINGE

37A442

EARTH CLIP 85A562

BASE HOLDER 15A5688 X 4

SCREW Q1A1030-10-128 X 4

PLASTIC GEAR 11A144-1

SCREW

Q1A1030-12-128X4

SUPPORT(BACK)

34A677

PARTS LIST OF CABINET

LOCATION

T560GCSHBAAN

CBPC560GCN CONVERSION BOARD

SPECIFICATION

KEPC560EN KEY BOARD

11A 140- 1 WIRE CLAMP 12A 381- 1 RUBBER FOOT 15A 5674- 1 CABLE CLAMP 15A 5676- 1 BASE PLATE 15A 5679- 2 MAIN FRAME 15A 5689- 1 GND. CABLE CLAMP 19A 550- 2 EARTH SPRING 26A 800- 13 LCD BAR-CODE 33A 3679- 1 POWER LENS 33A 3783- 1 ENCODER KNOB 33A 3784- 1 KEY PAD (L) 33A 3784- 2 KEY PAD (R) 34A 675- 2 - AL BACK COVER 34A 676- 1 - AT SUPPORT FRONT 34A 677- 1 - AT SUPPORT BACK 34A 678- 1 - AL BASE 34A 798- 1 - AL FRONT BEZEL

!

37A 442- 1 LCD HINGE 40A 155- 164 - 1 ID LABEL LM-500 TCO’99 41A 401- 927 - 03 OWNER’S MANUAL 44A 3137- 1 WOODEN FLAT PALLETS 44A 3203- 1 EPS (L) 44A 3203- 2 EPS (R) 44A 3203- 6 CARTON 45A 113- 1 PE BAG 45A 114- 1 PE BAG 45A 116- 1 CLIP BAG 70A L15- 1 - AOC DRIVE DISK 79A L15- 2 - S INVERTER BY SAMPO 80A L15- 2 - LI ADAPTOR BY LI NEARITY 85A 548- 3 SHIELD CBPC 85A 557- 2 SHIELD INVERTOR 85A 560- 1 SHILED CPT 85A 561- 1 SHILED 85A 562- 1 EARTH CLIP 85A 583- 1 SOFT-SHIELD 85A 583- 2 SOFT-SHIELD 89A 173- L15 - 4A SIGNAL CABLE 89A 176- 30 - 1 FPC CABLE 30P 89A 176- 45 - 1 FPC CABLE 45P 89A 404C- 18N - IS POWER CORD 95A 8014- 5 - 4 HARNESS B1A 1030- 5 - 128 SCREW B1A 1030- 8 - 128 SCREW M1A 330- 6 - 128 SCREW M1A 1030- 10 - 128 SCREW M1A 1740- 12 - 128 SCREW Q1A 340- 12 - 128 SCREW Q1A 340- 16 - 128 SCREW Q1A 1030- 10 - 128 SCREW Q1A 1030- 12 - 128 SCREW 750A LCD- 150 - 2 LCD PANEL CLAA150XA03

PARTS LIST OF CONVERSION BOARD

LOCATION CBPC560GCN SPECIFICATION

CN303 33A 3802- 5H WAFER 5P PLUG RIGHT ANELE CN302 33A 3802- 9H WAFER 9P PLUG RIGHT ANELE CN202 33A 3804- 30 WAFER FH12-30S-0.5SH CN201 33A 3804- 45 WAFER FH12-45S-0.5SH CN200 33A 8013- 14 - H 14P PLUG 40A 152- 30 CBPC560GCN LABEL U200 56A 562- 8 ZAN1 PQFP-160 U304 56A 563- 1 IC LM2596S-5.0 U305 56A 563- 7 AIC1084-33M U302 56A 1125- 61 - C M6759 U203 56A 1133- 16 IC 24LC21A/SN U300 56A 1133- 17 IC AT24C04N-10SC Q200 57A 417- 4 PMBS3904 Q250 57A 417- 4 PMBS3904 Q303 57A 417- 4 PMBS3904 Q304 57A 417- 4 PMBS3904 Q201 57A 748- 1 SI2304DS D211 57A 754- 1 BAT54C-GS08 RP300 61A 125- 103 - 8 CHIP ARRAY 10K OHM 1/16W 8P4R JP201 61A 0603- 000 CHIP 0 OHM 1/16W JP211 61A 0603- 000 CHIP 0 OHM 1/16W JP222 61A 0603- 000 CHIP 0 OHM 1/16W JP300 61A 0603- 000 CHIP 0 OHM 1/16W L204 61A 0603- 000 CHIP 0 OHM 1/16W L205 61A 0603- 000 CHIP 0 OHM 1/16W L206 61A 0603- 000 CHIP 0 OHM 1/16W R200 61A 0603- 000 CHIP 0 OHM 1/16W R201 61A 0603- 000 CHIP 0 OHM 1/16W R202 61A 0603- 000 CHIP 0 OHM 1/16W R203 61A 0603- 000 CHIP 0 OHM 1/16W R207 61A 0603- 000 CHIP 0 OHM 1/16W R208 61A 0603- 000 CHIP 0 OHM 1/16W R317 61A 0603- 000 CHIP 0 OHM 1/16W R211 61A 0603- 101 CHIP 100 OHM 1/16W R212 61A 0603- 101 CHIP 100 OHM 1/16W R218 61A 0603- 101 CHIP 100 OHM 1/16W R219 61A 0603- 101 CHIP 100 OHM 1/16W R220 61A 0603- 101 CHIP 100 OHM 1/16W R227 61A 0603- 101 CHIP 100 OHM 1/16W R213 61A 0603- 102 CHIP 1KOHM 1/16W R214 61A 0603- 102 CHIP 1KOHM 1/16W R216 61A 0603- 103 CHIP 10K OHM 1/16W R217 61A 0603- 103 CHIP 10K OHM 1/16W R223 61A 0603- 103 CHIP 10K OHM 1/16W R300 61A 0603- 103 CHIP 10K OHM 1/16W R301 61A 0603- 103 CHIP 10K OHM 1/16W R309 61A 0603- 103 CHIP 10K OHM 1/16W R311 61A 0603- 103 CHIP 10K OHM 1/16W R313 61A 0603- 103 CHIP 10K OHM 1/16W R314 61A 0603- 103 CHIP 10K OHM 1/16W R315 61A 0603- 103 CHIP 10K OHM 1/16W R326 61A 0603- 103 CHIP 10K OHM 1/16W R327 61A 0603- 103 CHIP 10K OHM 1/16W R328 61A 0603- 103 CHIP 10K OHM 1/16W R329 61A 0603- 103 CHIP 10K OHM 1/16W R400 61A 0603- 103 CHIP 10K OHM 1/16W R401 61A 0603- 103 CHIP 10K OHM 1/16W R224 61A 0603- 104 CHIP 100K OHM 1/16W R225 61A 0603- 104 CHIP 100K OHM 1/16W

LOCATION CBPC560GCN SPECIFICATION

R209 61A 0603- 202 CHIP 2K OHM 1/16W R210 61A 0603- 202 CHIP 2K OHM 1/16W R226 61A 0603- 302 CHIP 3K OHM 1/16W R229 61A 0603- 511 CHIP 510 OHM 1/16W R204 61A 0603- 750 CHIP 75 OHM 1/16W R205 61A 0603- 750 CHIP 75 OHM 1/16W R206 61A 0603- 750 CHIP 75 OHM 1/16W CP301 65A 600- 102 - 8T CP302 65A 600- 102 - 8T CP201 65A 600- 220 - 8T CP202 65A 600- 220 - 8T CP203 65A 600- 220 - 8T CP204 65A 600- 220 - 8T CP205 65A 600- 220 - 8T CP206 65A 600- 220 - 8T CP207 65A 600- 220 - 8T CP208 65A 600- 220 - 8T CP209 65A 600- 220 - 8T CP210 65A 600- 220 - 8T CP211 65A 600- 220 - 8T CP212 65A 600- 220 - 8T C235 65A 0603- 101 - 32 C236 65A 0603- 101 - 32 C229 65A 0603- 103 - 32 C230 65A 0603- 103 - 32 C231 65A 0603- 103 - 32 C232 65A 0603- 103 - 32 C233 65A 0603- 103 - 32 C234 65A 0603- 103 - 32 C251 65A 0603- 103 - 32 C201 65A 0603- 104 - 12 CHIP 0.1UF 16V C202 65A 0603- 104 - 12 CHIP 0.1UF 16V C204 65A 0603- 104 - 12 CHIP 0.1UF 16V C205 65A 0603- 104 - 12 CHIP 0.1UF 16V C207 65A 0603- 104 - 12 CHIP 0.1UF 16V C208 65A 0603- 104 - 12 CHIP 0.1UF 16V C209 65A 0603- 104 - 12 CHIP 0.1UF 16V C210 65A 0603- 104 - 12 CHIP 0.1UF 16V C211 65A 0603- 104 - 12 CHIP 0.1UF 16V C212 65A 0603- 104 - 12 CHIP 0.1UF 16V C213 65A 0603- 104 - 12 CHIP 0.1UF 16V C215 65A 0603- 104 - 12 CHIP 0.1UF 16V C217 65A 0603- 104 - 12 CHIP 0.1UF 16V C218 65A 0603- 104 - 12 CHIP 0.1UF 16V C219 65A 0603- 104 - 12 CHIP 0.1UF 16V C220 65A 0603- 104 - 12 CHIP 0.1UF 16V C221 65A 0603- 104 - 12 CHIP 0.1UF 16V C222 65A 0603- 104 - 12 CHIP 0.1UF 16V C223 65A 0603- 104 - 12 CHIP 0.1UF 16V C225 65A 0603- 104 - 12 CHIP 0.1UF 16V C226 65A 0603- 104 - 12 CHIP 0.1UF 16V C227 65A 0603- 104 - 12 CHIP 0.1UF 16V C228 65A 0603- 104 - 12 CHIP 0.1UF 16V C237 65A 0603- 104 - 12 CHIP 0.1UF 16V C244 65A 0603- 104 - 12 CHIP 0.1UF 16V C245 65A 0603- 104 - 12 CHIP 0.1UF 16V C246 65A 0603- 104 - 12 CHIP 0.1UF 16V C261 65A 0603- 104 - 12 CHIP 0.1UF 16V C300 65A 0603- 104 - 12 CHIP 0.1UF 16V C304 65A 0603- 104 - 12 CHIP 0.1UF 16V C308 65A 0603- 104 - 12 CHIP 0.1UF 16V

CHIP ARRAY 1000PF 8P CHIP ARRAY 1000PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP ARRAY 22PF 8P CHIP 100PF 50V CHIP 100PF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V CHIP 0.01UF 50V

LOCATION CBPC560GCN SPECIFICATION

C311 65A 0603- 104 - 12 CHIP 0.1UF 16V C250 65A 0603- 330 - 31 C262 65A 0603- 330 - 31 C303 65A 0603- 330 - 31 C306 65A 0603- 330 - 31 C307 67A 305- 331 - 6 330UF +-20% 35V C309 67A 305- 331 - 6 330UF +-20% 35V C310 67A 305- 331 - 6 330UF +-20% 35V C312 67A 305- 331 - 6 330UF +-20% 35V C200 67A 312- 220 - 3 C203 67A 312- 220 - 3 C206 67A 312- 220 - 3 C214 67A 312- 220 - 3 C216 67A 312- 220 - 3 C224 67A 312- 220 - 3 C305 67A 312- 220 - 3 C313 67A 312- 220 - 3 C314 67A 312- 220 - 3 FB301 71A 55- 28 BEAD R215 71A 56- 1 CHIP BEAD 120 OHM LP201 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP202 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP203 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP204 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP205 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP206 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP207 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP208 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP209 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP210 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP211 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM LP212 71A 56A- 121 - 8T CHIP BEAD ARRAY 120 OHM L207 71A 56G- 151 - A CHIP BEAD 150 OHM L200 71A 57G- 601 CHIP BEAD 600 OHM L201 71A 57G- 601 CHIP BEAD 600 OHM L202 71A 57G- 601 CHIP BEAD 600 OHM L203 71A 57G- 601 CHIP BEAD 600 OHM L300 73A 253- 108 - LI CHOKE COIL VR501 75A 335- 103 10K OHM +-30% MTG U302 87A 202- 44 IC SOCKET 44P 90A 372- 2 X300 93A 22- 55 CRYSTAL 20MHz HC-49US U201 93A 22- 57 OSCILATOR 50MHz D200 93A 39- 139 ZENER DIODE 5.6V D201 93A 39- 139 ZENER DIODE 5.6V D208 93A 39- 139 ZENER DIODE 5.6V D209 93A 39- 139 ZENER DIODE 5.6V D210 93A 39- 139 ZENER DIODE 5.6V D300 93A 60- 211 DIODE SMB340 D202 93A 64- 32 DIODE LL4148 D203 93A 64- 32 DIODE LL4148 D204 93A 64- 32 DIODE LL4148 D205 93A 64- 32 DIODE LL4148 D206 93A 64- 32 DIODE LL4148 D207 93A 64- 32 DIODE LL4148 D301 93A 64- 32 DIODE LL4148 D302 93A 64- 32 DIODE LL4148 95A 3261- 2 715A 763- 2B

-

HEAT SINK

24 HARNESS

TF-1560F(GU) LCD

33PF 50V NPO 33PF 50V NPO 33PF 50V NPO 33PF 50V NPO

SMD EC 22uF 16V 85C C SIZE SMD EC 22uF 16V 85C C SIZE SMD EC 22uF 16V 85C C SIZE SMD EC 22uF 16V 85C C SIZE SMD EC 22uF 16V 85C C SIZE SMD EC 22uF 16V 85C C SIZE SMD EC 22uF 16V 85C C SIZE SMD EC 22uF 16V 85C C SIZE SMD EC 22uF 16V 85C C SIZE

PARTS LIST OF KEY PC BOARD

LOCATION

KEPC560EN

33A 3648- 1 PCB HOLDER 40A 152- 35 LABEL Q101 57A 419- PP - T TR. 2PC945P Q102 57A 419- PP - T TR. 2PC945P R101 61A 602- 103 - 52T 10K OHM +-5% 1/6W R102 61A 602- 103 - 52T 10K OHM +-5% 1/6W R103 61A 602- 103 - 52T 10K OHM +-5% 1/6W R104 61A 602- 103 - 52T 10K OHM +-5% 1/6W R105 61A 602- 103 - 52T 10K OHM +-5% 1/6W R107 61A 602- 103 - 52T 10K OHM +-5% 1/6W R108 61A 602- 103 - 52T 10K OHM +-5% 1/6W R106 61A 602- 221 - 52T 220 OHM +-5% 1/6W C101 65A 450- 104 - 7T 0.1uF +80-20% Y5V 50V SW101 77A 600- 1 - G TACT WITH SW105 77A 600- 1 - G TACT WITH T101 77A 700- 1 EC11B20244 9MM ENCODER DP101 81A 10- 5 - BH LED BL-BYG204-RR-DP-1.6% J101 95A 90- 23 TIN COATED J102 95A 90- 23 TIN COATED J103 95A 90- 23 TIN COATED 95A 8014- 9 - 5 HARNESS 270mm 9P-9P 715A 706- 2 KEY BOARD

SPECIFICATION

9. POWER SYSTEM AND CONSUMPTION CURRENT

ADAPTER MODULE Input AC 110V, 60Hz/240V, 50Hz Output DC 12V 3.5A

Main board power system

LM2596S-5, 12V to 5V (3A SPEC)

INVERTER MODULE Input DC 12V Output AC 1500V/30K-50KHz Current 9mA

5V

AIC1084, 5V to 3.3V (5A SPEC)

3.3V

To Hannstar – Panel (consumption current arround 363mA MAX) and GMZAN1

To CPU, Eeprom, 24c21, control-inverter-on.off 860mA when Cable not Connected 841mA when Normal operation

800mA when Cable not Connected 760mA when Normal operation

CN302

(Panel-Select)

R320 R322 R324

10K (NC)

(NC)

0

1234

C304

8765

R217

10K

D209

R216

5.5V 10K

D208

5.5V

R101 R102 R103 R104 R105

1/4W

10K

R318

R319

KEY

10K

SW101 SW102

KEY PAD

123456789

+3.3V

U200

+5V

8765

RP300

RVDD2

RVDD1

SRVDD2

SRVDD1

10K

+5V

10K

(NC)

R325R323R321

(NC)0(NC)0(NC)

+5V

10K (NC)

0

+5V

R329R328

10K10K

1234

CP302CP301

10001000

8765

R220

100

R219

100

VCC

10K

1/4W

SW104 SW105

SW103

AUTO

KEY

LCD

2SC945

C101

KEY

ENTER

LEFT

ON/OFF

RIGHT

0.1

R107 R106

10K 1/4W

4321

HDATA0

HDATA

99

MFB7

105

MFB8

104

MFB8

MFB9

102

HCLK

103

IRQ

IRO

101

HFS

98

MFB5

107

R317

0

MFB6

106

R316

NC

MFB10

124

MFB11

123

109

MFB4

MFB3

110

MFB2

111

MFB1

112

MFB0

VDDA

D202

1N4148

L204

D203

0.15uH

1N4148

VDDA

D204

1N4148

L205

D205

1N4148

VDDA

D206

1N4148

L206 D207

1N4148

+3.3V

R209

R218

2K

100

R213

1K

Q101

DUAL

DP101

LED1

R108

220 1/4W

113

RED+

95

R200

R206

C229

C247

0

75

10nF

22

(NC)

RED-

94

R203

C232

0

10nF

GREEN+

91

R201

R205

C230

0

C248

75

10nF

(NC)

GREEN-

90

R207

C233

0

10nF

BLUE+

87

R202

R204

C231

0

C249

75

10nF

(NC)

BLUE-

86

R208

C234

0

R210

10nF

2K

HSYNC/CS

150

R214

R212

1K

C236

D201

100

5.6V100

VSYNC

148

R211

100

C235

D200

100 5.6V

Reserved

2

PSCAN

3

Reserved

4

Reserved

5

Reserved

59

Reserved

60

Reserved

83

NC

97

Reserved

130

Reserved

135

XTAL(Reserved)

142

Reserved

145

Reserved

147

Reserved

152

STI_TM1

153

JP101

1

VCC

2

LCD ON/OFF

3

KEY LEFT

4

KEY RIGHT

5

KEY ENTER

6

AUTO KEY

7

RVSS1

CVSS1

SRVSS1

RVSS3

CVSS2

LED ORANGE

8

LED GREEN

Q102

9

2SC945

10K 1/4W

RVSS2

1 8 18 30 41 49 61 72 114 126 140 151 158 78 80 81 82 85 89 93 131 132 133 134 127 138 144 146

GND

VDDA

RVDDA

DVDDA

SVDDA

TCLK1

+3.3V

R230

14313713612912896928884149139125108797765584033211211

0

(NC)

TCLK

C206

TCLK

141

10

13 14 15

16 17

19

20 22 23

24 25

26

27 28 29

31 32

34

35 36 37

38 39

42

46 47 48

50 51

52

53 54 55

56 57

62

63 64 66

67 68

693

70 71 73

74 75

76

43 44 45

117

116 115

120

119 118

122

121

100

154

155 156

157 159

160

6

7 9

PD47

PD46 PD45

PD44 PD43

PD42 PD41

PD40 PD39

PD38 PD37

PD36 PD35

PD34 PD33

PD32 PD31

PD30 PD29

PD28 PD27

PD26 PD25

PD24 PD23

PD22 PD21

PD20 PD19

PD18 PD17

PD16 PD15

PD14 PD13

PD12 PD11

PD10 PD9

PD8 PD7

PD6 PD5

PD4 PD3

PD2 PD1

PD0 PVS

PHS PBIAS

PPWR PDISPE

PCLKA

L203

L200

L201

L202

PCLK

L207

C262

120

33

R305 R306

10K

(NC)

R326

D302

10K

1N4148

R307

C314

10K

22UF

(NC)

C207 C208 C209 C210 C211 C212 C213

22UF

0.1 0.1 0.1 0.1 0.1 0.1 0.1

C216

22UF

C224

1UH

C225 C226 C227 C228

22UF

0.1 0.1 0.1 0.1

C200

1UH

C202C201

22UF

0.10.1

C203

1UH

C205C204

22UF

0.10.1

U201

C237

1UH 50MHz

0.1

1458

VCC

SB

OUT

GND

+5V

R303 R304

U301

R302

270

MTV121

270

(NC)

2

OSD_CLK

10

VREF

5

HREF

15

R

14

G

13

B

12

FBKG

6

SSB

U303

DS1813 (NC)

2

VCC

1

RST

+5V

R312

C313

10K

D301

22UF

(NC)

1N4148

Q300

R313

MMBT3904

10K

(NC)

RST

PD13-1 PD12-1 PD41-1 PD40-1

1

2

CP202

22

8

7

PD7-1 PD6-1 PD39-1 PD38-1

1

2

CP204

22

8

7

PD1-1 PD0-1 PD37-1 PD36-1

1

2

CP206

22

8

7

R401

10K

JP201

0

R223

Q250

JP202

MMBT3904 10K

PANLE_EN

PD31-1 PD30-1 PD47-1 PD46-1

CP208

22

PD25-1 PD24-1 PD45-1 PD44-1

1

2

CP210

22

8

7

PD19-1 PD18-1 PD43-1 PD42-1

1

2

CP212

22

8

7

R309

R311

10K

Q304

MMBT3904

R315

10K

123 12345

JP301

LP201

120

8

1

PD14

7

2

PD15

6

3

PD16

5

4

PD17

1

2

3

4

8

7

6

5

LP203

120

PD8

8

1

7

2

PD9

6

3

PD10

5

4

PD11

1

2

3

4

8

7

6

5

LP205

120

PD2

8

1

7

2

PD3

6

3

PD4

5

4

PD5

1

2

3

4

8

7

6

5

+12V

R224

100K

R225

100K

Q201

MGSF1N03

C245

Q200

0.1

MMBT3904

R226

C426

0.1

LP207LP208

120120

PD32

88

11

77

22

PD33

66

33

PD34

55

44

PD35

11

22

33

44

88

77

66

55

LP209

120

PD26

8

1

7

2

PD27

6

3

PD28

5

4

PD29

1

2

3

4

8

7

6

5

LP211

120

PD20

8

1

7

2

PD21

6

3

PD22

5

4

PD23

1

2

3

4

8

7

6

5

R522

10K7

VR501

10K

R523

10K7

+12V

CN303

LP202

120

PD13

8

1

7

2

PD12

C223C222C221C220C219C218C217

6

0.10.10.10.10.10.10.1

3

PD41

5

4

PD40

3

VDDA

DVDDA

SVDDA

RVDDA

C214

C215

22UF

0.1

TCLK

R215

C250

120

0.1

11

HTOME

4

VDD1

9

VDD2

C301 C302

0.1 (NC)

1

VSS1

16

VSS2

SDA

7

SDA

SCL

8

SCL

NC

3

GND

R229

510

4

6

5

LP204

120

PD7

8

1

7

2

PD6

6

3

PD39

5

4

PD38

3

4

6

5

LP206

120

PD1

8

1

7

2

PD0

6

3

PD37

5

4

PD36

3

4

6

5

PPWR

R400

10K

PD31 PD30 PD47 PD46

LP210

120

PD25

8

1

7

2

PD24

6

3

PD45

0.1

5

4

PD44

(NC)

3

4

6

5

LP212

120

PD19

8

1

7

2

PD18

6

3

PD43

5

4

PD42

3

4

6

5

+5V

PBIAS

Q303

MMBT3904

R314

10K

BACKLIGH

JP300

0

SVDD

DVDD

CVDD4

RVDD3

CVDD2

CVDD1

SYN_VDD

ADC_VDDA

ADC_VDD1

ADC_VDD2

RVSS4

CVSS4

CVSS3

DVSS

SRVSS2

SYN_VSS

SVSS

ADC_GND2

ADC_GND1

DAC_SVDDA

PLL_RVDDA

PLL_SVDDA

PLL_DVDDA

DAC_DVDDA

ADC_RVDDA

ADC_GVDDA

ADC_BVDDA

SUB_GNDA

ADC_BGNDA

ADC_GNDA

PD47

PD46 PD45

PD44

PD43 PD42 PD41

PD40 PD39

PD38

PD37 PD36 PD35

PD34 PD33

PD32

PD31 PD30 PD29

PD28 PD27

PD26

PD25 PD24 PD23

PD22 PD21

PD20

PD19 PD18 PD17

PD16 PD15

PD14

PD13 PD12 PD11

PD10

PD9

PD8

PD7 PD6 PD5

PD4 PD3

PD2

PD1 PD0 PVS

PHS

PBIAS

PPWR

PDISPE PCLKA PCLKB

OSD_CLK

OSD_VREF OSD_HREF

OSD_DATA2

OSD_DATA1 OSD_DATA0

OSD_FSW

OSD_DATA3

RESETn

STI_TM2

SCAN_IN1 Reserved

SCAN_IN2 SCAN_OUT1

SCAN_OUT2

ADC_RGNDA

ADC_GGNDA

PLL_DGNDA

PLL_SGNDA

SUB_SGNDA

SUB_DGNDA

DAC_DGNDA

PLL_RGNDA

DAC_SGNDA

SUB_RGNDA

PLL_GNDAADC_AGND

CN201

45

PCLK

44 43

PDISPE

42 41

PVS

40 39

PD14-1

PHS

PD15-1

38

PD16-1

37

PD17-1

36 35

CP201

22

PD17-1

34

PD16-1

33

PD15-1

32

PD14-1

31 30

PD13-1

29

PD12-1

28

PD41-1

27

PD8-1

PD40-1

PD9-1

26

PD10-1

25

PD11-1

24

PD10-1

CP203

23

22

PD9-1

22

PD8-1

21 20

PD7-1

19

PD6-1

18

PD39-1

17

PD38-1

16

PD2-1

15

PD3-1

PD5-1

PD4-1

14

PD5-1

PD4-1

13

PD3-1

12

CP205

PD2-1

22

11 10

PD1-1

9

PD0-1

8

PD37-1

7

PD36-1

6 5

+5V

R526

R528

10K

4

10K

JP201

3

0

+3.3V

2

JP202

R529 R527

1

00

PANEL_P

3K

PD32-1 PD33-1 PD34-1

CN202

PD35-1

30

PD35-1

29

CP207

PD34-1

22

28

PD33-1

27

PD32-1

26 25

PD31-1

24

PD30-1

23

PD47-1

22

PD46-1

21

PD26-1

20

PD27-1

PD29-1

PD28-1

19

PD29-1

PD28-1

18

PD27-1

17

CP209

PD26-1

22

16 15

PD25-1

14

PD24-1

13

PD45-1

12

PD44-1

11 10

PD23-1

PD20-1

9

PD22-1

PD21-1

8

PD22-1

PD21-1

7

PD23-1

PD20-1

6

CP211

5

22

PD19-1

4

PD18-1

3

PD43-1

2

PD42-1

1

C383FA-1

U302

8XC51/PLCC

HDATA0

24

P2.0/A8

T2/P1.0

2

MFB7

25

P2.1/A9

T2EX/P1.1

3

MFB8

26

P2.2/A10

4

P1.2

MFB9

27

P1.3

P2.3/A11

5

HCLK

28

P1.4

P2.4/A12

6

HFS

29

P1.5

P2.5/A13

7

BACKLIGHT_EN

30

P1.6

P2.6/A14

8

PANLE_EN

31

P1.7

P2.7/A15

9

RST

32

RST

PSEN

10

33

ALE/PROG

RXD

RXD/P3.0

11

TXD

WP

36

P0.7/AD7

TXD/P3.1

13

IRQ

37

P0.6/AD6

INT0/P3.2

14

MFB2

38

P0.5/AD5

15

INT1/P3.3

SDA

39

P0.4/AD4

16

T0/P3.4

SCL

40

P0.3/AD3

17

T1/P3.5

R327

10K

R227

100

C251

D210

1nF

5.6V

CN200

RXD

14

TXD

13 12 11

VGA_VSYNC

10

VGA_HSYNC

9

/VGA_CON

8 7 6 5

GREEN

4 3

RED

2 1

CN301

POWER+12V

+12V

FB301

C308

C307

330UF 0.1

35V

COREPOWER

10/24/2000

RST1

41

P0.2/AD2

18

WR/P3.6

/VGA_CON

42

P0.1/AD1

19

RD/P3.7

43

P0.0/AD0

XTAL2

TCLK1

XTAL2

20

R222

0

(NC)

C303

33

U304

LM2596S-5.0

+5V

TO263

4

FBK

1

VIN

2

Vout

GND

/ON

D300

53

B320

44

VCC X300

20MHz

35

EA/VP

XTAL1

21

NC

GND

NC

C305

C306

33

R301R300

10K10K

5

SI

6

SCK

L300 C309

33uH

22UF 0.1

22 1 12 23 34

+5V

U300

24LC04

R330

8

10K

VCC

C300

0.1

JP221

WP

0

7

WP

JP222

1

A0

2

A1

3

A2

4

VSS

21

+5V

D211

BAT54

3

U203

24LC21A3

8

VCC

1

5

SDANC

2

6

SCL

NC

C244

0.1

3

7

VCLK

NC

GND

4

+3.3V

U305

AIC1084

312

VoutVin

C312

C310

GND

330UF

C311

330UF

0.1 35V

35V 330UF 35V

Tatung VL5A9DA Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual