Taskit Stamp9261 Technical Manual
l
Stamp9261
Technical Manual
taskit GmbH
Seelenbinderstrasse 33
D-12555 Berlin
http://www.taskit.de
++49 30 611295-0
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© taskit GmbH, Berlin
All rights reserved. This document and the products referred to herein are copyrighted works of
taskit GmbH. Information in this document is subject to change without notice. No part of this
document may be reproduced or transmitted in any form, without the express written permission of
taskit GmbH. If however, your only means of access is electronic, permission to print one copy is
hereby granted. Neither taskit GmbH nor taskit’s distributors assume any liability arising from the
use of this manual or any product described herein.
Copyright (C) taskit GmbH, Berlin V1.00en (17.03.2008)
1.INTRODUCTION ............................................................................................................................................... 5
2.SCOPE ................................................................................................................................................................. 6
3.OVERVIEW OF TECHNICAL CHARACTERISTICS ................................................................................. 7
3.1.CPU ................................................................................................................................................................ 7
3.2.MEMORY ........................................................................................................................................................... 7
3.3.INTERFACES AND EXTERNALS SIGNALS .................................................................................................................... 7
3.4.MISCELLANEOUS ................................................................................................................................................. 7
3.5.POWER SUPPLY ................................................................................................................................................. 7
3.6.DIMENSIONS ...................................................................................................................................................... 7
4.HARDWARE DESCRIPTION .......................................................................................................................... 8
4.1.MECHANICS ....................................................................................................................................................... 8
4.2.ARM926EJ-S™ CORE .................................................................................................................................... 8
4.3.MEMORY ........................................................................................................................................................... 9
a)Flash memory ............................................................................................................................................... 9
b)Boot Mode Select Signal (BMS) .................................................................................................................. 9
c)EEPROM ...................................................................................................................................................... 9
d)SDRAM ......................................................................................................................................................... 9
e)SRAM ............................................................................................................................................................ 9
f)DataFlash ...................................................................................................................................................... 9
4.4.BATTERY BACKUP ............................................................................................................................................. 10
4.5.RESET CONTROLLER (RSTC) ............................................................................................................................ 10
4.6.SERIAL NUMBER ............................................................................................................................................... 10
4.7.CLOCK GENERATOR AND POWER MANAGEMENT CONTROLLER (PMC) .................................................................... 11
a)SAM9261 Clocks ......................................................................................................................................... 11
b)Programmable Clocks ................................................................................................................................ 11
c)PMC Control Functions .............................................................................................................................. 11
d)PMC Supervisory Functions ....................................................................................................................... 11
4.8.REAL-TIME TIMER (RTT) ................................................................................................................................. 12
4.9.TIMER COUNTER (TC) ...................................................................................................................................... 12
4.10.PERIODIC INTERVAL TIMER (PIT) ..................................................................................................................... 12
4.11.WATCHDOG TIMER ......................................................................................................................................... 12
4.12.BUS MATRIX ................................................................................................................................................. 13
4.13.LCD CONTROLLER (LCDC) .......................................................................................................................... 14
a)LCDC Initialization and LCD Power Sequencing ..................................................................................... 14
b)LCDC Video Memory Selection ................................................................................................................. 14
c)LCDC Frame Buffer ................................................................................................................................... 14
4.14.LCDC DMA AND FIFO .............................................................................................................................. 15
4.15.DISPLAY (TFT) ............................................................................................................................................. 15
4.16. TOUCHSCREEN .............................................................................................................................................. 15
4.17. ADVANCED INTERRUPT CONTROLLER (AIC) ..................................................................................................... 15
4.18. PERIPHERAL DMA CONTROLLER (PDC) ......................................................................................................... 16
a) PDC Registers ........................................................................................................................................... 16
b) PDC Interrupts .......................................................................................................................................... 16
4.19. DEBUG UNIT (DBGU) ................................................................................................................................. 17
4.20. JTAG UNIT ................................................................................................................................................ 17
4.21. TWO-WIRE INTERFACE (TWI) ......................................................................................................................... 18
4.22. MULTIMEDIA CARD INTERFACE (MCI) ........................................................................................................... 19
4.23. USB HOST PORTS (UHP) ............................................................................................................................. 20
a) External Parts ........................................................................................................................................... 20
b) VBUS considerations for USB Host .......................................................................................................... 20
c) Layout considerations ................................................................................................................................ 20
4.24.USB DEVICE PORT (UDP) ............................................................................................................................ 21
a)External Parts ............................................................................................................................................ 21
b)Operation with VBUS as a Supply .............................................................................................................. 21
c)Layout considerations ................................................................................................................................. 21
4.25.ETHERNET CONTROLLER .................................................................................................................................. 22
a)MAC Address .............................................................................................................................................. 22
b)Layout considerations ................................................................................................................................. 22
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c)Ethernet LEDs ............................................................................................................................................. 22
4.26. SYNCHRONOUS / ASYNCHRONOUS SERIAL INTERFACES (USART) ....................................................................... 23
a)USART Modes ............................................................................................................................................. 23
b)Signals of the serial interfaces .................................................................................................................... 23
c)Hardware Interrupts of the Serial Interfaces ............................................................................................. 24
4.27.SYNCHRONOUS PERIPHERAL INTERFACE (SPI) .................................................................................................... 25
4.28.SYNCHRONOUS SERIAL CONTROLLER (SSC) ...................................................................................................... 25
4.29.PARALLEL INPUT /OUTPUT CONTROLLER (PIO) ................................................................................................. 26
4.30.POWER MANAGEMENT ..................................................................................................................................... 27
a)Beware of tampering with the LCDC ! ....................................................................................................... 27
b)Idle Mode .................................................................................................................................................... 27
c)Slowing down MCK .................................................................................................................................... 27
d)Low Power SDRAM .................................................................................................................................... 27
5.STAMP9261 STARTER KIT ........................................................................................................................... 28
5.1.STARTER KIT CONTENTS ................................................................................................................................... 28
5.2.PANEL-CARD EVB .......................................................................................................................................... 28
a)First Steps ................................................................................................................................................... 28
b)Power Supply ............................................................................................................................................. 28
c)RS232 Interface ........................................................................................................................................... 28
d)Connectors .................................................................................................................................................. 28
e)Rotary Encoder ........................................................................................................................................... 29
6.SCHEMATICS OF "PANEL-CARD EVB" EVALUATION AND PROTOTYPING BOARD .............. 30
6.1.DISCLAIMER .................................................................................................................................................... 30
6.2.BUS CONNECTOR ............................................................................................................................................ 31
6.3.INTERFACES ..................................................................................................................................................... 32
6.4.POWER SUPPLY ................................................................................................................................................ 33
6.5.EXTENSION CONNECTORS ................................................................................................................................... 34
6.6.HID DEVICES .................................................................................................................................................. 35
7.ADDRESS MAP (PHYSICAL ADDRESS SPACE) ...................................................................................... 36
8.PERIPHERAL IDENTIFIERS ........................................................................................................................ 37
9.STAMP ADAPTOR .......................................................................................................................................... 38
9.1.CONNECTOR PIN ASSIGNMENT AND PIN MULTIPLEXING ......................................................................................... 38
9.2.CONNECTOR PIN DESCRIPTION ............................................................................................................................ 39
9.3.STAMP ADAPTOR SCHEMATICS AND DIMENSIONS .................................................................................................. 42
a)Dimensions ................................................................................................................................................. 42
b)Bus Interface ............................................................................................................................................... 44
c)Wrapfield .................................................................................................................................................... 45
d)Ethernet ...................................................................................................................................................... 46
10.DC CHARACTERISTICS ............................................................................................................................. 47
DC CHARACTERISTICS ............................................................................................................................................. 47
CLOCKS CHARACTERISTICS ........................................................................................................................................ 47
11.STAMP9261 PIN ASSIGNMENT ................................................................................................................. 48
12.ENVIRONMENTAL RATINGS ................................................................................................................... 50
13.STAMP9261 DIMENSIONS .......................................................................................................................... 51
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1. Introduction
The Stamp is intended to be used as a small size "intelligent" display module as well as a universal
Linux CPU card. It can be used anywhere where restricted energy and space requirements play a role.
The Stamp9261 has all the necessary interfaces to support a huge variety of peripheral devices.
Equipped with a 32-Bit parallel bus it gives fast access to a number of chips and additional devices.
The ARM architecture as a modern and widely supported processor architecture is currently the
platform of choice for medium performance embedded devices. Almost all major processor
manufacturers have ARM products in their portfolio.
The availability of the widespread operating system "Linux" for the ARM platform opens access to a
broad range of software, including tools, drivers, and software libraries. Programs written for ARM can
easily be cross-compiled for the PC platform for testing and debugging.
Examples of actual or potential applications are: terminals, measuring and test equipment, datalogging, as well as any simple or more complex control and automation tasks.
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2. Scope
This document describes the most important hardware features of the SAM9261 Stamp9261. It
includes all informations necessary to develop a customer specific hardware for the Stamp9261. The
Operating System Linux is described in a further document.
The manual comprises only a brief description of the AT91SAM9261 processor, as this is already
described in depth in the manual of the manufacturer Atmel (document 6062). Descriptions of the
ARM core ARM926EJ-S are available from Atmel and also at http://www.arm.org. It is much
recommended to have a look at these documents for a thorough understanding of the processor and
its integrated peripherals.
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3. Overview of Technical Characteristics
3.1. CPU
Atmel AT91SAM9261 Embedded Processor featuring an ARM926EJ-S™ ARM® Thumb® Core
- CPU clock 200+ MHz
- 16kB Instruction Cache
- 16kB Data Cache
- Memory Management Unit (MMU)
- 3.3V Supply Voltage, 1.2V Core Voltage
3.2. Memory
- 16 or 64 MB flash memory (optional 128 MB)
- 32MB or 64MB SDRAM
- 128 KB serial Dataflash
- 160 KB Fast SRAM
- 256 Bytes EEPROM
3.3. Interfaces and externals signals
- 2x 100-pin fine-pitch low-profile Connectors (Hirose FX8)
- Ethernet 10/100 Mbit MAC
- Dual USB 2.0 Full Speed (12 MBit/s) Hosts
- USB 2.0 Full Speed (12 MBit/s) Device
- 3 USARTs
- 1 UART
- 1 Synchronous Serial Controller (SSC, I²S)
- 2 Serial Peripheral Interfaces (SPI)
- 1 Two Wire Interface (TWI, I²C)
- 1 MultiMedia Card Interface
- JTAG debug port
- Digital Ports – up to 39 available
- Control Signals: IRQs, BMS, SHDN, WKUP
- 4 Programmable Clocks
- LCD/TFT-Controller up to 2048x2048 pixel, 24 Bit color depth
- 32-Bit parallel CPU-Bus
Some of the various functions are realized by multiplexing connector pins; therefore not all functions
may be used at the same time (see table in chapter 11).
3.4. Miscellaneous
- Three 16-Bit Timer/Counter
- Real Time Timer (RTT), with battery backup support
- Periodic Interval Timer (PIT)
- Watchdog Timer (WDT)
- Unique Hardware Serial Number
- extended temperature range, -25°C ... +70°C
3.5. Power Supply
- 3.3V power supply
- 3V backup power supply, e.g. from a lithium battery
3.6. Dimensions
- Dimensions: 53x38x4 mm (WxDxH)
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4. Hardware Description
4.1. Mechanics
The Stamp9261 was designed as a flexible CPU-Module, which can be connected to base boards via
2x 100-pin fine-pitch low profile Hirose FX8 connectors.
The size of the Stamp9261's PCB is only 53x38x4 mm fitting it in even the smallest design. While
having implemented the sensible CPU, SDRAM and Flash design it still exports almost all possible
CPU-Pins on it's connectors to allow a flexible design on base boards.
4.2. ARM926EJ-S™ Core
Here are some of the most important features of the SAM9261 core:
- up to 240 MHz CPU Clock
- 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
- 32 bit Data Bus
- Memory Management Unit
- ARM Thumb Instruction Format supported
- DSP Instruction Extensions
- ARM Jazelle® Technology for Java® Acceleration
- EmbeddedICE™ Debug Communication Channel Support
- Mid-level implementation Embedded Trace Macrocell (ETM)
Some of these features – like Jazelle – are currently not supported by the operating system of the
Stamp9261.
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4.3. Memory
a) Flash memory
• Flash memory layout
The Stamp9261 can be equipped with 16MB, 32MB, 64MB, 128MB Flash memory. This is organized
in blocks of 128KB. Each block can be erased individually.
The flash memory is made up of 1 IC. In case that 128MB chips should be installed, the PIO line PC0
is used as A26, as the CPU has only 26 external address lines.
• Limited number of erase cycles
The Flash memory consists of "Large Sector Flash-ICs" (e.g. Spansion’s S29GL256 or similar). Only
a limited number of erase cycles per block are tolerable for these devices (usually one hundred
thousand erase cycles are guaranteed by the manufacturer). This means that the flash memory, in
particular the flash disk, is not suitable for permanent write operations of a program, since the
permissible number of erase cycles per block might be exceeded in a relatively short time. A RAM disk
must be used for such purposes.
b) Boot Mode Select Signal (BMS)
This pin is normally low and enables the standard boot code from the Stamp9261's flash memory. If
pulled high, the Stamp9261 boots from the internal ROM of the SAM9261 processor. The ROM code
initializes the CPU and tries to boot from an external DataFlash® memory. Currently, the Stamp9261
provides no support for using the ROM code. This ROM-boot program also supports the SAM-BA
programming tool from Atmel©
c) EEPROM
256 Bytes within a serial EEPROM are available to store configuration data. The EEPROM is
accessed via the TWI.
d) SDRAM
The Stamp9261 can be equipped with up to 64MB SDRAM. The starter-kit Stamp9261 is equipped
with 64MB Mobile SDRAM.
e) SRAM
The SAM9261 processor integrates 160 KB of fast static RAM which can be used as "Tightly Coupled
Memory" (TCM) with dedicated instruction and data blocks. Time-critical sections of the code, e.g.
interrupt handlers, are recommended to be placed within the SRAM, as well as critical data sections
like the stack.
f) DataFlash
A 128 KB Dataflash connected to the processor's SPI-Bus is provided. It can be used for booting
purposes or storing configuration data in designs without further flash memory
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4.4. Battery backup
The following parts of the SAM9261 Processor can be backed-up by a battery:
- the Slow Clock Oscillator;
- the Real Time Timer;
- the Reset Controller;
- the four General Purpose Backup Registers.
It is recommended to always use a backup power supply (normally a battery) in order to speed up the
boot-up time and to avoid reset problems.
4.5. Reset Controller (RSTC)
The SAM9261 has an integrated Reset Controller which samples the backup and the core voltage
(both typically at 1.2V). As the Stamp9261 uses an additional reset comparator to supervise the 3.3V
supply, the user reset function of the RSTC should always be enabled. This requires the presence of a
backup voltage (VDDBU) when the card is powered down.
4.6. Serial Number
Every Stamp9261 has a unique 48-bit hardware serial number chip which can be used by application
software. A Linux driver for reading the serial number is available.
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4.7. Clock Generator and Power Management Controller (PMC)
a) SAM9261 Clocks
The Stamp9261's SAM9261 Processor generates its necessary clocks based on two crystal
oscillators:
- Slow Clock (SLCK) Oscillator, running at 32768 Hz,
- Main Clock Oscillator, running at 18.432 MHz.
From the Main Clock Oscillator, the Clock Generator produces two further clocks by using two PLLs:
- PLLA provides the 200 MHz Processor Clock (PCK) and the
- Master Clock (MCK) = PCK/2 = 100 MHz
- PLLB provides the 96 MHz USB Clock.
Apart from the USB Clock, most of the peripheral clocks are derived from MCK:
- SDRAM, LCDC, USART, SPI, TWI, SSC, PIT, TC.
The TC unit can also run on SLCK. The RTT always runs on SLCK.
b) Programmable Clocks
Four programmable clock outputs PCK0, PCK1, PCK2 and PCK3 are available on the connectors of
the Stamp9261. They can individually be programmed to the SLCK, PLLA, PLLB, and Main Clock, as
well as these values divided by 2, 4, 8, 16, 32, or 64.
c) PMC Control Functions
The PMC has a Peripheral Clock register which allows to enable or disable the clocks of all integrated
peripherals individually using their "Peripheral Identifier" (see table Peripheral Identifiers).
The System Clock register allows to enable or disable each of the following clocks individually:
- Processor clock,
- LCD clock (HCK1)
- USB Host clock (common for both channels)
- USB Device clock
- Programmable Clocks
The HCK0 bit mentioned in the Atmel manual is not used in the SAM9261 processor.
d) PMC Supervisory Functions
The PMC provides status flags for the
- Main Oscillator
- Master Clock
- PLLA
- PLLB
- Programmable Clocks
The PMC status register provides "Clock Ready" or, respectively, "PLL Lock" status bits for each of
these clocks. An interrupt is generated when any of these bits changes from 0 to 1.
The Main Oscillator frequency can be measured by using the PMC Main Clock Frequency register.
The SLCK is used as reference for the measurement.
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4.8. Real-time Timer (RTT)
The Real-time Timer is a 32-bit counter combined with a 16-bit prescaler running at Slow Clock
(SLCK = 32768 Hz). As the RTT keeps running if only the backup supply voltage is availbale, it is used
as a Real-time clock on the Stamp9261.
The RTT can generate an interrupt every time the prescaler rolls over. Usually the RTT is configured
to generate an interrupt every second, so the prescaler will be programmed with the value 7FFFh.
The RTT can also generate an alarm if a preprogrammed 32-bit value is reached by the counter.
4.9. Timer Counter (TC)
The TC consists of three independent 16-bit Timer/Counter units. They may be cascaded to form a 32bit or 48-bit timer/counter. On the Stamp9261, the external signals are not available as they are
multiplexed on the Processor with the upper 16 bits of the data bus. The timers can therefore only run
on the internal clock sources:
- MCK/2, MCK/8, MCK/32, MCK/128, SLCK,
- or the output of another timer channel.
4.10. Periodic Interval Timer (PIT)
The PIT consists of a 20-bit counter running on MCK / 16. This counter can be preloaded with any
value between 1 and 220. The counter increments until the preloaded value is reached. At this stage it
rolls over and generates an interrupt. An additional 12-bit counter counts the interrupts of the 20 bit
counter.
The PIT is intended for use as the operating system’s scheduler interrupt.
4.11. Watchdog Timer
The watchdog timer is a 12-bit timer running at 256 Hz (Slow Clock / 128) The maximum watchdog
timeout period is therefore equal to 16 seconds. If enabled, the watchdog timer asserts a hardware
reset at the end of the timeout period. The application program must always reset the watchdog timer
before the timeout is reached. If an application program has crashed for some reason, the watchdog
timer will reset the system, thereby reproducing a well defined state once again.
The Watchdog Mode Register can be written only once. After a Processor Reset, the watchdog is
already activated and running with the maximum timeout period. Once the watchdog has been
reconfigured or deactivated by writing to the Watchdog Mode Register, only a Processor Reset can
change its mode once again.
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4.12. Bus Matrix
The SAM9261 Processor's Bus Matrix consists of 5 masters and 5 slaves:
The Bus Masters are:
- ARM926EJS Core Instruction Fetch,
- ARM926EJS Core Data I/O,
- USB Host DMA,
- LCDC-DMA,
- Peripheral DMA Controller (PDC).
Bus Slaves are:
- internal ROM,
- internal SRAM,
- EBI,
- internal peripherals,
- LCDC and USB Host port.
EBI connects to external devices. In the case of the Stamp9261 these consist in the SDRAM, the flash
memory and the Ethernet Controller. The LCDC and the USB Host ports share a common slave bus
connection.
The Bus Matrix provides independent paths for each Master/Slave connection. For example, the
LCDC-DMA can fetch video data from its video RAM (which we assume is allocated within the
SDRAM) at the same time as the USART DMA (a PDC channel) stores data within the internal SRAM.
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4.13. LCD Controller (LCDC)
The LCD Controller of the SAM9261 processor (theoretically) supports displays with a resolution up to
2048x2048 pixels with a color depth of 24 bit per pixel, or 8 bit per color. To implement a fitting LCD,
glue hardware is necessary.
The LCD controller relies on a relatively simple frame buffer concept, which means that all graphics
and character functions have to be implemented in software: character sets and graphic primitives are
not integrated in the controller.
a) LCDC Initialization and LCD Power Sequencing
LCD cells (pixels) should not be subjected to DC power for prolonged periods of time, as chemical
decomposition might take place. The LCD controller therefore provides for a strict AC control of the
LCD pixels. To do so, the LCD controller has to be initialized appropriately. Switching on the LCD
supply voltage therefore has to take place after the LCDC initialization or shortly before.
Accordingly, the LCDC should not be powered down without deactivating the LCD supply voltage. The
same is true if the LCDC is stopped indirectly by stopping the respective clock source, namely the
PLLA.
The LCD backlight supply is not involved in these considerations. It may switched on or off at any time
independently of the state of the LCDC.
b) LCDC Video Memory Selection
The video memory of the LCDC is part of the working memory of the processor. It might either reside
in the internal SRAM, as well as in the external SDRAM. Using the internal SRAM has the advantage
that the LCDC can access its video memory via an autonomous bus and does not affect the processor
performance. However, as the internal SRAM has a capacity of only 160 KBytes, the color depth for a
QVGA display is only 16 bit / pixel (320 x 240 x 2 = 153600 bytes are necessary). For a high quality
display 16 bit per pixel might not be sufficient.
On the other hand, using the SDRAM as video memory has the advantage that there is plenty of
space for all resolutions. Also the internal SRAM is now available for time critical software sections. Of
course the LCDC will now be permanently scanning its video memory and might therefore reduce the
overall performance to some degree.
c) LCDC Frame Buffer
The LCDC video memory is organized as a frame buffer in a straight forward way. It supports color
depths of 1, 2, 4, 8, 16, or 24 bit per pixel. The video data is stored in a packed form with no unused
bits in the video memory.
The color resolutions of 1, 2, 4, and 8 bpp (bits per pixel) use a palette table which is made up of 16-bit
entries. The value of each pixel in the frame buffer serves as an index into the palette table. The value
of the respective palette table entry is output to the display by the LCDC.
Each palette table entry has the form
Bit 15 Bit[14..10] Bit[9..5] Bit[4..0]
Intensity Bit Blue[7..3] Green[7..3] Red[7..3]
The bits 2..0 of each color channel are not used in the palletized configuration – they are set to zero.
The intensity bit sets the least significant valid bits of every color, that is, the bits 2, 10, and 18 of a 24bit LCDC output word.
The same scheme as above is used in the 16-bit color resolution configuration, although in this case
the frame buffer entry is output directly to the display instead of indexing a palette table.
In the 24-bit color resolution configuration, each frame buffer entry consists of one byte for each color:
Bit[23..16] Bit[15..8] Bit[7..0]
Blue[7..0] Green[7..0] Red[7..0]
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The "BGR" (blue-green-red) sequence in the SAM9261 LCDC is not frequently used by graphics
libraries or bitmaps ("RGB" is more of a standard), neither is the use of bit 15 as an intensity bit. Of
course, the first problem can be circumvented by connecting the LCDC lines to the LCD in a way
deviating from the Atmel designation, that is, by exchanging the "blue" against the "red" lines.
The Linux frame buffer driver offers a function which returns the information about the frame buffer
structure including the assignment of each frame buffer bit to a color channel bit. It is recommended
that graphics software uses this function in order to achieve a correct color representation.
4.14. LCDC DMA and FIFO
To provide for a periodic display refresh, the LCDC comprises a DMA channel and a 2 KB FIFO.
4.15. Display (TFT)
The Stamp9261 is provided without a display. The implementation of a display design is subject to the
user.
4.16. Touchscreen
The SPI-based ADS7843 is is implemented on the Evaluation-Board Design. It is connected to the
Second SPI-Bus of the AT91SAM9261. It's Pins are multiplexed with the Knob on the EvaluationBoard so both input devices can't be used at the same time.
4.17. Advanced Interrupt Controller (AIC)
The Advanced Interrupt Controller can handle up to 32 internal or external interrupt sources. On the
SAM9261 processor, only 24 of them are actually used.
The AIC integrates an 8-level priority controller.
Interrupt sources can be programmed to be level sensitive or edge triggered. The polarity can be
programmed for all external interrupt sources.
There are three external interrupt signals available on the connectors of the Stamp9261:
- IRQ0, IRQ1, and IRQ2.
Moreover, all PIO lines can be used to generate a PIO interrupt. However, the PIO lines can only
generate level change interrupts, that is, positive as well as negative edges will generate an interrupt.
The PIO interrupt itself (PIO to AIC line) is usually programmed to be level-sensitive. Otherwise
interrupts will be lost if multiple PIO lines source an interrupt simultaneously.
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4.18. Peripheral DMA Controller (PDC)
The PDC provides both a receive and a transmit channel for each of the following full-duplex devices:
- USARTs
- Debug UART
- SPIs
- SSCs
The following half duplex device uses one bidirectional DMA channel:
- MCI
The DMA controllers of the USB Host interface and the LCD controller have specific characteristics
and are not part of the PDC.
The address space of the DMA registers of one DMA channel as well as the interrupt of that channel
are assigned to the appropriate peripheral. The PDC registers thus do not occupy a contiguous
address range.
a) PDC Registers
A DMA channel consists of a
- pointer register
- counter register
- new pointer register
- new counter register
- status register (enable/disable status)
- control (enable/disable) register
The counter register has 16 bits. The maximum buffer size for a single DMA transfer is thus limited to
64kB. The PDC supports 8-bit, 16-bit and 32-bit data words. They are selected according to the
requirements of the associated peripheral device.
b) PDC Interrupts
There are four kinds of interrupt generated by the PDC:
- End of Receive Buffer
- End of Transmit Buffer
- Receive Buffer Full
- Transmit Buffer Empty
The "End of Receive Buffer" / "End of Transmit Buffer" interrupts signify that the DMA counter has
reached zero. The DMA pointer and counter register will be reloaded from the reload registers ("DMA
new pointer register" and "DMA new counter register") provided that the "DMA new counter register"
has a non-zero value. Otherwise a "Receive Buffer Full" or, respectively, a "Transmit Buffer Empty"
interrupt is generated, and the DMA transfer terminates. Both reload registers are set to zero
automatically after having been copied to the DMA pointer and counter registers.
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