TAOS TSL210 Datasheet
TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
640 × 1 Sensor-Element Organization
200 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range...2000:1 (66 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 5 MHz
Single 5-V Supply
Description
The TSL210 linear sensor array consists of five
sections of 128 photodiodes, each with
associated charge amplifier circuitry , running from
a common clock. These sections can be
connected to form a contiguous 640 × 1 pixel
array. Device pixels measure 120 µm (H) by
70 µm (W) with 125-µm center-to-center pixel
spacing. Operation is simplified by internal logic
that requires only a serial input (SI1 through SI5)
for each section and a common clock for the five
sections.
The device is intended for use in a wide variety of
applications including contact imaging, mark and
code reading, bar-code reading, edge detection
and positioning, OCR, level detection, and linear
and rotational encoding.
PACKAGE
(TOP VIEW)
1 V
DD
2 CLK
3 SI1
4 AO1
5 SO1
6 SI2
7 AO2
8 SO2
9 GND
10 SI3
11 AO3
12 SO3
13 SI4
14 AO4
15 SO4
16 SI5
17 AO5
18 SO5
Functional Block Diagram (each section)
Pixel 1
Integrator
Reset
_
+
Sample/
Output
Switch Control Logic
CLK 128-Bit Shift Register
SI
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Company
Pixel
2
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 Plano, TX 75074 (972) 673-0759
www.taosinc.com
Pixel
3
Q3Q2Q1
Q128
Pixel
128
Analog
Bus
Output
Amplifier
Gain
Trim
V
DD
AO
R
L
(External
GND
Copyright 2002, TAOS Inc.
330
Load)
SO
1
TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
Terminal Functions
TERMINAL
NAME NO.
AO1 4 O Analog output of section 1.
AO2 7 O Analog output of section 2.
AO3 11 O Analog output of section 3.
AO4 14 O Analog output of section 4.
AO5 17 O Analog output of section 5.
CLK 2 I Clock input for all sections. The clock controls the charge transfer, pixel output, and reset.
GND 9 Ground (substrate). All voltages are referenced to the substrate.
SI1 3 I SI1 defines the start of the data out sequence for section 1.
SI2 6 I SI2 defines the start of the data out sequence for section 2.
SI3 10 I SI3 defines the start of the data out sequence for section 3.
SI4 13 I SI4 defines the start of the data out sequence for section 4.
SI5 16 I SI5 defines the start of the data out sequence for section 5.
SO1 5 O SO1 provides the signal to drive the SI2 input in serial mode or
SO2 8 O SO2 provides the signal to drive the SI3 input in serial mode or
SO3 12 O SO3 provides the signal to drive the SI4 input in serial mode or
SO4 15 O SO4 provides the signal to drive the SI5 input in serial mode or
SO5 18 O SO5 provides the signal to drive the SI input of another device for cascading or as an
VDD 1 Supply voltage for both analog and digital circuits.
I/O DESCRIPTION
end of data
end of data
end of data
end of data
for section 1 in parallel mode.
for section 2 in parallel mode.
for section 3 in parallel mode.
for section 4 in parallel mode.
end of data
indication.
Detailed Description
The device consists of five sections of 128 photodiodes (called pixels — 640 total in the device) arranged in a
linear array. Each section has its own signal input and output lines, and all five sections are connected to a
common clock line. Light energy impinging on a pixel generates photocurrent that is then integrated by the active
integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel
and the integration time. The voltage output developed for each pixel is according to the following relationship:
V
= V
where:
out
V
out
V
drk
R
E
e
t
int
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(µJ/cm2)
e
is the incident irradiance in µW/cm
is integration time in seconds
+ (Re) (Ee) (t
drk
2
)
int
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LUMENOLOGY
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TSL210
640 × 1 LINEAR SENSOR ARRAY
TAOS039 – AUGUST 2002
The output and reset of the integrators in each section are controlled by a 128-bit shift register and reset logic.
An output cycle is initiated by clocking in a logic 1 on SI. As the SI pulse is clocked through the shift register,
the charge stored on the sampling capacitors of each pixel is sequentially connected to a charge-coupled output
amplifier that generates a voltage on analog output AO (given above). After being read, the pixel integrator is
then reset, and the next integration period begins for that pixel. On the 129th clock rising edge, the SO pulse
is clocked out on SO signifying the end of the read cycle. The section is then ready for another read cycle. The
SO of each section can be connected to SI on the next section in the array (Figure 4). SO can be used to signify
the read is complete.
AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is
nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device
is not in the output phase, AO is in a high impedance state.
A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.
The
LUMENOLOGY
Company
www.taosinc.com
Copyright 2002, TAOS Inc.
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