TAOS TSL201R Datasheet



TSL201R

64  1 LINEAR SENSOR ARRAY



TAOS030B – AUGUST 2002

 64 × 1 Sensor-Element Organization
 200 Dots-Per-Inch (DPI) Sensor Pitch
 High Linearity and Uniformity

SI 1

DIP PACKAGE

(TOP VIEW)

8 NC

 Wide Dynamic Range...2000:1 (66 dB)
 Output Referenced to Ground

CLK 2

7 GND

 Low Image Lag . . . 0.5% Typ
 Operation to 5 MHz

AO 3

6 GND

 Single 5-V Supply

V

 Replacement for TSL201

4

DD

NC – No internal connection

Description

The TSL201R linear sensor array consists of a 64 × 1 array of photodiodes and associated charge amplifier
circuitry. The pixels measure 120 µm (H) by 70 µm (W) with 125-µm center-to-center spacing and 55-µm
spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI)
signal and a clock.

The TSL201R is intended for use in a wide variety of applications including mark detection and code reading,
optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear
and rotary encoding.

5 NC

Functional Block Diagram

Pixel 1

Integrator

Reset

_
+

Sample/

Output

Switch Control Logic

2

CLK 64-Bit Shift Register

1

SI

Pixel

2

Pixel

3

Pixel

64

Analog

Bus

Q3Q2Q1

Q64

Output
Amplifier

Gain
Trim

4

V

3

AO

6, 7

GND

DD

R

L

(External
330 
Load)

The

LUMENOLOGY

 Company

Texas Advanced Optoelectronic Solutions Inc.



800 Jupiter Road, Suite 205  Plano, TX 75074  [phone]

www.taosinc.com



Copyright  2002, TAOS Inc.

1

TSL201R
64  1 LINEAR SENSOR ARRAY

TAOS030B – AUGUST 2002

Terminal Functions

TERMINAL

NAME NO.

AO 3 Analog output.
CLK 2 Clock. The clock controls charge transfer, pixel output, and reset.
GND 6, 7 Ground (substrate). All voltages are referenced to the substrate.
SI 1 Serial input. SI defines the start of the data-out sequence.
V

DD

4 Supply voltage. Supply voltage for both analog and digital circuits.

DESCRIPTION

Detailed Description

The sensor consists of 64 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.

The output and reset of the integrators is controlled by a 64-bit shift register and reset logic. An output cycle is
initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)†. As the SI pulse
is clocked through the 64-bit shift register, the charge on the sampling capacitor of each pixel is sequentially
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
low, the pixel integrator is reset. On the 65th clock rising edge, the SI pulse is clocked out of the shift register
and the output assumes a high-impedance state. Note that this 65th clock pulse is required to terminate the
output of the 64th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented
as early as the 66th clock pulse, thereby initiating another pixel output cycle.

The voltage developed at analog output (AO) is given by:

V

= V

out

+ (Re) (Ee) (t

drk

)

int

where:

V

out

V

drk

R
E

e

t

int

is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(µJ/cm2)

e

is the incident irradiance in µW/cm

2

is integration time in seconds

AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is
nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device
is not in the output phase, AO is in a high impedance state.

A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.

†

For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.

Copyright  2002, TAOS Inc.

2



www.taosinc.com

The

LUMENOLOGY



 Company

TSL201R

64  1 LINEAR SENSOR ARRAY

TAOS030B – AUGUST 2002

Absolute Maximum Ratings

†

Supply voltage range, VDD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VDD) –20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high impedance or

power-off state, VO –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

(V

= 0 to VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

O

Continuous current through VDD or GND –40 mA to 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog output current range, IO –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA –25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD tolerance, human body model 2000 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions (see Figure 1 and Figure 2)

MIN NOM MAX UNIT

Supply voltage, V
Input voltage, V
High-level input voltage, V
Low-level input voltage, V
Wavelength of light source, λ 400 1000 nm
Clock frequency, f
Sensor integration time, t
Operating free-air temperature, T

Load resistance, R
Load capacitance, C

DD

I

IH

IL

clock

int

A

L

L

4.5 5 5.5 V
0 V
2 V
0 0.8 V

5 5000 kHz

0.017 100 ms
0 70 °C

300 4700 Ω

DD
DD

470 pF

V
V

The

LUMENOLOGY

 Company



www.taosinc.com

Copyright  2002, TAOS Inc.



3