TAOS TSL1410R Datasheet



TSL1410R

1280 × 1 LINEAR SENSOR ARRAY WITH HOLD



TAOS043 – AUGUST 2002

 1280 × 1 Sensor-Element Organization
 400 Dot-Per-Inch (DPI) Sensor Pitch
 High Linearity and Uniformity
 Wide Dynamic Range...4000:1 (72 dB)
 Output Referenced to Ground
 Low Image Lag ... 0.5% Typ
 Operation to 8 MHz
 Single 3-V to 5-V Supply
 Rail-to-Rail Output Swing (AO)
 No External Load Resistor Required
 Replacement for TSL1410

Description

The TSL1410R linear sensor array consists of t w o
sections of 640 photodiodes, each with
associated charge amplifier circuitry, aligned to
form a contiguous 1280 × 1 pixel array. The device
incorporates a pixel data-hold function that
provides simultaneous-integration start and stop
times for all pixels. The pixels measure 63.5 µm by

55.5 µm with 63.5-µm center-to-center spacing
and 8-µm spacing between pixels. Operation is
simplified by internal logic that requires only a
serial-input (SI) pulse and a clock.

(TOP VIEW)

1
2
3
4
5
6
7
8

9
10
11
12
13

V

PP

SI1
HOLD1
CLK1
GND
AO1
SO1
SI2
HOLD2
CLK2
SO2
AO2
V

DD

The device is intended for use in a wide variety of applications including mark and code reading, OCR and
contact imaging, edge detection and positioning, and optical encoding.

Functional Block Diagram (each section)

Pixel 1 (641)

3, 9

Hold

4,10

CLK 640-Bit Shift Register (2 each)

2,8

SI

Integrator

Reset

_
+

Sample/

Output

Switch Control Logic

Pixel

2

(642)

Pixel

3

(643)

Q3Q2Q1Hold

Pixel

640

(1280)

Q640 (Q1280)

Analog

Bus

Output
Buffer

Gain
Trim

13

6, 12

7, 11

V

DD

AO

5

GND

SO

The

LUMENOLOGY

 Company

Texas Advanced Optoelectronic Solutions Inc.



800 Jupiter Road, Suite 205  Plano, TX 75074  [phone]

www.taosinc.com



Copyright  2002, TAOS Inc.

1

TSL1410R

1280 × 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS043 – AUGUST 2002

Terminal Functions

TERMINAL

NAME NO.

AO1 6 O Analog output, section 1.
AO2 12 O Analog output, section 2.
CLK1 4 I Clock, section 1. CLK1 controls charge transfer, pixel output, and reset.
CLK2 10 I Clock, section 2. CLK2 controls charge transfer, pixel output, and reset.
GND 5 Ground (substrate). All voltages are referenced to GND.

HOLD1 3 I
HOLD2 9 I Hold signal. HOLD2 shifts pixel data to parallel buffer. HOLD2 is normally connected to SI2 in parallel mode.

SI1 2 I Serial input (section 1). SI1 defines the start of the data-out sequence.
SI2 8 I Serial input (section 2). SI2 defines the start of the data-out sequence.
SO1 7 O Serial output (section 1). SO1 provides a signal to drive the SI2 input in serial mode.

SO2 11 O
V

DD

V

PP

I/O DESCRIPTION

Hold signal. HOLD1 shifts pixel data to parallel buffer. HOLD1 is normally connected to SI1 and HOLD2 in
serial mode and to SI1 in parallel mode.

Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an
end-of-data indication.

13 Supply voltage for both analog and digital circuitry.

1 Normally grounded.

Detailed Description

The sensor consists of 1280 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel
generates photocurrent that is then integrated by the active integration circuitry associated with that pixel.

During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The
amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time.

The output and reset of the integrators are controlled by a 640-bit shift register and reset logic. An output cycle is initiated
by clocking in a logic 1 on SI. Another signal, called HOLD, is generated from the rising edge of SI1 when SI1 and HOLD1
are connected together. This causes all 640 sampling capacitors to be disconnected from their respective integrators and
starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling
capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO.
The integrator reset period ends 18 clock cycles after the SI pulse is clocked in. Then the next integration period begins.
On the 640th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section
2 (when SO1 is connected to SI2). The rising edge of the 641st clock cycle terminates the SO1 pulse, and returns the analog
output AO of section 1 to high-impedance state. Similarly, SO2 is clocked out on the 1280th clock pulse. Note that a 1281st
clock pulse is needed to terminate the SO2 pulse and return AO of Section 2 to the high-impedance state. Sections 1 and
2 may be operated in parallel or in serial fashion.

AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing. With V

for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:

where:

V

out

V

drk

R
E

e

t

int

is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(µJ/cm2)

e

is the incident irradiance in µW/cm
is integration time in seconds

= 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V

DD

V

out

= V

+ (Re) (Ee)(t

drk

2

int

)

A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.

Copyright  2002, TAOS Inc.

2



www.taosinc.com

The

LUMENOLOGY



 Company

TSL1410R

1280 × 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS043 – AUGUST 2002

Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VDD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) or (VI > VDD) –20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high impedance or power-off state, VO –0.3 V to VDD + 0.3 V. . .
Continuous output current, I

(V

= 0 to VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

O

Continuous current through VDD or GND –40 mA to 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog output current range, IO –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum light exposure at 638 nm 5 mJ/cm

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

MIN NOM MAX UNIT

Supply voltage, V
Input voltage, V
High-level input voltage, V
Low-level input voltage, V
Wavelength of light source, λ 400 1100 nm
Clock frequency, f
Sensor integration time, Serial, t
Sensor integration time, Parallel, t
Setup time, serial input, t
Hold time, serial input, t
Operating free-air temperature, T

Load capacitance, C
Load resistance, R

NOTE 1: SI must go low before the rising edge of the next clock pulse.

DD

I

IH

IL

clock

int

int

su(SI)

(see Note 1) 0 ns

h(SI)

A

L

L

3 5 5.5 V
0 V

VDD × 0.7 V

0 VDD × 0.3 V

5 8000 kHz

0.162 100 ms

0.082 100 ms
20 ns

0 70 °C

300 Ω

DD
DD

330 pF

V
V

†

2

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LUMENOLOGY

 Company



www.taosinc.com

Copyright  2002, TAOS Inc.



3