TAOS TSL1402R Datasheet

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TSL1402R

256 × 1 LINEAR SENSOR ARRAY WITH HOLD

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TAOS041 – AUGUST 2002

 256 × 1 Sensor-Element Organization

(TOP VIEW)

 400 Dots-Per-Inch (DPI) Sensor Pitch
 High Linearity and Uniformity
 Wide Dynamic Range...4000:1 (72 dB)
 Output Referenced to Ground
 Low Image Lag ... 0.5% Typ
 Operation to 8 MHz

VDD 1

SI1 2
CLK 3
AO1 4

GND 5

14 NC
13 SO1
12 GND
11 NC
10 SI2

 Single 3-V to 5-V Supply
 Rail-to-Rail Output Swing (AO)
 No External Load Resistor Required
 Replacement for TSL1402

SO2 6

NC 7

NC – No internal connection

Description

The TSL1402R linear sensor array consists of two sections of 128 photodiodes each and associated charge
amplifier circuitry, aligned to form a contiguous 256 × 1 pixel array. The device incorporates a pixel data-hold
function that provides simultaneous integration start and stop times for all pixels. The pixels measure 63.5 µm
by 55.5 µm, with 63.5-µm center-to-center spacing and 8-µm spacing between pixels. Operation is simplified
by internal logic requiring only a serial-input pulse (SI) and a clock.

The TSL1402R is intended for use in a wide variety of applications including mark and code reading, OCR and
contact imaging, edge detection and positioning, and optical encoding.

9 NC
8 AO2

Functional Block Diagram (each section – pin numbers apply to section 1)

Pixel 1

_
+

Sample/Hold/

3

CLK 128-Bit Shift Register

2

SI

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Integrator

Reset

Output

Switch Control Logic

Pixel

2



Pixel

3

Q3Q2Q1Hold

Pixel

128

Analog

Bus

Q128

Texas Advanced Optoelectronic Solutions Inc.

800 Jupiter Road, Suite 205  Plano, TX 75074  [phone]

www.taosinc.com

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Output
Buffer

Gain
Trim

Copyright  2002, TAOS Inc.

1

V

DD

4

AO

5

GND

13

SO

1

TSL1402R

256 × 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS041 – AUGUST 2002

Terminal Functions

TERMINAL

NAME NO.

AO1 4 Analog output of section 1.
AO2 8 Analog output of section 2.
CLK 3 Clock. Clk controls charge transfer, pixel output, and reset.
GND 5,12 Ground (substrate). All voltages are referenced to GND.

NC
SI1 2 Serial input (section 1). SI1 defines the start of the data-out sequence for section 1.

SI2 10 Serial input (section 2). SI2 defines the start of the data-out sequence for section 2.
SO1 13 Serial output (section 1). SO1 provides a signal to drive the SI2 input (in serial connection).

SO2 6
V

DD

7, 9,

11, 14

No internal connection.

Serial output (section 2). SO2 provides a signal to drive the SI input of another device for
cascading or as an end-of-data indication.

1 Supply voltage. Supply voltage for both analog and digital circuitry.

DESCRIPTION

Detailed Description

Device operation (assumes serial connection)

The sensor consists of 256 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a
pixel generates photocurrent, which is then integrated by the active integration circuitry associated with that
pixel.

During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel
and the integration time.

The output and reset of the integrators is controlled by a 256-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI1. An internal signal, called Hold, is generated from the rising edge of
SI1 and simultaneously transmitted to sections 1 and 2. This causes all 256 sampling capacitors to be
disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked
through the shift register, the charge stored on the sampling capacitors is sequentially connected to a
charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first
18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the
128th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for
section 2 (SI2). The rising edge of the 129th clock cycle terminates the SO1 pulse, and returns the analog output
AO1 of section 1 to high-impedance state. Analog output AO2 now becomes the active output. As in section
2, SO2 is clocked out on the 256th clock pulse. Note that a 257th clock pulse is needed to terminate the SO2
pulse and return AO2 to the high-impedance state.

Copyright  2002, TAOS Inc.

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TSL1402R

256 × 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS041 – AUGUST 2002

AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing. With V

for saturation light level.
The voltage developed at analog output (AO) is given by:

where:

V

out

V

drk

R
E

e

t

int

is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(µJ/cm2)

e

is the incident irradiance in µW/cm
is integration time in seconds

When the device is not in the output phase, AO is in a high-impedance state.

The TSL1402R can be connected in the serial mode, where it takes 256 clocks to read out all pixels, or in the
parallel mode where it takes 128 clocks to read out all pixels (see
9 and 10).

A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.

= 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V

DD

V

= V

out

+ (Re) (Ee)(t

drk

2

int

)

APPLICATION INFORMATION

and FIgures

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3

TSL1402R

256 × 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS041 – AUGUST 2002

Absolute Maximum Ratings

†

Supply voltage range, VDD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) or (VI > VDD) –20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high impedance or power-off state, VO –0.3 V to VDD + 0.3 V. . .
Continuous output current, I

(V

= 0 to VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

O

Continuous current through VDD or GND –40 mA to 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog output current range, IO –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum light exposure at 638 nm 5 mJ/cm

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions (see Figure 1 and Figure 2)

MIN NOM MAX UNIT

Supply voltage, V
Input voltage, V
High-level input voltage, V
Low-level input voltage, V
Wavelength of light source, λ 400 1000 nm
Clock frequency, f
Sensor integration time, Parallel, t
Sensor integration time, Serial, t
Setup time, serial input, t
Hold time, serial input, t
Operating free-air temperature, T

NOTE 1: SI must go low before the rising edge of the next clock pulse.

DD

I

IH

IL

clock

int

int

su(SI)

(see Note 1) 0 ns

h(SI)

A

3 5 5.5 V
0 V
2 V
0 0.8 V

5 8000 kHz

0.018 100 ms

0.034 100 ms
20 ns

0 70 °C

DD
DD

V
V

2

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