TAOS TSL1401R Datasheet

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TSL1401R

128 × 1 LINEAR SENSOR ARRAY WITH HOLD



TAOS035B – AUGUST 2002

 128 × 1 Sensor-Element Organization
 400 Dots-Per-Inch (DPI) Sensor Pitch
 High Linearity and Uniformity

SI 1

DIP PACKAGE

(TOP VIEW)

8 NC

 Wide Dynamic Range...4000:1 (72 dB)
 Output Referenced to Ground

CLK 2

7 GND

 Low Image Lag . . . 0.5% Typ
 Operation to 8 MHz

AO 3

6 GND

 Single 3-V to 5-V Supply
 Rail-to-Rail Output Swing (AO)

DD

4

5 NC

V

 No External Load Resistor Required
 Replacement for TSL1401

Description

The TSL1401R linear sensor array consists of a 128 × 1 array of photodiodes, associated charge amplifier
circuitry, and an internal pixel data-hold function that provides simultaneous-integration start and stop times for
all pixels. The pixels measure 63.5 µm (H) by 55.5 µm (W) with 63.5-µm center-to-center spacing and 8-µm
spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI)
signal and a clock.

NC – No internal connection

Functional Block Diagram

Pixel 1

2

CLK 128-Bit Shift Register

1

SI

The

LUMENOLOGY

 Company

Integrator

Reset

_
+

Sample/

Output

Switch Control Logic

Pixel

2



Texas Advanced Optoelectronic Solutions Inc.

800 Jupiter Road, Suite 205  Plano, TX 75074  [phone]

www.taosinc.com

Pixel

3

6, 7

4

V

DD

3

AO

GND

1

Pixel

128

Analog

Bus

Q3Q2Q1Hold

Q128



Output
Buffer

Gain
Trim

Copyright  2002, TAOS Inc.

TSL1401R

128 × 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS035B – AUGUST 2002

Terminal Functions

TERMINAL

NAME NO.

AO 3 Analog output.
CLK 2 Clock. The clock controls charge transfer, pixel output, and reset.
GND 6, 7 Ground (substrate). All voltages are referenced to the substrate.
NC 5, 8 No internal connection.
SI 1 Serial input. SI defines the start of the data-out sequence.
V

DD

4 Supply voltage. Supply voltage for both analog and digital circuits.

DESCRIPTION

Detailed Description

The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.

During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the
integration time.

The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition,
SI must go low before the next rising edge of the clock. An internal signal, called Hold, is generated from the
rising edge of SI and transmitted to analog switches in the pixel circuit. This causes all 128 sampling capacitors
to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is
clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a
charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first
18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the
129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a
high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and
return the internal logic to a known state. A subsequent SI pulse may be presented as early as the 130th clock
pulse, thereby initiating another pixel output cycle.

AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail
output voltage swing. With V

for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by:

where:

V

out

V

drk

R
E

e

t

int

is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(µJ/cm2)

e

is the incident irradiance in µW/cm
is integration time in seconds

= 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V

DD

= V

V

out

+ (Re) (Ee)(t

drk

2

int

)

A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device.
The TSL1401R is intended for use in a wide variety of applications, including: image scanning, mark and code

reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical
linear and rotary encoding.

Copyright  2002, TAOS Inc.



The

LUMENOLOGY

 Company

2

www.taosinc.com



TSL1401R

128 × 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS035B – AUGUST 2002

Absolute Maximum Ratings

†

Supply voltage range, VDD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI –0.3 V to VDD + 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) or (VI > VDD) –20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high impedance or power-off state, VO –0.3 V to VDD + 0.3 V. . .
Continuous output current, I

(V

= 0 to VDD) –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

O

Continuous current through VDD or GND –40 mA to 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog output current range, IO –25 mA to 25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum light exposure at 638 nm 5 mJ/cm

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions (see Figure 1 and Figure 2)

MIN NOM MAX UNIT

Supply voltage, V
Input voltage, V
High-level input voltage, V
Low-level input voltage, V
Wavelength of light source, λ 400 1000 nm
Clock frequency, f
Sensor integration time, t
Setup time, serial input, t
Hold time, serial input, t
Operating free-air temperature, T

NOTE 1: SI must go low before the rising edge of the next clock pulse.

DD

I

IH

IL

clock

int

su(SI)

(see Note 1) 0 ns

h(SI)

A

3 5 5.5 V
0 V
2 V
0 0.8 V

5 8000 kHz

0.018 100 ms
20 ns

0 70 °C

DD
DD

V
V

2

The

LUMENOLOGY

 Company



www.taosinc.com

Copyright  2002, TAOS Inc.



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