TAOS TSL1301 Datasheet
TSL1301
102 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS006B – JUNE 2001
102 × 1 Sensor-Element Organization
(TOP VIEW)
300 Dots-Per-Inch (DPI) Sensor Pitch
High Sensitivity
Output Referenced to Ground
Excellent High-Temperature Dark Signal
Characteristics
Operation to 2 MHz
SI
1
CLK
V
NC – No internal connection
AO
DD
2
3
4
NC
8
GND
7
GND
6
NC
5
Single 5-V Supply
Description
The TSL1301 linear sensor array consists of a 102 × 1 array of photodiodes, associated charge amplifier
circuitry, and a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels.
The pixels measure 85 µm by 77 µm with 85-µm center-to-center spacing and 8-µm spacing between pixels.
Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock.
The TSL1301 is intended for use in a wide variety of applications including mark and code reading, OCR and
contact imaging, edge detection and positioning, and optical encoding.
Functional Block Diagram
Pixel 1
_
+
Sample/
Output
Integrator
Reset
Pixel
2
Pixel
3
Pixel
102
Analog
Bus
Output
Amplifier
V
DD
4
6,7
3
AO
R
L
(External
Load)
Switch Control Logic
Hold
2
CLK 102-Bit Shift Register
1
SI
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Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 Plano, TX 75074 (972) 673-0759
Gain
Trim
Q3Q2Q1
Q102
Copyright 2001, TAOS Inc.
1
TSL1301
102 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS006B – JUNE 2001
Terminal Functions
TERMINAL
NAME NO.
AO 3 Analog output
CLK 2 Clock. The clock controls charge transfer, pixel output, and reset.
GND 6, 7 Ground (substrate). All voltages are referenced to the substrate.
NC 5, 8 No internal connection
SI 1 Serial input. SI defines the start of the data-out sequence.
V
DD
4 Supply voltage. Supply voltage for both analog and digital circuits.
DESCRIPTION
Detailed Description
The sensor consists of 102 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the
integration time.
The output and reset of the integrators is controlled by a 102-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI. An internal signal, called Hold, is generated from the rising edge of SI
and transmitted to analog switches in the pixel circuit. This causes all 102 sampling capacitors to be
disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked
through the shift register, the charge stored on the sampling capacitors is sequentially connected to a
charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first
18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the
103rd clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a
high impedance state. Note that this 103rd clock pulse is required to terminate the output of the 102nd pixel,
and return the internal logic to a known state. A subsequent SI pulse may be presented as early as the 104th
clock pulse, thereby initiating another pixel output cycle.
AO is driven by a source follower that requires an external pulldown resistor. When the output is not in the output
phase, it is in a high-impedance state. The output is nominally 0 V for no light input and 2 V for a nominal
white-level output, with a nominal full-scale (saturation) voltage of 3 V.
The TSL1301 is intended for use in a wide variety of applications, including: image scanning, mark and code
reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical
linear and rotary encoding.
Copyright 2001, TAOS Inc.
2
www.taosinc.com
TSL1301
102 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS006B – JUNE 2001
Absolute Maximum Ratings
†
Supply voltage, VDD 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input current range, II –20 mA to 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
–25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN NOM MAX UNIT
Supply voltage, V
Input voltage, V
High-level input voltage, V
Low-level input voltage, V
Wavelength of light source, λ 400 1000 nm
Clock frequency, f
Sensor integration time, t
Setup time, serial input, t
Hold time, serial input, t
Operating free-air temperature, T
NOTE 1: SI must go low before the rising edge of the next clock pulse.
DD
I
IH
IL
clock
int
su(SI)
(see Note 1) 0 ns
h(SI)
A
4.5 5 5.5 V
0 V
VDD × 0.7 V
0 VDD × 0.3 V
5 2000 kHz
0.0425 100 ms
20 ns
0 70 °C
DD
DD
V
V
CLK
SI
Internal
Reset
Integration
AO
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18 Clock Cycles
Not Integrating Integrating
103 Clock Cycles
Figure 1. Timing Waveforms
Hi-ZHi-Z
Copyright 2001, TAOS Inc.
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