Tandy Deluxe User Manual

Cat. No. 25-3047

Deluxe

Graphics Display Adapter

User's Manual

TANDY

8

TERMS AND CONDITIONS

EQUIPMENT AND SOFTWARE PURCHASED FROM A RADIO SHACK COMPANY-OWNED

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OF

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software included with the Equipment or licensed separately (the "Software") meets the specifications, capacity,
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Equipment and Software are to function, and for its installation.

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Equipment, RADIO SHACK warrants to the original CUSTOMER that the Equipment
is stored is free from manufacturing defects. This warranty is only applicable to purchases of Radio Shack and Tandy

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remedy, in the event of a Software manufacturing defect, is its repair or replacement within thirty (30) calendar days of the
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The

warranties granted herein give the original CUSTOMER specific legal rights, and the original CUSTOMER may have other rights

which vary from state to state. 8J83

stated

provided herein no employee, agent, franchisee, dealer or other person is authorized to give any warranties of any

provided herein, Radio Shack shall have no liability or responsibility

sold,

leased, licensed or

from

Radio Shack company-owned computer centers, retail stores and from Radio

warranty

period,

the defective Equipment must

the

purchase price, at RADIO SHACK's election

Center,

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furnished

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and

Warranty provisions herein shall inure to the benefit of

the

Software

resulting from

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the

only

and

the medium upon which the Software

be

returned to a Radio Shack Computer

The

original CUSTOMER'S exclusive

to

customer

or any

other

but not

limited

to,

any interruption

the

use or

operation

exceed

RADIO SHACK

for backup orarchival purposes or if

software

RADIO

on one

computer, subject to

SHACK,

the author, ownewnd/or

Center,

and

sole expense.

set

forth

herein.

person

or entity

of

service,

of

the

"Equipment"

the amount paid by

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Software

additional

copies

a

FCC ID: EKS56ARES400

Certified to comply with Class B limits, Part 15 of FCC Rules.

See instructions if interference to radio reception is suspected.

This equipment generates and uses radio frequency energy and
if not installed and used properly, that is, in strict accordance
with the manufacturer's instructions, may cause interference to
radio and television reception. Please note that all peripherals
must be attached with shielded cables to prevent interference.

It has been type tested and found to comply with the limits for a
Class B computing device in accordance with the specifications
in Subpart J of Part 15 of FCC Rules, which are designed to
provide reasonable protection against such interference in a
residential installation. If this equipment does cause interference
to radio or television reception, which can be determined by
turning the equipment off and on, the user is encouraged
to try to correct the interference by one or more of the
following measures.

1.

Reorient the receiving antenna.

2.

Relocate the computer with respect to the receiver.

3. Plug the computer into a different outlet so that the computer
and receiver are on different branch circuits.

4.

If necessary, the user should consult the dealer or an

experienced radio/television technician for additional
suggestions.

2

TABLE OF CONTENTS

Page
Section 1
Introduction 5

Section 2
Programming The DGDA 7

Section 3
Specifications 23

Section 4
DGDA Switch/Jumper Settings 25

Section 5
Video Timing Diagram 27

3

4

SECTION 1
INTRODUCTION

Features of the Tandy Deluxe Graphics
Display Adapter (DGDA)

The DGDA is designed for use with the Tandy
Monitor. The combination provides you with a high quality
640x400 text and graphics display in conjunction with your
existing software. Additional graphics modes are available with
appropriate software drivers. The DGDA is compatible with
drivers written for the Super Res 400 and Graphix Plus II
display adapters from STB Systems, Inc.

The DGDA is switch selectable to function as a

monochrome/color graphics adapter, or as a color graphics

adapter only.
The DGDA can be plugged into any available expansion slot

in a Tandy 1200 HD or compatible computer. The configuration
switch on the DGDA is factory pre-set for most applications.
See Section 4 for optional settings. Consult the owner's manual
of your computer for information regarding installation and

system switch settings. NOTE: Set the system switches

for color.

The DGDA will provide you with the following display
capabilities:

CM-1

Color

Text Display

• High resolution 80 character x 25 line display with 8x16
character

• Dual 256 character sets in ROM or EPROM.

• Underline, blink, reverse video, hidden and dual intensity
character attributes.

cell.

5

Graphics Display

• Supports the following display modes:
320 x 200* x 4 color graphics
640x200* x2 color graphics

• Supports the following display modes with appropriate
software drivers:
320 x 200* x 16 color graphics
640 x 200* x 4 color graphics
640 x 400 x 2 color graphics

*Each of the 200 lines are drawn twice in order to fill the full 400

line screen.

The DGDA can be used with a VM-1 Monochrome Monitor. An
optional cable is required. The cable is available from Radio
Shack National Parts. Ask for Part No. AW-0027.

6

SECTION 2

PROGRAMMING

THE DGDA

This section of the manual covers material of interest to those
who intend to write programs that use advanced features of the

DGDA. A basic understanding of the operation of the Tandy
1200's standard video display adapters and ROM BIOS is
assumed.
additional programming information.

If you intend to write programs that directly manipulate the
DGDA's control registers, be careful of the values you set into

the registers.
The DGDA board can be divided into 4 major sections: the

mode switch, 6845 CRT controller chip (CRTC), control and
status registers, and the 64Kb of video display memory.

DGDA Mode Switch

Refer to the Tandy Technical Reference Manual for

1

2&3

4

5

6,7,8

OFF

ON
OFF-OFF
OFF-ON

ON-OFF
ON-ON
OFF
ON
OFF
ON

Board responds as BOTH Monochrome
and Color Adapter cards.

Color/Graphics adapter only
High Resolution monitor (25 KHZ H.F.)
High Resolution monitor (25 KHZ H.F.)
High Resolution monitor (25 KHZ H.F.)

High Resolution monitor (25 KHZ H.F.)
Vertical Sync Negative (Inverted)
Vertical Sync Positive
Horizontal Sync Negative (Inverted)

Horizontal Sync Positive
These 3 switches control which colors

are sent to the mono display (6 = red,
7 =

green,

OFF blocks it.

8 = blue). ON sends the color,

7

Depending upon the settings of the DGDA's configuration
switch (Switch 1), the DGDA can be configured as a
color/graphics or as a monochrome and color/graphics adapter.

SWITCH 1

OFF

ON

If the DGDA is set to respond as either adapter, any I/O

accesses at the monochrome/printer adapter's 6845 CRT

register addresses will switch the board into monochrome

adapter mode and any accesses to the color/graphics adapter's

CRTC registers will place the board into color/graphics

adapter mode.
Throughout the rest of this manual, I/O control register

addresses are given as two hex numbers in parentheses:

MODE

Both adapters. Software controls adapter mode.
Color/graphics adapter only.

(MONO/COL)

The first number is the address that the monochrome adapter

responds to and the second number is the color/graphics

adapter address. Individual register bits are referred to as a

2 hex digit "bit-mask."

CRTC Controller Chip

The 6845 CRT Controller Chip (CRTC) is the main control

circuit of the DGDA board. It produces all the timing, control,

synchronization, and display addresses for the board.

CRTC Address Register (3B4/3D4)

The CRTC contains 16 control registers. These registers control

the timing position and width of the monitor sync pulses, display

and text cursor. The registers are accessed by first outputting

the number of the register to be accessed (0-15) into the CRTC

Address Register. This register is write-only. Its value cannot be

read back by software.

8

CRTC Data Register (3B5/3D5)

Once

the

CRTC Address Register

of

the

CRTC register

value

is

written
described briefly
refer

to a

6845 CRTC data sheet.

or

read

in the

to be

accessed (0-15),

via

this

following table.

has

I/O

address.

been

the

The

For a

6845 CRTC Register Definitions

set to the

register's data

full description,

number

registers

are

REG

0

1

2

READ/WRITE

Write

Write

Write

FUNCTION

HTOTAL—Total number
cells

per

scan line minus 1.
MODE register clock rate control
(01) sets
cell
determines
horizontal sync pulses

HDISP—Total number
displayed
memory WORDS from
are displayed. Cells from HDISP

HTOTAL-1
and screen border area. HDISP
added
address after each character

has been displayed.

applications each SCAN LINE
within

increments

8192 bytes.

HSPOS—Contains
location
sync pulse.
increased
shifted left

the

on the

to the

the

of the

timing

scan line. This register thus

the

frequency

per

character row. Display

are

used

video

character

the

display address

start

As

this register

in

value

the

on the

screen.

of

character
The

of

each character

of the

and

scan lines.

of

characters

0 to

HDISP-1

for

sync pulses

RAM

display

row

In

graphics

row

temporarily

the

character cell

of the

horizontal

is

picture

is

bit

to

is

3

Write

WIDTH—The lower four bits

register determine

horizontal sync pluse.

range from
character cell time

bit

01

upper four bits should

in the

9

0-15

MODE register.

the

width

Its

value

character cells.

is

determined

be set to 0's.

of

this

of the

may

The

The

by

REG
4

READ/WRITE

Write

FUNCTION

VTOTAL—This register is set with
the total number of character ROWS

(0-127) per frame of video. VTOTAL

together with the MAXSCAN register

(R9) determine the coarse frequency
of the vertical sync pulses.

5

6

7

8

9

10

Write

Write

Write

Write

Write

Write

VADJ—This register sets the number
of extra scan lines to add to each
video frame (0-31). It is used to
"fine-tune" the frequency of the
vertical sync pulse.

VDISP—This register determines the
number of character ROWS (0-127)
that are shown on the screen.

VSP—This register contains the
character row number of the start
of the vertical sync pulse (0-127).

Increasing the value of this register
will move the picture UP on
the screen.

INTERLACE —For normal, non-

interlaced use set this register to the
value "2".

MAXSCAN—This register is set
with how many scan lines tall each
character row is minus 1.

CURSOR START—The lower 5

bits of this register should be loaded

with the scan line number of the

character cell where the text cursor

should start (0-31). If the upper

three bits of this register are set

to "001XXXXX" then the cursor is

turned off.

10

REG

11

READ/WRITE

Write

FUNCTION

CURSOR END—This register is
loaded with the number of the last
scan line of the text cursor (0-31).
By changing the values in registers

R10 and

text cursor can be changed from an

underline to a block, dash, etc.

R11,

the shape of the

12,13

14,15

Write

Read/Write

START ADDRESS —These two
registers contain the number of
WORDS in the display RAM buffer to
skip before starting the display. R13 is
the lower 8 bits of the WORD (2 byte)
count. R12 is the upper 6 bits.

CURSOR ADDRESS —These two
registers contain the WORD offset
of the character/attribute word in
display RAM where the flashing text
cursor should appear. R15 is the

lower 8 bits of the WORD count.
R14 is the upper 6 bits.

Mode Control Register (3B8/3D8)

The MODE register is a 6 bit register that controls the basic
operating mode of the DGDA board. This register is a write only

register. The value stored in the register cannot be read back.

BIT

FUNCTION

01

VIDEO CLOCK RATE CONTROL—When set to a "0",
the video data is shifted out as a 11.144 Mhz dot (pixel)

rate.

The character CRTC character clock rate is .720

microseconds/char. This is used for 40 column text
displays and the standard IBM graphics modes. When
set to a
character rate is 0.360 microseconds/char. This is used
for 80 column text displays and the high resolution 16
color and 4 color graphics modes.

"1",

the dot clock rate is 22.285 Mhz and the

11

FUNCTION

BIT
02

GRAPHICS ENABLE—When set to a "0", the board is
in Text mode and the video display is produced via the
CHARACTER GENERATOR read-only-memory. When
set to a
mapped GRAPHICS generator circuitry. If software
operates the board at the Monochrome Display
addresses, this bit is ignored and the display is forced

into TEXT mode.

04

This bit is only used in the 4 color graphics modes.

It should normally be set to a "0". If set to a
CYAN/MAGENTA/WHITE pallette is changed to
CYAN/RED/WHITE.

"1",

the video display is produced by the bit-

"1"

the

08

10

20

VIDEO ENABLE—When set to a "0", the video display
are turned off. When set to a
sent to the active video monitor. The setting
of this bit is forced to a
configures the board for 80 column text displays in
COLOR/GRAPHICS adapter modes.

640 DOT GRAPHICS ENABLE—When set to "0", the
graphics display circuitry is set to display a picture with
320 dots/line. Setting this bit to a
dot display. This bit is used only when the GRAPHICS
bit (02) is set to a

BLINK ENABLE —When set to a "0", text characters

cannot blink, but can be shown with up to 16 different

background colors. When set to a
background color intensity for all characters is
determined by bit 10 of the COLOR register described
below and background intensity BIT (80) of the display

RAM character attribute byte will control the blinking of

the character (if set, the character will blink). This bit is

used only when the GRAPHICS bit (04) is set to a "0".

"1"

"1".

"1",

the video display is

whenever software

"1"

produces a 640

"1"

the character

12

Color Control Register (3B9/3D9)

This register is a 6 bit write-only register that controls the color
processing circuitry.

BIT

FUNCTION

01

Blue—In TEXT modes this bit has no function. In

4-color GRAPHICS modes, this bit controls the color

blue of the BACKGROUND color (00) pixels.

02

Green — In
4-color GRAPHICS modes, this bit controls the color
green of the BACKGROUND color (00) pixels.

04

Red

— In TEXT modes this bit has no function. In

4-color GRAPHICS modes, this bit controls the color

red of the BACKGROUND color (00) pixels.

TEXT modes this bit has no function. In

INTENSITY—

08

In 4-color GRAPHICS modes, this bit controls the
intensity of the BACKGROUND color (00) pixels.

10

In TEXT modes this bit controls the character
background intensity of all the characters on the

screen if the BLINK bit (20) is set in the MODE register.

In 4-color GRAPHICS modes, this bit controls the
INTENSITY of the foreground color set. A
high intensity colors, a "0" selects normal.

20

In 4-color GRAPHICS modes this bit selects which of
two color "pallettes" is displayed. When set to a "0" the
available colors are BACKGROUND/GREEN/RED/

BROWN. A "1"

MAGENTA/WHITE. This is ignored in all other modes.

In

TEXT modes this bit has no function.

selects BACKGROUND/CYAN/

"1"

selects

13

Status Register (3BA/3DA)

This is a 4 bit read-only register that software can check to
determine various information about the display.

When read at the MONOCHROME Adapter address (3BA) the
following information is returned:

FUNCTION

BIT

HSYNC—The current state of the display monitor

01

horizontal sync pulse can be monitored here. A
indicates the pulse is active.

02

Always "0"

04

Always "0"
VIDEO

08

showing a lighted pixel. When read as a "0" the display

is showing an unlighted pixel. This information helps

diagnostic programs test the operation of the board.

When this register is read at the COLOR/GRAPHICS address

(3DA) the following information is returned:

FUNCTION

BIT

DISPLAY INACTIVE —Set to a

01

beam is in the SYNC or BORDER areas of the display.
This bit is a "0" during the active portion of the display.

Note that the DGDA display memory can be accessed
at any time without causing "snow" to appear in the

picture. Programs that wait for this bit to be set before

accessing the display memory will run much faster if
they are modified to NOT wait on the bit.

DOTS

—When read as a

"1"

"1"

the display is

when the display

"1"

02

Always "0"

04

Always
VSYNC—While this bit is a

08

within the vertical sync area. This information is useful
for special animation effects, etc.

"1"

"1",

the display beam is

14

Video Display Memory

The DGDA has 64 kilobytes (Kb) of dual-ported video display

memory shared between the expansion bus and the 6845
CRTC video display controller. The bus may access the video
memory at any time without causing any "snow" to appear
in the picture. The board may generate 0-2 wait states
depending upon the timing of the memory request. The
video display memory supports DMA (direct memory access
controller) requests.

Software using the monochrome display adapter accesses
the 32Kb of video display memory at segment address B000.
Color/graphics adapter software accesses the 32Kb of memory
at segment address B800.

The standard Color/Graphics Adapter memory appears to
the system as a single 16Kb block of memory duplicated at

segments B800 and BC00. The DGDA has independent 16Kb
memory blocks at these segments. Software that expects the
same data to appear in both 16Kb segments may need to be
modified to work with the DGDA's extra memory.

The CRTC sequentially accesses the video display memory,
fetching and displaying a 16-bit word of data every 360 or
720ns, depending upon how the CLOCK RATE bit (01) of the
MODE register is set. The MODE register also determines how
this word of data will appear on the screen.

The DGDA has two modes of displaying the video memory
word,

Text and Graphics. Bit 02 of the MODE register

determines the mode.

Text Mode

If bit 02 of the MODE register is low, the board is in TEXT
mode and the word of video data is sent to the CHARACTER
GENERATOR logic.

The even byte of each word contains the number of the
character to display. The standard character set contains 256

unique characters numbered from 0-255.

15

The odd byte (attribute byte) determines the color of the
character dots and their surrounding background. The lower
four bits contain the color code of the character's dots. The
upper four bits determine the color of the dots in the character
matrix that surround the character outline.

Even Byte—Character Code

Bits 7 6 5 4 3 2 1 0

character code 00 - FF

Odd

Byte —

Bits 7 6 5 4 3 2 10

I R G B I R G B

BACKGROUND FOREGROUND

Sixteen unique colors are available for the foreground or
background. These colors are formed by combining the basic

colors Red, Green, and Blue with an optional Intensity bit.

Character Color

COLOR CODE

0

1
2
3
4
5
6
7
8
9

10
11
12

SCREEN COLOR

Black
Blue
Green
Cyan (pale blue)

Red

Magenta (purple)
Yellow
White

Dark Grey

Bright Blue

Bright Green

Bright Cyan

Bright Red

16

COLOR CODE

SCREEN COLOR

13
14

15

* Some color monitors ignore the Intensity signal and colors

8-15 appear the same as 0-7.

* By properly combining foreground and background colors,

special effects such as reverse video, hi-lighting, and hidden
text can be obtained.

Blinking Text

The background intensity bit (80 or ODD bytes) in the video
display word is shared with the character BLINK logic. If bit 20
of the MODE register is "0", then all 16 colors are available for
character backgrounds. If the bit is set to a

intensity bit (80) is changed to be a "BLINK CHARACTER" bit
and the background intensity for ALL characters is supplied
from bit 10 of the COLOR REGISTER.

Bright Magenta
Bright Yellow

Bright White

"1",

the background

Character Generator ROM

The patterns of dots that make up the characters that the

DGDA displays in text modes are stored in a computer chip

called a read-only-memory or ROM. The character generator

ROM actually contains the patterns for the TWO sets of 256
characters. The first 256 characters (4096 bytes) contains the
color/graphics adapter characters. The next 256 characters
(4096 bytes) are the monochrome display adapter characters.
The board automatically switches between the character sets
based upon how the 6845 CRT controller chip MAX SCAN LINE
register (R9) is programmed. Values less than 10 will select
the color graphics set. Values of 10 or above will select the
monochrome display set.

17

The color graphics adapter set shows characters as an 8 x 8

matrix of closely spaced dots. The monochrome character set is
formed in an 8 x 14 matrix. Each byte in the EPROM contains
one scan line of 8 dots for a character. Each character is

stored in the EPROM as a 16 byte block; the patterns for each

character are aligned in the first 8 or 14 bytes of the 16 byte

blocks. Since there is no spacing between adjacent character

cells on the screen, continuous line and block graphics

characters are easily made.

The contents of the standard ROM supplied with the boards

cannot be changed. For applications that require a different or

customized character set the standard ROM chip (the 28 pin

device on the DGDA labeled CGEN) may be replaced by a user

programmable part called an EPROM (Erasable Programmable
Read Only Memory). The EPROM used on the DGDA board is
an industry standard 2764 type device with an access time of
450ns (nanoseconds) or faster. This type of device contains
8K bytes of data. The contents of an EPROM may be erased
by exposing it to ultraviolet light. A device called an EPROM
Programmer may be used to write new data into an
erased EPROM.

Graphic Modes

If bit 02 of the MODE register is set to a
operating as a Color/Graphics adapter, then the video display
words are shown on the screen as a series of independently
colored dots. Depending upon the settings of the 640

GRAPHICS (10) and CLOCK RATE (01) bits in the MODE

register, the DGDA will show these 16 bits in one of four

basic ways:

NOTE:

If a value greater than or equal to 16 is loaded into the

Max Scan Register (09) of the 6845, the DGDA will be
placed into a 400 line graphics mode.

18

"1"

and the DGDA is

MODE

REGISTER

Bit 10

1
1

01

0

Graphics Resolution

16 pixels of 2 colors (640 x 200/352 x 2 colors)

1

8 pixels of 4 colors (640 x 200 x 4 colors)

0
0

1
1

0

*Modes not available on the standard Color/Graphics Adapter.

These modes use all 64Kb of the display RAM. The standard
modes use 16Kb.

Two Color Mode

In this mode, each bit in the word produces one dot on the
screen.
"1"

produce dots of the color indicated by the BACKGROUND

bits (08, 04, 02, & 01) of the COLOR register.

0

1

0

1
1

The dot is always black if the bit is a "0". Bits set to a

Bit: 7 6 5 4 3 2 10

Bit: 7 6 5 4 3 2 10

8 pixels of 4 colors (320 x 200 x 4 colors)
4 pixels of 16 colors (320 x 200 x 16 colors)

16 pixels of 2 colors (640 x 400 x 2)

8 pixels of 4 colors (640 x 400 x 4 colors)*
4 pixels of 16 colors (320 x 400 x 16 colors)*

EVEN BYTE

CO CO CO CO CO CO CO CO

ODD BYTE

CO CO CO CO CO CO CO CO

Sixteen Color Mode

This mode divides each 16 bit word into 4 "nibbles" of 4 bits

each.

The four bits of each nibble represent the color number

(0-15) as shown in the color table in the text section above.

EVEN BYTE

Bit: 7 6 5 4 3 2 10

C3 C2 C1 CO C3 C2 C1 CO

ODD BYTE

Bit: 7 6 5 4 3 2 10

C3 C2 C1 CO C3 C2 C1 CO

19

Four Color Mode

This mode treats each word as 8 pixels of 2 adjacent bits (C1
and CO). Each pair of bits produce a dot that can be one of four
colors. Bit 20 in the COLOR register and bit 04 in the MODE

register select one of three available "pallettes" of four colors.
Setting bit 10 in the COLOR register will intensify all the
foreground colors on the screen.

EVEN BYTE

Bit: 7 6 5 4 3 2 10

C1 CO C1 CO C1 CO C1 CO

ODD BYTE

Bit: 7 6 5 4 3 2 10

C1 CO C1 CO C1 CO C1 CO

REGISTER BITS

Color

20

0

0

1

1

or

Mode

04

0

1

0

1

Pixel

C1

0
0

1
1

0
0

1
1

0

0
1
1

CO

0

1

0

1

0

1

0

1
0

1

0

1

COLOR

Color Reg BACKGROUND
bits
Green

Red
Brown
Color Reg BACKGROUND
bits
Cyan

Magenta
White

Color Reg BACKGROUND

bits

Cyan

Red

White

20

In 200 line graphics modes, the CRTC chip should be
programmed to display either 100 character rows of 2 scan lines
per row (for standard resolutions of 320 x 200 x 4 color and
640 x 200 x 2 color), or 50 character rows of 4 scan lines per
row (for the extra modes of 320 x 200 x 16 color and
640x200x4 coior).

In 400 line graphics modes, the CRTC chip should be
programmed to display either 100 character rows of 4 scan lines
per row (for resolutions of 640 x 400 x
of 8 scan lines per row (for resolutions of 640 x 400 x 4 and
320x400x16).

The CRTC chip produces a series of sequential addresses as it
fetches display words for each scan line of the picture from

video memory. Note however that each scan line within every

character row is offset in the video memory 8192 bytes (2000

hex) from the preceding scan line of the character row.

2),

or 50 character rows

CHARACTER

SCAN LINE

00

01

02*

03*

* These higher resolution modes require all 64Kb of video

display memory.

ROW

NO.

OFFSET FROM START OF BUFFER

&H0000
&H2000
&H4000
&H6000

21

l\3

DGDA Typical Register Values

Resolution: 80x25
Adapter Mode: Monochrome
Text/Graphics: Text

RO-HOR TOTAL
R1-HORDISP
R2-HSYNC POSN
R3-HS WIDTH
R4-VERT TOTAL
R5-VERT ADJ
R6-VERT DISP
R7-VSYNC POSN
R8-INTERLACE
R9-MAX SCAN
R10-CUR START
R11-CURSOR END
R12-START (H)
R13-START (L)
R14-CURSOR (H)
R15-CURSOR (L)

MODE REG VALUE
MODE REG ADDR

COLOR REG VALUE
COLOR REG ADDR
CRTC CHIP ADDR

VIDEO MEMORY
SEGMENT

VIDEO MEMORY
LENGTH

61
50
52
OF
19
06
19
19
02
OD
OB
OC
00

00
00
00

29
3B8

30
3B9
3B4

B000

OFFF

80x50

Monochrome

Text

61
50
52

OF
2E
06
32
2C
02

17
05
07
00
00
00
00

29
3B8

30
3B9
3B4

B000

1FFF

640 x 400 x 2
Monochrome

Graphics

31
28
29

08
6C
06

64

68

02

13
06
07
00
00
00
00

1E
3D8

2F
3D9
3D4

B000

7FFF

640 x 400 x 4

Color

Graphics

71
50
59

OC
3F
06
32
38
02
17
OB
OC
00
00
00
00

1B
3D8

30
3D9
3D4

B000*

FFFF

320x400x16

Color

Graphics

71
50
59

OC
3F
06
32
38
02

17
OB
OC
00
00
00
00

2B
3D8

30
3D9
3D4

B0O0-

FFFF

40x25

Color

Text

38
28
2D
OA
1F
06
19
1C
02
07
06
07
00
00
00
00

2C
3D8

30
3D9
3D4

B800

3FFF

80x25

Color

Text

71
50
5A
OA
1F
06
19
1C
02
07
06
07
00
00
00
00

2D
3D8

30
3D9
3D4

B800

3FFF

640x200x2

Color

Graphics

38
28
2D
OA
7F
06
64
70
02
01
06
07
00
00
00
00

1E
3D8

3F
3D9
3D4

B800

3FFF

320x200x4

Color

Graphics

38
28
2D
OA
7F
06
64
70
02
01
06
07
00
00
00
00

2A
3D8

30
3D9
3D4

B800

7FFF

640x200x4

Color ,

Graphics

71
50
59
OC
3F
06
32
38
02
03
06
07
00
00
00
00

1B
3D8

30
3D9
3D4

B800

7FFF

320x200x16

Color

Graphics

71
50
59
OC
3F
06
32
38
02
03
06
07
00
00
00
00

2B
3D8

30
3D9
3D4

B800

7FFF

Note:

All values given in hex.

*These graphics modes require 64K of memory. Therefore, the starting address is at B000.

SECTION 3
SPECIFICATIONS

The display connector on the DGDA is brought out via a 9 pin
cable connector located on the DGDA mounting bracket. This
connector is used to connect a cable from the DGDA to a
Tandy

CM-1

Color Monitor. The pinouts of this connector are

defined below:

9 PIN "D"

1
2
3
4

5
6

7

8

9

POWER CONSUMPTION: 7.5 Watts
OUTPUTS: Video Signals = TTL level, positive polarity

Sync Signals = TTL level, positive polarity

(default)*

*Sync signal polarity is switch selectable.

DIMENSIONS: 13.2 "x 4.2"

DESCRIPTION

Ground
Ground

Red
Green
Blue
Intensity
Composite
Horizontal Sync
Vertical Sync

23

24

SECTION 4
DGDA SWITCH/JUMPER

SETTINGS

1.

Locate the switch box on the DGDA. (See Figure 1.)

W7

W1

2.

Figure 2 gives you the factory pre-set switch settings. This

allows the DGDA to work with a Tandy CM-1 Color Monitor.
Check to be sure the switches are set correctly.

3. Refer to the following switch summary for optional
switch settings.

SWITCH BOX

Figure

Figure 2 —DGDA Switch Settings

1 — DGDA

Diagram

4.

Jumper

across the lower two pins.

W1

is not connected. Jumper W7 has a shorting plug

25

Switch Summary

OFF

1

ON
OFF-OFF

4

5

OFF-ON
ON-OFF
ON-ON
OFF
ON
OFF
ON

2&3

6,7,8

NOTES ON SETTING SWITCHES

Switches 2 and 3—Leave these switches in the OFF position.

Board responds as BOTH Monochrome
and Color Adapter boards.

Color/Graphics adapter only.
High Resolution monitor (25 KHZ H Sync)
High Resolution monitor (25 KHZ H Sync)
High Resolution monitor (25 KHZ H Sync)
High Resolution monitor (25 KHZ H Sync)
Vertical Sync Negative (Inverted)
Vertical Sync Positive

Horizontal Sync Negative (Inverted)
Horizontal Sync Positive

These 2 switches determine which colors
are sent to the mono display (6 = red,
7 =

green,

OFF blocks it.

8 = blue). ON sends the color,

Switches 4 and 5—Consult the spec's of your monitor to set
these switches.

26

SECTION 5

VIDEO TIMING DIAGRAM

Horizontal Sync

Horizontal Sync Rate may vary.

fh

= 26.4 Khz

fdot = 22.285 Mhz

fv = 60hz

Vertical Sync

27

RADIO SHACK, A Division of Tandy Corporation

U.S.A.:

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CANADA:

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WORTH,

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TEXAS 76102

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39

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