Tandy 26-3334 Service Manual

TANDY'

/~\

Service

COLOR

with

IMTSC/PAL VERSION

512K Expansion RAM Card

Catalog Number:

COMPUTER 3

Ul

26-3334

CUSTOM

MANUFACTURED FOR

RADIO

SHACK,

DIVISION

A

TANDY CORPORATION

OF

SECTION I. GENERAL

TABLE

OF

CONTENTS

1.1

1.2

1

1.4

1.5 Chip Control

1.6

SECTION

2.1 Technical

2.2 Physical

SECTION III.

3.1 Disassembly

3.2 Assembly

3.3

SECTION

4.1

Introduction

System

Memory

3

.

I/O

68B09E

512K

NTSC

Description

Map

Control

Vector

II.

SPECIFICATIONS

DISASSEMBLY/ASSEMBLY

RAM Upgrade

BLOCK

IV.

Version

4.2 PAL Version

SECTION

V.

THEORY

Registers

Registers

Registers

Instructions

DIAGRAM

OF OPERATION

5
5

8

9

11

22

23

25

26
26

27

28

29

5.1 MC68B09E/MBL68B09E/HD68B09E

5.2 Memory

5.3 TCC1014

5.4

5.5 PIAs

5.6 Keyboard

5.7 ROM

5.8 DAC Circuitry

5.9

PAL Encoder

SALT

5.10 Cassette

5.11

RS-232C

5.12 Cartridge

(RAM)

(VC2645QC)

<IC4 and

Interface

(IC2)

Circuitry

Tape Format

Connector

Connector

(PAL

IC5)

(IC7)

Version

(IC5)

Information

(JK3)

(CNl)

Only)

5.13 Power Transformer

5.14 Joysticks

5.15

SECTION

6.1 Introduction

6.2

TV

VI.

Video

No

Wrong

Switch

Box (NTSC

TROUBLESHOOTING

Problems

Display/No

Color

Version

Sync/Noisy

No Color

Random

RGB

Composite

(PAL

Character/Clear

Problem

Video

Version

Only)

Signal

Screen/No

Adjustment

(IC1)

Only)

Video

,

, 55

Sign-on

30
34
36
38

39

40

41

42

44

47
47
49

52

52
53

54
55
55
55

....55

55

56

-2-

Keyboard

6 .

No Keyboard

6.4

6.5

Process

Cassette

ing

Motor
Write

Read Problem

6.6 RS-232C

6.7 Sound

Problem

6.8 Joystick

6.9 Cartridge

6.10

6.11

Power

NTSC

PAL

Major

NTSC

Supply

Vers ion

Version

Waveforms

Vers ion

PAL Version

Problems

Problem

Problems

Control

Problem

Problem

Problem

Problem

Check

Entry/Wrong

Problem

Character

56

56
56
56
56
56

56
57
57
57

57

58

58

61

64
64

70

SECTION

PCB VIEWS

ELECTRICAL

SECTION

PCB VIEWS

ELECTRICAL

EXPLODED
EXPLODED

SEMICONDUCTOR

SCHEMATIC

SECTION

PCB VIEWS

ELECTRICAL
EXPLODED
EXPLODED

SEMICONDUCTOR

SCHEMATIC

VII. 512K

PARTS

VIII. NTSC

PARTS LIST

VIEW
VIEW

DIAGRAM

IX.

PAL VERSION

PARTS
VIEW
VIEW

DIAGRAM

EXPANSION

LIST

VERSION

PARTS

LIST

INFORMATION

LIST

PARTS LIST

INFORMATION

RAM CARD

78
79

82
84
90

91

93

103

1 08

1 1

1

121

122
126

19

-3-

LIST

OF

FIGURES

1-1.

1-2.

1-3.

3-1.

3-2

3-3.
3-4.

4-1.

5-1.
5-2.

5-3.

5-4.

5-5

5-6.
5-7.
5-8.
5-9.

5-10.
5-11.
5-12.
5-13.
5-14.
5-15.

5-16.

Memory

Removal
Removal

Main PCB

Block

NTSC

PAL

MC68B09E
MC68B09E
MC68B09E

DRAM
DRAM

.

Color

MMU Block

PIA

Color

DAC

SALT

Color

I/O

RS-232C

Joystick

Antenna

Color
Color

512K

Computer

Computer

Map

for SAM

of Top
of

Main PCB

RAM Card

Diagram

Version

Version

Programming

Pin

Read/Write

Block

Diagram

Timing

Computer

Diagram

Block

Diagram

Computer

Block

Block

Diagram

Diagram

Computer

Circuitry

Connector

Schematic

Switch

3

Installation

Memory

3

Control

Cover

Model

Assignments

Timing

Address

3

Keyboard

3

(IC7)

(IC8)

3 Power

Pinout

Box

Schematic

Map

Register

at 0.89

Decoding

Array

Supply

MHz

7

8

21

26
26

][ 2 7

27

28
28
29

30

31

33
34
35
36

37
39

40
42
44

45
45

48

52

....53

1

2
3

Line

Alternate
Cartridge

Printer

Line

Connector

LIST

OF

Variables

Printer

-4-

TABLES

Variable

Signals

Values

,

50
50

51

SECTION I.

GENERAL

1.1 Introduction

The

Color

version

Computer

the

same

predecessor,

latest in

Figure 1-1

installation

The

Color

internal

is

accessed

up.

Other

may

be

on

the right

optional

allows

installed

selection

active

either by

the

Multi-pak

peripheral

external

the

Color

memory

All input

Color

of the

and

the RGB

CM-8),

of

the unit.

joystick input

left),

output

television

Computer

Tandy's

of

It is

2.

reliable

but it

electronic

shows

of

Computer

BASIC

program in

when the unit

program

inserted

side

Multi-pak

up

to four program

at

the

of

the

at

any one

software

Interface.

devices,

disk

drive,

Computer

storage and

and output

Computer

program

module/cartridge

monitor

are located

These

ports (right and

Serial I/O,
jack

(for standard

set and

monitor), POWER

RESET

switch

on the

PAL

rear

switch.

A recessed

(for selecting

-

TV

version)

3/4

is

panel of the unit.

is

3

popular

designed
operation

refined

a

Color

to provide

as its

incorporates

technology.

a

typical

the

Color

3

Computer

contains

ROM which

is powered

modules/cartridges

into

the

receptacle

of the

Interface

unit.

module

paks

same time, with

specific module

time

selected

by

or

a switch

Additional

such as

an

may be added

3 for

additional

retrieval.

3,

ports

with

the

for the

exception

output (for

on

the rear

include the

Cassette

I/O, TV

color

composite

ON/OFF switch and

channel

either

for NTSC and

also located

channel

1/2

on the

an

An

to be

panel

the

on

to

slot

for

3.

1.2

System

The

primary

Computer

Description

are

3

Large Scale

plus Random

Read Only

chips

are labeled

diagram

With

only

Random
Memory

Color

Computer

Access Memory (RAM)

Memory

as CPU,

these

Access

(ROM)

provide video

Analog

RGB).

communication

I/O interfaces

The

main

system

(CPU,

CPU

select

data. In

of

performing

IC1).

to

component

is the

provide

the

proper address

addition,

mathematical

on the

ROM

providing

set of

CPU

execute

operation,

address

switch

performs

all of the

Following

residing

CPU.

data.

(IC2)

has

the CPU

instructions.

would run

instructions.

the CPU

in ROM,

has

been

the

programmable

this,

in

functions

performed by

Integration

(ROM).

on

the block

ACVC and

four chips,

Memory (RAM),

and

a

power

3 will

output (RF,

However,

with

the outside

must be

of

Central

It is

the function

or request

the CPU

a limited

and

logical

the function

with

Without

wild and

jumps

after the

pressed,

reset

ROM is

program

the BASIC

in

of the

(LSI)

These

two

Color

four

chips,

and

four

PIAs.

plus

Read

supply, the

operate and

Composite,

to allow

world,

added.

any computer

Processing

of the

data and

for

this

is

capable

set

of

operations

of

a predefined

ROM,

randomly

In

normal

to

the start

reset

and

then

to set

devices.

interpreter

control

of the

Only

Unit

the

up

Note:

peripheral

unplug

cord.

device

Before

the

This

or

to the

installing

device,

Color
will

prevent

any

always

Computer's

damage

Color

Computer

remember

power

to the

3.

to

-5-

RAM

(IC16

for

the

currently

standard

x

but

4

256K

x

Paragraph

-

programs

being

unit,

may

ICs

1

3.3 on

instructions.)

RAM

is

used

display.

be

observed

use one

display

normal

located

execution

Normally,

portion

will

usage,

in

ROM,

of

IC19)

provides

and/or

executed.

these

be

upgraded

as an

option.

page 28

In

addition,

to

generate

no

because

of

the

RAM and

use another.

the BASIC

will

control

programs

storage

data

In

four

ICs

to

sixteen

(See

for

the

the

video

conflict

program

the

During

interpreter,

located

the

are 64K

same

will

will

the

in RAM.

all

other modes

Computer

mode,

text

192

it

screen,

graphics

designed

video

signals

analog

ACVC

can

512K

bytes.

(Memory

support

each

with

though

address

During

2.

generates

and

screen.

to output

-

RGB.

expand

Having

Management

banks

2

a 9-line

the CPU

lines.

included

High-Resolution

40 x

24 or

320 x

It

two

192

is

different

composite

memory

of

space up

a

built-in

Unit),

256K-byte

address

possesses

in

or

also

video

it

bus,

only

the

can

RAM,

Color

80

x 24

640 x

and

to

MMU

even

16

A central

Computer

Video

refresh

the

RAM,

system

ACVC

comprises

Generator)

3

Chip

and

It

timing

component

is

(IC6).

address

also

function

High-Resolution

the

Advanced

This

provides

and

device

the VDG

mode,

in

the

Color
Color

chip

provides

multiplexing

all of

selection.

(Video

which

in

addition

Display

supports

for
the

to

The

remaining

Computer

(I/O)

communication.

important

the

keyboard,

operator

I/O

circuits

joystick

output,

circuitry

is

3

devoted

part

of

which

to

enter

are

provided

input,

cassette

and RS-232C

in

the

to

Input/Output

The

most

this

circuitry

allows

the

information.

to

input

input

and

Color

is

Other

allow

and

output.

-6-

-7-

1 .

Memory

3

Map

Figure 1-2

large

blocks

Computer

The

rest

following

I/O

•

Chip Control

•

68B09E

•

shows the

of memory

3.

of

the

registers:

Control

Vector

breakdown

section

Register

Register

Register

in the

itemizes

of the

Color

the

$?FFfF

S7FFOO

S7E000-

S7COO0-

S7A0O0-

$78000-

$70600-
$70400-
$70000-

S6E00O-

S6C000-

$68000-

$60000-

SUPER

EXTENDED BASIC

CARTRIDGE

COLOR BASIC

EXTEND

COLOR

STANDARD

HIGH

RESOLUTION

TEXT

SCREEN

HIGH

RESOLUTION

GRAPHIC

SCREEN

ROM

TEXT

BASIC

SCREEN

68B09E

CONTROL

-REGISTER,

VECTOR,

I/O

h

O

i-

o
o

5

o

u
X

5
<

n.

SOOOOO

Figure

-8-

1-2.

Color Computer

Memory

3

Map

1.4

FFOO

FFOO:

FF01:

I/O

-

Control

FF03

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

BIT

BIT

BIT

BIT

BIT
BIT
BIT
BIT

Registers

=

KEYBOARD
KEYBOARD

1

KEYBOARD

2

KEYBOARD

3

KEYBOARD

4

KEYBOARD

5

KEYBOARD

6

JOYSTICK

7

Control of HSYNC

Interrupt

1

Control

Polarity

Normally

SEL

1:

1 Always
1 Always

Not

used

Horizontal

ROW
ROW

ROW

ROW

ROW

PIA

1

2
3

4

5

IC5

and right
and Left
and right
and

Left

ROW 6
ROW 7

COMPARISON INPUT

(63.5us)

of Interrupt

LSB

=

Changes

of

1:

sync interrupt

joystick switch 1

joystick switch 1

joystick

joystick

f
t

(0

=

=

1

=

=

1

switch 2

switch 2

IRQ*
IRQ*

Flag

falling

Flag set

rising

FFOO

the two

to the data

analog

flag

to CPU Disabled
to CPU Enabled

set

on the

edge

of HS

on the

edge

of HS

direction

MUX

select lines

register

FF02:

FF03:

BIT

BIT

BIT

BIT
BIT
BIT

BIT

BIT

BIT

BIT

BIT
BIT
BIT
BIT
BIT
BIT

=

1

=

2

=

3

=

4

=

5

=

6

=

7

KEYBOARD
KEYBOARD
KEYBOARD
KEYBOARD
KEYBOARD
KEYBOARD
KEYBOARD
KEYBOARD

Control

Interrupt

Control

NORMALLY

SEL

2:

1 Always
1 Always

Not

used

Field

sync

COLUMN 1
COLUMN
COLUMN
COLUMN
COLUMN

COLUMN

COLUMN
COLUMN

VSYNC

of

of Interrupt

1;

2
3

4
5
6

/RAM SIZE

7

8

(16.667ms)

=

changes FF02

MSB

of the two

interrupt

OUTPUT

Polarity

flag

=

CO

=

1

1

/"0

=

-

u

to the data

analog

MUX

IRQ*

to CPU Disabled

IRQ*

to CPU Enabled

sets flag
sets

flag

direction

select lines

on falling
on rising

register

edge

edge

FS

FS

-9-

FF20

FF20:

FF21;

-

BIT

BIT

BIT

BIT
BIT
BIT
BIT

FF23

BIT
BIT

BIT
BIT

BIT
BIT
BIT
BIT

BIT

=

CASSETTE

=

1

RS-232C

=

2

6 BIT

=

3

4

5

6

7

=

=
=
=

BIT

6

BIT

6

BIT

6
6 BIT
6 BIT

Control

(RS-232C

Interrupt

1

Control

Polarity

Normally 1:0=

Cassette

1

Always

1

Always

Not

Used

CD

Interrupt

DATA

D/A
D/A
D/A

D/A
D/A
D/A

of

of

PIA

DATA

OUTPUT

LSB

MSB

the

status)

Interrupt

Motor

Flag

IC4

INPUT

CD

changes

fO

\l

fO

(^1

U

FF20

=

=

=
=

=

Control: =

FIRQ*
FIRQ*

sets
sets

to

OFF

to CPU
to

flag
flag

the

CPU

on
on

data

=

1

Disabled

Enabled

falling

rising

direction

ON

edge

edge

register

CD

CD

FF22:

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

FF23:

BIT

BIT

BIT
BIT
BIT
BIT
BIT

BIT

-

FF40

FFBF:

Note: FF22,

(Bit

through

3

=

RS-232C

=

1

SINGLE

=

2

RAM SIZE

=

RGB

3

=

4

=

5

=

6

=

7

VDG
VDG

VDG
VDG

Monitor

CONTROL
CONTROL
CONTROL
CONTROL

Control

Interrupt

1 Control

Polarity

2

Normally

Sound

3

4

1 Always

5

6

7

Always

1

Not

=

Cartridge

Not

used

FF23

are

Bit

used

7) affects

DATA

INPUT

BIT

SOUND

INPUT

Sensing

OUTPUT
OUTPUT

OUTPUT
OUTPUT

of the

of

Interrupt

1:

Enable

Interrupt

duplicated

OUTPUT

INPUT

Cartridge

= changes

Flag

in

tcclOH

this

IC

CSS

GMO

GM1 &

GM2

A*/G

1

fO

^1

U

FF22

(VC2645QC),

(TCC1014)

=
=

=
=

=

to

& UP

INVERT

FIRQ*
FIRQ*

sets
gets

the

only.

PER/

to
to

flag
flag

data

LOWER

CPU
CPU

on
on

direction

and

V.D.G

CASE*

Disabled

Enabled

falling

rising

Control

edge

CART*

edge

CART*

register

Bit

-10-

1.5 Chip Control Registers

-

FF90

FFDF

ACVC IC6

FF90:

FF91:

Initialization Register (INITO)

BIT

7

BIT

6

BIT

5

BIT

4

BIT

3

BIT

2

BIT

1

BIT

Initialization

BIT

7

BIT

6

BIT

5

BIT

4

BIT

3

BIT

2

BIT

1

BIT =

=
=
=
=
=
=

=
=

=

COCO

M/P

IEN
FEN

MC3
MC2

MCI

MCO

MCI

1

1

TINS

TR

=

Color Computer 1 and 2 Compatible

=

MMU

=

Chip IRQ

=

Chip FIRQ

=

DRAM

=

Standard SCS

ROM map
ROM

map control (See

MCO

X

16K

32K

1

32K

Register 1 (INIT1)

Timer

MMU Task

enabled

output enabled

output enabled

XFEXX is

at

control (See

ROM mapping

Internal, 16K

Internal

External

Input

(except for

Select: 1

Register

constant

table
table

External

=

Select

below)

below)

vectors)

70 nsec

/

63 psec

FF92:

FF93:

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

Interrupt

-

7

6

4

6
5

4

3
2

-

=

TMR

5

=

HBORD

=

VBORD

3

=

2

EI2

=

1

Ell

=

EIO

Fast

Fast Int

-

7

-

=

TMR

=

HBORD

=

VBORD

=

EI2

=

1

Ell

=

EIO

Interrupt

Request

Request

Enable

Interrupt

Horizontal

Register (IRQENR)

from

Border IRQ

Vertical Border

Serial Data

Keyboard

Cartridge

IRQ

IRQ

IRQ

enabled

Enable

Interrupt

Horizontal

Vertical

Serial

Keyboard

from

Border FIRQ

Border FIRQ

Data FIRQ

FIRQ

Cartridge FIRQ

Timer

IRQ

enabled

enabled

enabled

Register

Timer

enabled

enabled

enabled

enabled

enabled

(FIRQENR)

enabled

enabled

enabled

-11-

FF94:

FF95:

FF96:
FF97:
FF98:

TIMER:

BIT
BIT
BIT
BIT
BIT

BIT
BIT

BIT

Timer

Timer

Most
Least

This

MSB,

MHz

14

the count

enabled),

Reserved
Reserved

Video

Mode

BP

BPI

MOCH

H50

LPR2

LPR1

=

LPRO

Significant

Significant

is

12-bit

a

the

count

or

horizontal sync,

falls

and the

Register

1

1

1

Lines
Lines
Lines

Nibble

Byte

interval

is

automatically

through

count

=

alphanumeric,

=

Burst

=

monochrome

=

50 Hz

vertical sync

per

per
per row

timer.

begun.

as

selected

zero,

is

phase

an interrupt

automatically

1

inverted

(on

row

(See

row

(See
(See

When

a

value is

The input

by TINS

reloaded,

=

bit

plane

composite)

table
table

table

below)
below)

below)

loaded into

clock is

(bit

is

generated (if

the

either

FF91).

of

5

As

FF99;

BIT
BIT

BIT
BIT

BIT
BIT
BIT
BIT

Video

=
=
=

=

3

=

2

=

1

=

LPR2

1

1
1

1

Resolution

LPF1

LPFO

HRES2

HRES1

HRESO

CRES1

CRESO

LPFI

LPR1

LPFO

LPRO

Lines

one

1

two

three

1

eight

nine

1

(reserved)
twelve

1

(reserved)

Register

Lines

Lines

per field
per

Horizontal

17)

Horizontal
Horizontal

Color
Color

resolution
resolution

Lines

per

(See

field

resolution

resolution
resolution

per field

character

(Graphics

(CoCo 1 and
(CoCo 1 and

(CoCo

table below)

(See

(See

Video

row

modes)

CoCo
CoCo 2

1

and

CoCo

Video

resolution)

only)

2

only)

2 only)

resolution

on

page

1

1

1

1

192

200

Reserved

225

-12-

FF9A: Border

BIT

7

BIT

6

BIT
BIT

BIT
BIT
BIT
BIT

=

5

=

4

=

3

=

2

=

1

=

Register

RED1

GRN1

BLU1

REDO
GRNO
BLUO

bits

(AIL

are for

Most significant red
Most significant
Most significant

Least significant red
Least significant

Least significant

CoCo

I

bit

green bit

blue bit

bit

green bit

bit

blue

and

CoCo 2 compatibility).

FF9B:

FF9C:

FF9D:

FF9E:

BIT

7

BIT

6

BIT

5

BIT

4

BIT
BIT
BIT
BIT

=

3

=

2

=

1

=

NOTE: In

BIT
BIT
BIT
BIT
BIT
BIT
BIT 1
BIT

BIT

BIT

BIT
BIT

BIT

BIT
BIT
BIT

=

7

»

6

=

5

=

4

=

3

=

2

=
=

=

7

=

6

=

5

=

4

=

3

=

2

=

1

=

Reserved

Vertical Scroll

Register

VSC3 (Vert.
VSC2

VSC1

VSCO

the CoCo mode, the VSC

Vertical Offset

Y18

1 Register

(Vert. Offset)

Y17

Y16
Y15

Y14

Y13
Y12
Yll

Vertical Offset

Y10

Y9

Register

(Vert, Offset)

Y8

Y7

Y6
Y5
Y4
Y3

Scroll)

' s

must be

initialized

to OF

hex.

NOTE:

SAM

In

bits

CoCo mode,

-

F6

FO.

Y15

Also in

-

Y9

CoCo

are

not effective, and

-

mode,

Y18

-13-

are controlled

Y16 should be

all others

1,

by

0.

FF9F:

BIT
BIT
BIT
BIT
BIT
BIT

BIT
BIT

Horizontal

=

7

HVEN!

=

X6

6

=

X5

5

=

X4

4

=

3

X3

=

2

X2

=

1

XI

=

XO

Offset

Horizontal
Horizontal
Horizontal
Horizontal
Horizontal
Horizontal

Horizontal
Horizontal

Register

Virtual

Offset
Offset
Offset
Offset

Offset
Offset
Offset

Enable

address
address
address
address
address
address
address

NOTE:

the HRES

HVEN

somewhat

(the

displayed

character

attribute

enables

bits

larger

mode,

(or

and

than

screen)

the

64,

a

horizontal

CRES

bits

the

by

screen

if

double-wide

screen

selected.

displayed

means

of

width

width

This

screen.

the horizontal

is

128

is

selected).

will

The

characters

of

128

allow

user

offset

regardless

bytes

regardless

a "virtual"

can move

bits.

of

screen

the "window"

In

of

-14-

Memory

Management Unit

(MMU)

XFFAO

The

memory

-

8-bit

with

extends

up

to 512K

The MMU

6-bit

elements

registers

to

address.

TR bit

The

of

relationship

address

Corresponding

(CPU DATA)

XFFAF,

CPU

the address

its

6 bits

in

16

bytes

consists

in this

are used by

These

FF91

is

as

Bit

(task

follows:

memory

address

DO-D5

(Write

the

Color

address

lines

of

memory

of

a multiplexer

RAM

the

registers

register

between

the data

D5

A18

only)

Computer

lines

to

19

(AO

($00000

array

computer

are

divided

select bit)

D4 D3

AI7 A16

3 can

-

(AO

is an MMU

-

A18). This

-

$7FFFF).

and

a

to

determine

A15).

16

into

in

the

D2

A15 A14

directly

The

x 6-bit

task

register,

the

2 sets,

determines

task

register

Dl

address

memory

allows

of

proper 8K

8 registers

which

DO

A13

only

management

the

computer

RAM array.

and

set is

and

the

64K

bytes

unit

to

Each

the

task

segment

per set. The

selected.

generated

of

(MMU)

address

of the

of memory

AI3-AI5

TR bit

AO-A3

When the

(XFF00

address

When

the CPU

register

CPU

-

XFFFF),

of

to be

needs

the

writes

to access

CPU

task

register

data

written

memory outside

address

lines

which

to the MMU,

to when SELECT

-

A13

the MMU

-

A0

goes

the

standard

A15 and

will

A3 determine

the

access

high.

AI3-AI8

(Extended addresses)

and

I/O

TR

bit

determine the

while SELECT

the

address

control

is

of

the task

range

low.

-15-

The

data

memory

TR

from

access,

A15

the MMU

according

A14 A13

is

then used

to the

(Address

as

the upper

following:

range)

6 address

MMU

location

lines

address

(A13

-

A18) for

It

is

important

FF90

must

the

desired

designated

in

the

top

be

pre-loaded

1

1 1

1

1

1

1

1

1 1

1

1 1

1

1

1 1

1 1

to

be

cleared,

addressing

set

of

of 512K

into

1

1

1 X2000

1

1

note

that,

and

information

task

registers.

RAM,

with

the MMU:

XOOOO

X2000
X4000
X6000

X8000

XA000
XC000

XEOOO

XOOOO

X4000

X6000
X8000

XA000
XC000
XEOOO

the M/P

in

the

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

X1FFF
X3FFF
X5FFF
X7FFF
X9FFF
XBFFF
XDFFF
XFFFF

X1FFF

X3FFF
X5FFF
X7FFF
X9FFF
XBFFF

XDFFF

XFFFF

order

bit

for

For

TR

bit

for

the MMU

FF90

of

each

segment

example,

set

to

must

if

0,

FFAO

FFA1

FFA2

FFA3

FFA4

FFA5
FFA6
FFA7

FFA8
FFA9

FFAA

FFAB

FFAC
FFAD

FFAE
FFAF

to function,

be set.

must

a

the

be

standard

following

Prior

loaded

64K

the

CoCo bit

to doing

into

map is

values

of

this,

the

desired

should

NOTE;

MMU

address

Data

Location

FFAO

FFA1

FFA2

FFA3

FFA4

FFA5

FFA6

FFA7

loaded

can

Data

be

(Hex)

38

39

3A

3B

3C

3D

3E

3F

selected

Data

freely

(Bin)

111000

111001

111010

111011

111100

111101

111

110

111111

within

the

Address

74000

76000

78000

7A000

7CO0O

7E000

range

70000

72000

of $00

-

-

-

-

-

-

-

-

range

71FFF

73FFF

75FFF

77FFF

79FFF

7BFFF

7DFFF

7FFFF

-

$3F.

-16-

COLOR

PALETTE

FFBO

For

-

the RGB

Corresponding

For

the

intensity

Corresponding

Some

Color

White
Black
Bright

Medium

Dark

Medium

FFBF:

16

output,

Data Bit

RGB

output

Composite

level

Data Bit

composite

output

Examples:

Color

Green
Green

Green

Magenta

addresses,

the bits

D5

Rl

output,

and P

is

D5

II

6 bits

are defined

D4

Gl Bl

the bits

phase:

D4

10

Binary

111111

000000

010010
010000

000010

101000

each

D3

D2

RO

are

D3 D2

P3

P2

RGB

as follows:

Dl

GO

defined

Dl

PI

Hex

(3F)
(00)
(12)

(10)

(02)
(28)

DO

BO

as

DO

P0

Binary

110000

000000

100010

010010
000010

010101

follows,

Composite

where 1

Hex

(30)
(00)
(22)
(12)
(02)
(15)

is

For

CoCo

compatibility,

initialization.

FFBO

FFB1

FFB2
FFB3
FFB4

FFB5
FFB6
FFB7
FFB8

FFB9

FFBA

FFBB
FFBC
FFBD

FFBE

FFBF

NOTE:

For

the

PAL

(NOTE:

Green

Yellow

Blue

Red

Buff
Cyan

Magenta

Orange

Black

Green
Black

Buff

Black

Green
Black

Orange

version,

the

These

following

are

(12)
(36)
(09)
(24)

(3F)

(10)
(2D)

(26)
(00)

(12)

(00)
(3F)
(00)
(12)

(00)

(26)

ignore

the

the

values

RGB

table

should

values.)

attributed

be

loaded

to

composite,

upon

-17-

VIDEO

The

combination

The

following

RESOLUTION

resolutions

of HRES and

CRES bits

are

supported:

determine

the

resolution

of the

screen.

Alphanumerics:

RES Bit

Mode

32

character

40

character

80

character

Graphics:

BP

Pixels

640

640

512
512

320
320
256

256

256

160

=

BP

0,

HRES2

=

, CoCo

1

Colors

4 1

2

4 1

2

16

4

16

4

2

16 1

CoCo

1

=

HRES2

=

HRES1

HRESO

HRES1

1 1

1

1

1

1

HRESO

I

1

1

1

CRES1

CRESO

CRES1

1

1

1

CRESO

1

1

1

1

In addition

to the

Alphanumerics
Alphanumerics

Semigraphics

Inverted

-

4

64X64 Color Graphics

128 X
128
128
128
128
128

256

64 Graphics

X

64 Color Graphics

X

96 Graphics

X

96 Color Graphics

X

192 Graphics

X

192 Color Graphics

X

192 Graphics

above

modes,

the previous

COLOR COMPUTER MODE

MC6883 (SAM)

DISPLAY MODE

V2

1

1 1

1 1

1 1

VI V0

1

1

1

1 1

CoCo modes

SELECTION

REG.

7 6

are

available.

FF22

5 4 3

X X
X

X

1

1
1 1 CSS

1 1

X CSS
X X

1 CSS

1 CSS

1

1

1

1

CSS

CSS

CSS
CSS
CSS

CSS

-18-

ALPHANUMERIC MODES

Text

screen memory:

BOTE:

Even Byte

BIT

7

BIT

BIT
BIT
BIT
BIT
BIT
BIT

Odd

BIT
BIT

BIT
BIT
BIT

BIT

BIT

BIT =

=

6

Character bit

=

5

Character bit

=

Character

4

=

3

Character bit

=

2

Character bit

=

1

Character bit

=

Character bit

Byte

=

BLINK

7

=

UNDLN

6

=

FGND2

5

=

FGND1

4

=

PGNDO

3

=

BGND2

2

=

BGND1

1

BGNDO

Attributes

(Character byte)

6
5

bit

4

3
2

1

(Attribul

te byte)

Characters
Characters

Foreground

Foreground
Foreground
Background
Background
Background

are not available

blink

at

are underlined

color bit
color bit
color bit
color bit
color bit
color bit

when

CoCo

sec.

1/2

rate

(pallette addr.)
(pallette addr.)
(pallette addr.)

(pallette addr.)
(pallette
(pallette

1.

addr.)
addr.)

-19-

GRAPHICS

16 Color

Byte

4 Color

Byte

2 Color

Byte

Pallette

MODES

Modes:

from

Bit
Bit
Bit
Bit
Bit

Bit

Bit

Bit

Modes:

from

Bit

Bit
Bit

Bit
Bit

Bit
Bit
Bit

Modes:

from

Bit
Bit

Bit
Bit
Bit
Bit
Bit
Bit

Addresses

(CRES1

DRAM

7
6

5

4

3
2

1

(CRES1

DRAM

7

6

5

4

3

2

1

(CRES1

DRAM

7

6
5

4

3

2

1

=

1,

PA3,
PA2,

PAI, First
PAO, First
PA3,
PA2,

PAI,

PAO,

=

CRESO

0,

PAI, First
PAO,

PAI,

PAO,
PAI,
PAO,
PAI,
PAO,

=

CRESO

0,

PAO,

PAO,
PAO,
PAO, Fourth
PAO,
PAO,

PAO,

PAO,

CRESO

First
First

Second
Second

Second
Second

First

Second

Second

Third

Third

Fourth

Fourth

First

Second

Third

Fifth
Sixth

Seventh

Eighth

=

0)

Pixel
Pixel

Pixel
Pixel

Pixel

Pixel
Pixel
Pixel

=

1)

Pixel
Pixel

Pixel

Pixel
Pixel
Pixel

Pixel

Pixel

=

0)

Pixel

Pixel

Pixel

Pixel

Pixel
Pixel

Pixel

Pixel

PA3

PA2

1

1

1

1

1

1

1

1

PAI

1

1

1

1

1

1

1

1

PAO

1

1

1

1

1

1

1

1

Address

of

Contents

FFBO

FFB1
FFB2

FFB3

FFB4

FFB5
FFB6

FFB7

FFB8
FFB9

FFBA

FFBB
FFBC
FFBD

FFBE
FFBF

Displayed

-20-

SAM

CONTROL REGISTERS

Clear Set

FFCO
FFC2
FFC4
FFC6
FFC8

FFCA

FFCC

FFCE
FFDO

FFD2
FFD8
FFDE

-

FFC1

-

FFC3

-

FFC5

-

FFC7

-

FFC9

-

FFCB F2

-

FFCD F3

-

FFCF F4

-

FFD1 F5

-

FFD3 F6

-

FFD9

-

FFDF

(FFCO

VO

VI

V2
FO

Fl

-

FFDF)

CoCo graphics

graphics mode

CoCo
CoCo graphics mode
CoCo Vertical offset
CoCo

Vertical offset

CoCo Vertical
CoCo Vertical
CoCo Vertical

CoCo Vertical

CoCo Vertical

Rl

MPU

Speed

TY

ROM

disable

mode

offset

offset
offset
offset
offset

select
select
select

NOTE:

These

bits work like

(MC6883/SN74LS785)

group

the bit

in the

semigraphics

(data

is cleared. The

CoCo

don't

is

mode,

mode

FFDF

FFDE

FFD9

FFD8
FFD3

FFD2

FFD1

FFD0

FFCF

FFCE

FFCD

FFCC
FFCB

FFCA

FFC9
FFC8
FFC7

FFC6
FFC5

FFC4

FFC3

FFC2

FFC1

FFCO

the ones in the

in that by writing

care),

the

bit

graphics modes

but the

other

two

supported is Semi Four.

TY

Rl

F6

F5

F4

F3

F2

F1

F0

V2

MAP

TYPE

CPU

RATE

DISPLAY

OFFSET

(BINARY)

DISPLAY

MODE

CONTROL

VI

(SAM)

Vfl

Motorola

to the upper

is set; by writing

address of

and vertical

bits

are valid anytime.

Address of

Display Element

-,

N.U.

Upper-

RG6, CG6

r

Left- Most

=

J

1

1

9

SAM

chip

to

the lower address,

offset bits

Note

+ (1/2K Offset)

9999

RG3

I-CG3

t-RG2

r-CG2

each two-address

are valid

the only

only

0.89MHz

-1.78MHz

I-CG1.RG1

AE,

r-AI,

1

9

S4,

(S=Set Bit,

C=Clear

Figure

1-3.

Bit,

Memory

all

Map

Bits

for SAM

-21-

are cleared when

Control

Register

SAM

is

reset)

1.6

FFEO

68B09E

-

FFFF

Vector

Registers

CPU

ICl

FFFF:

FFFE:

FFFD:

FFFC:

FFFB:

FFFA:

FFF9:

FFF8:

FFF7:

FFF6:

FFF5:

FFF4:

FFF3:

Reset

Reset

NMI

NMI

SWI1

SWI1

IRQ

IRQ

FIRQ

FIRQ

SWI2

SWI2

SWI3

vector LS

vector MS

vector LS

vector MS

vector

vector MS

vector

vector

LS

MS

vector

vector

vector LS

vector

vector LS

LS

LS

MS

MS

FFF2:

FFF1:

FFFO:

FFEF

LS;

MS:

SWI3

Reserved

Reserved

-

FFEO:

Least significant

Most

significant

vector

Not

MS

used

address

address

byte

byte

-22-

2.1

SECTION II. SPECIFICATIONS

Technical

CPU: 68B09E

8-bit

Clock Speed

MEMORY SIZE: ROM: 32K

128K

57 keys,

57 keys

KEYBOARD:

Number

RAM:

of keys:

Alphabetical

characters:

Numeric

characters: 10 keys

Space key:

Shift

key:

Clear key: 1

Enter

Break (ESC)

key:

key:

26 keys (A

1 key

keys

2

key

1 key

1 key

processor

-

Byte
Byte (Expandable

MHz/1.78 MHz

0.89

(for

BASIC)

up to 512K)

microprocessor-scanned

to

Z)

to

(0

9)

matrix

Punctuation

key:

Directional Control

key:

Function

Control

Alternate

key: 2 keys (Fl

key:

key: 1

7 keys

4 keys

1 key

key

keys

57

and

F2)

-23-

VIDEO

DISPLAY:

Character display:

Graphic

display:

INTERFACE:

Serial

interface:

Cassette interface:

Analog input

face

Bus

(for

line

JOYSTICK):

CONTROLS:

Power

Reset

switch:

switch:

inter-

512

(32

960 (40

1920

(80x24) upper/lower

x

256

x

320

640 x

RS-232C

5P DIN

6P DIN

PIN

40

Push

Key

x

16)

x

24)

192 dots
192 dots
192 dots

4P-DIN

1500 baud

x

2

conne

upper case characters

upper/lower

case

characters

case characters

8 colors

16 colors

4 colors

Channel

switch

RF

OUTPUT:

NTSC

PAL <;

Output

RF

Output

RF

Output

selector

r

CH

4

.

'

CH

iinpedance

Frequency

3

* 67.25

61.25

Frequency

1

2

57.25

64.25 +0.25

: 7 5 ohm

terminal:

level: NTSC

Slide

+

+

+

RCA

PAL

(Video)

0.25 MHz

0.25 MHz

(Video)

0.25 MHz

MHz

JACK

+2

67

_4

+

70

dBu

5dBp

Frequency

+

4.5

4.5

0.02 MHz

+

0.02 MHz

Frequency

+

5.5

5.5

0.02 MHz

+

0.02 MHz

(Sound)

(Sound)

-24-

VIDEO/

SOUND

ODTPUT:

Output

Output

RGB

Output

Output

terminal:

level:

(Analog)

terminal:

level

NTSC

PAL

Video:

Sync:

Sound:

/Sound

Red:

<

Green:

Blue:

Red:

f

Green:

RCA

lVp-p

0.71V

0.29V +

Less

OUTPUT

lOpin pin

0.8(+0.r

0.8(+0.i;

0.8(+0.i;

0.6(+0.i:

0.6(+0.11

JACK

+

than

0.1V (RL

0.1V

(RL

l.OVp-p

header

-

L)

2.0(+0.2)Vdc

-

L)

2.0(+0.2)Vdc

-

.)

2.0(+0.2)Vdc

-

.)

1.8(+0.2)Vdc

-

.)

1.8(+0.2)Vdc

=

75ohm)

=

75ohm)

=

(RL

(Bottom

600ohm)

side)

=

(RL

=

(RL

=

(RL

=

(RL

=

(RL

75ohm) positive

75ohm)

7

5ohm) positive

7

5ohm) positive

7

5ohm)

positive

positive

2.2

POWER

SUPPLY:

Physical

DIMENSIONS

NET

WEIGHT:

Blue:

Hsync:

Vsync:

Sound:

NTSC

PAL

(Cabinet

size):

Width:

Height: 3-1/8"

Depth: 10-3/8"

4.85 lbs

0.6(+0.i:

TTL

level

TTL

level

Less

AC

AC

than

120V/60Hz,

240V/50HZ;,

14-3/4"

kg)

(2.3

-

.)

1.8(+0.2)Vdc

positive

positive

l.OVp-p

(375 mm)

79 mm)

(

(264

mm)

0.2

0.125

=

(RL

Amp RMS

Amp RMS

=

(RL

600ohm)

typical

typical

75ohm) positive

-25-

SECTION

III.

DISASSEMBLY

/ASSEMBLY

3.1 Disassembly

1.

Disconnect

cables

2. Remove

power and

from

cartridge

applicable)

Turn

3.

a

to

4. Loosen

screws SI

S2)
the

3-1)

5. Disconnect

connector

keyboard

Then

6.

the unit

soft

surface

the keyboard

and

remove

and

mounting

base

to the

the

which

(Figure

disconnect

transformer

on

the main PCB

7.

Remove

screws S4)

PCB

(Figure

to

do

which

four

to

the bottom

remove

so by

attach

screws

3-2). If

the

removing

remove

the unit.

from

slot

over and

to

prevent

or

top

the six

two longer

screws

at the 3-pin

top

cable

is

3-2).

the

which

cover.

from

attached

power

(Figure 3-2).

(two

screws S3

which

case

it is

shield

it

to

the

the

from

16

signal

(if

place

it

damage

cover,

(four

screws

attach

(Figure

the

wire

to

connector

and two

attach

cover

necessary

the PCB,

rivets

PCB.

on

the

the

3.2 Assembly

Assemble

reverse

shield

the

order

is

attached

metal rivets.

in

place to

shielding.

Set

the wire

transformer

keyboard

Two

different

used

bottom

correct

ing.

The

strain

consists

the

plastic

of the unit.

cord is

strain

to the

to mount

cabinet.

type

relief

of wrapping

properly

relief

connections.

Color

Computer

of disassembly.

to the PCB

These

provide

assembly

and

shields

proper RFI

flat

from the

cable

connector on

types

the PCB

is used

bosses

Ensure

of screws

and

Ensure

that the

when reassembl-

on

the
the cord

on

the

that the

routed

to

the transformer

3

must

from

the PCB.

the

power

rear side

power

afford

to

in

the

The PCB

with

be

the

are

top and

cord

around

Figure 3-1.

Removal of Top

Cover

Figure

3-2.

^©

Removal

3-pin connector (CN7)

CN2

of Main

PCB

©

-26-

51 2K HAM Upgrade

3.3

To

upgrade a 128K memory unit

512K memory unit,

Instructions

follow

the

procedure below.

1. Remove the

described

(IC16-IC19)

of

the PCB (Figure 3-3),

unsolder

top cabinet

in

3.1. Remove

as

from the IC sockets

C65 82 pF ceramic

four ICs

capacitor and remove it.

Three

2.

nylon stand-offs

are

packaged with the RAM card. Insert

them into corresponding

the RAM

card

(Figure 3-4).

holes of

to a

L

\

*

[

m
2
O

)

±

J

Figure

C65

JiC

iC

|

licir

IB

19

CN4

3-3.

L

<=5

65

C

|

lor PAi_

1

1

Main

verftmn

;

[

J

PCB

3. Align the pin

card over CN4

slowly

Snap

4.

corresponding

lower the

each

stand-off

hole on

PCB.

Connect

5.

the computer's AC cord and

signal cables

run

the following program

verify

memory

6. Secure the

proper

chips.

top

cabinets.

<Test Prograra>

10 WIDTH 40: PALETTE

POKE&HFFD9,0

20
30 FOR

40

50 LP0KE

A=&H0OOOO

D=RND(2

55)

A,D

60 B=LPEEK(A)

70

LOCATE

80 LOCATE

IF BOD

90

10,2:

10,4:

THEN

PRIN^'ADDRESS^A

PRINT"DATA=";D

130

100 NEXT A
110 LOCATE

10,10:

120 P0KE&HFFD8,0:
130 LOCATE

10,6:

140 POKE&HFFD8,0:

socket of

through CN6,

the

RAM

then

Board.

into the

computer

the

to a TV monitor and

to

operation of the

new

and bottom

PALETTE

0,0:

5.H5FFFF

TO

PRINT"RAM

7,63:

STEP 512

TEST IS

END

PRINT"ERROR!

END

CLS8

GOOD!

Figure

1

3-4.

512K RAM

Card

-27-

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-29-

SECTION

5.1

MC68B09E/MBL68B09E/HD68BO9E

(IC1)

The

heart

Central

the
the Color Computer

modern

most

is

a

Circuit

instructions

interprets and

instructions, and stores

of the data operations

single

(LSI).

of

any computer system is

Processing Unit) CPU. In

as well

3,

microprocessors, the CPU

Large Scale Integration

The

CPU gathers

and data from memory,

executes the

the results

into memory.

Additionally, the CPU stores

and retrieves

data

from

various

input/output (I/O) devices.

The

68B09E

the most

microprocessor

are several

"size"

it is

whatever)

number

microprocessor

powerful

available

ways to

of

a microprocessor

8-bit,

of

16-bit, 32-bit,

One

.

way involves

data

interconnecting

8-bit

today.

determine

as

data

is

perhaps

the

(whether

or

the

lines

V.

in

to

There

THEORY

OF

OPERATION

the

processor

the

size

of

and

the

size

logical

operations

processor.

8-bit

contains

two

may be

another

also

data

four

additional

linked

16-bit

supports

mathematical

Therefore,

an

8-bit

the

power

Figure

of

the

processor,

of

5-1

68B09E

information

68B09E

data

possesses.

the

internal

of

the

Although

bus,

internally

16-bit

8-bit

together

register.

some

and

logical

although

the

16-bit

is

a

"programming

CPU.

may be

sheet.

Another

registers

mathematical

supported

the 68B09E

it

registers
registers

to

form

The

16-bit

operations.

it

is

technically

it

has

some

machines.

Additional

obtained

from

and

by

the

has

and

which

68B09E

of

model"

the

is

an

—

X

—

Y

-

U

—

Hardware

S

Figure

Index

Index

User

Stack Pointer

PC

v-

—

D

5-1.

Register

Register

Stack Pointer

68B09E

E

Programming

Pointer

Program

Accumulators

Direct Page

—

CC

Condition Code

Carry

Overflow

Zero

Negative

IRQ

Mask

Half

Carry

FIRQMask

Entire

Flag

Model

Registers

Counter

Register

Register

-30-